Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add mode2 reset support for aldebaran
v1: Aldebaran uses reset control to support mode2 reset. The sequences to
reset and restore hardware context are specific to a particular
configuration.
v2: Clear bus mastering before reset.
Fix coding style issues, drop unwanted variables and info log.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
142600e8
5d89bb2d
+463
-2
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
···
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71
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
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72
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
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arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
74
-
nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o
74
+
nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o
75
75
76
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# add DF block
77
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amdgpu-y += \
+407
drivers/gpu/drm/amd/amdgpu/aldebaran.c
+407
drivers/gpu/drm/amd/amdgpu/aldebaran.c
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#include "aldebaran.h"
25
+
#include "amdgpu_reset.h"
26
+
#include "amdgpu_amdkfd.h"
27
+
#include "amdgpu_dpm.h"
28
+
#include "amdgpu_job.h"
29
+
#include "amdgpu_ring.h"
30
+
#include "amdgpu_ras.h"
31
+
#include "amdgpu_psp.h"
32
+
#include "amdgpu_xgmi.h"
33
+
34
+
static struct amdgpu_reset_handler *
35
+
aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
36
+
struct amdgpu_reset_context *reset_context)
37
+
{
38
+
struct amdgpu_reset_handler *handler;
39
+
struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
40
+
41
+
if (reset_context->method != AMD_RESET_METHOD_NONE) {
42
+
dev_dbg(adev->dev, "Getting reset handler for method %d\n",
43
+
reset_context->method);
44
+
list_for_each_entry(handler, &reset_ctl->reset_handlers,
45
+
handler_list) {
46
+
if (handler->reset_method == reset_context->method)
47
+
return handler;
48
+
}
49
+
}
50
+
51
+
if (adev->gmc.xgmi.connected_to_cpu) {
52
+
list_for_each_entry(handler, &reset_ctl->reset_handlers,
53
+
handler_list) {
54
+
if (handler->reset_method == AMD_RESET_METHOD_MODE2) {
55
+
reset_context->method = AMD_RESET_METHOD_MODE2;
56
+
return handler;
57
+
}
58
+
}
59
+
}
60
+
61
+
dev_dbg(adev->dev, "Reset handler not found!\n");
62
+
63
+
return NULL;
64
+
}
65
+
66
+
static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
67
+
{
68
+
int r, i;
69
+
70
+
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
71
+
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
72
+
73
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
74
+
if (!(adev->ip_blocks[i].version->type ==
75
+
AMD_IP_BLOCK_TYPE_GFX ||
76
+
adev->ip_blocks[i].version->type ==
77
+
AMD_IP_BLOCK_TYPE_SDMA))
78
+
continue;
79
+
80
+
r = adev->ip_blocks[i].version->funcs->suspend(adev);
81
+
82
+
if (r) {
83
+
dev_err(adev->dev,
84
+
"suspend of IP block <%s> failed %d\n",
85
+
adev->ip_blocks[i].version->funcs->name, r);
86
+
return r;
87
+
}
88
+
89
+
adev->ip_blocks[i].status.hw = false;
90
+
}
91
+
92
+
return r;
93
+
}
94
+
95
+
static int
96
+
aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
97
+
struct amdgpu_reset_context *reset_context)
98
+
{
99
+
int r = 0;
100
+
struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
101
+
102
+
dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
103
+
/* Don't suspend on bare metal if we are not going to HW reset the ASIC */
104
+
if (!amdgpu_sriov_vf(adev))
105
+
r = aldebaran_mode2_suspend_ip(adev);
106
+
107
+
return r;
108
+
}
109
+
110
+
void aldebaran_async_reset(struct work_struct *work)
111
+
{
112
+
struct amdgpu_reset_handler *handler;
113
+
struct amdgpu_reset_control *reset_ctl =
114
+
container_of(work, struct amdgpu_reset_control, reset_work);
115
+
struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
116
+
117
+
list_for_each_entry(handler, &reset_ctl->reset_handlers,
118
+
handler_list) {
119
+
if (handler->reset_method == reset_ctl->active_reset) {
120
+
dev_dbg(adev->dev, "Resetting device\n");
121
+
handler->do_reset(adev);
122
+
break;
123
+
}
124
+
}
125
+
}
126
+
127
+
static int aldebaran_mode2_reset(struct amdgpu_device *adev)
128
+
{
129
+
/* disable BM */
130
+
pci_clear_master(adev->pdev);
131
+
adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
132
+
return adev->asic_reset_res;
133
+
}
134
+
135
+
static int
136
+
aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
137
+
struct amdgpu_reset_context *reset_context)
138
+
{
139
+
struct amdgpu_device *tmp_adev = NULL;
140
+
struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
141
+
int r = 0;
142
+
143
+
dev_dbg(adev->dev, "aldebaran perform hw reset\n");
144
+
if (reset_context->hive == NULL) {
145
+
/* Wrong context, return error */
146
+
return -EINVAL;
147
+
}
148
+
149
+
list_for_each_entry(tmp_adev, &reset_context->hive->device_list,
150
+
gmc.xgmi.head) {
151
+
mutex_lock(&tmp_adev->reset_cntl->reset_lock);
152
+
tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
153
+
}
154
+
/*
155
+
* Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch
156
+
* them together so that they can be completed asynchronously on multiple nodes
157
+
*/
158
+
list_for_each_entry(tmp_adev, &reset_context->hive->device_list,
159
+
gmc.xgmi.head) {
160
+
/* For XGMI run all resets in parallel to speed up the process */
161
+
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
162
+
if (!queue_work(system_unbound_wq,
163
+
&tmp_adev->reset_cntl->reset_work))
164
+
r = -EALREADY;
165
+
} else
166
+
r = aldebaran_mode2_reset(tmp_adev);
167
+
if (r) {
168
+
dev_err(tmp_adev->dev,
169
+
"ASIC reset failed with error, %d for drm dev, %s",
170
+
r, adev_to_drm(tmp_adev)->unique);
171
+
break;
172
+
}
173
+
}
174
+
175
+
/* For XGMI wait for all resets to complete before proceed */
176
+
if (!r) {
177
+
list_for_each_entry(tmp_adev,
178
+
&reset_context->hive->device_list,
179
+
gmc.xgmi.head) {
180
+
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
181
+
flush_work(&tmp_adev->reset_cntl->reset_work);
182
+
r = tmp_adev->asic_reset_res;
183
+
if (r)
184
+
break;
185
+
}
186
+
}
187
+
}
188
+
189
+
list_for_each_entry(tmp_adev, &reset_context->hive->device_list,
190
+
gmc.xgmi.head) {
191
+
mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
192
+
tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
193
+
}
194
+
195
+
return r;
196
+
}
197
+
198
+
static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
199
+
{
200
+
struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];
201
+
struct amdgpu_firmware_info *ucode;
202
+
struct amdgpu_ip_block *cmn_block;
203
+
int ucode_count = 0;
204
+
int i, r;
205
+
206
+
dev_dbg(adev->dev, "Reloading ucodes after reset\n");
207
+
for (i = 0; i < adev->firmware.max_ucodes; i++) {
208
+
ucode = &adev->firmware.ucode[i];
209
+
if (!ucode->fw)
210
+
continue;
211
+
switch (ucode->ucode_id) {
212
+
case AMDGPU_UCODE_ID_SDMA0:
213
+
case AMDGPU_UCODE_ID_SDMA1:
214
+
case AMDGPU_UCODE_ID_SDMA2:
215
+
case AMDGPU_UCODE_ID_SDMA3:
216
+
case AMDGPU_UCODE_ID_SDMA4:
217
+
case AMDGPU_UCODE_ID_SDMA5:
218
+
case AMDGPU_UCODE_ID_SDMA6:
219
+
case AMDGPU_UCODE_ID_SDMA7:
220
+
case AMDGPU_UCODE_ID_CP_MEC1:
221
+
case AMDGPU_UCODE_ID_CP_MEC1_JT:
222
+
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
223
+
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
224
+
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
225
+
case AMDGPU_UCODE_ID_RLC_G:
226
+
ucode_list[ucode_count++] = ucode;
227
+
break;
228
+
default:
229
+
break;
230
+
};
231
+
}
232
+
233
+
/* Reinit NBIF block */
234
+
cmn_block =
235
+
amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
236
+
if (unlikely(!cmn_block)) {
237
+
dev_err(adev->dev, "Failed to get BIF handle\n");
238
+
return -EINVAL;
239
+
}
240
+
r = cmn_block->version->funcs->resume(adev);
241
+
if (r)
242
+
return r;
243
+
244
+
/* Reinit GFXHUB */
245
+
adev->gfxhub.funcs->init(adev);
246
+
r = adev->gfxhub.funcs->gart_enable(adev);
247
+
if (r) {
248
+
dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
249
+
return r;
250
+
}
251
+
252
+
/* Reload GFX firmware */
253
+
r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
254
+
if (r) {
255
+
dev_err(adev->dev, "GFX ucode load failed after reset\n");
256
+
return r;
257
+
}
258
+
259
+
/* Resume RLC, FW needs RLC alive to complete reset process */
260
+
adev->gfx.rlc.funcs->resume(adev);
261
+
262
+
/* Wait for FW reset event complete */
263
+
r = smu_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
264
+
if (r) {
265
+
dev_err(adev->dev,
266
+
"Failed to get response from firmware after reset\n");
267
+
return r;
268
+
}
269
+
270
+
for (i = 0; i < adev->num_ip_blocks; i++) {
271
+
if (!(adev->ip_blocks[i].version->type ==
272
+
AMD_IP_BLOCK_TYPE_GFX ||
273
+
adev->ip_blocks[i].version->type ==
274
+
AMD_IP_BLOCK_TYPE_SDMA))
275
+
continue;
276
+
r = adev->ip_blocks[i].version->funcs->resume(adev);
277
+
if (r) {
278
+
dev_err(adev->dev,
279
+
"resume of IP block <%s> failed %d\n",
280
+
adev->ip_blocks[i].version->funcs->name, r);
281
+
return r;
282
+
}
283
+
284
+
adev->ip_blocks[i].status.hw = true;
285
+
}
286
+
287
+
for (i = 0; i < adev->num_ip_blocks; i++) {
288
+
if (!(adev->ip_blocks[i].version->type ==
289
+
AMD_IP_BLOCK_TYPE_GFX ||
290
+
adev->ip_blocks[i].version->type ==
291
+
AMD_IP_BLOCK_TYPE_SDMA ||
292
+
adev->ip_blocks[i].version->type ==
293
+
AMD_IP_BLOCK_TYPE_COMMON))
294
+
continue;
295
+
296
+
if (adev->ip_blocks[i].version->funcs->late_init) {
297
+
r = adev->ip_blocks[i].version->funcs->late_init(
298
+
(void *)adev);
299
+
if (r) {
300
+
dev_err(adev->dev,
301
+
"late_init of IP block <%s> failed %d after reset\n",
302
+
adev->ip_blocks[i].version->funcs->name,
303
+
r);
304
+
return r;
305
+
}
306
+
}
307
+
adev->ip_blocks[i].status.late_initialized = true;
308
+
}
309
+
310
+
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
311
+
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
312
+
313
+
return r;
314
+
}
315
+
316
+
static int
317
+
aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
318
+
struct amdgpu_reset_context *reset_context)
319
+
{
320
+
int r;
321
+
struct amdgpu_device *tmp_adev = NULL;
322
+
323
+
if (reset_context->hive == NULL) {
324
+
/* Wrong context, return error */
325
+
return -EINVAL;
326
+
}
327
+
328
+
list_for_each_entry(tmp_adev, &reset_context->hive->device_list,
329
+
gmc.xgmi.head) {
330
+
dev_info(tmp_adev->dev,
331
+
"GPU reset succeeded, trying to resume\n");
332
+
r = aldebaran_mode2_restore_ip(tmp_adev);
333
+
if (r)
334
+
goto end;
335
+
336
+
/*
337
+
* Add this ASIC as tracked as reset was already
338
+
* complete successfully.
339
+
*/
340
+
amdgpu_register_gpu_instance(tmp_adev);
341
+
342
+
/* Resume RAS */
343
+
amdgpu_ras_resume(tmp_adev);
344
+
345
+
/* Update PSP FW topology after reset */
346
+
if (reset_context->hive &&
347
+
tmp_adev->gmc.xgmi.num_physical_nodes > 1)
348
+
r = amdgpu_xgmi_update_topology(reset_context->hive,
349
+
tmp_adev);
350
+
351
+
if (!r) {
352
+
amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
353
+
354
+
r = amdgpu_ib_ring_tests(tmp_adev);
355
+
if (r) {
356
+
dev_err(tmp_adev->dev,
357
+
"ib ring test failed (%d).\n", r);
358
+
r = -EAGAIN;
359
+
tmp_adev->asic_reset_res = r;
360
+
goto end;
361
+
}
362
+
}
363
+
}
364
+
365
+
end:
366
+
return r;
367
+
}
368
+
369
+
static struct amdgpu_reset_handler aldebaran_mode2_handler = {
370
+
.reset_method = AMD_RESET_METHOD_MODE2,
371
+
.prepare_env = NULL,
372
+
.prepare_hwcontext = aldebaran_mode2_prepare_hwcontext,
373
+
.perform_reset = aldebaran_mode2_perform_reset,
374
+
.restore_hwcontext = aldebaran_mode2_restore_hwcontext,
375
+
.restore_env = NULL,
376
+
.do_reset = aldebaran_mode2_reset,
377
+
};
378
+
379
+
int aldebaran_reset_init(struct amdgpu_device *adev)
380
+
{
381
+
struct amdgpu_reset_control *reset_ctl;
382
+
383
+
reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
384
+
if (!reset_ctl)
385
+
return -ENOMEM;
386
+
387
+
reset_ctl->handle = adev;
388
+
reset_ctl->async_reset = aldebaran_async_reset;
389
+
reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
390
+
reset_ctl->get_reset_handler = aldebaran_get_reset_handler;
391
+
392
+
INIT_LIST_HEAD(&reset_ctl->reset_handlers);
393
+
INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
394
+
/* Only mode2 is handled through reset control now */
395
+
amdgpu_reset_add_handler(reset_ctl, &aldebaran_mode2_handler);
396
+
397
+
adev->reset_cntl = reset_ctl;
398
+
399
+
return 0;
400
+
}
401
+
402
+
int aldebaran_reset_fini(struct amdgpu_device *adev)
403
+
{
404
+
kfree(adev->reset_cntl);
405
+
adev->reset_cntl = NULL;
406
+
return 0;
407
+
}
+32
drivers/gpu/drm/amd/amdgpu/aldebaran.h
+32
drivers/gpu/drm/amd/amdgpu/aldebaran.h
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef __ALDEBARAN_H__
25
+
#define __ALDEBARAN_H__
26
+
27
+
#include "amdgpu.h"
28
+
29
+
int aldebaran_reset_init(struct amdgpu_device *adev);
30
+
int aldebaran_reset_fini(struct amdgpu_device *adev);
31
+
32
+
#endif
+16
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+16
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
···
36
36
{
37
37
int ret = 0;
38
38
39
+
switch (adev->asic_type) {
40
+
case CHIP_ALDEBARAN:
41
+
ret = aldebaran_reset_init(adev);
42
+
break;
43
+
default:
44
+
break;
45
+
}
46
+
39
47
return ret;
40
48
}
41
49
42
50
int amdgpu_reset_fini(struct amdgpu_device *adev)
43
51
{
44
52
int ret = 0;
53
+
54
+
switch (adev->asic_type) {
55
+
case CHIP_ALDEBARAN:
56
+
ret = aldebaran_reset_fini(adev);
57
+
break;
58
+
default:
59
+
break;
60
+
}
45
61
46
62
return ret;
47
63
}
+7
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+7
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
4024
4024
}
4025
4025
4026
4026
gfx_v9_0_cp_enable(adev, false);
4027
-
adev->gfx.rlc.funcs->stop(adev);
4028
4027
4028
+
/* Skip suspend with A+A reset */
4029
+
if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) {
4030
+
dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n");
4031
+
return 0;
4032
+
}
4033
+
4034
+
adev->gfx.rlc.funcs->stop(adev);
4029
4035
return 0;
4030
4036
}
4031
4037