tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2019-11-01' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"This is the regular drm fixes pull request for 5.4-rc6. It's a bit
larger than I'd like but then last week was quieter than usual.

The main fixes are amdgpu, and the two bigger area are navi fixes
which are the newest GPU range so still getting actively fixed up, but
also a bunch of clang stack alignment fixes (as amdgpu uses double in
some places).

Otherwise it's all fairly run of the mill fixes, i915, panfrost,
etnaviv, v3d and radeon, along with a core scheduler fix.

Summary:

amdgpu:
- clang alignment fixes
- Updated golden settings
- navi: gpuvm, sdma and display fixes
- Freesync fix
- Gamma fix for DCN
- DP dongle detection fix
- vega10: Fix for undervolting

radeon:
- reenable kexec fix for ppc

scheduler:
- set an error if hw job failed

i915:
- fix PCH reference clock for HSW/BDW
- TGL display PLL doc fix

panfrost:
- warning fix
- runtime pm fix
- bad pointer dereference fix

v3d:
- memleak fix

etnaviv:
- memory corruption fix
- deadlock fix
- reintroduce lost debug message"

* tag 'drm-fixes-2019-11-01' of git://anongit.freedesktop.org/drm/drm: (29 commits)
drm/amdgpu: enable -msse2 for GCC 7.1+ users
drm/amdgpu: fix stack alignment ABI mismatch for GCC 7.1+
drm/amdgpu: fix stack alignment ABI mismatch for Clang
drm/radeon: Fix EEH during kexec
drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE
drm/amdgpu/powerplay/vega10: allow undervolting in p7
dc.c:use kzalloc without test
drm/amd/display: setting the DIG_MODE to the correct value.
drm/amd/display: Passive DP->HDMI dongle detection fix
drm/amd/display: add 50us buffer as WA for pstate switch in active
drm/amd/display: Allow inverted gamma
drm/amd/display: do not synchronize "drr" displays
drm/amdgpu: If amdgpu_ib_schedule fails return back the error.
drm/sched: Set error to s_fence if HW job submission failed.
drm/amdgpu/gfx10: update gfx golden settings for navi12
drm/amdgpu/gfx10: update gfx golden settings for navi14
drm/amdgpu/gfx10: update gfx golden settings
drm/amd/display: Change Navi14's DWB flag to 1
drm/amdgpu/sdma5: do not execute 0-sized IBs (v2)
drm/amdgpu: Fix SDMA hang when performing VKexample test
...

Linus Torvalds 14616244 65a5bf1c

+224 -90
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
··· 218 218 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 219 219 struct dma_fence *fence = NULL, *finished; 220 220 struct amdgpu_job *job; 221 - int r; 221 + int r = 0; 222 222 223 223 job = to_amdgpu_job(sched_job); 224 224 finished = &job->base.s_fence->finished; ··· 243 243 job->fence = dma_fence_get(fence); 244 244 245 245 amdgpu_job_free_resources(job); 246 + 247 + fence = r ? ERR_PTR(r) : fence; 246 248 return fence; 247 249 } 248 250
+3 -3
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 93 93 { 94 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 95 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 96 - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), 96 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 97 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 98 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 99 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), ··· 140 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 141 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 142 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 143 - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), 143 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 144 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 145 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 146 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), ··· 179 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 180 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 181 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 182 - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100), 182 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 183 183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 184 184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 185 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+9
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
··· 151 151 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 152 152 153 153 tmp = mmGCVM_L2_CNTL3_DEFAULT; 154 + if (adev->gmc.translate_further) { 155 + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 156 + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 157 + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 158 + } else { 159 + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 160 + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 161 + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 162 + } 154 163 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 155 164 156 165 tmp = mmGCVM_L2_CNTL4_DEFAULT;
+1
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 309 309 310 310 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 311 311 job->vm_needs_flush = true; 312 + job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 312 313 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 313 314 r = amdgpu_job_submit(job, &adev->mman.entity, 314 315 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+9
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
··· 137 137 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 138 138 139 139 tmp = mmMMVM_L2_CNTL3_DEFAULT; 140 + if (adev->gmc.translate_further) { 141 + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 142 + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 143 + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 144 + } else { 145 + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 146 + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 147 + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 148 + } 140 149 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 141 150 142 151 tmp = mmMMVM_L2_CNTL4_DEFAULT;
+1
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 254 254 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 255 255 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 256 256 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 257 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 257 258 }; 258 259 259 260 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+12 -7
drivers/gpu/drm/amd/display/dc/calcs/Makefile
··· 24 24 # It calculates Bandwidth and Watermarks values for HW programming 25 25 # 26 26 27 - ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) 28 - cc_stack_align := -mpreferred-stack-boundary=4 29 - else ifneq ($(call cc-option, -mstack-alignment=16),) 30 - cc_stack_align := -mstack-alignment=16 27 + calcs_ccflags := -mhard-float -msse 28 + 29 + ifdef CONFIG_CC_IS_GCC 30 + ifeq ($(call cc-ifversion, -lt, 0701, y), y) 31 + IS_OLD_GCC = 1 32 + endif 31 33 endif 32 34 33 - calcs_ccflags := -mhard-float -msse $(cc_stack_align) 34 - 35 - ifdef CONFIG_CC_IS_CLANG 35 + ifdef IS_OLD_GCC 36 + # Stack alignment mismatch, proceed with caution. 37 + # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 38 + # (8B stack alignment). 39 + calcs_ccflags += -mpreferred-stack-boundary=4 40 + else 36 41 calcs_ccflags += -msse2 37 42 endif 38 43
+4
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 580 580 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 581 581 // Allocate memory for the vm_helper 582 582 dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL); 583 + if (!dc->vm_helper) { 584 + dm_error("%s: failed to create dc->vm_helper\n", __func__); 585 + goto fail; 586 + } 583 587 584 588 #endif 585 589 memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
+9
drivers/gpu/drm/amd/display/dc/core/dc_link.c
··· 2767 2767 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2768 2768 COLOR_DEPTH_UNDEFINED); 2769 2769 2770 + /* This second call is needed to reconfigure the DIG 2771 + * as a workaround for the incorrect value being applied 2772 + * from transmitter control. 2773 + */ 2774 + if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 2775 + stream->link->link_enc->funcs->setup( 2776 + stream->link->link_enc, 2777 + pipe_ctx->stream->signal); 2778 + 2770 2779 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 2771 2780 if (pipe_ctx->stream->timing.flags.DSC) { 2772 2781 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+6
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
··· 404 404 if (stream1->view_format != stream2->view_format) 405 405 return false; 406 406 407 + if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 408 + return false; 409 + 407 410 return true; 408 411 } 409 412 static bool is_dp_and_hdmi_sharable( ··· 1541 1538 { 1542 1539 1543 1540 if (!are_stream_backends_same(old_stream, stream)) 1541 + return false; 1542 + 1543 + if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1544 1544 return false; 1545 1545 1546 1546 return true;
+8 -14
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
··· 393 393 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 394 394 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 395 395 396 + rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red; 397 + rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green; 398 + rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue; 399 + 396 400 // All 3 color channels have same x 397 401 corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2), 398 402 dc_fixpt_from_int(region_start)); ··· 468 464 469 465 i = 1; 470 466 while (i != hw_points + 1) { 471 - if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 472 - rgb_plus_1->red = rgb->red; 473 - if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 474 - rgb_plus_1->green = rgb->green; 475 - if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 476 - rgb_plus_1->blue = rgb->blue; 477 - 478 467 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 479 468 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 480 469 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); ··· 559 562 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 560 563 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 561 564 565 + rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red; 566 + rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green; 567 + rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue; 568 + 562 569 corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2), 563 570 dc_fixpt_from_int(region_start)); 564 571 corner_points[0].green.x = corner_points[0].red.x; ··· 625 624 626 625 i = 1; 627 626 while (i != hw_points + 1) { 628 - if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 629 - rgb_plus_1->red = rgb->red; 630 - if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 631 - rgb_plus_1->green = rgb->green; 632 - if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 633 - rgb_plus_1->blue = rgb->blue; 634 - 635 627 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 636 628 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 637 629 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
+12 -7
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
··· 10 10 DCN20 += dcn20_dsc.o 11 11 endif 12 12 13 - ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) 14 - cc_stack_align := -mpreferred-stack-boundary=4 15 - else ifneq ($(call cc-option, -mstack-alignment=16),) 16 - cc_stack_align := -mstack-alignment=16 13 + CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse 14 + 15 + ifdef CONFIG_CC_IS_GCC 16 + ifeq ($(call cc-ifversion, -lt, 0701, y), y) 17 + IS_OLD_GCC = 1 18 + endif 17 19 endif 18 20 19 - CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse $(cc_stack_align) 20 - 21 - ifdef CONFIG_CC_IS_CLANG 21 + ifdef IS_OLD_GCC 22 + # Stack alignment mismatch, proceed with caution. 23 + # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 24 + # (8B stack alignment). 25 + CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-stack-boundary=4 26 + else 22 27 CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2 23 28 endif 24 29
+1 -1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 814 814 .num_audio = 6, 815 815 .num_stream_encoder = 5, 816 816 .num_pll = 5, 817 - .num_dwb = 0, 817 + .num_dwb = 1, 818 818 .num_ddc = 5, 819 819 }; 820 820
+12 -7
drivers/gpu/drm/amd/display/dc/dcn21/Makefile
··· 3 3 4 4 DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o 5 5 6 - ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) 7 - cc_stack_align := -mpreferred-stack-boundary=4 8 - else ifneq ($(call cc-option, -mstack-alignment=16),) 9 - cc_stack_align := -mstack-alignment=16 6 + CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse 7 + 8 + ifdef CONFIG_CC_IS_GCC 9 + ifeq ($(call cc-ifversion, -lt, 0701, y), y) 10 + IS_OLD_GCC = 1 11 + endif 10 12 endif 11 13 12 - CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse $(cc_stack_align) 13 - 14 - ifdef CONFIG_CC_IS_CLANG 14 + ifdef IS_OLD_GCC 15 + # Stack alignment mismatch, proceed with caution. 16 + # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 17 + # (8B stack alignment). 18 + CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-stack-boundary=4 19 + else 15 20 CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2 16 21 endif 17 22
+12 -7
drivers/gpu/drm/amd/display/dc/dml/Makefile
··· 24 24 # It provides the general basic services required by other DAL 25 25 # subcomponents. 26 26 27 - ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) 28 - cc_stack_align := -mpreferred-stack-boundary=4 29 - else ifneq ($(call cc-option, -mstack-alignment=16),) 30 - cc_stack_align := -mstack-alignment=16 27 + dml_ccflags := -mhard-float -msse 28 + 29 + ifdef CONFIG_CC_IS_GCC 30 + ifeq ($(call cc-ifversion, -lt, 0701, y), y) 31 + IS_OLD_GCC = 1 32 + endif 31 33 endif 32 34 33 - dml_ccflags := -mhard-float -msse $(cc_stack_align) 34 - 35 - ifdef CONFIG_CC_IS_CLANG 35 + ifdef IS_OLD_GCC 36 + # Stack alignment mismatch, proceed with caution. 37 + # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 38 + # (8B stack alignment). 39 + dml_ccflags += -mpreferred-stack-boundary=4 40 + else 36 41 dml_ccflags += -msse2 37 42 endif 38 43
+2 -1
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
··· 2577 2577 mode_lib->vba.MinActiveDRAMClockChangeMargin 2578 2578 + mode_lib->vba.DRAMClockChangeLatency; 2579 2579 2580 - if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) { 2580 + if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) { 2581 + mode_lib->vba.DRAMClockChangeWatermark += 25; 2581 2582 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; 2582 2583 } else { 2583 2584 if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+12 -7
drivers/gpu/drm/amd/display/dc/dsc/Makefile
··· 1 1 # 2 2 # Makefile for the 'dsc' sub-component of DAL. 3 3 4 - ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) 5 - cc_stack_align := -mpreferred-stack-boundary=4 6 - else ifneq ($(call cc-option, -mstack-alignment=16),) 7 - cc_stack_align := -mstack-alignment=16 4 + dsc_ccflags := -mhard-float -msse 5 + 6 + ifdef CONFIG_CC_IS_GCC 7 + ifeq ($(call cc-ifversion, -lt, 0701, y), y) 8 + IS_OLD_GCC = 1 9 + endif 8 10 endif 9 11 10 - dsc_ccflags := -mhard-float -msse $(cc_stack_align) 11 - 12 - ifdef CONFIG_CC_IS_CLANG 12 + ifdef IS_OLD_GCC 13 + # Stack alignment mismatch, proceed with caution. 14 + # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 15 + # (8B stack alignment). 16 + dsc_ccflags += -mpreferred-stack-boundary=4 17 + else 13 18 dsc_ccflags += -msse2 14 19 endif 15 20
+1 -3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
··· 5098 5098 5099 5099 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5100 5100 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 5101 - for (i = 0; i < podn_vdd_dep->count - 1; i++) 5102 - od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; 5103 - if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc) 5101 + for (i = 0; i < podn_vdd_dep->count; i++) 5104 5102 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; 5105 5103 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5106 5104 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
+2 -2
drivers/gpu/drm/etnaviv/etnaviv_dump.c
··· 180 180 etnaviv_cmdbuf_get_va(&submit->cmdbuf, 181 181 &gpu->mmu_context->cmdbuf_mapping)); 182 182 183 + mutex_unlock(&gpu->mmu_context->lock); 184 + 183 185 /* Reserve space for the bomap */ 184 186 if (n_bomap_pages) { 185 187 bomap_start = bomap = iter.data; ··· 222 220 etnaviv_core_dump_header(&iter, ETDUMP_BUF_BO, iter.data + 223 221 obj->base.size); 224 222 } 225 - 226 - mutex_unlock(&gpu->mmu_context->lock); 227 223 228 224 etnaviv_core_dump_header(&iter, ETDUMP_BUF_END, iter.data); 229 225
+4 -2
drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
··· 155 155 156 156 memcpy(buf, v2_context->mtlb_cpu, SZ_4K); 157 157 buf += SZ_4K; 158 - for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++, buf += SZ_4K) 159 - if (v2_context->mtlb_cpu[i] & MMUv2_PTE_PRESENT) 158 + for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) 159 + if (v2_context->mtlb_cpu[i] & MMUv2_PTE_PRESENT) { 160 160 memcpy(buf, v2_context->stlb_cpu[i], SZ_4K); 161 + buf += SZ_4K; 162 + } 161 163 } 162 164 163 165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu,
+14 -3
drivers/gpu/drm/etnaviv/etnaviv_mmu.c
··· 328 328 329 329 ret = etnaviv_cmdbuf_suballoc_map(suballoc, ctx, &ctx->cmdbuf_mapping, 330 330 global->memory_base); 331 - if (ret) { 332 - global->ops->free(ctx); 333 - return NULL; 331 + if (ret) 332 + goto out_free; 333 + 334 + if (global->version == ETNAVIV_IOMMU_V1 && 335 + ctx->cmdbuf_mapping.iova > 0x80000000) { 336 + dev_err(global->dev, 337 + "command buffer outside valid memory window\n"); 338 + goto out_unmap; 334 339 } 335 340 336 341 return ctx; 342 + 343 + out_unmap: 344 + etnaviv_cmdbuf_suballoc_unmap(ctx, &ctx->cmdbuf_mapping); 345 + out_free: 346 + global->ops->free(ctx); 347 + return NULL; 337 348 } 338 349 339 350 void etnaviv_iommu_restore(struct etnaviv_gpu *gpu,
+6 -5
drivers/gpu/drm/i915/display/intel_display.c
··· 9315 9315 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) 9316 9316 { 9317 9317 struct intel_encoder *encoder; 9318 - bool pch_ssc_in_use = false; 9319 9318 bool has_fdi = false; 9320 9319 9321 9320 for_each_intel_encoder(&dev_priv->drm, encoder) { ··· 9342 9343 * clock hierarchy. That would also allow us to do 9343 9344 * clock bending finally. 9344 9345 */ 9346 + dev_priv->pch_ssc_use = 0; 9347 + 9345 9348 if (spll_uses_pch_ssc(dev_priv)) { 9346 9349 DRM_DEBUG_KMS("SPLL using PCH SSC\n"); 9347 - pch_ssc_in_use = true; 9350 + dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); 9348 9351 } 9349 9352 9350 9353 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { 9351 9354 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n"); 9352 - pch_ssc_in_use = true; 9355 + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); 9353 9356 } 9354 9357 9355 9358 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { 9356 9359 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n"); 9357 - pch_ssc_in_use = true; 9360 + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); 9358 9361 } 9359 9362 9360 - if (pch_ssc_in_use) 9363 + if (dev_priv->pch_ssc_use) 9361 9364 return; 9362 9365 9363 9366 if (has_fdi) {
+15
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
··· 525 525 val = I915_READ(WRPLL_CTL(id)); 526 526 I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); 527 527 POSTING_READ(WRPLL_CTL(id)); 528 + 529 + /* 530 + * Try to set up the PCH reference clock once all DPLLs 531 + * that depend on it have been shut down. 532 + */ 533 + if (dev_priv->pch_ssc_use & BIT(id)) 534 + intel_init_pch_refclk(dev_priv); 528 535 } 529 536 530 537 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 531 538 struct intel_shared_dpll *pll) 532 539 { 540 + enum intel_dpll_id id = pll->info->id; 533 541 u32 val; 534 542 535 543 val = I915_READ(SPLL_CTL); 536 544 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 537 545 POSTING_READ(SPLL_CTL); 546 + 547 + /* 548 + * Try to set up the PCH reference clock once all DPLLs 549 + * that depend on it have been shut down. 550 + */ 551 + if (dev_priv->pch_ssc_use & BIT(id)) 552 + intel_init_pch_refclk(dev_priv); 538 553 } 539 554 540 555 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
+2 -2
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
··· 147 147 */ 148 148 DPLL_ID_ICL_MGPLL4 = 6, 149 149 /** 150 - * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5) 150 + * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 151 151 */ 152 152 DPLL_ID_TGL_MGPLL5 = 7, 153 153 /** 154 - * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6) 154 + * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 155 155 */ 156 156 DPLL_ID_TGL_MGPLL6 = 8, 157 157 };
+2
drivers/gpu/drm/i915/i915_drv.h
··· 1723 1723 struct work_struct idle_work; 1724 1724 } gem; 1725 1725 1726 + u8 pch_ssc_use; 1727 + 1726 1728 /* For i945gm vblank irq vs. C3 workaround */ 1727 1729 struct { 1728 1730 struct work_struct work;
+1 -1
drivers/gpu/drm/panfrost/panfrost_drv.c
··· 556 556 return 0; 557 557 558 558 err_out2: 559 + pm_runtime_disable(pfdev->dev); 559 560 panfrost_devfreq_fini(pfdev); 560 561 err_out1: 561 562 panfrost_device_fini(pfdev); 562 563 err_out0: 563 - pm_runtime_disable(pfdev->dev); 564 564 drm_dev_put(ddev); 565 565 return err; 566 566 }
+8 -7
drivers/gpu/drm/panfrost/panfrost_mmu.c
··· 224 224 return SZ_2M; 225 225 } 226 226 227 - void panfrost_mmu_flush_range(struct panfrost_device *pfdev, 228 - struct panfrost_mmu *mmu, 229 - u64 iova, size_t size) 227 + static void panfrost_mmu_flush_range(struct panfrost_device *pfdev, 228 + struct panfrost_mmu *mmu, 229 + u64 iova, size_t size) 230 230 { 231 231 if (mmu->as < 0) 232 232 return; ··· 406 406 spin_lock(&pfdev->as_lock); 407 407 list_for_each_entry(mmu, &pfdev->as_lru_list, list) { 408 408 if (as == mmu->as) 409 - break; 409 + goto found_mmu; 410 410 } 411 - if (as != mmu->as) 412 - goto out; 411 + goto out; 413 412 413 + found_mmu: 414 414 priv = container_of(mmu, struct panfrost_file_priv, mmu); 415 415 416 416 spin_lock(&priv->mm_lock); ··· 432 432 433 433 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE) 434 434 435 - int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, u64 addr) 435 + static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, 436 + u64 addr) 436 437 { 437 438 int ret, i; 438 439 struct panfrost_gem_object *bo;
+1
drivers/gpu/drm/panfrost/panfrost_perfcnt.c
··· 16 16 #include "panfrost_issues.h" 17 17 #include "panfrost_job.h" 18 18 #include "panfrost_mmu.h" 19 + #include "panfrost_perfcnt.h" 19 20 #include "panfrost_regs.h" 20 21 21 22 #define COUNTERS_PER_BLOCK 64
+14
drivers/gpu/drm/radeon/radeon_drv.c
··· 379 379 static void 380 380 radeon_pci_shutdown(struct pci_dev *pdev) 381 381 { 382 + #ifdef CONFIG_PPC64 383 + struct drm_device *ddev = pci_get_drvdata(pdev); 384 + #endif 385 + 382 386 /* if we are running in a VM, make sure the device 383 387 * torn down properly on reboot/shutdown 384 388 */ 385 389 if (radeon_device_is_virtual()) 386 390 radeon_pci_remove(pdev); 391 + 392 + #ifdef CONFIG_PPC64 393 + /* Some adapters need to be suspended before a 394 + * shutdown occurs in order to prevent an error 395 + * during kexec. 396 + * Make this power specific becauase it breaks 397 + * some non-power boards. 398 + */ 399 + radeon_suspend_kms(ddev, true, true, false); 400 + #endif 387 401 } 388 402 389 403 static int radeon_pmops_suspend(struct device *dev)
+16 -3
drivers/gpu/drm/scheduler/sched_main.c
··· 479 479 struct drm_sched_job *s_job, *tmp; 480 480 uint64_t guilty_context; 481 481 bool found_guilty = false; 482 + struct dma_fence *fence; 482 483 483 484 list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { 484 485 struct drm_sched_fence *s_fence = s_job->s_fence; ··· 493 492 dma_fence_set_error(&s_fence->finished, -ECANCELED); 494 493 495 494 dma_fence_put(s_job->s_fence->parent); 496 - s_job->s_fence->parent = sched->ops->run_job(s_job); 495 + fence = sched->ops->run_job(s_job); 496 + 497 + if (IS_ERR_OR_NULL(fence)) { 498 + s_job->s_fence->parent = NULL; 499 + dma_fence_set_error(&s_fence->finished, PTR_ERR(fence)); 500 + } else { 501 + s_job->s_fence->parent = fence; 502 + } 503 + 504 + 497 505 } 498 506 } 499 507 EXPORT_SYMBOL(drm_sched_resubmit_jobs); ··· 730 720 fence = sched->ops->run_job(sched_job); 731 721 drm_sched_fence_scheduled(s_fence); 732 722 733 - if (fence) { 723 + if (!IS_ERR_OR_NULL(fence)) { 734 724 s_fence->parent = dma_fence_get(fence); 735 725 r = dma_fence_add_callback(fence, &sched_job->cb, 736 726 drm_sched_process_job); ··· 740 730 DRM_ERROR("fence add callback failed (%d)\n", 741 731 r); 742 732 dma_fence_put(fence); 743 - } else 733 + } else { 734 + 735 + dma_fence_set_error(&s_fence->finished, PTR_ERR(fence)); 744 736 drm_sched_process_job(NULL, &sched_job->cb); 737 + } 745 738 746 739 wake_up(&sched->job_scheduled); 747 740 }
+4 -1
drivers/gpu/drm/v3d/v3d_gem.c
··· 557 557 558 558 if (args->bcl_start != args->bcl_end) { 559 559 bin = kcalloc(1, sizeof(*bin), GFP_KERNEL); 560 - if (!bin) 560 + if (!bin) { 561 + v3d_job_put(&render->base); 561 562 return -ENOMEM; 563 + } 562 564 563 565 ret = v3d_job_init(v3d, file_priv, &bin->base, 564 566 v3d_job_free, args->in_sync_bcl); 565 567 if (ret) { 566 568 v3d_job_put(&render->base); 569 + kfree(bin); 567 570 return ret; 568 571 } 569 572