tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"Here's a long-pending fixes pull request for arm-soc (I didn't send
one in the -rc4 cycle).

The larger deltas are from:

- A fixup of error paths in the mvsdio driver

- Header file move for a driver that hadn't been properly converted
to multiplatform on i.MX, which was causing build failures when
included

- Device tree updates for at91 dealing mostly with their new pinctrl
setup merged in 3.8 and mistakes in those initial configs

The rest are the normal mix of small fixes all over the place; sunxi,
omap, imx, mvebu, etc, etc."

* tag 'fixes-for-linus2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (40 commits)
mfd: vexpress-sysreg: Don't skip initialization on probe
ARM: vexpress: Enable A7 cores in V2P-CA15_A7's Device Tree
ARM: vexpress: extend the MPIDR range used for pen release check
ARM: at91/dts: correct comment in at91sam9x5.dtsi for mii
ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfig
ARM: at91/at91_dt_defconfig: remove memory specification to cmdline
ARM: at91/dts: add macb mii pinctrl config for kizbox
ARM: at91: rm9200: remake the BGA as default version
ARM: at91: fix gpios on i2c-gpio for RM9200 DT
ARM: at91/at91sam9x5 DTS: add SCK USART pins
ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts
ARM: at91/at91-pinctrl documentation: fix typo and add some details
ARM: kirkwood: fix missing #interrupt-cells property
mmc: mvsdio: use devm_ API to simplify/correct error paths.
clk: mvebu/clk-cpu.c: fix memory leakage
ARM: OMAP2+: omap4-panda: add UART2 muxing for WiLink shared transport
ARM: OMAP2+: DT node Timer iteration fix
ARM: OMAP2+: Fix section warning for omap_init_ocp2scp()
ARM: OMAP2+: fix build break for omapdrm
ARM: OMAP2: Fix missing omap2xxx_clkt_vps_late_init function calls
...

Linus Torvalds 1496ec13 ba2ab41f

+248 -220
+3 -2
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
··· 81 81 Required properties for pin configuration node: 82 82 - atmel,pins: 4 integers array, represents a group of pins mux and config 83 83 setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. 84 - The PERIPH 0 means gpio. 84 + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... 85 + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... 85 86 86 87 Bits used for CONFIG: 87 88 PULL_UP (1 << 0): indicate this pin need a pull up. ··· 127 126 pinctrl_dbgu: dbgu-0 { 128 127 atmel,pins = 129 128 <1 14 0x1 0x0 /* PB14 periph A */ 130 - 1 15 0x1 0x1>; /* PB15 periph with pullup */ 129 + 1 15 0x1 0x1>; /* PB15 periph A with pullup */ 131 130 }; 132 131 }; 133 132 };
+1 -1
arch/arm/boot/dts/armada-370-db.dts
··· 26 26 27 27 memory { 28 28 device_type = "memory"; 29 - reg = <0x00000000 0x20000000>; /* 512 MB */ 29 + reg = <0x00000000 0x40000000>; /* 1 GB */ 30 30 }; 31 31 32 32 soc {
+6 -8
arch/arm/boot/dts/armada-xp-mv78230.dtsi
··· 50 50 }; 51 51 52 52 gpio0: gpio@d0018100 { 53 - compatible = "marvell,armadaxp-gpio"; 54 - reg = <0xd0018100 0x40>, 55 - <0xd0018800 0x30>; 53 + compatible = "marvell,orion-gpio"; 54 + reg = <0xd0018100 0x40>; 56 55 ngpios = <32>; 57 56 gpio-controller; 58 57 #gpio-cells = <2>; 59 58 interrupt-controller; 60 59 #interrupts-cells = <2>; 61 - interrupts = <16>, <17>, <18>, <19>; 60 + interrupts = <82>, <83>, <84>, <85>; 62 61 }; 63 62 64 63 gpio1: gpio@d0018140 { 65 - compatible = "marvell,armadaxp-gpio"; 66 - reg = <0xd0018140 0x40>, 67 - <0xd0018840 0x30>; 64 + compatible = "marvell,orion-gpio"; 65 + reg = <0xd0018140 0x40>; 68 66 ngpios = <17>; 69 67 gpio-controller; 70 68 #gpio-cells = <2>; 71 69 interrupt-controller; 72 70 #interrupts-cells = <2>; 73 - interrupts = <20>, <21>, <22>; 71 + interrupts = <87>, <88>, <89>; 74 72 }; 75 73 }; 76 74 };
+9 -12
arch/arm/boot/dts/armada-xp-mv78260.dtsi
··· 51 51 }; 52 52 53 53 gpio0: gpio@d0018100 { 54 - compatible = "marvell,armadaxp-gpio"; 55 - reg = <0xd0018100 0x40>, 56 - <0xd0018800 0x30>; 54 + compatible = "marvell,orion-gpio"; 55 + reg = <0xd0018100 0x40>; 57 56 ngpios = <32>; 58 57 gpio-controller; 59 58 #gpio-cells = <2>; 60 59 interrupt-controller; 61 60 #interrupts-cells = <2>; 62 - interrupts = <16>, <17>, <18>, <19>; 61 + interrupts = <82>, <83>, <84>, <85>; 63 62 }; 64 63 65 64 gpio1: gpio@d0018140 { 66 - compatible = "marvell,armadaxp-gpio"; 67 - reg = <0xd0018140 0x40>, 68 - <0xd0018840 0x30>; 65 + compatible = "marvell,orion-gpio"; 66 + reg = <0xd0018140 0x40>; 69 67 ngpios = <32>; 70 68 gpio-controller; 71 69 #gpio-cells = <2>; 72 70 interrupt-controller; 73 71 #interrupts-cells = <2>; 74 - interrupts = <20>, <21>, <22>, <23>; 72 + interrupts = <87>, <88>, <89>, <90>; 75 73 }; 76 74 77 75 gpio2: gpio@d0018180 { 78 - compatible = "marvell,armadaxp-gpio"; 79 - reg = <0xd0018180 0x40>, 80 - <0xd0018870 0x30>; 76 + compatible = "marvell,orion-gpio"; 77 + reg = <0xd0018180 0x40>; 81 78 ngpios = <3>; 82 79 gpio-controller; 83 80 #gpio-cells = <2>; 84 81 interrupt-controller; 85 82 #interrupts-cells = <2>; 86 - interrupts = <24>; 83 + interrupts = <91>; 87 84 }; 88 85 89 86 ethernet@d0034000 {
+9 -12
arch/arm/boot/dts/armada-xp-mv78460.dtsi
··· 66 66 }; 67 67 68 68 gpio0: gpio@d0018100 { 69 - compatible = "marvell,armadaxp-gpio"; 70 - reg = <0xd0018100 0x40>, 71 - <0xd0018800 0x30>; 69 + compatible = "marvell,orion-gpio"; 70 + reg = <0xd0018100 0x40>; 72 71 ngpios = <32>; 73 72 gpio-controller; 74 73 #gpio-cells = <2>; 75 74 interrupt-controller; 76 75 #interrupts-cells = <2>; 77 - interrupts = <16>, <17>, <18>, <19>; 76 + interrupts = <82>, <83>, <84>, <85>; 78 77 }; 79 78 80 79 gpio1: gpio@d0018140 { 81 - compatible = "marvell,armadaxp-gpio"; 82 - reg = <0xd0018140 0x40>, 83 - <0xd0018840 0x30>; 80 + compatible = "marvell,orion-gpio"; 81 + reg = <0xd0018140 0x40>; 84 82 ngpios = <32>; 85 83 gpio-controller; 86 84 #gpio-cells = <2>; 87 85 interrupt-controller; 88 86 #interrupts-cells = <2>; 89 - interrupts = <20>, <21>, <22>, <23>; 87 + interrupts = <87>, <88>, <89>, <90>; 90 88 }; 91 89 92 90 gpio2: gpio@d0018180 { 93 - compatible = "marvell,armadaxp-gpio"; 94 - reg = <0xd0018180 0x40>, 95 - <0xd0018870 0x30>; 91 + compatible = "marvell,orion-gpio"; 92 + reg = <0xd0018180 0x40>; 96 93 ngpios = <3>; 97 94 gpio-controller; 98 95 #gpio-cells = <2>; 99 96 interrupt-controller; 100 97 #interrupts-cells = <2>; 101 - interrupts = <24>; 98 + interrupts = <91>; 102 99 }; 103 100 104 101 ethernet@d0034000 {
+2 -2
arch/arm/boot/dts/at91rm9200.dtsi
··· 336 336 337 337 i2c@0 { 338 338 compatible = "i2c-gpio"; 339 - gpios = <&pioA 23 0 /* sda */ 340 - &pioA 24 0 /* scl */ 339 + gpios = <&pioA 25 0 /* sda */ 340 + &pioA 26 0 /* scl */ 341 341 >; 342 342 i2c-gpio,sda-open-drain; 343 343 i2c-gpio,scl-open-drain;
+40 -20
arch/arm/boot/dts/at91sam9x5.dtsi
··· 143 143 atmel,pins = 144 144 <0 3 0x1 0x0>; /* PA3 periph A */ 145 145 }; 146 + 147 + pinctrl_usart0_sck: usart0_sck-0 { 148 + atmel,pins = 149 + <0 4 0x1 0x0>; /* PA4 periph A */ 150 + }; 146 151 }; 147 152 148 153 usart1 { ··· 159 154 160 155 pinctrl_usart1_rts: usart1_rts-0 { 161 156 atmel,pins = 162 - <3 27 0x3 0x0>; /* PC27 periph C */ 157 + <2 27 0x3 0x0>; /* PC27 periph C */ 163 158 }; 164 159 165 160 pinctrl_usart1_cts: usart1_cts-0 { 166 161 atmel,pins = 167 - <3 28 0x3 0x0>; /* PC28 periph C */ 162 + <2 28 0x3 0x0>; /* PC28 periph C */ 163 + }; 164 + 165 + pinctrl_usart1_sck: usart1_sck-0 { 166 + atmel,pins = 167 + <2 28 0x3 0x0>; /* PC29 periph C */ 168 168 }; 169 169 }; 170 170 ··· 182 172 183 173 pinctrl_uart2_rts: uart2_rts-0 { 184 174 atmel,pins = 185 - <0 0 0x2 0x0>; /* PB0 periph B */ 175 + <1 0 0x2 0x0>; /* PB0 periph B */ 186 176 }; 187 177 188 178 pinctrl_uart2_cts: uart2_cts-0 { 189 179 atmel,pins = 190 - <0 1 0x2 0x0>; /* PB1 periph B */ 180 + <1 1 0x2 0x0>; /* PB1 periph B */ 181 + }; 182 + 183 + pinctrl_usart2_sck: usart2_sck-0 { 184 + atmel,pins = 185 + <1 2 0x2 0x0>; /* PB2 periph B */ 191 186 }; 192 187 }; 193 188 194 189 usart3 { 195 190 pinctrl_uart3: usart3-0 { 196 191 atmel,pins = 197 - <3 23 0x2 0x1 /* PC22 periph B with pullup */ 198 - 3 23 0x2 0x0>; /* PC23 periph B */ 192 + <2 23 0x2 0x1 /* PC22 periph B with pullup */ 193 + 2 23 0x2 0x0>; /* PC23 periph B */ 199 194 }; 200 195 201 196 pinctrl_usart3_rts: usart3_rts-0 { 202 197 atmel,pins = 203 - <3 24 0x2 0x0>; /* PC24 periph B */ 198 + <2 24 0x2 0x0>; /* PC24 periph B */ 204 199 }; 205 200 206 201 pinctrl_usart3_cts: usart3_cts-0 { 207 202 atmel,pins = 208 - <3 25 0x2 0x0>; /* PC25 periph B */ 203 + <2 25 0x2 0x0>; /* PC25 periph B */ 204 + }; 205 + 206 + pinctrl_usart3_sck: usart3_sck-0 { 207 + atmel,pins = 208 + <2 26 0x2 0x0>; /* PC26 periph B */ 209 209 }; 210 210 }; 211 211 212 212 uart0 { 213 213 pinctrl_uart0: uart0-0 { 214 214 atmel,pins = 215 - <3 8 0x3 0x0 /* PC8 periph C */ 216 - 3 9 0x3 0x1>; /* PC9 periph C with pullup */ 215 + <2 8 0x3 0x0 /* PC8 periph C */ 216 + 2 9 0x3 0x1>; /* PC9 periph C with pullup */ 217 217 }; 218 218 }; 219 219 220 220 uart1 { 221 221 pinctrl_uart1: uart1-0 { 222 222 atmel,pins = 223 - <3 16 0x3 0x0 /* PC16 periph C */ 224 - 3 17 0x3 0x1>; /* PC17 periph C with pullup */ 223 + <2 16 0x3 0x0 /* PC16 periph C */ 224 + 2 17 0x3 0x1>; /* PC17 periph C with pullup */ 225 225 }; 226 226 }; 227 227 ··· 260 240 261 241 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { 262 242 atmel,pins = 263 - <1 8 0x1 0x0 /* PA8 periph A */ 264 - 1 11 0x1 0x0 /* PA11 periph A */ 265 - 1 12 0x1 0x0 /* PA12 periph A */ 266 - 1 13 0x1 0x0 /* PA13 periph A */ 267 - 1 14 0x1 0x0 /* PA14 periph A */ 268 - 1 15 0x1 0x0 /* PA15 periph A */ 269 - 1 16 0x1 0x0 /* PA16 periph A */ 270 - 1 17 0x1 0x0>; /* PA17 periph A */ 243 + <1 8 0x1 0x0 /* PB8 periph A */ 244 + 1 11 0x1 0x0 /* PB11 periph A */ 245 + 1 12 0x1 0x0 /* PB12 periph A */ 246 + 1 13 0x1 0x0 /* PB13 periph A */ 247 + 1 14 0x1 0x0 /* PB14 periph A */ 248 + 1 15 0x1 0x0 /* PB15 periph A */ 249 + 1 16 0x1 0x0 /* PB16 periph A */ 250 + 1 17 0x1 0x0>; /* PB17 periph A */ 271 251 }; 272 252 }; 273 253
+6 -6
arch/arm/boot/dts/cros5250-common.dtsi
··· 96 96 fifo-depth = <0x80>; 97 97 card-detect-delay = <200>; 98 98 samsung,dw-mshc-ciu-div = <3>; 99 - samsung,dw-mshc-sdr-timing = <2 3 3>; 100 - samsung,dw-mshc-ddr-timing = <1 2 3>; 99 + samsung,dw-mshc-sdr-timing = <2 3>; 100 + samsung,dw-mshc-ddr-timing = <1 2>; 101 101 102 102 slot@0 { 103 103 reg = <0>; ··· 120 120 fifo-depth = <0x80>; 121 121 card-detect-delay = <200>; 122 122 samsung,dw-mshc-ciu-div = <3>; 123 - samsung,dw-mshc-sdr-timing = <2 3 3>; 124 - samsung,dw-mshc-ddr-timing = <1 2 3>; 123 + samsung,dw-mshc-sdr-timing = <2 3>; 124 + samsung,dw-mshc-ddr-timing = <1 2>; 125 125 126 126 slot@0 { 127 127 reg = <0>; ··· 141 141 fifo-depth = <0x80>; 142 142 card-detect-delay = <200>; 143 143 samsung,dw-mshc-ciu-div = <3>; 144 - samsung,dw-mshc-sdr-timing = <2 3 3>; 145 - samsung,dw-mshc-ddr-timing = <1 2 3>; 144 + samsung,dw-mshc-sdr-timing = <2 3>; 145 + samsung,dw-mshc-ddr-timing = <1 2>; 146 146 147 147 slot@0 { 148 148 reg = <0>;
+12 -2
arch/arm/boot/dts/dove-cubox.dts
··· 26 26 }; 27 27 28 28 &uart0 { status = "okay"; }; 29 - &sdio0 { status = "okay"; }; 30 29 &sata0 { status = "okay"; }; 31 30 &i2c0 { status = "okay"; }; 31 + 32 + &sdio0 { 33 + status = "okay"; 34 + /* sdio0 card detect is connected to wrong pin on CuBox */ 35 + cd-gpios = <&gpio0 12 1>; 36 + }; 32 37 33 38 &spi0 { 34 39 status = "okay"; ··· 47 42 }; 48 43 49 44 &pinctrl { 50 - pinctrl-0 = <&pmx_gpio_18>; 45 + pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>; 51 46 pinctrl-names = "default"; 47 + 48 + pmx_gpio_12: pmx-gpio-12 { 49 + marvell,pins = "mpp12"; 50 + marvell,function = "gpio"; 51 + }; 52 52 53 53 pmx_gpio_18: pmx-gpio-18 { 54 54 marvell,pins = "mpp18";
+4 -4
arch/arm/boot/dts/exynos5250-smdk5250.dts
··· 115 115 fifo-depth = <0x80>; 116 116 card-detect-delay = <200>; 117 117 samsung,dw-mshc-ciu-div = <3>; 118 - samsung,dw-mshc-sdr-timing = <2 3 3>; 119 - samsung,dw-mshc-ddr-timing = <1 2 3>; 118 + samsung,dw-mshc-sdr-timing = <2 3>; 119 + samsung,dw-mshc-ddr-timing = <1 2>; 120 120 121 121 slot@0 { 122 122 reg = <0>; ··· 139 139 fifo-depth = <0x80>; 140 140 card-detect-delay = <200>; 141 141 samsung,dw-mshc-ciu-div = <3>; 142 - samsung,dw-mshc-sdr-timing = <2 3 3>; 143 - samsung,dw-mshc-ddr-timing = <1 2 3>; 142 + samsung,dw-mshc-sdr-timing = <2 3>; 143 + samsung,dw-mshc-ddr-timing = <1 2>; 144 144 145 145 slot@0 { 146 146 reg = <0>;
+16
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
··· 1 1 /include/ "kirkwood.dtsi" 2 + /include/ "kirkwood-6281.dtsi" 2 3 3 4 / { 4 5 chosen { ··· 7 6 }; 8 7 9 8 ocp@f1000000 { 9 + pinctrl: pinctrl@10000 { 10 + pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0 11 + &pmx_ns2_sata0 &pmx_ns2_sata1>; 12 + pinctrl-names = "default"; 13 + 14 + pmx_ns2_sata0: pmx-ns2-sata0 { 15 + marvell,pins = "mpp21"; 16 + marvell,function = "sata0"; 17 + }; 18 + pmx_ns2_sata1: pmx-ns2-sata1 { 19 + marvell,pins = "mpp20"; 20 + marvell,function = "sata1"; 21 + }; 22 + }; 23 + 10 24 serial@12000 { 11 25 clock-frequency = <166666667>; 12 26 status = "okay";
+2
arch/arm/boot/dts/kirkwood.dtsi
··· 36 36 reg = <0x10100 0x40>; 37 37 ngpios = <32>; 38 38 interrupt-controller; 39 + #interrupt-cells = <2>; 39 40 interrupts = <35>, <36>, <37>, <38>; 40 41 }; 41 42 ··· 47 46 reg = <0x10140 0x40>; 48 47 ngpios = <18>; 49 48 interrupt-controller; 49 + #interrupt-cells = <2>; 50 50 interrupts = <39>, <40>, <41>; 51 51 }; 52 52
+2
arch/arm/boot/dts/kizbox.dts
··· 48 48 49 49 macb0: ethernet@fffc4000 { 50 50 phy-mode = "mii"; 51 + pinctrl-0 = <&pinctrl_macb_rmii 52 + &pinctrl_macb_rmii_mii_alt>; 51 53 status = "okay"; 52 54 }; 53 55
+4 -2
arch/arm/boot/dts/sunxi.dtsi
··· 60 60 }; 61 61 62 62 uart0: uart@01c28000 { 63 - compatible = "ns8250"; 63 + compatible = "snps,dw-apb-uart"; 64 64 reg = <0x01c28000 0x400>; 65 65 interrupts = <1>; 66 66 reg-shift = <2>; 67 + reg-io-width = <4>; 67 68 clock-frequency = <24000000>; 68 69 status = "disabled"; 69 70 }; 70 71 71 72 uart1: uart@01c28400 { 72 - compatible = "ns8250"; 73 + compatible = "snps,dw-apb-uart"; 73 74 reg = <0x01c28400 0x400>; 74 75 interrupts = <2>; 75 76 reg-shift = <2>; 77 + reg-io-width = <4>; 76 78 clock-frequency = <24000000>; 77 79 status = "disabled"; 78 80 };
-2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
··· 45 45 reg = <1>; 46 46 }; 47 47 48 - /* A7s disabled till big.LITTLE patches are available... 49 48 cpu2: cpu@2 { 50 49 device_type = "cpu"; 51 50 compatible = "arm,cortex-a7"; ··· 62 63 compatible = "arm,cortex-a7"; 63 64 reg = <0x102>; 64 65 }; 65 - */ 66 66 }; 67 67 68 68 memory@80000000 {
+2 -1
arch/arm/configs/at91_dt_defconfig
··· 19 19 CONFIG_SOC_AT91SAM9263=y 20 20 CONFIG_SOC_AT91SAM9G45=y 21 21 CONFIG_SOC_AT91SAM9X5=y 22 + CONFIG_SOC_AT91SAM9N12=y 22 23 CONFIG_MACH_AT91SAM_DT=y 23 24 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 24 25 CONFIG_AT91_TIMER_HZ=128 ··· 32 31 CONFIG_ZBOOT_ROM_BSS=0x0 33 32 CONFIG_ARM_APPENDED_DTB=y 34 33 CONFIG_ARM_ATAG_DTB_COMPAT=y 35 - CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" 34 + CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" 36 35 CONFIG_KEXEC=y 37 36 CONFIG_AUTO_ZRELADDR=y 38 37 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+2
arch/arm/kernel/debug.S
··· 100 100 b 1b 101 101 ENDPROC(printch) 102 102 103 + #ifdef CONFIG_MMU 103 104 ENTRY(debug_ll_addr) 104 105 addruart r2, r3, ip 105 106 str r2, [r0] 106 107 str r3, [r1] 107 108 mov pc, lr 108 109 ENDPROC(debug_ll_addr) 110 + #endif 109 111 110 112 #else 111 113
+2
arch/arm/mach-at91/setup.c
··· 105 105 switch (socid) { 106 106 case ARCH_ID_AT91RM9200: 107 107 at91_soc_initdata.type = AT91_SOC_RM9200; 108 + if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) 109 + at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; 108 110 at91_boot_soc = at91rm9200_soc; 109 111 break; 110 112
+1
arch/arm/mach-imx/Kconfig
··· 851 851 select HAVE_CAN_FLEXCAN if CAN 852 852 select HAVE_IMX_GPC 853 853 select HAVE_IMX_MMDC 854 + select HAVE_IMX_SRC 854 855 select HAVE_SMP 855 856 select MFD_SYSCON 856 857 select PINCTRL
+3
arch/arm/mach-imx/clk-imx6q.c
··· 436 436 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 437 437 clk_prepare_enable(clk[clks_init_on[i]]); 438 438 439 + /* Set initial power mode */ 440 + imx6q_set_lpm(WAIT_CLOCKED); 441 + 439 442 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 440 443 base = of_iomap(np, 0); 441 444 WARN_ON(!base);
+1
arch/arm/mach-imx/common.h
··· 142 142 extern void imx6q_clock_map_io(void); 143 143 144 144 extern void imx_cpu_die(unsigned int cpu); 145 + extern int imx_cpu_kill(unsigned int cpu); 145 146 146 147 #ifdef CONFIG_PM 147 148 extern void imx6q_pm_init(void);
+1 -1
arch/arm/mach-imx/devices/platform-imx-fb.c
··· 54 54 .flags = IORESOURCE_IRQ, 55 55 }, 56 56 }; 57 - return imx_add_platform_device_dmamask("imx-fb", 0, 57 + return imx_add_platform_device_dmamask(data->devid, 0, 58 58 res, ARRAY_SIZE(res), 59 59 pdata, sizeof(*pdata), DMA_BIT_MASK(32)); 60 60 }
+6 -4
arch/arm/mach-imx/hotplug.c
··· 46 46 void imx_cpu_die(unsigned int cpu) 47 47 { 48 48 cpu_enter_lowpower(); 49 - imx_enable_cpu(cpu, false); 49 + cpu_do_idle(); 50 + } 50 51 51 - /* spin here until hardware takes it down */ 52 - while (1) 53 - ; 52 + int imx_cpu_kill(unsigned int cpu) 53 + { 54 + imx_enable_cpu(cpu, false); 55 + return 1; 54 56 }
arch/arm/mach-imx/iram.h include/linux/platform_data/imx-iram.h
+1 -2
arch/arm/mach-imx/iram_alloc.c
··· 22 22 #include <linux/module.h> 23 23 #include <linux/spinlock.h> 24 24 #include <linux/genalloc.h> 25 - 26 - #include "iram.h" 25 + #include "linux/platform_data/imx-iram.h" 27 26 28 27 static unsigned long iram_phys_base; 29 28 static void __iomem *iram_virt_base;
+1
arch/arm/mach-imx/platsmp.c
··· 92 92 .smp_boot_secondary = imx_boot_secondary, 93 93 #ifdef CONFIG_HOTPLUG_CPU 94 94 .cpu_die = imx_cpu_die, 95 + .cpu_kill = imx_cpu_kill, 95 96 #endif 96 97 };
+1
arch/arm/mach-imx/pm-imx6q.c
··· 41 41 cpu_suspend(0, imx6q_suspend_finish); 42 42 imx_smp_prepare(); 43 43 imx_gpc_post_resume(); 44 + imx6q_set_lpm(WAIT_CLOCKED); 44 45 break; 45 46 default: 46 47 return -EINVAL;
+10 -4
arch/arm/mach-integrator/pci_v3.c
··· 475 475 { 476 476 int ret = 0; 477 477 478 + if (!ap_syscon_base) 479 + return -EINVAL; 480 + 478 481 if (nr == 0) { 479 482 sys->mem_offset = PHYS_PCI_MEM_BASE; 480 483 ret = pci_v3_setup_resources(sys); 481 - /* Remap the Integrator system controller */ 482 - ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); 483 - if (!ap_syscon_base) 484 - return -EINVAL; 485 484 } 486 485 487 486 return ret; ··· 495 496 unsigned long flags; 496 497 unsigned int temp; 497 498 int ret; 499 + 500 + /* Remap the Integrator system controller */ 501 + ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); 502 + if (!ap_syscon_base) { 503 + pr_err("unable to remap the AP syscon for PCIv3\n"); 504 + return; 505 + } 498 506 499 507 pcibios_min_mem = 0x00100000; 500 508
-38
arch/arm/mach-kirkwood/board-ns2.c
··· 18 18 #include <linux/gpio.h> 19 19 #include <linux/of.h> 20 20 #include "common.h" 21 - #include "mpp.h" 22 21 23 22 static struct mv643xx_eth_platform_data ns2_ge00_data = { 24 23 .phy_addr = MV643XX_ETH_PHY_ADDR(8), 25 - }; 26 - 27 - static unsigned int ns2_mpp_config[] __initdata = { 28 - MPP0_SPI_SCn, 29 - MPP1_SPI_MOSI, 30 - MPP2_SPI_SCK, 31 - MPP3_SPI_MISO, 32 - MPP4_NF_IO6, 33 - MPP5_NF_IO7, 34 - MPP6_SYSRST_OUTn, 35 - MPP7_GPO, /* Fan speed (bit 1) */ 36 - MPP8_TW0_SDA, 37 - MPP9_TW0_SCK, 38 - MPP10_UART0_TXD, 39 - MPP11_UART0_RXD, 40 - MPP12_GPO, /* Red led */ 41 - MPP14_GPIO, /* USB fuse */ 42 - MPP16_GPIO, /* SATA 0 power */ 43 - MPP17_GPIO, /* SATA 1 power */ 44 - MPP18_NF_IO0, 45 - MPP19_NF_IO1, 46 - MPP20_SATA1_ACTn, 47 - MPP21_SATA0_ACTn, 48 - MPP22_GPIO, /* Fan speed (bit 0) */ 49 - MPP23_GPIO, /* Fan power */ 50 - MPP24_GPIO, /* USB mode select */ 51 - MPP25_GPIO, /* Fan rotation fail */ 52 - MPP26_GPIO, /* USB device vbus */ 53 - MPP28_GPIO, /* USB enable host vbus */ 54 - MPP29_GPIO, /* Blue led (slow register) */ 55 - MPP30_GPIO, /* Blue led (command register) */ 56 - MPP31_GPIO, /* Board power off */ 57 - MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ 58 - MPP33_GPO, /* Fan speed (bit 2) */ 59 - 0 60 24 }; 61 25 62 26 #define NS2_GPIO_POWER_OFF 31 ··· 35 71 /* 36 72 * Basic setup. Needs to be called early. 37 73 */ 38 - kirkwood_mpp_conf(ns2_mpp_config); 39 - 40 74 if (of_machine_is_compatible("lacie,netspace_lite_v2") || 41 75 of_machine_is_compatible("lacie,netspace_mini_v2")) 42 76 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+2
arch/arm/mach-mvebu/Makefile
··· 1 1 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ 2 2 -I$(srctree)/arch/arm/plat-orion/include 3 3 4 + AFLAGS_coherency_ll.o := -Wa,-march=armv7-a 5 + 4 6 obj-y += system-controller.o 5 7 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o 6 8 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+6
arch/arm/mach-omap2/board-omap4panda.c
··· 397 397 OMAP_PULL_ENA), 398 398 OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), 399 399 400 + /* UART2 - BT/FM/GPS shared transport */ 401 + OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0), 402 + OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), 403 + OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0), 404 + OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), 405 + 400 406 { .reg_offset = OMAP_MUX_TERMINATOR }, 401 407 }; 402 408
+2
arch/arm/mach-omap2/cclock2420_data.c
··· 1935 1935 omap2_init_clk_hw_omap_clocks(c->lk.clk); 1936 1936 } 1937 1937 1938 + omap2xxx_clkt_vps_late_init(); 1939 + 1938 1940 omap2_clk_disable_autoidle_all(); 1939 1941 1940 1942 omap2_clk_enable_init_clocks(enable_init_clks,
+2
arch/arm/mach-omap2/cclock2430_data.c
··· 2050 2050 omap2_init_clk_hw_omap_clocks(c->lk.clk); 2051 2051 } 2052 2052 2053 + omap2xxx_clkt_vps_late_init(); 2054 + 2053 2055 omap2_clk_disable_autoidle_all(); 2054 2056 2055 2057 omap2_clk_enable_init_clocks(enable_init_clks,
+6 -7
arch/arm/mach-omap2/cclock44xx_data.c
··· 2026 2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 2027 2027 * state when turning the ABE clock domain. Workaround this by 2028 2028 * locking the ABE DPLL on boot. 2029 + * Lock the ABE DPLL in any case to avoid issues with audio. 2029 2030 */ 2030 - if (cpu_is_omap446x()) { 2031 - rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); 2032 - if (!rc) 2033 - rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); 2034 - if (rc) 2035 - pr_err("%s: failed to configure ABE DPLL!\n", __func__); 2036 - } 2031 + rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); 2032 + if (!rc) 2033 + rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); 2034 + if (rc) 2035 + pr_err("%s: failed to configure ABE DPLL!\n", __func__); 2037 2036 2038 2037 return 0; 2039 2038 }
+1 -1
arch/arm/mach-omap2/devices.c
··· 639 639 return cnt; 640 640 } 641 641 642 - static void omap_init_ocp2scp(void) 642 + static void __init omap_init_ocp2scp(void) 643 643 { 644 644 struct omap_hwmod *oh; 645 645 struct platform_device *pdev;
+2 -1
arch/arm/mach-omap2/drm.c
··· 25 25 #include <linux/dma-mapping.h> 26 26 #include <linux/platform_data/omap_drm.h> 27 27 28 + #include "soc.h" 28 29 #include "omap_device.h" 29 30 #include "omap_hwmod.h" 30 31 ··· 57 56 oh->name); 58 57 } 59 58 60 - platform_data.omaprev = GET_OMAP_REVISION(); 59 + platform_data.omaprev = GET_OMAP_TYPE; 61 60 62 61 return platform_device_register(&omap_drm_device); 63 62
+5 -1
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
··· 2132 2132 * currently reset very early during boot, before I2C is 2133 2133 * available, so it doesn't seem that we have any choice in 2134 2134 * the kernel other than to avoid resetting it. 2135 + * 2136 + * Also, McPDM needs to be configured to NO_IDLE mode when it 2137 + * is in used otherwise vital clocks will be gated which 2138 + * results 'slow motion' audio playback. 2135 2139 */ 2136 - .flags = HWMOD_EXT_OPT_MAIN_CLK, 2140 + .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, 2137 2141 .mpu_irqs = omap44xx_mcpdm_irqs, 2138 2142 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 2139 2143 .main_clk = "mcpdm_fck",
+2 -6
arch/arm/mach-omap2/timer.c
··· 165 165 struct device_node *np; 166 166 167 167 for_each_matching_node(np, match) { 168 - if (!of_device_is_available(np)) { 169 - of_node_put(np); 168 + if (!of_device_is_available(np)) 170 169 continue; 171 - } 172 170 173 - if (property && !of_get_property(np, property, NULL)) { 174 - of_node_put(np); 171 + if (property && !of_get_property(np, property, NULL)) 175 172 continue; 176 - } 177 173 178 174 of_add_property(np, &device_disabled); 179 175 return np;
+1 -1
arch/arm/mach-s3c64xx/mach-crag6410-module.c
··· 47 47 .bus_num = 0, 48 48 .chip_select = 0, 49 49 .mode = SPI_MODE_0, 50 - .irq = S3C_EINT(5), 50 + .irq = S3C_EINT(4), 51 51 .controller_data = &wm0010_spi_csinfo, 52 52 .platform_data = &wm0010_pdata, 53 53 },
+2
arch/arm/mach-s3c64xx/pm.c
··· 338 338 for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) 339 339 pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); 340 340 341 + #ifdef CONFIG_S3C_DEV_FB 341 342 if (dev_get_platdata(&s3c_device_fb.dev)) 342 343 pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev); 344 + #endif 343 345 344 346 return 0; 345 347 }
+1 -1
arch/arm/plat-versatile/headsmp.S
··· 20 20 */ 21 21 ENTRY(versatile_secondary_startup) 22 22 mrc p15, 0, r0, c0, c0, 5 23 - and r0, r0, #15 23 + bic r0, #0xff000000 24 24 adr r4, 1f 25 25 ldmia r4, {r5, r6} 26 26 sub r4, r4, r5
+6 -3
drivers/clk/mvebu/clk-cpu.c
··· 124 124 125 125 clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL); 126 126 if (WARN_ON(!clks)) 127 - return; 127 + goto clks_out; 128 128 129 129 for_each_node_by_type(dn, "cpu") { 130 130 struct clk_init_data init; ··· 134 134 int cpu, err; 135 135 136 136 if (WARN_ON(!clk_name)) 137 - return; 137 + goto bail_out; 138 138 139 139 err = of_property_read_u32(dn, "reg", &cpu); 140 140 if (WARN_ON(err)) 141 - return; 141 + goto bail_out; 142 142 143 143 sprintf(clk_name, "cpu%d", cpu); 144 144 parent_clk = of_clk_get(node, 0); ··· 167 167 return; 168 168 bail_out: 169 169 kfree(clks); 170 + while(ncpus--) 171 + kfree(cpuclk[ncpus].clk_name); 172 + clks_out: 170 173 kfree(cpuclk); 171 174 } 172 175
+1 -1
drivers/media/platform/coda.c
··· 23 23 #include <linux/slab.h> 24 24 #include <linux/videodev2.h> 25 25 #include <linux/of.h> 26 + #include <linux/platform_data/imx-iram.h> 26 27 27 - #include <mach/iram.h> 28 28 #include <media/v4l2-ctrls.h> 29 29 #include <media/v4l2-device.h> 30 30 #include <media/v4l2-ioctl.h>
+20 -12
drivers/mfd/vexpress-sysreg.c
··· 313 313 } 314 314 315 315 316 - void __init vexpress_sysreg_early_init(void __iomem *base) 316 + void __init vexpress_sysreg_setup(struct device_node *node) 317 317 { 318 - struct device_node *node = of_find_compatible_node(NULL, NULL, 319 - "arm,vexpress-sysreg"); 320 - 321 - if (node) 322 - base = of_iomap(node, 0); 323 - 324 - if (WARN_ON(!base)) 318 + if (WARN_ON(!vexpress_sysreg_base)) 325 319 return; 326 - 327 - vexpress_sysreg_base = base; 328 320 329 321 if (readl(vexpress_sysreg_base + SYS_MISC) & SYS_MISC_MASTERSITE) 330 322 vexpress_master_site = VEXPRESS_SITE_DB2; ··· 328 336 WARN_ON(!vexpress_sysreg_config_bridge); 329 337 } 330 338 339 + void __init vexpress_sysreg_early_init(void __iomem *base) 340 + { 341 + vexpress_sysreg_base = base; 342 + vexpress_sysreg_setup(NULL); 343 + } 344 + 331 345 void __init vexpress_sysreg_of_early_init(void) 332 346 { 333 - vexpress_sysreg_early_init(NULL); 347 + struct device_node *node = of_find_compatible_node(NULL, NULL, 348 + "arm,vexpress-sysreg"); 349 + 350 + if (node) { 351 + vexpress_sysreg_base = of_iomap(node, 0); 352 + vexpress_sysreg_setup(node); 353 + } else { 354 + pr_info("vexpress-sysreg: No Device Tree node found."); 355 + } 334 356 } 335 357 336 358 ··· 432 426 return -EBUSY; 433 427 } 434 428 435 - if (!vexpress_sysreg_base) 429 + if (!vexpress_sysreg_base) { 436 430 vexpress_sysreg_base = devm_ioremap(&pdev->dev, res->start, 437 431 resource_size(res)); 432 + vexpress_sysreg_setup(pdev->dev.of_node); 433 + } 438 434 439 435 if (!vexpress_sysreg_base) { 440 436 dev_err(&pdev->dev, "Failed to obtain base address!\n");
+30 -62
drivers/mmc/host/mvsdio.c
··· 50 50 struct timer_list timer; 51 51 struct mmc_host *mmc; 52 52 struct device *dev; 53 - struct resource *res; 54 - int irq; 55 53 struct clk *clk; 56 54 int gpio_card_detect; 57 55 int gpio_write_protect; ··· 716 718 if (!r || irq < 0 || !mvsd_data) 717 719 return -ENXIO; 718 720 719 - r = request_mem_region(r->start, SZ_1K, DRIVER_NAME); 720 - if (!r) 721 - return -EBUSY; 722 - 723 721 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); 724 722 if (!mmc) { 725 723 ret = -ENOMEM; ··· 725 731 host = mmc_priv(mmc); 726 732 host->mmc = mmc; 727 733 host->dev = &pdev->dev; 728 - host->res = r; 729 734 host->base_clock = mvsd_data->clock / 2; 735 + host->clk = ERR_PTR(-EINVAL); 730 736 731 737 mmc->ops = &mvsd_ops; 732 738 ··· 746 752 747 753 spin_lock_init(&host->lock); 748 754 749 - host->base = ioremap(r->start, SZ_4K); 755 + host->base = devm_request_and_ioremap(&pdev->dev, r); 750 756 if (!host->base) { 751 757 ret = -ENOMEM; 752 758 goto out; ··· 759 765 760 766 mvsd_power_down(host); 761 767 762 - ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host); 768 + ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host); 763 769 if (ret) { 764 770 pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq); 765 771 goto out; 766 - } else 767 - host->irq = irq; 772 + } 768 773 769 774 /* Not all platforms can gate the clock, so it is not 770 775 an error if the clock does not exists. */ 771 - host->clk = clk_get(&pdev->dev, NULL); 772 - if (!IS_ERR(host->clk)) { 776 + host->clk = devm_clk_get(&pdev->dev, NULL); 777 + if (!IS_ERR(host->clk)) 773 778 clk_prepare_enable(host->clk); 774 - } 775 779 776 780 if (mvsd_data->gpio_card_detect) { 777 - ret = gpio_request(mvsd_data->gpio_card_detect, 778 - DRIVER_NAME " cd"); 781 + ret = devm_gpio_request_one(&pdev->dev, 782 + mvsd_data->gpio_card_detect, 783 + GPIOF_IN, DRIVER_NAME " cd"); 779 784 if (ret == 0) { 780 - gpio_direction_input(mvsd_data->gpio_card_detect); 781 785 irq = gpio_to_irq(mvsd_data->gpio_card_detect); 782 - ret = request_irq(irq, mvsd_card_detect_irq, 783 - IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING, 784 - DRIVER_NAME " cd", host); 786 + ret = devm_request_irq(&pdev->dev, irq, 787 + mvsd_card_detect_irq, 788 + IRQ_TYPE_EDGE_RISING | 789 + IRQ_TYPE_EDGE_FALLING, 790 + DRIVER_NAME " cd", host); 785 791 if (ret == 0) 786 792 host->gpio_card_detect = 787 793 mvsd_data->gpio_card_detect; 788 794 else 789 - gpio_free(mvsd_data->gpio_card_detect); 795 + devm_gpio_free(&pdev->dev, 796 + mvsd_data->gpio_card_detect); 790 797 } 791 798 } 792 799 if (!host->gpio_card_detect) 793 800 mmc->caps |= MMC_CAP_NEEDS_POLL; 794 801 795 802 if (mvsd_data->gpio_write_protect) { 796 - ret = gpio_request(mvsd_data->gpio_write_protect, 797 - DRIVER_NAME " wp"); 803 + ret = devm_gpio_request_one(&pdev->dev, 804 + mvsd_data->gpio_write_protect, 805 + GPIOF_IN, DRIVER_NAME " wp"); 798 806 if (ret == 0) { 799 - gpio_direction_input(mvsd_data->gpio_write_protect); 800 807 host->gpio_write_protect = 801 808 mvsd_data->gpio_write_protect; 802 809 } ··· 819 824 return 0; 820 825 821 826 out: 822 - if (host) { 823 - if (host->irq) 824 - free_irq(host->irq, host); 825 - if (host->gpio_card_detect) { 826 - free_irq(gpio_to_irq(host->gpio_card_detect), host); 827 - gpio_free(host->gpio_card_detect); 828 - } 829 - if (host->gpio_write_protect) 830 - gpio_free(host->gpio_write_protect); 831 - if (host->base) 832 - iounmap(host->base); 833 - } 834 - if (r) 835 - release_resource(r); 836 - if (mmc) 837 - if (!IS_ERR_OR_NULL(host->clk)) { 827 + if (mmc) { 828 + if (!IS_ERR(host->clk)) 838 829 clk_disable_unprepare(host->clk); 839 - clk_put(host->clk); 840 - } 841 830 mmc_free_host(mmc); 831 + } 842 832 843 833 return ret; 844 834 } ··· 832 852 { 833 853 struct mmc_host *mmc = platform_get_drvdata(pdev); 834 854 835 - if (mmc) { 836 - struct mvsd_host *host = mmc_priv(mmc); 855 + struct mvsd_host *host = mmc_priv(mmc); 837 856 838 - if (host->gpio_card_detect) { 839 - free_irq(gpio_to_irq(host->gpio_card_detect), host); 840 - gpio_free(host->gpio_card_detect); 841 - } 842 - mmc_remove_host(mmc); 843 - free_irq(host->irq, host); 844 - if (host->gpio_write_protect) 845 - gpio_free(host->gpio_write_protect); 846 - del_timer_sync(&host->timer); 847 - mvsd_power_down(host); 848 - iounmap(host->base); 849 - release_resource(host->res); 857 + mmc_remove_host(mmc); 858 + del_timer_sync(&host->timer); 859 + mvsd_power_down(host); 850 860 851 - if (!IS_ERR(host->clk)) { 852 - clk_disable_unprepare(host->clk); 853 - clk_put(host->clk); 854 - } 855 - mmc_free_host(mmc); 856 - } 861 + if (!IS_ERR(host->clk)) 862 + clk_disable_unprepare(host->clk); 863 + mmc_free_host(mmc); 864 + 857 865 platform_set_drvdata(pdev, NULL); 858 866 return 0; 859 867 }
+12 -1
drivers/video/imxfb.c
··· 139 139 struct clk *clk_ahb; 140 140 struct clk *clk_per; 141 141 enum imxfb_type devtype; 142 + bool enabled; 142 143 143 144 /* 144 145 * These are the addresses we mapped ··· 537 536 538 537 static void imxfb_enable_controller(struct imxfb_info *fbi) 539 538 { 539 + 540 + if (fbi->enabled) 541 + return; 542 + 540 543 pr_debug("Enabling LCD controller\n"); 541 544 542 545 writel(fbi->screen_dma, fbi->regs + LCDC_SSA); ··· 561 556 clk_prepare_enable(fbi->clk_ipg); 562 557 clk_prepare_enable(fbi->clk_ahb); 563 558 clk_prepare_enable(fbi->clk_per); 559 + fbi->enabled = true; 564 560 565 561 if (fbi->backlight_power) 566 562 fbi->backlight_power(1); ··· 571 565 572 566 static void imxfb_disable_controller(struct imxfb_info *fbi) 573 567 { 568 + if (!fbi->enabled) 569 + return; 570 + 574 571 pr_debug("Disabling LCD controller\n"); 575 572 576 573 if (fbi->backlight_power) ··· 584 575 clk_disable_unprepare(fbi->clk_per); 585 576 clk_disable_unprepare(fbi->clk_ipg); 586 577 clk_disable_unprepare(fbi->clk_ahb); 578 + fbi->enabled = false; 587 579 588 580 writel(0, fbi->regs + LCDC_RMCR); 589 581 } ··· 739 729 740 730 memset(fbi, 0, sizeof(struct imxfb_info)); 741 731 732 + fbi->devtype = pdev->id_entry->driver_data; 733 + 742 734 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); 743 735 744 736 info->fix.type = FB_TYPE_PACKED_PIXELS; ··· 801 789 return -ENOMEM; 802 790 803 791 fbi = info->par; 804 - fbi->devtype = pdev->id_entry->driver_data; 805 792 806 793 if (!fb_mode) 807 794 fb_mode = pdata->mode[0].mode.name;