Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'wangxun-interrupts'
Jiawen Wu says:
====================
Wangxun interrupt and RxTx support
Configure interrupt, setup RxTx ring, support to receive and transmit
packets.
change log:
v3:
- Use upper_32_bits() to avoid compile warning.
- Remove useless codes.
v2:
- Andrew Lunn: https://lore.kernel.org/netdev/Y86kDphvyHj21IxK@lunn.ch/
- Add a judgment when allocate dma for descriptor.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
+3574
-18
+1
drivers/net/ethernet/wangxun/Kconfig
+1
drivers/net/ethernet/wangxun/Kconfig
+1
-1
drivers/net/ethernet/wangxun/libwx/Makefile
+1
-1
drivers/net/ethernet/wangxun/libwx/Makefile
+674
-1
drivers/net/ethernet/wangxun/libwx/wx_hw.c
+674
-1
drivers/net/ethernet/wangxun/libwx/wx_hw.c
···
8
8
#include <linux/pci.h>
9
9
10
10
#include "wx_type.h"
11
+
#include "wx_lib.h"
11
12
#include "wx_hw.h"
12
13
13
14
static void wx_intr_disable(struct wx *wx, u64 qmask)
14
15
{
15
16
u32 mask;
16
17
17
-
mask = (qmask & 0xFFFFFFFF);
18
+
mask = (qmask & U32_MAX);
18
19
if (mask)
19
20
wr32(wx, WX_PX_IMS(0), mask);
20
21
···
25
24
wr32(wx, WX_PX_IMS(1), mask);
26
25
}
27
26
}
27
+
28
+
void wx_intr_enable(struct wx *wx, u64 qmask)
29
+
{
30
+
u32 mask;
31
+
32
+
mask = (qmask & U32_MAX);
33
+
if (mask)
34
+
wr32(wx, WX_PX_IMC(0), mask);
35
+
if (wx->mac.type == wx_mac_sp) {
36
+
mask = (qmask >> 32);
37
+
if (mask)
38
+
wr32(wx, WX_PX_IMC(1), mask);
39
+
}
40
+
}
41
+
EXPORT_SYMBOL(wx_intr_enable);
42
+
43
+
/**
44
+
* wx_irq_disable - Mask off interrupt generation on the NIC
45
+
* @wx: board private structure
46
+
**/
47
+
void wx_irq_disable(struct wx *wx)
48
+
{
49
+
struct pci_dev *pdev = wx->pdev;
50
+
51
+
wr32(wx, WX_PX_MISC_IEN, 0);
52
+
wx_intr_disable(wx, WX_INTR_ALL);
53
+
54
+
if (pdev->msix_enabled) {
55
+
int vector;
56
+
57
+
for (vector = 0; vector < wx->num_q_vectors; vector++)
58
+
synchronize_irq(wx->msix_entries[vector].vector);
59
+
60
+
synchronize_irq(wx->msix_entries[vector].vector);
61
+
} else {
62
+
synchronize_irq(pdev->irq);
63
+
}
64
+
}
65
+
EXPORT_SYMBOL(wx_irq_disable);
28
66
29
67
/* cmd_addr is used for some special command:
30
68
* 1. to be sector address, when implemented erase sector command
···
805
765
}
806
766
EXPORT_SYMBOL(wx_flush_sw_mac_table);
807
767
768
+
static int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool)
769
+
{
770
+
u32 i;
771
+
772
+
if (is_zero_ether_addr(addr))
773
+
return -EINVAL;
774
+
775
+
for (i = 0; i < wx->mac.num_rar_entries; i++) {
776
+
if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) {
777
+
if (ether_addr_equal(addr, wx->mac_table[i].addr)) {
778
+
if (wx->mac_table[i].pools != (1ULL << pool)) {
779
+
memcpy(wx->mac_table[i].addr, addr, ETH_ALEN);
780
+
wx->mac_table[i].pools |= (1ULL << pool);
781
+
wx_sync_mac_table(wx);
782
+
return i;
783
+
}
784
+
}
785
+
}
786
+
787
+
if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE)
788
+
continue;
789
+
wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED |
790
+
WX_MAC_STATE_IN_USE);
791
+
memcpy(wx->mac_table[i].addr, addr, ETH_ALEN);
792
+
wx->mac_table[i].pools |= (1ULL << pool);
793
+
wx_sync_mac_table(wx);
794
+
return i;
795
+
}
796
+
return -ENOMEM;
797
+
}
798
+
808
799
static int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool)
809
800
{
810
801
u32 i;
···
858
787
return 0;
859
788
}
860
789
return -ENOMEM;
790
+
}
791
+
792
+
static int wx_available_rars(struct wx *wx)
793
+
{
794
+
u32 i, count = 0;
795
+
796
+
for (i = 0; i < wx->mac.num_rar_entries; i++) {
797
+
if (wx->mac_table[i].state == 0)
798
+
count++;
799
+
}
800
+
801
+
return count;
802
+
}
803
+
804
+
/**
805
+
* wx_write_uc_addr_list - write unicast addresses to RAR table
806
+
* @netdev: network interface device structure
807
+
* @pool: index for mac table
808
+
*
809
+
* Writes unicast address list to the RAR table.
810
+
* Returns: -ENOMEM on failure/insufficient address space
811
+
* 0 on no addresses written
812
+
* X on writing X addresses to the RAR table
813
+
**/
814
+
static int wx_write_uc_addr_list(struct net_device *netdev, int pool)
815
+
{
816
+
struct wx *wx = netdev_priv(netdev);
817
+
int count = 0;
818
+
819
+
/* return ENOMEM indicating insufficient memory for addresses */
820
+
if (netdev_uc_count(netdev) > wx_available_rars(wx))
821
+
return -ENOMEM;
822
+
823
+
if (!netdev_uc_empty(netdev)) {
824
+
struct netdev_hw_addr *ha;
825
+
826
+
netdev_for_each_uc_addr(ha, netdev) {
827
+
wx_del_mac_filter(wx, ha->addr, pool);
828
+
wx_add_mac_filter(wx, ha->addr, pool);
829
+
count++;
830
+
}
831
+
}
832
+
return count;
833
+
}
834
+
835
+
/**
836
+
* wx_mta_vector - Determines bit-vector in multicast table to set
837
+
* @wx: pointer to private structure
838
+
* @mc_addr: the multicast address
839
+
*
840
+
* Extracts the 12 bits, from a multicast address, to determine which
841
+
* bit-vector to set in the multicast table. The hardware uses 12 bits, from
842
+
* incoming rx multicast addresses, to determine the bit-vector to check in
843
+
* the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
844
+
* by the MO field of the MCSTCTRL. The MO field is set during initialization
845
+
* to mc_filter_type.
846
+
**/
847
+
static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr)
848
+
{
849
+
u32 vector = 0;
850
+
851
+
switch (wx->mac.mc_filter_type) {
852
+
case 0: /* use bits [47:36] of the address */
853
+
vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
854
+
break;
855
+
case 1: /* use bits [46:35] of the address */
856
+
vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
857
+
break;
858
+
case 2: /* use bits [45:34] of the address */
859
+
vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
860
+
break;
861
+
case 3: /* use bits [43:32] of the address */
862
+
vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
863
+
break;
864
+
default: /* Invalid mc_filter_type */
865
+
wx_err(wx, "MC filter type param set incorrectly\n");
866
+
break;
867
+
}
868
+
869
+
/* vector can only be 12-bits or boundary will be exceeded */
870
+
vector &= 0xFFF;
871
+
return vector;
872
+
}
873
+
874
+
/**
875
+
* wx_set_mta - Set bit-vector in multicast table
876
+
* @wx: pointer to private structure
877
+
* @mc_addr: Multicast address
878
+
*
879
+
* Sets the bit-vector in the multicast table.
880
+
**/
881
+
static void wx_set_mta(struct wx *wx, u8 *mc_addr)
882
+
{
883
+
u32 vector, vector_bit, vector_reg;
884
+
885
+
wx->addr_ctrl.mta_in_use++;
886
+
887
+
vector = wx_mta_vector(wx, mc_addr);
888
+
wx_dbg(wx, " bit-vector = 0x%03X\n", vector);
889
+
890
+
/* The MTA is a register array of 128 32-bit registers. It is treated
891
+
* like an array of 4096 bits. We want to set bit
892
+
* BitArray[vector_value]. So we figure out what register the bit is
893
+
* in, read it, OR in the new bit, then write back the new value. The
894
+
* register is determined by the upper 7 bits of the vector value and
895
+
* the bit within that register are determined by the lower 5 bits of
896
+
* the value.
897
+
*/
898
+
vector_reg = (vector >> 5) & 0x7F;
899
+
vector_bit = vector & 0x1F;
900
+
wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
901
+
}
902
+
903
+
/**
904
+
* wx_update_mc_addr_list - Updates MAC list of multicast addresses
905
+
* @wx: pointer to private structure
906
+
* @netdev: pointer to net device structure
907
+
*
908
+
* The given list replaces any existing list. Clears the MC addrs from receive
909
+
* address registers and the multicast table. Uses unused receive address
910
+
* registers for the first multicast addresses, and hashes the rest into the
911
+
* multicast table.
912
+
**/
913
+
static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev)
914
+
{
915
+
struct netdev_hw_addr *ha;
916
+
u32 i, psrctl;
917
+
918
+
/* Set the new number of MC addresses that we are being requested to
919
+
* use.
920
+
*/
921
+
wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
922
+
wx->addr_ctrl.mta_in_use = 0;
923
+
924
+
/* Clear mta_shadow */
925
+
wx_dbg(wx, " Clearing MTA\n");
926
+
memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow));
927
+
928
+
/* Update mta_shadow */
929
+
netdev_for_each_mc_addr(ha, netdev) {
930
+
wx_dbg(wx, " Adding the multicast addresses:\n");
931
+
wx_set_mta(wx, ha->addr);
932
+
}
933
+
934
+
/* Enable mta */
935
+
for (i = 0; i < wx->mac.mcft_size; i++)
936
+
wr32a(wx, WX_PSR_MC_TBL(0), i,
937
+
wx->mac.mta_shadow[i]);
938
+
939
+
if (wx->addr_ctrl.mta_in_use > 0) {
940
+
psrctl = rd32(wx, WX_PSR_CTL);
941
+
psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
942
+
psrctl |= WX_PSR_CTL_MFE |
943
+
(wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT);
944
+
wr32(wx, WX_PSR_CTL, psrctl);
945
+
}
946
+
947
+
wx_dbg(wx, "Update mc addr list Complete\n");
948
+
}
949
+
950
+
/**
951
+
* wx_write_mc_addr_list - write multicast addresses to MTA
952
+
* @netdev: network interface device structure
953
+
*
954
+
* Writes multicast address list to the MTA hash table.
955
+
* Returns: 0 on no addresses written
956
+
* X on writing X addresses to MTA
957
+
**/
958
+
static int wx_write_mc_addr_list(struct net_device *netdev)
959
+
{
960
+
struct wx *wx = netdev_priv(netdev);
961
+
962
+
if (!netif_running(netdev))
963
+
return 0;
964
+
965
+
wx_update_mc_addr_list(wx, netdev);
966
+
967
+
return netdev_mc_count(netdev);
861
968
}
862
969
863
970
/**
···
1092
843
}
1093
844
}
1094
845
EXPORT_SYMBOL(wx_disable_rx);
846
+
847
+
static void wx_enable_rx(struct wx *wx)
848
+
{
849
+
u32 psrctl;
850
+
851
+
/* enable mac receiver */
852
+
wr32m(wx, WX_MAC_RX_CFG,
853
+
WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
854
+
855
+
wr32m(wx, WX_RDB_PB_CTL,
856
+
WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN);
857
+
858
+
if (wx->mac.set_lben) {
859
+
psrctl = rd32(wx, WX_PSR_CTL);
860
+
psrctl |= WX_PSR_CTL_SW_EN;
861
+
wr32(wx, WX_PSR_CTL, psrctl);
862
+
wx->mac.set_lben = false;
863
+
}
864
+
}
865
+
866
+
/**
867
+
* wx_set_rxpba - Initialize Rx packet buffer
868
+
* @wx: pointer to private structure
869
+
**/
870
+
static void wx_set_rxpba(struct wx *wx)
871
+
{
872
+
u32 rxpktsize, txpktsize, txpbthresh;
873
+
874
+
rxpktsize = wx->mac.rx_pb_size << WX_RDB_PB_SZ_SHIFT;
875
+
wr32(wx, WX_RDB_PB_SZ(0), rxpktsize);
876
+
877
+
/* Only support an equally distributed Tx packet buffer strategy. */
878
+
txpktsize = wx->mac.tx_pb_size;
879
+
txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX;
880
+
wr32(wx, WX_TDB_PB_SZ(0), txpktsize);
881
+
wr32(wx, WX_TDM_PB_THRE(0), txpbthresh);
882
+
}
883
+
884
+
static void wx_configure_port(struct wx *wx)
885
+
{
886
+
u32 value, i;
887
+
888
+
value = WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ;
889
+
wr32m(wx, WX_CFG_PORT_CTL,
890
+
WX_CFG_PORT_CTL_D_VLAN |
891
+
WX_CFG_PORT_CTL_QINQ,
892
+
value);
893
+
894
+
wr32(wx, WX_CFG_TAG_TPID(0),
895
+
ETH_P_8021Q | ETH_P_8021AD << 16);
896
+
wx->tpid[0] = ETH_P_8021Q;
897
+
wx->tpid[1] = ETH_P_8021AD;
898
+
for (i = 1; i < 4; i++)
899
+
wr32(wx, WX_CFG_TAG_TPID(i),
900
+
ETH_P_8021Q | ETH_P_8021Q << 16);
901
+
for (i = 2; i < 8; i++)
902
+
wx->tpid[i] = ETH_P_8021Q;
903
+
}
904
+
905
+
/**
906
+
* wx_disable_sec_rx_path - Stops the receive data path
907
+
* @wx: pointer to private structure
908
+
*
909
+
* Stops the receive data path and waits for the HW to internally empty
910
+
* the Rx security block
911
+
**/
912
+
static int wx_disable_sec_rx_path(struct wx *wx)
913
+
{
914
+
u32 secrx;
915
+
916
+
wr32m(wx, WX_RSC_CTL,
917
+
WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS);
918
+
919
+
return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY,
920
+
1000, 40000, false, wx, WX_RSC_ST);
921
+
}
922
+
923
+
/**
924
+
* wx_enable_sec_rx_path - Enables the receive data path
925
+
* @wx: pointer to private structure
926
+
*
927
+
* Enables the receive data path.
928
+
**/
929
+
static void wx_enable_sec_rx_path(struct wx *wx)
930
+
{
931
+
wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0);
932
+
WX_WRITE_FLUSH(wx);
933
+
}
934
+
935
+
void wx_set_rx_mode(struct net_device *netdev)
936
+
{
937
+
struct wx *wx = netdev_priv(netdev);
938
+
u32 fctrl, vmolr, vlnctrl;
939
+
int count;
940
+
941
+
/* Check for Promiscuous and All Multicast modes */
942
+
fctrl = rd32(wx, WX_PSR_CTL);
943
+
fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE);
944
+
vmolr = rd32(wx, WX_PSR_VM_L2CTL(0));
945
+
vmolr &= ~(WX_PSR_VM_L2CTL_UPE |
946
+
WX_PSR_VM_L2CTL_MPE |
947
+
WX_PSR_VM_L2CTL_ROPE |
948
+
WX_PSR_VM_L2CTL_ROMPE);
949
+
vlnctrl = rd32(wx, WX_PSR_VLAN_CTL);
950
+
vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN);
951
+
952
+
/* set all bits that we expect to always be set */
953
+
fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE;
954
+
vmolr |= WX_PSR_VM_L2CTL_BAM |
955
+
WX_PSR_VM_L2CTL_AUPE |
956
+
WX_PSR_VM_L2CTL_VACC;
957
+
vlnctrl |= WX_PSR_VLAN_CTL_VFE;
958
+
959
+
wx->addr_ctrl.user_set_promisc = false;
960
+
if (netdev->flags & IFF_PROMISC) {
961
+
wx->addr_ctrl.user_set_promisc = true;
962
+
fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE;
963
+
/* pf don't want packets routing to vf, so clear UPE */
964
+
vmolr |= WX_PSR_VM_L2CTL_MPE;
965
+
vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
966
+
}
967
+
968
+
if (netdev->flags & IFF_ALLMULTI) {
969
+
fctrl |= WX_PSR_CTL_MPE;
970
+
vmolr |= WX_PSR_VM_L2CTL_MPE;
971
+
}
972
+
973
+
if (netdev->features & NETIF_F_RXALL) {
974
+
vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE);
975
+
vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
976
+
/* receive bad packets */
977
+
wr32m(wx, WX_RSC_CTL,
978
+
WX_RSC_CTL_SAVE_MAC_ERR,
979
+
WX_RSC_CTL_SAVE_MAC_ERR);
980
+
} else {
981
+
vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE;
982
+
}
983
+
984
+
/* Write addresses to available RAR registers, if there is not
985
+
* sufficient space to store all the addresses then enable
986
+
* unicast promiscuous mode
987
+
*/
988
+
count = wx_write_uc_addr_list(netdev, 0);
989
+
if (count < 0) {
990
+
vmolr &= ~WX_PSR_VM_L2CTL_ROPE;
991
+
vmolr |= WX_PSR_VM_L2CTL_UPE;
992
+
}
993
+
994
+
/* Write addresses to the MTA, if the attempt fails
995
+
* then we should just turn on promiscuous mode so
996
+
* that we can at least receive multicast traffic
997
+
*/
998
+
count = wx_write_mc_addr_list(netdev);
999
+
if (count < 0) {
1000
+
vmolr &= ~WX_PSR_VM_L2CTL_ROMPE;
1001
+
vmolr |= WX_PSR_VM_L2CTL_MPE;
1002
+
}
1003
+
1004
+
wr32(wx, WX_PSR_VLAN_CTL, vlnctrl);
1005
+
wr32(wx, WX_PSR_CTL, fctrl);
1006
+
wr32(wx, WX_PSR_VM_L2CTL(0), vmolr);
1007
+
}
1008
+
EXPORT_SYMBOL(wx_set_rx_mode);
1009
+
1010
+
static void wx_set_rx_buffer_len(struct wx *wx)
1011
+
{
1012
+
struct net_device *netdev = wx->netdev;
1013
+
u32 mhadd, max_frame;
1014
+
1015
+
max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1016
+
/* adjust max frame to be at least the size of a standard frame */
1017
+
if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
1018
+
max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
1019
+
1020
+
mhadd = rd32(wx, WX_PSR_MAX_SZ);
1021
+
if (max_frame != mhadd)
1022
+
wr32(wx, WX_PSR_MAX_SZ, max_frame);
1023
+
}
1024
+
1025
+
/* Disable the specified rx queue */
1026
+
void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring)
1027
+
{
1028
+
u8 reg_idx = ring->reg_idx;
1029
+
u32 rxdctl;
1030
+
int ret;
1031
+
1032
+
/* write value back with RRCFG.EN bit cleared */
1033
+
wr32m(wx, WX_PX_RR_CFG(reg_idx),
1034
+
WX_PX_RR_CFG_RR_EN, 0);
1035
+
1036
+
/* the hardware may take up to 100us to really disable the rx queue */
1037
+
ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN),
1038
+
10, 100, true, wx, WX_PX_RR_CFG(reg_idx));
1039
+
1040
+
if (ret == -ETIMEDOUT) {
1041
+
/* Just for information */
1042
+
wx_err(wx,
1043
+
"RRCFG.EN on Rx queue %d not cleared within the polling period\n",
1044
+
reg_idx);
1045
+
}
1046
+
}
1047
+
EXPORT_SYMBOL(wx_disable_rx_queue);
1048
+
1049
+
static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring)
1050
+
{
1051
+
u8 reg_idx = ring->reg_idx;
1052
+
u32 rxdctl;
1053
+
int ret;
1054
+
1055
+
ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN,
1056
+
1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx));
1057
+
1058
+
if (ret == -ETIMEDOUT) {
1059
+
/* Just for information */
1060
+
wx_err(wx,
1061
+
"RRCFG.EN on Rx queue %d not set within the polling period\n",
1062
+
reg_idx);
1063
+
}
1064
+
}
1065
+
1066
+
static void wx_configure_srrctl(struct wx *wx,
1067
+
struct wx_ring *rx_ring)
1068
+
{
1069
+
u16 reg_idx = rx_ring->reg_idx;
1070
+
u32 srrctl;
1071
+
1072
+
srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1073
+
srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ |
1074
+
WX_PX_RR_CFG_RR_BUF_SZ |
1075
+
WX_PX_RR_CFG_SPLIT_MODE);
1076
+
/* configure header buffer length, needed for RSC */
1077
+
srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT;
1078
+
1079
+
/* configure the packet buffer length */
1080
+
srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT;
1081
+
1082
+
wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
1083
+
}
1084
+
1085
+
static void wx_configure_tx_ring(struct wx *wx,
1086
+
struct wx_ring *ring)
1087
+
{
1088
+
u32 txdctl = WX_PX_TR_CFG_ENABLE;
1089
+
u8 reg_idx = ring->reg_idx;
1090
+
u64 tdba = ring->dma;
1091
+
int ret;
1092
+
1093
+
/* disable queue to avoid issues while updating state */
1094
+
wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
1095
+
WX_WRITE_FLUSH(wx);
1096
+
1097
+
wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32));
1098
+
wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba));
1099
+
1100
+
/* reset head and tail pointers */
1101
+
wr32(wx, WX_PX_TR_RP(reg_idx), 0);
1102
+
wr32(wx, WX_PX_TR_WP(reg_idx), 0);
1103
+
ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx);
1104
+
1105
+
if (ring->count < WX_MAX_TXD)
1106
+
txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT;
1107
+
txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT;
1108
+
1109
+
/* reinitialize tx_buffer_info */
1110
+
memset(ring->tx_buffer_info, 0,
1111
+
sizeof(struct wx_tx_buffer) * ring->count);
1112
+
1113
+
/* enable queue */
1114
+
wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl);
1115
+
1116
+
/* poll to verify queue is enabled */
1117
+
ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE,
1118
+
1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx));
1119
+
if (ret == -ETIMEDOUT)
1120
+
wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx);
1121
+
}
1122
+
1123
+
static void wx_configure_rx_ring(struct wx *wx,
1124
+
struct wx_ring *ring)
1125
+
{
1126
+
u16 reg_idx = ring->reg_idx;
1127
+
union wx_rx_desc *rx_desc;
1128
+
u64 rdba = ring->dma;
1129
+
u32 rxdctl;
1130
+
1131
+
/* disable queue to avoid issues while updating state */
1132
+
rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1133
+
wx_disable_rx_queue(wx, ring);
1134
+
1135
+
wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32));
1136
+
wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba));
1137
+
1138
+
if (ring->count == WX_MAX_RXD)
1139
+
rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT;
1140
+
else
1141
+
rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT;
1142
+
1143
+
rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT;
1144
+
wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl);
1145
+
1146
+
/* reset head and tail pointers */
1147
+
wr32(wx, WX_PX_RR_RP(reg_idx), 0);
1148
+
wr32(wx, WX_PX_RR_WP(reg_idx), 0);
1149
+
ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx);
1150
+
1151
+
wx_configure_srrctl(wx, ring);
1152
+
1153
+
/* initialize rx_buffer_info */
1154
+
memset(ring->rx_buffer_info, 0,
1155
+
sizeof(struct wx_rx_buffer) * ring->count);
1156
+
1157
+
/* initialize Rx descriptor 0 */
1158
+
rx_desc = WX_RX_DESC(ring, 0);
1159
+
rx_desc->wb.upper.length = 0;
1160
+
1161
+
/* enable receive descriptor ring */
1162
+
wr32m(wx, WX_PX_RR_CFG(reg_idx),
1163
+
WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN);
1164
+
1165
+
wx_enable_rx_queue(wx, ring);
1166
+
wx_alloc_rx_buffers(ring, wx_desc_unused(ring));
1167
+
}
1168
+
1169
+
/**
1170
+
* wx_configure_tx - Configure Transmit Unit after Reset
1171
+
* @wx: pointer to private structure
1172
+
*
1173
+
* Configure the Tx unit of the MAC after a reset.
1174
+
**/
1175
+
static void wx_configure_tx(struct wx *wx)
1176
+
{
1177
+
u32 i;
1178
+
1179
+
/* TDM_CTL.TE must be before Tx queues are enabled */
1180
+
wr32m(wx, WX_TDM_CTL,
1181
+
WX_TDM_CTL_TE, WX_TDM_CTL_TE);
1182
+
1183
+
/* Setup the HW Tx Head and Tail descriptor pointers */
1184
+
for (i = 0; i < wx->num_tx_queues; i++)
1185
+
wx_configure_tx_ring(wx, wx->tx_ring[i]);
1186
+
1187
+
wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10);
1188
+
1189
+
if (wx->mac.type == wx_mac_em)
1190
+
wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1);
1191
+
1192
+
/* enable mac transmitter */
1193
+
wr32m(wx, WX_MAC_TX_CFG,
1194
+
WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE);
1195
+
}
1196
+
1197
+
/**
1198
+
* wx_configure_rx - Configure Receive Unit after Reset
1199
+
* @wx: pointer to private structure
1200
+
*
1201
+
* Configure the Rx unit of the MAC after a reset.
1202
+
**/
1203
+
static void wx_configure_rx(struct wx *wx)
1204
+
{
1205
+
u32 psrtype, i;
1206
+
int ret;
1207
+
1208
+
wx_disable_rx(wx);
1209
+
1210
+
psrtype = WX_RDB_PL_CFG_L4HDR |
1211
+
WX_RDB_PL_CFG_L3HDR |
1212
+
WX_RDB_PL_CFG_L2HDR |
1213
+
WX_RDB_PL_CFG_TUN_TUNHDR |
1214
+
WX_RDB_PL_CFG_TUN_TUNHDR;
1215
+
wr32(wx, WX_RDB_PL_CFG(0), psrtype);
1216
+
1217
+
/* enable hw crc stripping */
1218
+
wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP);
1219
+
1220
+
if (wx->mac.type == wx_mac_sp) {
1221
+
u32 psrctl;
1222
+
1223
+
/* RSC Setup */
1224
+
psrctl = rd32(wx, WX_PSR_CTL);
1225
+
psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */
1226
+
psrctl |= WX_PSR_CTL_RSC_DIS;
1227
+
wr32(wx, WX_PSR_CTL, psrctl);
1228
+
}
1229
+
1230
+
/* set_rx_buffer_len must be called before ring initialization */
1231
+
wx_set_rx_buffer_len(wx);
1232
+
1233
+
/* Setup the HW Rx Head and Tail Descriptor Pointers and
1234
+
* the Base and Length of the Rx Descriptor Ring
1235
+
*/
1236
+
for (i = 0; i < wx->num_rx_queues; i++)
1237
+
wx_configure_rx_ring(wx, wx->rx_ring[i]);
1238
+
1239
+
/* Enable all receives, disable security engine prior to block traffic */
1240
+
ret = wx_disable_sec_rx_path(wx);
1241
+
if (ret < 0)
1242
+
wx_err(wx, "The register status is abnormal, please check device.");
1243
+
1244
+
wx_enable_rx(wx);
1245
+
wx_enable_sec_rx_path(wx);
1246
+
}
1247
+
1248
+
static void wx_configure_isb(struct wx *wx)
1249
+
{
1250
+
/* set ISB Address */
1251
+
wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32));
1252
+
if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
1253
+
wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma));
1254
+
}
1255
+
1256
+
void wx_configure(struct wx *wx)
1257
+
{
1258
+
wx_set_rxpba(wx);
1259
+
wx_configure_port(wx);
1260
+
1261
+
wx_set_rx_mode(wx->netdev);
1262
+
1263
+
wx_enable_sec_rx_path(wx);
1264
+
1265
+
wx_configure_tx(wx);
1266
+
wx_configure_rx(wx);
1267
+
wx_configure_isb(wx);
1268
+
}
1269
+
EXPORT_SYMBOL(wx_configure);
1095
1270
1096
1271
/**
1097
1272
* wx_disable_pcie_master - Disable PCI-express master access
+5
drivers/net/ethernet/wangxun/libwx/wx_hw.h
+5
drivers/net/ethernet/wangxun/libwx/wx_hw.h
···
4
4
#ifndef _WX_HW_H_
5
5
#define _WX_HW_H_
6
6
7
+
void wx_intr_enable(struct wx *wx, u64 qmask);
8
+
void wx_irq_disable(struct wx *wx);
7
9
int wx_check_flash_load(struct wx *wx, u32 check_bit);
8
10
void wx_control_hw(struct wx *wx, bool drv);
9
11
int wx_mng_present(struct wx *wx);
···
22
20
void wx_flush_sw_mac_table(struct wx *wx);
23
21
int wx_set_mac(struct net_device *netdev, void *p);
24
22
void wx_disable_rx(struct wx *wx);
23
+
void wx_set_rx_mode(struct net_device *netdev);
24
+
void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring);
25
+
void wx_configure(struct wx *wx);
25
26
int wx_disable_pcie_master(struct wx *wx);
26
27
int wx_stop_adapter(struct wx *wx);
27
28
void wx_reset_misc(struct wx *wx);
+2004
drivers/net/ethernet/wangxun/libwx/wx_lib.c
+2004
drivers/net/ethernet/wangxun/libwx/wx_lib.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
3
+
4
+
#include <linux/etherdevice.h>
5
+
#include <net/page_pool.h>
6
+
#include <linux/iopoll.h>
7
+
#include <linux/pci.h>
8
+
9
+
#include "wx_type.h"
10
+
#include "wx_lib.h"
11
+
#include "wx_hw.h"
12
+
13
+
/* wx_test_staterr - tests bits in Rx descriptor status and error fields */
14
+
static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,
15
+
const u32 stat_err_bits)
16
+
{
17
+
return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
18
+
}
19
+
20
+
static bool wx_can_reuse_rx_page(struct wx_rx_buffer *rx_buffer,
21
+
int rx_buffer_pgcnt)
22
+
{
23
+
unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
24
+
struct page *page = rx_buffer->page;
25
+
26
+
/* avoid re-using remote and pfmemalloc pages */
27
+
if (!dev_page_is_reusable(page))
28
+
return false;
29
+
30
+
#if (PAGE_SIZE < 8192)
31
+
/* if we are only owner of page we can reuse it */
32
+
if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
33
+
return false;
34
+
#endif
35
+
36
+
/* If we have drained the page fragment pool we need to update
37
+
* the pagecnt_bias and page count so that we fully restock the
38
+
* number of references the driver holds.
39
+
*/
40
+
if (unlikely(pagecnt_bias == 1)) {
41
+
page_ref_add(page, USHRT_MAX - 1);
42
+
rx_buffer->pagecnt_bias = USHRT_MAX;
43
+
}
44
+
45
+
return true;
46
+
}
47
+
48
+
/**
49
+
* wx_reuse_rx_page - page flip buffer and store it back on the ring
50
+
* @rx_ring: rx descriptor ring to store buffers on
51
+
* @old_buff: donor buffer to have page reused
52
+
*
53
+
* Synchronizes page for reuse by the adapter
54
+
**/
55
+
static void wx_reuse_rx_page(struct wx_ring *rx_ring,
56
+
struct wx_rx_buffer *old_buff)
57
+
{
58
+
u16 nta = rx_ring->next_to_alloc;
59
+
struct wx_rx_buffer *new_buff;
60
+
61
+
new_buff = &rx_ring->rx_buffer_info[nta];
62
+
63
+
/* update, and store next to alloc */
64
+
nta++;
65
+
rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
66
+
67
+
/* transfer page from old buffer to new buffer */
68
+
new_buff->page = old_buff->page;
69
+
new_buff->page_dma = old_buff->page_dma;
70
+
new_buff->page_offset = old_buff->page_offset;
71
+
new_buff->pagecnt_bias = old_buff->pagecnt_bias;
72
+
}
73
+
74
+
static void wx_dma_sync_frag(struct wx_ring *rx_ring,
75
+
struct wx_rx_buffer *rx_buffer)
76
+
{
77
+
struct sk_buff *skb = rx_buffer->skb;
78
+
skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
79
+
80
+
dma_sync_single_range_for_cpu(rx_ring->dev,
81
+
WX_CB(skb)->dma,
82
+
skb_frag_off(frag),
83
+
skb_frag_size(frag),
84
+
DMA_FROM_DEVICE);
85
+
86
+
/* If the page was released, just unmap it. */
87
+
if (unlikely(WX_CB(skb)->page_released))
88
+
page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
89
+
}
90
+
91
+
static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,
92
+
union wx_rx_desc *rx_desc,
93
+
struct sk_buff **skb,
94
+
int *rx_buffer_pgcnt)
95
+
{
96
+
struct wx_rx_buffer *rx_buffer;
97
+
unsigned int size;
98
+
99
+
rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
100
+
size = le16_to_cpu(rx_desc->wb.upper.length);
101
+
102
+
#if (PAGE_SIZE < 8192)
103
+
*rx_buffer_pgcnt = page_count(rx_buffer->page);
104
+
#else
105
+
*rx_buffer_pgcnt = 0;
106
+
#endif
107
+
108
+
prefetchw(rx_buffer->page);
109
+
*skb = rx_buffer->skb;
110
+
111
+
/* Delay unmapping of the first packet. It carries the header
112
+
* information, HW may still access the header after the writeback.
113
+
* Only unmap it when EOP is reached
114
+
*/
115
+
if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) {
116
+
if (!*skb)
117
+
goto skip_sync;
118
+
} else {
119
+
if (*skb)
120
+
wx_dma_sync_frag(rx_ring, rx_buffer);
121
+
}
122
+
123
+
/* we are reusing so sync this buffer for CPU use */
124
+
dma_sync_single_range_for_cpu(rx_ring->dev,
125
+
rx_buffer->dma,
126
+
rx_buffer->page_offset,
127
+
size,
128
+
DMA_FROM_DEVICE);
129
+
skip_sync:
130
+
rx_buffer->pagecnt_bias--;
131
+
132
+
return rx_buffer;
133
+
}
134
+
135
+
static void wx_put_rx_buffer(struct wx_ring *rx_ring,
136
+
struct wx_rx_buffer *rx_buffer,
137
+
struct sk_buff *skb,
138
+
int rx_buffer_pgcnt)
139
+
{
140
+
if (wx_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
141
+
/* hand second half of page back to the ring */
142
+
wx_reuse_rx_page(rx_ring, rx_buffer);
143
+
} else {
144
+
if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma)
145
+
/* the page has been released from the ring */
146
+
WX_CB(skb)->page_released = true;
147
+
else
148
+
page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
149
+
150
+
__page_frag_cache_drain(rx_buffer->page,
151
+
rx_buffer->pagecnt_bias);
152
+
}
153
+
154
+
/* clear contents of rx_buffer */
155
+
rx_buffer->page = NULL;
156
+
rx_buffer->skb = NULL;
157
+
}
158
+
159
+
static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
160
+
struct wx_rx_buffer *rx_buffer,
161
+
union wx_rx_desc *rx_desc)
162
+
{
163
+
unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
164
+
#if (PAGE_SIZE < 8192)
165
+
unsigned int truesize = WX_RX_BUFSZ;
166
+
#else
167
+
unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
168
+
#endif
169
+
struct sk_buff *skb = rx_buffer->skb;
170
+
171
+
if (!skb) {
172
+
void *page_addr = page_address(rx_buffer->page) +
173
+
rx_buffer->page_offset;
174
+
175
+
/* prefetch first cache line of first page */
176
+
prefetch(page_addr);
177
+
#if L1_CACHE_BYTES < 128
178
+
prefetch(page_addr + L1_CACHE_BYTES);
179
+
#endif
180
+
181
+
/* allocate a skb to store the frags */
182
+
skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256);
183
+
if (unlikely(!skb))
184
+
return NULL;
185
+
186
+
/* we will be copying header into skb->data in
187
+
* pskb_may_pull so it is in our interest to prefetch
188
+
* it now to avoid a possible cache miss
189
+
*/
190
+
prefetchw(skb->data);
191
+
192
+
if (size <= WX_RXBUFFER_256) {
193
+
memcpy(__skb_put(skb, size), page_addr,
194
+
ALIGN(size, sizeof(long)));
195
+
rx_buffer->pagecnt_bias++;
196
+
197
+
return skb;
198
+
}
199
+
200
+
if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))
201
+
WX_CB(skb)->dma = rx_buffer->dma;
202
+
203
+
skb_add_rx_frag(skb, 0, rx_buffer->page,
204
+
rx_buffer->page_offset,
205
+
size, truesize);
206
+
goto out;
207
+
208
+
} else {
209
+
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
210
+
rx_buffer->page_offset, size, truesize);
211
+
}
212
+
213
+
out:
214
+
#if (PAGE_SIZE < 8192)
215
+
/* flip page offset to other buffer */
216
+
rx_buffer->page_offset ^= truesize;
217
+
#else
218
+
/* move offset up to the next cache line */
219
+
rx_buffer->page_offset += truesize;
220
+
#endif
221
+
222
+
return skb;
223
+
}
224
+
225
+
static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,
226
+
struct wx_rx_buffer *bi)
227
+
{
228
+
struct page *page = bi->page;
229
+
dma_addr_t dma;
230
+
231
+
/* since we are recycling buffers we should seldom need to alloc */
232
+
if (likely(page))
233
+
return true;
234
+
235
+
page = page_pool_dev_alloc_pages(rx_ring->page_pool);
236
+
WARN_ON(!page);
237
+
dma = page_pool_get_dma_addr(page);
238
+
239
+
bi->page_dma = dma;
240
+
bi->page = page;
241
+
bi->page_offset = 0;
242
+
page_ref_add(page, USHRT_MAX - 1);
243
+
bi->pagecnt_bias = USHRT_MAX;
244
+
245
+
return true;
246
+
}
247
+
248
+
/**
249
+
* wx_alloc_rx_buffers - Replace used receive buffers
250
+
* @rx_ring: ring to place buffers on
251
+
* @cleaned_count: number of buffers to replace
252
+
**/
253
+
void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
254
+
{
255
+
u16 i = rx_ring->next_to_use;
256
+
union wx_rx_desc *rx_desc;
257
+
struct wx_rx_buffer *bi;
258
+
259
+
/* nothing to do */
260
+
if (!cleaned_count)
261
+
return;
262
+
263
+
rx_desc = WX_RX_DESC(rx_ring, i);
264
+
bi = &rx_ring->rx_buffer_info[i];
265
+
i -= rx_ring->count;
266
+
267
+
do {
268
+
if (!wx_alloc_mapped_page(rx_ring, bi))
269
+
break;
270
+
271
+
/* sync the buffer for use by the device */
272
+
dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
273
+
bi->page_offset,
274
+
WX_RX_BUFSZ,
275
+
DMA_FROM_DEVICE);
276
+
277
+
rx_desc->read.pkt_addr =
278
+
cpu_to_le64(bi->page_dma + bi->page_offset);
279
+
280
+
rx_desc++;
281
+
bi++;
282
+
i++;
283
+
if (unlikely(!i)) {
284
+
rx_desc = WX_RX_DESC(rx_ring, 0);
285
+
bi = rx_ring->rx_buffer_info;
286
+
i -= rx_ring->count;
287
+
}
288
+
289
+
/* clear the status bits for the next_to_use descriptor */
290
+
rx_desc->wb.upper.status_error = 0;
291
+
292
+
cleaned_count--;
293
+
} while (cleaned_count);
294
+
295
+
i += rx_ring->count;
296
+
297
+
if (rx_ring->next_to_use != i) {
298
+
rx_ring->next_to_use = i;
299
+
/* update next to alloc since we have filled the ring */
300
+
rx_ring->next_to_alloc = i;
301
+
302
+
/* Force memory writes to complete before letting h/w
303
+
* know there are new descriptors to fetch. (Only
304
+
* applicable for weak-ordered memory model archs,
305
+
* such as IA-64).
306
+
*/
307
+
wmb();
308
+
writel(i, rx_ring->tail);
309
+
}
310
+
}
311
+
312
+
u16 wx_desc_unused(struct wx_ring *ring)
313
+
{
314
+
u16 ntc = ring->next_to_clean;
315
+
u16 ntu = ring->next_to_use;
316
+
317
+
return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
318
+
}
319
+
320
+
/**
321
+
* wx_is_non_eop - process handling of non-EOP buffers
322
+
* @rx_ring: Rx ring being processed
323
+
* @rx_desc: Rx descriptor for current buffer
324
+
* @skb: Current socket buffer containing buffer in progress
325
+
*
326
+
* This function updates next to clean. If the buffer is an EOP buffer
327
+
* this function exits returning false, otherwise it will place the
328
+
* sk_buff in the next buffer to be chained and return true indicating
329
+
* that this is in fact a non-EOP buffer.
330
+
**/
331
+
static bool wx_is_non_eop(struct wx_ring *rx_ring,
332
+
union wx_rx_desc *rx_desc,
333
+
struct sk_buff *skb)
334
+
{
335
+
u32 ntc = rx_ring->next_to_clean + 1;
336
+
337
+
/* fetch, update, and store next to clean */
338
+
ntc = (ntc < rx_ring->count) ? ntc : 0;
339
+
rx_ring->next_to_clean = ntc;
340
+
341
+
prefetch(WX_RX_DESC(rx_ring, ntc));
342
+
343
+
/* if we are the last buffer then there is nothing else to do */
344
+
if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
345
+
return false;
346
+
347
+
rx_ring->rx_buffer_info[ntc].skb = skb;
348
+
349
+
return true;
350
+
}
351
+
352
+
static void wx_pull_tail(struct sk_buff *skb)
353
+
{
354
+
skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
355
+
unsigned int pull_len;
356
+
unsigned char *va;
357
+
358
+
/* it is valid to use page_address instead of kmap since we are
359
+
* working with pages allocated out of the lomem pool per
360
+
* alloc_page(GFP_ATOMIC)
361
+
*/
362
+
va = skb_frag_address(frag);
363
+
364
+
/* we need the header to contain the greater of either ETH_HLEN or
365
+
* 60 bytes if the skb->len is less than 60 for skb_pad.
366
+
*/
367
+
pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256);
368
+
369
+
/* align pull length to size of long to optimize memcpy performance */
370
+
skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
371
+
372
+
/* update all of the pointers */
373
+
skb_frag_size_sub(frag, pull_len);
374
+
skb_frag_off_add(frag, pull_len);
375
+
skb->data_len -= pull_len;
376
+
skb->tail += pull_len;
377
+
}
378
+
379
+
/**
380
+
* wx_cleanup_headers - Correct corrupted or empty headers
381
+
* @rx_ring: rx descriptor ring packet is being transacted on
382
+
* @rx_desc: pointer to the EOP Rx descriptor
383
+
* @skb: pointer to current skb being fixed
384
+
*
385
+
* Check for corrupted packet headers caused by senders on the local L2
386
+
* embedded NIC switch not setting up their Tx Descriptors right. These
387
+
* should be very rare.
388
+
*
389
+
* Also address the case where we are pulling data in on pages only
390
+
* and as such no data is present in the skb header.
391
+
*
392
+
* In addition if skb is not at least 60 bytes we need to pad it so that
393
+
* it is large enough to qualify as a valid Ethernet frame.
394
+
*
395
+
* Returns true if an error was encountered and skb was freed.
396
+
**/
397
+
static bool wx_cleanup_headers(struct wx_ring *rx_ring,
398
+
union wx_rx_desc *rx_desc,
399
+
struct sk_buff *skb)
400
+
{
401
+
struct net_device *netdev = rx_ring->netdev;
402
+
403
+
/* verify that the packet does not have any known errors */
404
+
if (!netdev ||
405
+
unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) &&
406
+
!(netdev->features & NETIF_F_RXALL))) {
407
+
dev_kfree_skb_any(skb);
408
+
return true;
409
+
}
410
+
411
+
/* place header in linear portion of buffer */
412
+
if (!skb_headlen(skb))
413
+
wx_pull_tail(skb);
414
+
415
+
/* if eth_skb_pad returns an error the skb was freed */
416
+
if (eth_skb_pad(skb))
417
+
return true;
418
+
419
+
return false;
420
+
}
421
+
422
+
/**
423
+
* wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
424
+
* @q_vector: structure containing interrupt and ring information
425
+
* @rx_ring: rx descriptor ring to transact packets on
426
+
* @budget: Total limit on number of packets to process
427
+
*
428
+
* This function provides a "bounce buffer" approach to Rx interrupt
429
+
* processing. The advantage to this is that on systems that have
430
+
* expensive overhead for IOMMU access this provides a means of avoiding
431
+
* it by maintaining the mapping of the page to the system.
432
+
*
433
+
* Returns amount of work completed.
434
+
**/
435
+
static int wx_clean_rx_irq(struct wx_q_vector *q_vector,
436
+
struct wx_ring *rx_ring,
437
+
int budget)
438
+
{
439
+
unsigned int total_rx_bytes = 0, total_rx_packets = 0;
440
+
u16 cleaned_count = wx_desc_unused(rx_ring);
441
+
442
+
do {
443
+
struct wx_rx_buffer *rx_buffer;
444
+
union wx_rx_desc *rx_desc;
445
+
struct sk_buff *skb;
446
+
int rx_buffer_pgcnt;
447
+
448
+
/* return some buffers to hardware, one at a time is too slow */
449
+
if (cleaned_count >= WX_RX_BUFFER_WRITE) {
450
+
wx_alloc_rx_buffers(rx_ring, cleaned_count);
451
+
cleaned_count = 0;
452
+
}
453
+
454
+
rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean);
455
+
if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD))
456
+
break;
457
+
458
+
/* This memory barrier is needed to keep us from reading
459
+
* any other fields out of the rx_desc until we know the
460
+
* descriptor has been written back
461
+
*/
462
+
dma_rmb();
463
+
464
+
rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt);
465
+
466
+
/* retrieve a buffer from the ring */
467
+
skb = wx_build_skb(rx_ring, rx_buffer, rx_desc);
468
+
469
+
/* exit if we failed to retrieve a buffer */
470
+
if (!skb) {
471
+
rx_buffer->pagecnt_bias++;
472
+
break;
473
+
}
474
+
475
+
wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
476
+
cleaned_count++;
477
+
478
+
/* place incomplete frames back on ring for completion */
479
+
if (wx_is_non_eop(rx_ring, rx_desc, skb))
480
+
continue;
481
+
482
+
/* verify the packet layout is correct */
483
+
if (wx_cleanup_headers(rx_ring, rx_desc, skb))
484
+
continue;
485
+
486
+
/* probably a little skewed due to removing CRC */
487
+
total_rx_bytes += skb->len;
488
+
489
+
skb_record_rx_queue(skb, rx_ring->queue_index);
490
+
skb->protocol = eth_type_trans(skb, rx_ring->netdev);
491
+
napi_gro_receive(&q_vector->napi, skb);
492
+
493
+
/* update budget accounting */
494
+
total_rx_packets++;
495
+
} while (likely(total_rx_packets < budget));
496
+
497
+
u64_stats_update_begin(&rx_ring->syncp);
498
+
rx_ring->stats.packets += total_rx_packets;
499
+
rx_ring->stats.bytes += total_rx_bytes;
500
+
u64_stats_update_end(&rx_ring->syncp);
501
+
q_vector->rx.total_packets += total_rx_packets;
502
+
q_vector->rx.total_bytes += total_rx_bytes;
503
+
504
+
return total_rx_packets;
505
+
}
506
+
507
+
static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring)
508
+
{
509
+
return netdev_get_tx_queue(ring->netdev, ring->queue_index);
510
+
}
511
+
512
+
/**
513
+
* wx_clean_tx_irq - Reclaim resources after transmit completes
514
+
* @q_vector: structure containing interrupt and ring information
515
+
* @tx_ring: tx ring to clean
516
+
* @napi_budget: Used to determine if we are in netpoll
517
+
**/
518
+
static bool wx_clean_tx_irq(struct wx_q_vector *q_vector,
519
+
struct wx_ring *tx_ring, int napi_budget)
520
+
{
521
+
unsigned int budget = q_vector->wx->tx_work_limit;
522
+
unsigned int total_bytes = 0, total_packets = 0;
523
+
unsigned int i = tx_ring->next_to_clean;
524
+
struct wx_tx_buffer *tx_buffer;
525
+
union wx_tx_desc *tx_desc;
526
+
527
+
if (!netif_carrier_ok(tx_ring->netdev))
528
+
return true;
529
+
530
+
tx_buffer = &tx_ring->tx_buffer_info[i];
531
+
tx_desc = WX_TX_DESC(tx_ring, i);
532
+
i -= tx_ring->count;
533
+
534
+
do {
535
+
union wx_tx_desc *eop_desc = tx_buffer->next_to_watch;
536
+
537
+
/* if next_to_watch is not set then there is no work pending */
538
+
if (!eop_desc)
539
+
break;
540
+
541
+
/* prevent any other reads prior to eop_desc */
542
+
smp_rmb();
543
+
544
+
/* if DD is not set pending work has not been completed */
545
+
if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD)))
546
+
break;
547
+
548
+
/* clear next_to_watch to prevent false hangs */
549
+
tx_buffer->next_to_watch = NULL;
550
+
551
+
/* update the statistics for this packet */
552
+
total_bytes += tx_buffer->bytecount;
553
+
total_packets += tx_buffer->gso_segs;
554
+
555
+
/* free the skb */
556
+
napi_consume_skb(tx_buffer->skb, napi_budget);
557
+
558
+
/* unmap skb header data */
559
+
dma_unmap_single(tx_ring->dev,
560
+
dma_unmap_addr(tx_buffer, dma),
561
+
dma_unmap_len(tx_buffer, len),
562
+
DMA_TO_DEVICE);
563
+
564
+
/* clear tx_buffer data */
565
+
dma_unmap_len_set(tx_buffer, len, 0);
566
+
567
+
/* unmap remaining buffers */
568
+
while (tx_desc != eop_desc) {
569
+
tx_buffer++;
570
+
tx_desc++;
571
+
i++;
572
+
if (unlikely(!i)) {
573
+
i -= tx_ring->count;
574
+
tx_buffer = tx_ring->tx_buffer_info;
575
+
tx_desc = WX_TX_DESC(tx_ring, 0);
576
+
}
577
+
578
+
/* unmap any remaining paged data */
579
+
if (dma_unmap_len(tx_buffer, len)) {
580
+
dma_unmap_page(tx_ring->dev,
581
+
dma_unmap_addr(tx_buffer, dma),
582
+
dma_unmap_len(tx_buffer, len),
583
+
DMA_TO_DEVICE);
584
+
dma_unmap_len_set(tx_buffer, len, 0);
585
+
}
586
+
}
587
+
588
+
/* move us one more past the eop_desc for start of next pkt */
589
+
tx_buffer++;
590
+
tx_desc++;
591
+
i++;
592
+
if (unlikely(!i)) {
593
+
i -= tx_ring->count;
594
+
tx_buffer = tx_ring->tx_buffer_info;
595
+
tx_desc = WX_TX_DESC(tx_ring, 0);
596
+
}
597
+
598
+
/* issue prefetch for next Tx descriptor */
599
+
prefetch(tx_desc);
600
+
601
+
/* update budget accounting */
602
+
budget--;
603
+
} while (likely(budget));
604
+
605
+
i += tx_ring->count;
606
+
tx_ring->next_to_clean = i;
607
+
u64_stats_update_begin(&tx_ring->syncp);
608
+
tx_ring->stats.bytes += total_bytes;
609
+
tx_ring->stats.packets += total_packets;
610
+
u64_stats_update_end(&tx_ring->syncp);
611
+
q_vector->tx.total_bytes += total_bytes;
612
+
q_vector->tx.total_packets += total_packets;
613
+
614
+
netdev_tx_completed_queue(wx_txring_txq(tx_ring),
615
+
total_packets, total_bytes);
616
+
617
+
#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
618
+
if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
619
+
(wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
620
+
/* Make sure that anybody stopping the queue after this
621
+
* sees the new next_to_clean.
622
+
*/
623
+
smp_mb();
624
+
625
+
if (__netif_subqueue_stopped(tx_ring->netdev,
626
+
tx_ring->queue_index) &&
627
+
netif_running(tx_ring->netdev))
628
+
netif_wake_subqueue(tx_ring->netdev,
629
+
tx_ring->queue_index);
630
+
}
631
+
632
+
return !!budget;
633
+
}
634
+
635
+
/**
636
+
* wx_poll - NAPI polling RX/TX cleanup routine
637
+
* @napi: napi struct with our devices info in it
638
+
* @budget: amount of work driver is allowed to do this pass, in packets
639
+
*
640
+
* This function will clean all queues associated with a q_vector.
641
+
**/
642
+
static int wx_poll(struct napi_struct *napi, int budget)
643
+
{
644
+
struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi);
645
+
int per_ring_budget, work_done = 0;
646
+
struct wx *wx = q_vector->wx;
647
+
bool clean_complete = true;
648
+
struct wx_ring *ring;
649
+
650
+
wx_for_each_ring(ring, q_vector->tx) {
651
+
if (!wx_clean_tx_irq(q_vector, ring, budget))
652
+
clean_complete = false;
653
+
}
654
+
655
+
/* Exit if we are called by netpoll */
656
+
if (budget <= 0)
657
+
return budget;
658
+
659
+
/* attempt to distribute budget to each queue fairly, but don't allow
660
+
* the budget to go below 1 because we'll exit polling
661
+
*/
662
+
if (q_vector->rx.count > 1)
663
+
per_ring_budget = max(budget / q_vector->rx.count, 1);
664
+
else
665
+
per_ring_budget = budget;
666
+
667
+
wx_for_each_ring(ring, q_vector->rx) {
668
+
int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget);
669
+
670
+
work_done += cleaned;
671
+
if (cleaned >= per_ring_budget)
672
+
clean_complete = false;
673
+
}
674
+
675
+
/* If all work not completed, return budget and keep polling */
676
+
if (!clean_complete)
677
+
return budget;
678
+
679
+
/* all work done, exit the polling mode */
680
+
if (likely(napi_complete_done(napi, work_done))) {
681
+
if (netif_running(wx->netdev))
682
+
wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx));
683
+
};
684
+
685
+
return min(work_done, budget - 1);
686
+
}
687
+
688
+
static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size)
689
+
{
690
+
if (likely(wx_desc_unused(tx_ring) >= size))
691
+
return 0;
692
+
693
+
netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
694
+
695
+
/* For the next check */
696
+
smp_mb();
697
+
698
+
/* We need to check again in a case another CPU has just
699
+
* made room available.
700
+
*/
701
+
if (likely(wx_desc_unused(tx_ring) < size))
702
+
return -EBUSY;
703
+
704
+
/* A reprieve! - use start_queue because it doesn't call schedule */
705
+
netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
706
+
707
+
return 0;
708
+
}
709
+
710
+
static void wx_tx_map(struct wx_ring *tx_ring,
711
+
struct wx_tx_buffer *first)
712
+
{
713
+
struct sk_buff *skb = first->skb;
714
+
struct wx_tx_buffer *tx_buffer;
715
+
u16 i = tx_ring->next_to_use;
716
+
unsigned int data_len, size;
717
+
union wx_tx_desc *tx_desc;
718
+
skb_frag_t *frag;
719
+
dma_addr_t dma;
720
+
u32 cmd_type;
721
+
722
+
cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS;
723
+
tx_desc = WX_TX_DESC(tx_ring, i);
724
+
725
+
tx_desc->read.olinfo_status = cpu_to_le32(skb->len << WX_TXD_PAYLEN_SHIFT);
726
+
727
+
size = skb_headlen(skb);
728
+
data_len = skb->data_len;
729
+
dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
730
+
731
+
tx_buffer = first;
732
+
733
+
for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
734
+
if (dma_mapping_error(tx_ring->dev, dma))
735
+
goto dma_error;
736
+
737
+
/* record length, and DMA address */
738
+
dma_unmap_len_set(tx_buffer, len, size);
739
+
dma_unmap_addr_set(tx_buffer, dma, dma);
740
+
741
+
tx_desc->read.buffer_addr = cpu_to_le64(dma);
742
+
743
+
while (unlikely(size > WX_MAX_DATA_PER_TXD)) {
744
+
tx_desc->read.cmd_type_len =
745
+
cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD);
746
+
747
+
i++;
748
+
tx_desc++;
749
+
if (i == tx_ring->count) {
750
+
tx_desc = WX_TX_DESC(tx_ring, 0);
751
+
i = 0;
752
+
}
753
+
tx_desc->read.olinfo_status = 0;
754
+
755
+
dma += WX_MAX_DATA_PER_TXD;
756
+
size -= WX_MAX_DATA_PER_TXD;
757
+
758
+
tx_desc->read.buffer_addr = cpu_to_le64(dma);
759
+
}
760
+
761
+
if (likely(!data_len))
762
+
break;
763
+
764
+
tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
765
+
766
+
i++;
767
+
tx_desc++;
768
+
if (i == tx_ring->count) {
769
+
tx_desc = WX_TX_DESC(tx_ring, 0);
770
+
i = 0;
771
+
}
772
+
tx_desc->read.olinfo_status = 0;
773
+
774
+
size = skb_frag_size(frag);
775
+
776
+
data_len -= size;
777
+
778
+
dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
779
+
DMA_TO_DEVICE);
780
+
781
+
tx_buffer = &tx_ring->tx_buffer_info[i];
782
+
}
783
+
784
+
/* write last descriptor with RS and EOP bits */
785
+
cmd_type |= size | WX_TXD_EOP | WX_TXD_RS;
786
+
tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
787
+
788
+
netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount);
789
+
790
+
skb_tx_timestamp(skb);
791
+
792
+
/* Force memory writes to complete before letting h/w know there
793
+
* are new descriptors to fetch. (Only applicable for weak-ordered
794
+
* memory model archs, such as IA-64).
795
+
*
796
+
* We also need this memory barrier to make certain all of the
797
+
* status bits have been updated before next_to_watch is written.
798
+
*/
799
+
wmb();
800
+
801
+
/* set next_to_watch value indicating a packet is present */
802
+
first->next_to_watch = tx_desc;
803
+
804
+
i++;
805
+
if (i == tx_ring->count)
806
+
i = 0;
807
+
808
+
tx_ring->next_to_use = i;
809
+
810
+
wx_maybe_stop_tx(tx_ring, DESC_NEEDED);
811
+
812
+
if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more())
813
+
writel(i, tx_ring->tail);
814
+
815
+
return;
816
+
dma_error:
817
+
dev_err(tx_ring->dev, "TX DMA map failed\n");
818
+
819
+
/* clear dma mappings for failed tx_buffer_info map */
820
+
for (;;) {
821
+
tx_buffer = &tx_ring->tx_buffer_info[i];
822
+
if (dma_unmap_len(tx_buffer, len))
823
+
dma_unmap_page(tx_ring->dev,
824
+
dma_unmap_addr(tx_buffer, dma),
825
+
dma_unmap_len(tx_buffer, len),
826
+
DMA_TO_DEVICE);
827
+
dma_unmap_len_set(tx_buffer, len, 0);
828
+
if (tx_buffer == first)
829
+
break;
830
+
if (i == 0)
831
+
i += tx_ring->count;
832
+
i--;
833
+
}
834
+
835
+
dev_kfree_skb_any(first->skb);
836
+
first->skb = NULL;
837
+
838
+
tx_ring->next_to_use = i;
839
+
}
840
+
841
+
static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb,
842
+
struct wx_ring *tx_ring)
843
+
{
844
+
u16 count = TXD_USE_COUNT(skb_headlen(skb));
845
+
struct wx_tx_buffer *first;
846
+
unsigned short f;
847
+
848
+
/* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD,
849
+
* + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD,
850
+
* + 2 desc gap to keep tail from touching head,
851
+
* + 1 desc for context descriptor,
852
+
* otherwise try next time
853
+
*/
854
+
for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
855
+
count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->
856
+
frags[f]));
857
+
858
+
if (wx_maybe_stop_tx(tx_ring, count + 3))
859
+
return NETDEV_TX_BUSY;
860
+
861
+
/* record the location of the first descriptor for this packet */
862
+
first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
863
+
first->skb = skb;
864
+
first->bytecount = skb->len;
865
+
first->gso_segs = 1;
866
+
867
+
wx_tx_map(tx_ring, first);
868
+
869
+
return NETDEV_TX_OK;
870
+
}
871
+
872
+
netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
873
+
struct net_device *netdev)
874
+
{
875
+
unsigned int r_idx = skb->queue_mapping;
876
+
struct wx *wx = netdev_priv(netdev);
877
+
struct wx_ring *tx_ring;
878
+
879
+
if (!netif_carrier_ok(netdev)) {
880
+
dev_kfree_skb_any(skb);
881
+
return NETDEV_TX_OK;
882
+
}
883
+
884
+
/* The minimum packet size for olinfo paylen is 17 so pad the skb
885
+
* in order to meet this minimum size requirement.
886
+
*/
887
+
if (skb_put_padto(skb, 17))
888
+
return NETDEV_TX_OK;
889
+
890
+
if (r_idx >= wx->num_tx_queues)
891
+
r_idx = r_idx % wx->num_tx_queues;
892
+
tx_ring = wx->tx_ring[r_idx];
893
+
894
+
return wx_xmit_frame_ring(skb, tx_ring);
895
+
}
896
+
EXPORT_SYMBOL(wx_xmit_frame);
897
+
898
+
void wx_napi_enable_all(struct wx *wx)
899
+
{
900
+
struct wx_q_vector *q_vector;
901
+
int q_idx;
902
+
903
+
for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
904
+
q_vector = wx->q_vector[q_idx];
905
+
napi_enable(&q_vector->napi);
906
+
}
907
+
}
908
+
EXPORT_SYMBOL(wx_napi_enable_all);
909
+
910
+
void wx_napi_disable_all(struct wx *wx)
911
+
{
912
+
struct wx_q_vector *q_vector;
913
+
int q_idx;
914
+
915
+
for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
916
+
q_vector = wx->q_vector[q_idx];
917
+
napi_disable(&q_vector->napi);
918
+
}
919
+
}
920
+
EXPORT_SYMBOL(wx_napi_disable_all);
921
+
922
+
/**
923
+
* wx_set_rss_queues: Allocate queues for RSS
924
+
* @wx: board private structure to initialize
925
+
*
926
+
* This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
927
+
* to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
928
+
*
929
+
**/
930
+
static void wx_set_rss_queues(struct wx *wx)
931
+
{
932
+
wx->num_rx_queues = wx->mac.max_rx_queues;
933
+
wx->num_tx_queues = wx->mac.max_tx_queues;
934
+
}
935
+
936
+
static void wx_set_num_queues(struct wx *wx)
937
+
{
938
+
/* Start with base case */
939
+
wx->num_rx_queues = 1;
940
+
wx->num_tx_queues = 1;
941
+
wx->queues_per_pool = 1;
942
+
943
+
wx_set_rss_queues(wx);
944
+
}
945
+
946
+
/**
947
+
* wx_acquire_msix_vectors - acquire MSI-X vectors
948
+
* @wx: board private structure
949
+
*
950
+
* Attempts to acquire a suitable range of MSI-X vector interrupts. Will
951
+
* return a negative error code if unable to acquire MSI-X vectors for any
952
+
* reason.
953
+
*/
954
+
static int wx_acquire_msix_vectors(struct wx *wx)
955
+
{
956
+
struct irq_affinity affd = {0, };
957
+
int nvecs, i;
958
+
959
+
nvecs = min_t(int, num_online_cpus(), wx->mac.max_msix_vectors);
960
+
961
+
wx->msix_entries = kcalloc(nvecs,
962
+
sizeof(struct msix_entry),
963
+
GFP_KERNEL);
964
+
if (!wx->msix_entries)
965
+
return -ENOMEM;
966
+
967
+
nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs,
968
+
nvecs,
969
+
PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
970
+
&affd);
971
+
if (nvecs < 0) {
972
+
wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);
973
+
kfree(wx->msix_entries);
974
+
wx->msix_entries = NULL;
975
+
return nvecs;
976
+
}
977
+
978
+
for (i = 0; i < nvecs; i++) {
979
+
wx->msix_entries[i].entry = i;
980
+
wx->msix_entries[i].vector = pci_irq_vector(wx->pdev, i);
981
+
}
982
+
983
+
/* one for msix_other */
984
+
nvecs -= 1;
985
+
wx->num_q_vectors = nvecs;
986
+
wx->num_rx_queues = nvecs;
987
+
wx->num_tx_queues = nvecs;
988
+
989
+
return 0;
990
+
}
991
+
992
+
/**
993
+
* wx_set_interrupt_capability - set MSI-X or MSI if supported
994
+
* @wx: board private structure to initialize
995
+
*
996
+
* Attempt to configure the interrupts using the best available
997
+
* capabilities of the hardware and the kernel.
998
+
**/
999
+
static int wx_set_interrupt_capability(struct wx *wx)
1000
+
{
1001
+
struct pci_dev *pdev = wx->pdev;
1002
+
int nvecs, ret;
1003
+
1004
+
/* We will try to get MSI-X interrupts first */
1005
+
ret = wx_acquire_msix_vectors(wx);
1006
+
if (ret == 0 || (ret == -ENOMEM))
1007
+
return ret;
1008
+
1009
+
wx->num_rx_queues = 1;
1010
+
wx->num_tx_queues = 1;
1011
+
wx->num_q_vectors = 1;
1012
+
1013
+
/* minmum one for queue, one for misc*/
1014
+
nvecs = 1;
1015
+
nvecs = pci_alloc_irq_vectors(pdev, nvecs,
1016
+
nvecs, PCI_IRQ_MSI | PCI_IRQ_LEGACY);
1017
+
if (nvecs == 1) {
1018
+
if (pdev->msi_enabled)
1019
+
wx_err(wx, "Fallback to MSI.\n");
1020
+
else
1021
+
wx_err(wx, "Fallback to LEGACY.\n");
1022
+
} else {
1023
+
wx_err(wx, "Failed to allocate MSI/LEGACY interrupts. Error: %d\n", nvecs);
1024
+
return nvecs;
1025
+
}
1026
+
1027
+
pdev->irq = pci_irq_vector(pdev, 0);
1028
+
1029
+
return 0;
1030
+
}
1031
+
1032
+
/**
1033
+
* wx_cache_ring_rss - Descriptor ring to register mapping for RSS
1034
+
* @wx: board private structure to initialize
1035
+
*
1036
+
* Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV.
1037
+
*
1038
+
**/
1039
+
static void wx_cache_ring_rss(struct wx *wx)
1040
+
{
1041
+
u16 i;
1042
+
1043
+
for (i = 0; i < wx->num_rx_queues; i++)
1044
+
wx->rx_ring[i]->reg_idx = i;
1045
+
1046
+
for (i = 0; i < wx->num_tx_queues; i++)
1047
+
wx->tx_ring[i]->reg_idx = i;
1048
+
}
1049
+
1050
+
static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head)
1051
+
{
1052
+
ring->next = head->ring;
1053
+
head->ring = ring;
1054
+
head->count++;
1055
+
}
1056
+
1057
+
/**
1058
+
* wx_alloc_q_vector - Allocate memory for a single interrupt vector
1059
+
* @wx: board private structure to initialize
1060
+
* @v_count: q_vectors allocated on wx, used for ring interleaving
1061
+
* @v_idx: index of vector in wx struct
1062
+
* @txr_count: total number of Tx rings to allocate
1063
+
* @txr_idx: index of first Tx ring to allocate
1064
+
* @rxr_count: total number of Rx rings to allocate
1065
+
* @rxr_idx: index of first Rx ring to allocate
1066
+
*
1067
+
* We allocate one q_vector. If allocation fails we return -ENOMEM.
1068
+
**/
1069
+
static int wx_alloc_q_vector(struct wx *wx,
1070
+
unsigned int v_count, unsigned int v_idx,
1071
+
unsigned int txr_count, unsigned int txr_idx,
1072
+
unsigned int rxr_count, unsigned int rxr_idx)
1073
+
{
1074
+
struct wx_q_vector *q_vector;
1075
+
int ring_count, default_itr;
1076
+
struct wx_ring *ring;
1077
+
1078
+
/* note this will allocate space for the ring structure as well! */
1079
+
ring_count = txr_count + rxr_count;
1080
+
1081
+
q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
1082
+
GFP_KERNEL);
1083
+
if (!q_vector)
1084
+
return -ENOMEM;
1085
+
1086
+
/* initialize NAPI */
1087
+
netif_napi_add(wx->netdev, &q_vector->napi,
1088
+
wx_poll);
1089
+
1090
+
/* tie q_vector and wx together */
1091
+
wx->q_vector[v_idx] = q_vector;
1092
+
q_vector->wx = wx;
1093
+
q_vector->v_idx = v_idx;
1094
+
if (cpu_online(v_idx))
1095
+
q_vector->numa_node = cpu_to_node(v_idx);
1096
+
1097
+
/* initialize pointer to rings */
1098
+
ring = q_vector->ring;
1099
+
1100
+
if (wx->mac.type == wx_mac_sp)
1101
+
default_itr = WX_12K_ITR;
1102
+
else
1103
+
default_itr = WX_7K_ITR;
1104
+
/* initialize ITR */
1105
+
if (txr_count && !rxr_count)
1106
+
/* tx only vector */
1107
+
q_vector->itr = wx->tx_itr_setting ?
1108
+
default_itr : wx->tx_itr_setting;
1109
+
else
1110
+
/* rx or rx/tx vector */
1111
+
q_vector->itr = wx->rx_itr_setting ?
1112
+
default_itr : wx->rx_itr_setting;
1113
+
1114
+
while (txr_count) {
1115
+
/* assign generic ring traits */
1116
+
ring->dev = &wx->pdev->dev;
1117
+
ring->netdev = wx->netdev;
1118
+
1119
+
/* configure backlink on ring */
1120
+
ring->q_vector = q_vector;
1121
+
1122
+
/* update q_vector Tx values */
1123
+
wx_add_ring(ring, &q_vector->tx);
1124
+
1125
+
/* apply Tx specific ring traits */
1126
+
ring->count = wx->tx_ring_count;
1127
+
1128
+
ring->queue_index = txr_idx;
1129
+
1130
+
/* assign ring to wx */
1131
+
wx->tx_ring[txr_idx] = ring;
1132
+
1133
+
/* update count and index */
1134
+
txr_count--;
1135
+
txr_idx += v_count;
1136
+
1137
+
/* push pointer to next ring */
1138
+
ring++;
1139
+
}
1140
+
1141
+
while (rxr_count) {
1142
+
/* assign generic ring traits */
1143
+
ring->dev = &wx->pdev->dev;
1144
+
ring->netdev = wx->netdev;
1145
+
1146
+
/* configure backlink on ring */
1147
+
ring->q_vector = q_vector;
1148
+
1149
+
/* update q_vector Rx values */
1150
+
wx_add_ring(ring, &q_vector->rx);
1151
+
1152
+
/* apply Rx specific ring traits */
1153
+
ring->count = wx->rx_ring_count;
1154
+
ring->queue_index = rxr_idx;
1155
+
1156
+
/* assign ring to wx */
1157
+
wx->rx_ring[rxr_idx] = ring;
1158
+
1159
+
/* update count and index */
1160
+
rxr_count--;
1161
+
rxr_idx += v_count;
1162
+
1163
+
/* push pointer to next ring */
1164
+
ring++;
1165
+
}
1166
+
1167
+
return 0;
1168
+
}
1169
+
1170
+
/**
1171
+
* wx_free_q_vector - Free memory allocated for specific interrupt vector
1172
+
* @wx: board private structure to initialize
1173
+
* @v_idx: Index of vector to be freed
1174
+
*
1175
+
* This function frees the memory allocated to the q_vector. In addition if
1176
+
* NAPI is enabled it will delete any references to the NAPI struct prior
1177
+
* to freeing the q_vector.
1178
+
**/
1179
+
static void wx_free_q_vector(struct wx *wx, int v_idx)
1180
+
{
1181
+
struct wx_q_vector *q_vector = wx->q_vector[v_idx];
1182
+
struct wx_ring *ring;
1183
+
1184
+
wx_for_each_ring(ring, q_vector->tx)
1185
+
wx->tx_ring[ring->queue_index] = NULL;
1186
+
1187
+
wx_for_each_ring(ring, q_vector->rx)
1188
+
wx->rx_ring[ring->queue_index] = NULL;
1189
+
1190
+
wx->q_vector[v_idx] = NULL;
1191
+
netif_napi_del(&q_vector->napi);
1192
+
kfree_rcu(q_vector, rcu);
1193
+
}
1194
+
1195
+
/**
1196
+
* wx_alloc_q_vectors - Allocate memory for interrupt vectors
1197
+
* @wx: board private structure to initialize
1198
+
*
1199
+
* We allocate one q_vector per queue interrupt. If allocation fails we
1200
+
* return -ENOMEM.
1201
+
**/
1202
+
static int wx_alloc_q_vectors(struct wx *wx)
1203
+
{
1204
+
unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1205
+
unsigned int rxr_remaining = wx->num_rx_queues;
1206
+
unsigned int txr_remaining = wx->num_tx_queues;
1207
+
unsigned int q_vectors = wx->num_q_vectors;
1208
+
int rqpv, tqpv;
1209
+
int err;
1210
+
1211
+
for (; v_idx < q_vectors; v_idx++) {
1212
+
rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1213
+
tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1214
+
err = wx_alloc_q_vector(wx, q_vectors, v_idx,
1215
+
tqpv, txr_idx,
1216
+
rqpv, rxr_idx);
1217
+
1218
+
if (err)
1219
+
goto err_out;
1220
+
1221
+
/* update counts and index */
1222
+
rxr_remaining -= rqpv;
1223
+
txr_remaining -= tqpv;
1224
+
rxr_idx++;
1225
+
txr_idx++;
1226
+
}
1227
+
1228
+
return 0;
1229
+
1230
+
err_out:
1231
+
wx->num_tx_queues = 0;
1232
+
wx->num_rx_queues = 0;
1233
+
wx->num_q_vectors = 0;
1234
+
1235
+
while (v_idx--)
1236
+
wx_free_q_vector(wx, v_idx);
1237
+
1238
+
return -ENOMEM;
1239
+
}
1240
+
1241
+
/**
1242
+
* wx_free_q_vectors - Free memory allocated for interrupt vectors
1243
+
* @wx: board private structure to initialize
1244
+
*
1245
+
* This function frees the memory allocated to the q_vectors. In addition if
1246
+
* NAPI is enabled it will delete any references to the NAPI struct prior
1247
+
* to freeing the q_vector.
1248
+
**/
1249
+
static void wx_free_q_vectors(struct wx *wx)
1250
+
{
1251
+
int v_idx = wx->num_q_vectors;
1252
+
1253
+
wx->num_tx_queues = 0;
1254
+
wx->num_rx_queues = 0;
1255
+
wx->num_q_vectors = 0;
1256
+
1257
+
while (v_idx--)
1258
+
wx_free_q_vector(wx, v_idx);
1259
+
}
1260
+
1261
+
void wx_reset_interrupt_capability(struct wx *wx)
1262
+
{
1263
+
struct pci_dev *pdev = wx->pdev;
1264
+
1265
+
if (!pdev->msi_enabled && !pdev->msix_enabled)
1266
+
return;
1267
+
1268
+
pci_free_irq_vectors(wx->pdev);
1269
+
if (pdev->msix_enabled) {
1270
+
kfree(wx->msix_entries);
1271
+
wx->msix_entries = NULL;
1272
+
}
1273
+
}
1274
+
EXPORT_SYMBOL(wx_reset_interrupt_capability);
1275
+
1276
+
/**
1277
+
* wx_clear_interrupt_scheme - Clear the current interrupt scheme settings
1278
+
* @wx: board private structure to clear interrupt scheme on
1279
+
*
1280
+
* We go through and clear interrupt specific resources and reset the structure
1281
+
* to pre-load conditions
1282
+
**/
1283
+
void wx_clear_interrupt_scheme(struct wx *wx)
1284
+
{
1285
+
wx_free_q_vectors(wx);
1286
+
wx_reset_interrupt_capability(wx);
1287
+
}
1288
+
EXPORT_SYMBOL(wx_clear_interrupt_scheme);
1289
+
1290
+
int wx_init_interrupt_scheme(struct wx *wx)
1291
+
{
1292
+
int ret;
1293
+
1294
+
/* Number of supported queues */
1295
+
wx_set_num_queues(wx);
1296
+
1297
+
/* Set interrupt mode */
1298
+
ret = wx_set_interrupt_capability(wx);
1299
+
if (ret) {
1300
+
wx_err(wx, "Allocate irq vectors for failed.\n");
1301
+
return ret;
1302
+
}
1303
+
1304
+
/* Allocate memory for queues */
1305
+
ret = wx_alloc_q_vectors(wx);
1306
+
if (ret) {
1307
+
wx_err(wx, "Unable to allocate memory for queue vectors.\n");
1308
+
wx_reset_interrupt_capability(wx);
1309
+
return ret;
1310
+
}
1311
+
1312
+
wx_cache_ring_rss(wx);
1313
+
1314
+
return 0;
1315
+
}
1316
+
EXPORT_SYMBOL(wx_init_interrupt_scheme);
1317
+
1318
+
irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data)
1319
+
{
1320
+
struct wx_q_vector *q_vector = data;
1321
+
1322
+
/* EIAM disabled interrupts (on this vector) for us */
1323
+
if (q_vector->rx.ring || q_vector->tx.ring)
1324
+
napi_schedule_irqoff(&q_vector->napi);
1325
+
1326
+
return IRQ_HANDLED;
1327
+
}
1328
+
EXPORT_SYMBOL(wx_msix_clean_rings);
1329
+
1330
+
void wx_free_irq(struct wx *wx)
1331
+
{
1332
+
struct pci_dev *pdev = wx->pdev;
1333
+
int vector;
1334
+
1335
+
if (!(pdev->msix_enabled)) {
1336
+
free_irq(pdev->irq, wx);
1337
+
return;
1338
+
}
1339
+
1340
+
for (vector = 0; vector < wx->num_q_vectors; vector++) {
1341
+
struct wx_q_vector *q_vector = wx->q_vector[vector];
1342
+
struct msix_entry *entry = &wx->msix_entries[vector];
1343
+
1344
+
/* free only the irqs that were actually requested */
1345
+
if (!q_vector->rx.ring && !q_vector->tx.ring)
1346
+
continue;
1347
+
1348
+
free_irq(entry->vector, q_vector);
1349
+
}
1350
+
1351
+
free_irq(wx->msix_entries[vector].vector, wx);
1352
+
}
1353
+
EXPORT_SYMBOL(wx_free_irq);
1354
+
1355
+
/**
1356
+
* wx_setup_isb_resources - allocate interrupt status resources
1357
+
* @wx: board private structure
1358
+
*
1359
+
* Return 0 on success, negative on failure
1360
+
**/
1361
+
int wx_setup_isb_resources(struct wx *wx)
1362
+
{
1363
+
struct pci_dev *pdev = wx->pdev;
1364
+
1365
+
wx->isb_mem = dma_alloc_coherent(&pdev->dev,
1366
+
sizeof(u32) * 4,
1367
+
&wx->isb_dma,
1368
+
GFP_KERNEL);
1369
+
if (!wx->isb_mem) {
1370
+
wx_err(wx, "Alloc isb_mem failed\n");
1371
+
return -ENOMEM;
1372
+
}
1373
+
1374
+
return 0;
1375
+
}
1376
+
EXPORT_SYMBOL(wx_setup_isb_resources);
1377
+
1378
+
/**
1379
+
* wx_free_isb_resources - allocate all queues Rx resources
1380
+
* @wx: board private structure
1381
+
*
1382
+
* Return 0 on success, negative on failure
1383
+
**/
1384
+
void wx_free_isb_resources(struct wx *wx)
1385
+
{
1386
+
struct pci_dev *pdev = wx->pdev;
1387
+
1388
+
dma_free_coherent(&pdev->dev, sizeof(u32) * 4,
1389
+
wx->isb_mem, wx->isb_dma);
1390
+
wx->isb_mem = NULL;
1391
+
}
1392
+
EXPORT_SYMBOL(wx_free_isb_resources);
1393
+
1394
+
u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx)
1395
+
{
1396
+
u32 cur_tag = 0;
1397
+
1398
+
cur_tag = wx->isb_mem[WX_ISB_HEADER];
1399
+
wx->isb_tag[idx] = cur_tag;
1400
+
1401
+
return (__force u32)cpu_to_le32(wx->isb_mem[idx]);
1402
+
}
1403
+
EXPORT_SYMBOL(wx_misc_isb);
1404
+
1405
+
/**
1406
+
* wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
1407
+
* @wx: pointer to wx struct
1408
+
* @direction: 0 for Rx, 1 for Tx, -1 for other causes
1409
+
* @queue: queue to map the corresponding interrupt to
1410
+
* @msix_vector: the vector to map to the corresponding queue
1411
+
*
1412
+
**/
1413
+
static void wx_set_ivar(struct wx *wx, s8 direction,
1414
+
u16 queue, u16 msix_vector)
1415
+
{
1416
+
u32 ivar, index;
1417
+
1418
+
if (direction == -1) {
1419
+
/* other causes */
1420
+
msix_vector |= WX_PX_IVAR_ALLOC_VAL;
1421
+
index = 0;
1422
+
ivar = rd32(wx, WX_PX_MISC_IVAR);
1423
+
ivar &= ~(0xFF << index);
1424
+
ivar |= (msix_vector << index);
1425
+
wr32(wx, WX_PX_MISC_IVAR, ivar);
1426
+
} else {
1427
+
/* tx or rx causes */
1428
+
msix_vector |= WX_PX_IVAR_ALLOC_VAL;
1429
+
index = ((16 * (queue & 1)) + (8 * direction));
1430
+
ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
1431
+
ivar &= ~(0xFF << index);
1432
+
ivar |= (msix_vector << index);
1433
+
wr32(wx, WX_PX_IVAR(queue >> 1), ivar);
1434
+
}
1435
+
}
1436
+
1437
+
/**
1438
+
* wx_write_eitr - write EITR register in hardware specific way
1439
+
* @q_vector: structure containing interrupt and ring information
1440
+
*
1441
+
* This function is made to be called by ethtool and by the driver
1442
+
* when it needs to update EITR registers at runtime. Hardware
1443
+
* specific quirks/differences are taken care of here.
1444
+
*/
1445
+
static void wx_write_eitr(struct wx_q_vector *q_vector)
1446
+
{
1447
+
struct wx *wx = q_vector->wx;
1448
+
int v_idx = q_vector->v_idx;
1449
+
u32 itr_reg;
1450
+
1451
+
if (wx->mac.type == wx_mac_sp)
1452
+
itr_reg = q_vector->itr & WX_SP_MAX_EITR;
1453
+
else
1454
+
itr_reg = q_vector->itr & WX_EM_MAX_EITR;
1455
+
1456
+
itr_reg |= WX_PX_ITR_CNT_WDIS;
1457
+
1458
+
wr32(wx, WX_PX_ITR(v_idx), itr_reg);
1459
+
}
1460
+
1461
+
/**
1462
+
* wx_configure_vectors - Configure vectors for hardware
1463
+
* @wx: board private structure
1464
+
*
1465
+
* wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/LEGACY
1466
+
* interrupts.
1467
+
**/
1468
+
void wx_configure_vectors(struct wx *wx)
1469
+
{
1470
+
struct pci_dev *pdev = wx->pdev;
1471
+
u32 eitrsel = 0;
1472
+
u16 v_idx;
1473
+
1474
+
if (pdev->msix_enabled) {
1475
+
/* Populate MSIX to EITR Select */
1476
+
wr32(wx, WX_PX_ITRSEL, eitrsel);
1477
+
/* use EIAM to auto-mask when MSI-X interrupt is asserted
1478
+
* this saves a register write for every interrupt
1479
+
*/
1480
+
wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL);
1481
+
} else {
1482
+
/* legacy interrupts, use EIAM to auto-mask when reading EICR,
1483
+
* specifically only auto mask tx and rx interrupts.
1484
+
*/
1485
+
wr32(wx, WX_PX_GPIE, 0);
1486
+
}
1487
+
1488
+
/* Populate the IVAR table and set the ITR values to the
1489
+
* corresponding register.
1490
+
*/
1491
+
for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) {
1492
+
struct wx_q_vector *q_vector = wx->q_vector[v_idx];
1493
+
struct wx_ring *ring;
1494
+
1495
+
wx_for_each_ring(ring, q_vector->rx)
1496
+
wx_set_ivar(wx, 0, ring->reg_idx, v_idx);
1497
+
1498
+
wx_for_each_ring(ring, q_vector->tx)
1499
+
wx_set_ivar(wx, 1, ring->reg_idx, v_idx);
1500
+
1501
+
wx_write_eitr(q_vector);
1502
+
}
1503
+
1504
+
wx_set_ivar(wx, -1, 0, v_idx);
1505
+
if (pdev->msix_enabled)
1506
+
wr32(wx, WX_PX_ITR(v_idx), 1950);
1507
+
}
1508
+
EXPORT_SYMBOL(wx_configure_vectors);
1509
+
1510
+
/**
1511
+
* wx_clean_rx_ring - Free Rx Buffers per Queue
1512
+
* @rx_ring: ring to free buffers from
1513
+
**/
1514
+
static void wx_clean_rx_ring(struct wx_ring *rx_ring)
1515
+
{
1516
+
struct wx_rx_buffer *rx_buffer;
1517
+
u16 i = rx_ring->next_to_clean;
1518
+
1519
+
rx_buffer = &rx_ring->rx_buffer_info[i];
1520
+
1521
+
/* Free all the Rx ring sk_buffs */
1522
+
while (i != rx_ring->next_to_alloc) {
1523
+
if (rx_buffer->skb) {
1524
+
struct sk_buff *skb = rx_buffer->skb;
1525
+
1526
+
if (WX_CB(skb)->page_released)
1527
+
page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
1528
+
1529
+
dev_kfree_skb(skb);
1530
+
}
1531
+
1532
+
/* Invalidate cache lines that may have been written to by
1533
+
* device so that we avoid corrupting memory.
1534
+
*/
1535
+
dma_sync_single_range_for_cpu(rx_ring->dev,
1536
+
rx_buffer->dma,
1537
+
rx_buffer->page_offset,
1538
+
WX_RX_BUFSZ,
1539
+
DMA_FROM_DEVICE);
1540
+
1541
+
/* free resources associated with mapping */
1542
+
page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
1543
+
__page_frag_cache_drain(rx_buffer->page,
1544
+
rx_buffer->pagecnt_bias);
1545
+
1546
+
i++;
1547
+
rx_buffer++;
1548
+
if (i == rx_ring->count) {
1549
+
i = 0;
1550
+
rx_buffer = rx_ring->rx_buffer_info;
1551
+
}
1552
+
}
1553
+
1554
+
rx_ring->next_to_alloc = 0;
1555
+
rx_ring->next_to_clean = 0;
1556
+
rx_ring->next_to_use = 0;
1557
+
}
1558
+
1559
+
/**
1560
+
* wx_clean_all_rx_rings - Free Rx Buffers for all queues
1561
+
* @wx: board private structure
1562
+
**/
1563
+
void wx_clean_all_rx_rings(struct wx *wx)
1564
+
{
1565
+
int i;
1566
+
1567
+
for (i = 0; i < wx->num_rx_queues; i++)
1568
+
wx_clean_rx_ring(wx->rx_ring[i]);
1569
+
}
1570
+
EXPORT_SYMBOL(wx_clean_all_rx_rings);
1571
+
1572
+
/**
1573
+
* wx_free_rx_resources - Free Rx Resources
1574
+
* @rx_ring: ring to clean the resources from
1575
+
*
1576
+
* Free all receive software resources
1577
+
**/
1578
+
static void wx_free_rx_resources(struct wx_ring *rx_ring)
1579
+
{
1580
+
wx_clean_rx_ring(rx_ring);
1581
+
kvfree(rx_ring->rx_buffer_info);
1582
+
rx_ring->rx_buffer_info = NULL;
1583
+
1584
+
/* if not set, then don't free */
1585
+
if (!rx_ring->desc)
1586
+
return;
1587
+
1588
+
dma_free_coherent(rx_ring->dev, rx_ring->size,
1589
+
rx_ring->desc, rx_ring->dma);
1590
+
1591
+
rx_ring->desc = NULL;
1592
+
1593
+
if (rx_ring->page_pool) {
1594
+
page_pool_destroy(rx_ring->page_pool);
1595
+
rx_ring->page_pool = NULL;
1596
+
}
1597
+
}
1598
+
1599
+
/**
1600
+
* wx_free_all_rx_resources - Free Rx Resources for All Queues
1601
+
* @wx: pointer to hardware structure
1602
+
*
1603
+
* Free all receive software resources
1604
+
**/
1605
+
static void wx_free_all_rx_resources(struct wx *wx)
1606
+
{
1607
+
int i;
1608
+
1609
+
for (i = 0; i < wx->num_rx_queues; i++)
1610
+
wx_free_rx_resources(wx->rx_ring[i]);
1611
+
}
1612
+
1613
+
/**
1614
+
* wx_clean_tx_ring - Free Tx Buffers
1615
+
* @tx_ring: ring to be cleaned
1616
+
**/
1617
+
static void wx_clean_tx_ring(struct wx_ring *tx_ring)
1618
+
{
1619
+
struct wx_tx_buffer *tx_buffer;
1620
+
u16 i = tx_ring->next_to_clean;
1621
+
1622
+
tx_buffer = &tx_ring->tx_buffer_info[i];
1623
+
1624
+
while (i != tx_ring->next_to_use) {
1625
+
union wx_tx_desc *eop_desc, *tx_desc;
1626
+
1627
+
/* Free all the Tx ring sk_buffs */
1628
+
dev_kfree_skb_any(tx_buffer->skb);
1629
+
1630
+
/* unmap skb header data */
1631
+
dma_unmap_single(tx_ring->dev,
1632
+
dma_unmap_addr(tx_buffer, dma),
1633
+
dma_unmap_len(tx_buffer, len),
1634
+
DMA_TO_DEVICE);
1635
+
1636
+
/* check for eop_desc to determine the end of the packet */
1637
+
eop_desc = tx_buffer->next_to_watch;
1638
+
tx_desc = WX_TX_DESC(tx_ring, i);
1639
+
1640
+
/* unmap remaining buffers */
1641
+
while (tx_desc != eop_desc) {
1642
+
tx_buffer++;
1643
+
tx_desc++;
1644
+
i++;
1645
+
if (unlikely(i == tx_ring->count)) {
1646
+
i = 0;
1647
+
tx_buffer = tx_ring->tx_buffer_info;
1648
+
tx_desc = WX_TX_DESC(tx_ring, 0);
1649
+
}
1650
+
1651
+
/* unmap any remaining paged data */
1652
+
if (dma_unmap_len(tx_buffer, len))
1653
+
dma_unmap_page(tx_ring->dev,
1654
+
dma_unmap_addr(tx_buffer, dma),
1655
+
dma_unmap_len(tx_buffer, len),
1656
+
DMA_TO_DEVICE);
1657
+
}
1658
+
1659
+
/* move us one more past the eop_desc for start of next pkt */
1660
+
tx_buffer++;
1661
+
i++;
1662
+
if (unlikely(i == tx_ring->count)) {
1663
+
i = 0;
1664
+
tx_buffer = tx_ring->tx_buffer_info;
1665
+
}
1666
+
}
1667
+
1668
+
netdev_tx_reset_queue(wx_txring_txq(tx_ring));
1669
+
1670
+
/* reset next_to_use and next_to_clean */
1671
+
tx_ring->next_to_use = 0;
1672
+
tx_ring->next_to_clean = 0;
1673
+
}
1674
+
1675
+
/**
1676
+
* wx_clean_all_tx_rings - Free Tx Buffers for all queues
1677
+
* @wx: board private structure
1678
+
**/
1679
+
void wx_clean_all_tx_rings(struct wx *wx)
1680
+
{
1681
+
int i;
1682
+
1683
+
for (i = 0; i < wx->num_tx_queues; i++)
1684
+
wx_clean_tx_ring(wx->tx_ring[i]);
1685
+
}
1686
+
EXPORT_SYMBOL(wx_clean_all_tx_rings);
1687
+
1688
+
/**
1689
+
* wx_free_tx_resources - Free Tx Resources per Queue
1690
+
* @tx_ring: Tx descriptor ring for a specific queue
1691
+
*
1692
+
* Free all transmit software resources
1693
+
**/
1694
+
static void wx_free_tx_resources(struct wx_ring *tx_ring)
1695
+
{
1696
+
wx_clean_tx_ring(tx_ring);
1697
+
kvfree(tx_ring->tx_buffer_info);
1698
+
tx_ring->tx_buffer_info = NULL;
1699
+
1700
+
/* if not set, then don't free */
1701
+
if (!tx_ring->desc)
1702
+
return;
1703
+
1704
+
dma_free_coherent(tx_ring->dev, tx_ring->size,
1705
+
tx_ring->desc, tx_ring->dma);
1706
+
tx_ring->desc = NULL;
1707
+
}
1708
+
1709
+
/**
1710
+
* wx_free_all_tx_resources - Free Tx Resources for All Queues
1711
+
* @wx: pointer to hardware structure
1712
+
*
1713
+
* Free all transmit software resources
1714
+
**/
1715
+
static void wx_free_all_tx_resources(struct wx *wx)
1716
+
{
1717
+
int i;
1718
+
1719
+
for (i = 0; i < wx->num_tx_queues; i++)
1720
+
wx_free_tx_resources(wx->tx_ring[i]);
1721
+
}
1722
+
1723
+
void wx_free_resources(struct wx *wx)
1724
+
{
1725
+
wx_free_isb_resources(wx);
1726
+
wx_free_all_rx_resources(wx);
1727
+
wx_free_all_tx_resources(wx);
1728
+
}
1729
+
EXPORT_SYMBOL(wx_free_resources);
1730
+
1731
+
static int wx_alloc_page_pool(struct wx_ring *rx_ring)
1732
+
{
1733
+
int ret = 0;
1734
+
1735
+
struct page_pool_params pp_params = {
1736
+
.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1737
+
.order = 0,
1738
+
.pool_size = rx_ring->size,
1739
+
.nid = dev_to_node(rx_ring->dev),
1740
+
.dev = rx_ring->dev,
1741
+
.dma_dir = DMA_FROM_DEVICE,
1742
+
.offset = 0,
1743
+
.max_len = PAGE_SIZE,
1744
+
};
1745
+
1746
+
rx_ring->page_pool = page_pool_create(&pp_params);
1747
+
if (IS_ERR(rx_ring->page_pool)) {
1748
+
rx_ring->page_pool = NULL;
1749
+
ret = PTR_ERR(rx_ring->page_pool);
1750
+
}
1751
+
1752
+
return ret;
1753
+
}
1754
+
1755
+
/**
1756
+
* wx_setup_rx_resources - allocate Rx resources (Descriptors)
1757
+
* @rx_ring: rx descriptor ring (for a specific queue) to setup
1758
+
*
1759
+
* Returns 0 on success, negative on failure
1760
+
**/
1761
+
static int wx_setup_rx_resources(struct wx_ring *rx_ring)
1762
+
{
1763
+
struct device *dev = rx_ring->dev;
1764
+
int orig_node = dev_to_node(dev);
1765
+
int numa_node = NUMA_NO_NODE;
1766
+
int size, ret;
1767
+
1768
+
size = sizeof(struct wx_rx_buffer) * rx_ring->count;
1769
+
1770
+
if (rx_ring->q_vector)
1771
+
numa_node = rx_ring->q_vector->numa_node;
1772
+
1773
+
rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
1774
+
if (!rx_ring->rx_buffer_info)
1775
+
rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL);
1776
+
if (!rx_ring->rx_buffer_info)
1777
+
goto err;
1778
+
1779
+
/* Round up to nearest 4K */
1780
+
rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc);
1781
+
rx_ring->size = ALIGN(rx_ring->size, 4096);
1782
+
1783
+
set_dev_node(dev, numa_node);
1784
+
rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1785
+
&rx_ring->dma, GFP_KERNEL);
1786
+
if (!rx_ring->desc) {
1787
+
set_dev_node(dev, orig_node);
1788
+
rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1789
+
&rx_ring->dma, GFP_KERNEL);
1790
+
}
1791
+
1792
+
if (!rx_ring->desc)
1793
+
goto err;
1794
+
1795
+
rx_ring->next_to_clean = 0;
1796
+
rx_ring->next_to_use = 0;
1797
+
1798
+
ret = wx_alloc_page_pool(rx_ring);
1799
+
if (ret < 0) {
1800
+
dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret);
1801
+
goto err;
1802
+
}
1803
+
1804
+
return 0;
1805
+
err:
1806
+
kvfree(rx_ring->rx_buffer_info);
1807
+
rx_ring->rx_buffer_info = NULL;
1808
+
dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
1809
+
return -ENOMEM;
1810
+
}
1811
+
1812
+
/**
1813
+
* wx_setup_all_rx_resources - allocate all queues Rx resources
1814
+
* @wx: pointer to hardware structure
1815
+
*
1816
+
* If this function returns with an error, then it's possible one or
1817
+
* more of the rings is populated (while the rest are not). It is the
1818
+
* callers duty to clean those orphaned rings.
1819
+
*
1820
+
* Return 0 on success, negative on failure
1821
+
**/
1822
+
static int wx_setup_all_rx_resources(struct wx *wx)
1823
+
{
1824
+
int i, err = 0;
1825
+
1826
+
for (i = 0; i < wx->num_rx_queues; i++) {
1827
+
err = wx_setup_rx_resources(wx->rx_ring[i]);
1828
+
if (!err)
1829
+
continue;
1830
+
1831
+
wx_err(wx, "Allocation for Rx Queue %u failed\n", i);
1832
+
goto err_setup_rx;
1833
+
}
1834
+
1835
+
return 0;
1836
+
err_setup_rx:
1837
+
/* rewind the index freeing the rings as we go */
1838
+
while (i--)
1839
+
wx_free_rx_resources(wx->rx_ring[i]);
1840
+
return err;
1841
+
}
1842
+
1843
+
/**
1844
+
* wx_setup_tx_resources - allocate Tx resources (Descriptors)
1845
+
* @tx_ring: tx descriptor ring (for a specific queue) to setup
1846
+
*
1847
+
* Return 0 on success, negative on failure
1848
+
**/
1849
+
static int wx_setup_tx_resources(struct wx_ring *tx_ring)
1850
+
{
1851
+
struct device *dev = tx_ring->dev;
1852
+
int orig_node = dev_to_node(dev);
1853
+
int numa_node = NUMA_NO_NODE;
1854
+
int size;
1855
+
1856
+
size = sizeof(struct wx_tx_buffer) * tx_ring->count;
1857
+
1858
+
if (tx_ring->q_vector)
1859
+
numa_node = tx_ring->q_vector->numa_node;
1860
+
1861
+
tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
1862
+
if (!tx_ring->tx_buffer_info)
1863
+
tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL);
1864
+
if (!tx_ring->tx_buffer_info)
1865
+
goto err;
1866
+
1867
+
/* round up to nearest 4K */
1868
+
tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc);
1869
+
tx_ring->size = ALIGN(tx_ring->size, 4096);
1870
+
1871
+
set_dev_node(dev, numa_node);
1872
+
tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1873
+
&tx_ring->dma, GFP_KERNEL);
1874
+
if (!tx_ring->desc) {
1875
+
set_dev_node(dev, orig_node);
1876
+
tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1877
+
&tx_ring->dma, GFP_KERNEL);
1878
+
}
1879
+
1880
+
if (!tx_ring->desc)
1881
+
goto err;
1882
+
1883
+
tx_ring->next_to_use = 0;
1884
+
tx_ring->next_to_clean = 0;
1885
+
1886
+
return 0;
1887
+
1888
+
err:
1889
+
kvfree(tx_ring->tx_buffer_info);
1890
+
tx_ring->tx_buffer_info = NULL;
1891
+
dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
1892
+
return -ENOMEM;
1893
+
}
1894
+
1895
+
/**
1896
+
* wx_setup_all_tx_resources - allocate all queues Tx resources
1897
+
* @wx: pointer to private structure
1898
+
*
1899
+
* If this function returns with an error, then it's possible one or
1900
+
* more of the rings is populated (while the rest are not). It is the
1901
+
* callers duty to clean those orphaned rings.
1902
+
*
1903
+
* Return 0 on success, negative on failure
1904
+
**/
1905
+
static int wx_setup_all_tx_resources(struct wx *wx)
1906
+
{
1907
+
int i, err = 0;
1908
+
1909
+
for (i = 0; i < wx->num_tx_queues; i++) {
1910
+
err = wx_setup_tx_resources(wx->tx_ring[i]);
1911
+
if (!err)
1912
+
continue;
1913
+
1914
+
wx_err(wx, "Allocation for Tx Queue %u failed\n", i);
1915
+
goto err_setup_tx;
1916
+
}
1917
+
1918
+
return 0;
1919
+
err_setup_tx:
1920
+
/* rewind the index freeing the rings as we go */
1921
+
while (i--)
1922
+
wx_free_tx_resources(wx->tx_ring[i]);
1923
+
return err;
1924
+
}
1925
+
1926
+
int wx_setup_resources(struct wx *wx)
1927
+
{
1928
+
int err;
1929
+
1930
+
/* allocate transmit descriptors */
1931
+
err = wx_setup_all_tx_resources(wx);
1932
+
if (err)
1933
+
return err;
1934
+
1935
+
/* allocate receive descriptors */
1936
+
err = wx_setup_all_rx_resources(wx);
1937
+
if (err)
1938
+
goto err_free_tx;
1939
+
1940
+
err = wx_setup_isb_resources(wx);
1941
+
if (err)
1942
+
goto err_free_rx;
1943
+
1944
+
return 0;
1945
+
1946
+
err_free_rx:
1947
+
wx_free_all_rx_resources(wx);
1948
+
err_free_tx:
1949
+
wx_free_all_tx_resources(wx);
1950
+
1951
+
return err;
1952
+
}
1953
+
EXPORT_SYMBOL(wx_setup_resources);
1954
+
1955
+
/**
1956
+
* wx_get_stats64 - Get System Network Statistics
1957
+
* @netdev: network interface device structure
1958
+
* @stats: storage space for 64bit statistics
1959
+
*/
1960
+
void wx_get_stats64(struct net_device *netdev,
1961
+
struct rtnl_link_stats64 *stats)
1962
+
{
1963
+
struct wx *wx = netdev_priv(netdev);
1964
+
int i;
1965
+
1966
+
rcu_read_lock();
1967
+
for (i = 0; i < wx->num_rx_queues; i++) {
1968
+
struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]);
1969
+
u64 bytes, packets;
1970
+
unsigned int start;
1971
+
1972
+
if (ring) {
1973
+
do {
1974
+
start = u64_stats_fetch_begin(&ring->syncp);
1975
+
packets = ring->stats.packets;
1976
+
bytes = ring->stats.bytes;
1977
+
} while (u64_stats_fetch_retry(&ring->syncp, start));
1978
+
stats->rx_packets += packets;
1979
+
stats->rx_bytes += bytes;
1980
+
}
1981
+
}
1982
+
1983
+
for (i = 0; i < wx->num_tx_queues; i++) {
1984
+
struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]);
1985
+
u64 bytes, packets;
1986
+
unsigned int start;
1987
+
1988
+
if (ring) {
1989
+
do {
1990
+
start = u64_stats_fetch_begin(&ring->syncp);
1991
+
packets = ring->stats.packets;
1992
+
bytes = ring->stats.bytes;
1993
+
} while (u64_stats_fetch_retry(&ring->syncp,
1994
+
start));
1995
+
stats->tx_packets += packets;
1996
+
stats->tx_bytes += bytes;
1997
+
}
1998
+
}
1999
+
2000
+
rcu_read_unlock();
2001
+
}
2002
+
EXPORT_SYMBOL(wx_get_stats64);
2003
+
2004
+
MODULE_LICENSE("GPL");
+32
drivers/net/ethernet/wangxun/libwx/wx_lib.h
+32
drivers/net/ethernet/wangxun/libwx/wx_lib.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* WangXun Gigabit PCI Express Linux driver
4
+
* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd.
5
+
*/
6
+
7
+
#ifndef _WX_LIB_H_
8
+
#define _WX_LIB_H_
9
+
10
+
void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count);
11
+
u16 wx_desc_unused(struct wx_ring *ring);
12
+
netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
13
+
struct net_device *netdev);
14
+
void wx_napi_enable_all(struct wx *wx);
15
+
void wx_napi_disable_all(struct wx *wx);
16
+
void wx_reset_interrupt_capability(struct wx *wx);
17
+
void wx_clear_interrupt_scheme(struct wx *wx);
18
+
int wx_init_interrupt_scheme(struct wx *wx);
19
+
irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data);
20
+
void wx_free_irq(struct wx *wx);
21
+
int wx_setup_isb_resources(struct wx *wx);
22
+
void wx_free_isb_resources(struct wx *wx);
23
+
u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx);
24
+
void wx_configure_vectors(struct wx *wx);
25
+
void wx_clean_all_rx_rings(struct wx *wx);
26
+
void wx_clean_all_tx_rings(struct wx *wx);
27
+
void wx_free_resources(struct wx *wx);
28
+
int wx_setup_resources(struct wx *wx);
29
+
void wx_get_stats64(struct net_device *netdev,
30
+
struct rtnl_link_stats64 *stats);
31
+
32
+
#endif /* _NGBE_LIB_H_ */
+314
drivers/net/ethernet/wangxun/libwx/wx_type.h
+314
drivers/net/ethernet/wangxun/libwx/wx_type.h
···
5
5
#define _WX_TYPE_H_
6
6
7
7
#include <linux/bitfield.h>
8
+
#include <linux/netdevice.h>
8
9
9
10
/* Vendor ID */
10
11
#ifndef PCI_VENDOR_ID_WANGXUN
···
66
65
/* port cfg Registers */
67
66
#define WX_CFG_PORT_CTL 0x14400
68
67
#define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
68
+
#define WX_CFG_PORT_CTL_QINQ BIT(2)
69
+
#define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
70
+
#define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
71
+
72
+
/* GPIO Registers */
73
+
#define WX_GPIO_DR 0x14800
74
+
#define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
75
+
#define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
76
+
#define WX_GPIO_DDR 0x14804
77
+
#define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
78
+
#define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
79
+
#define WX_GPIO_CTL 0x14808
80
+
#define WX_GPIO_INTEN 0x14830
81
+
#define WX_GPIO_INTEN_0 BIT(0)
82
+
#define WX_GPIO_INTEN_1 BIT(1)
83
+
#define WX_GPIO_INTMASK 0x14834
84
+
#define WX_GPIO_INTTYPE_LEVEL 0x14838
85
+
#define WX_GPIO_POLARITY 0x1483C
86
+
#define WX_GPIO_EOI 0x1484C
69
87
70
88
/*********************** Transmit DMA registers **************************/
71
89
/* transmit global control */
72
90
#define WX_TDM_CTL 0x18000
73
91
/* TDM CTL BIT */
74
92
#define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
93
+
#define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
75
94
76
95
/***************************** RDB registers *********************************/
77
96
/* receive packet buffer */
78
97
#define WX_RDB_PB_CTL 0x19000
79
98
#define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
80
99
#define WX_RDB_PB_CTL_DISABLED BIT(0)
100
+
#define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
101
+
#define WX_RDB_PB_SZ_SHIFT 10
81
102
/* statistic */
82
103
#define WX_RDB_PFCMACDAL 0x19210
83
104
#define WX_RDB_PFCMACDAH 0x19214
105
+
/* ring assignment */
106
+
#define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
107
+
#define WX_RDB_PL_CFG_L4HDR BIT(1)
108
+
#define WX_RDB_PL_CFG_L3HDR BIT(2)
109
+
#define WX_RDB_PL_CFG_L2HDR BIT(3)
110
+
#define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
111
+
#define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
84
112
85
113
/******************************* PSR Registers *******************************/
86
114
/* psr control */
···
127
97
#define WX_PSR_CTL_MO_SHIFT 5
128
98
#define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
129
99
#define WX_PSR_CTL_TPE BIT(4)
100
+
#define WX_PSR_MAX_SZ 0x15020
101
+
#define WX_PSR_VLAN_CTL 0x15088
102
+
#define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
103
+
#define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
130
104
/* mcasst/ucast overflow tbl */
131
105
#define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
132
106
#define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
107
+
108
+
/* VM L2 contorl */
109
+
#define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
110
+
#define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
111
+
#define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
112
+
#define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
113
+
#define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
114
+
#define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
115
+
#define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
116
+
#define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
133
117
134
118
/* Management */
135
119
#define WX_PSR_MNG_FLEX_SEL 0x1582C
···
166
122
#define WX_PSR_MAC_SWC_IDX 0x16210
167
123
#define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
168
124
125
+
/********************************* RSEC **************************************/
126
+
/* general rsec */
127
+
#define WX_RSC_CTL 0x17000
128
+
#define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
129
+
#define WX_RSC_CTL_CRC_STRIP BIT(2)
130
+
#define WX_RSC_CTL_RX_DIS BIT(1)
131
+
#define WX_RSC_ST 0x17004
132
+
#define WX_RSC_ST_RSEC_RDY BIT(0)
133
+
134
+
/****************************** TDB ******************************************/
135
+
#define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
136
+
#define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
137
+
138
+
/****************************** TSEC *****************************************/
139
+
/* Security Control Registers */
140
+
#define WX_TSC_CTL 0x1D000
141
+
#define WX_TSC_CTL_TX_DIS BIT(1)
142
+
#define WX_TSC_CTL_TSEC_DIS BIT(0)
143
+
#define WX_TSC_BUF_AE 0x1D00C
144
+
#define WX_TSC_BUF_AE_THR GENMASK(9, 0)
145
+
169
146
/************************************** MNG ********************************/
170
147
#define WX_MNG_SWFW_SYNC 0x1E008
171
148
#define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
···
200
135
#define WX_MAC_TX_CFG 0x11000
201
136
#define WX_MAC_TX_CFG_TE BIT(0)
202
137
#define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
138
+
#define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
203
139
#define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
204
140
#define WX_MAC_RX_CFG 0x11004
205
141
#define WX_MAC_RX_CFG_RE BIT(0)
···
217
151
/* Interrupt Registers */
218
152
#define WX_BME_CTL 0x12020
219
153
#define WX_PX_MISC_IC 0x100
154
+
#define WX_PX_MISC_ICS 0x104
155
+
#define WX_PX_MISC_IEN 0x108
156
+
#define WX_PX_INTA 0x110
157
+
#define WX_PX_GPIE 0x118
158
+
#define WX_PX_GPIE_MODEL BIT(0)
159
+
#define WX_PX_IC 0x120
220
160
#define WX_PX_IMS(_i) (0x140 + (_i) * 4)
161
+
#define WX_PX_IMC(_i) (0x150 + (_i) * 4)
162
+
#define WX_PX_ISB_ADDR_L 0x160
163
+
#define WX_PX_ISB_ADDR_H 0x164
221
164
#define WX_PX_TRANSACTION_PENDING 0x168
165
+
#define WX_PX_ITRSEL 0x180
166
+
#define WX_PX_ITR(_i) (0x200 + (_i) * 4)
167
+
#define WX_PX_ITR_CNT_WDIS BIT(31)
168
+
#define WX_PX_MISC_IVAR 0x4FC
169
+
#define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
170
+
171
+
#define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
172
+
#define WX_7K_ITR 595
173
+
#define WX_12K_ITR 336
174
+
#define WX_SP_MAX_EITR 0x00000FF8U
175
+
#define WX_EM_MAX_EITR 0x00007FFCU
222
176
223
177
/* transmit DMA Registers */
178
+
#define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
179
+
#define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
180
+
#define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
181
+
#define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
224
182
#define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
225
183
/* Transmit Config masks */
226
184
#define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
···
254
164
#define WX_PX_TR_CFG_THRE_SHIFT 8
255
165
256
166
/* Receive DMA Registers */
167
+
#define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
168
+
#define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
169
+
#define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
170
+
#define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
257
171
#define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
258
172
/* PX_RR_CFG bit definitions */
173
+
#define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
174
+
#define WX_PX_RR_CFG_RR_THER_SHIFT 16
175
+
#define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
176
+
#define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
177
+
#define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
178
+
* + at bit 8 offset (<< 12)
179
+
* = (<< 6)
180
+
*/
181
+
#define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
182
+
#define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
259
183
#define WX_PX_RR_CFG_RR_EN BIT(0)
260
184
261
185
/* Number of 80 microseconds we wait for PCI Express master disable */
···
297
193
#define WX_MAC_STATE_MODIFIED 0x2
298
194
#define WX_MAC_STATE_IN_USE 0x4
299
195
196
+
#define WX_MAX_RXD 8192
197
+
#define WX_MAX_TXD 8192
198
+
199
+
/* Supported Rx Buffer Sizes */
200
+
#define WX_RXBUFFER_256 256 /* Used for skb receive header */
201
+
#define WX_RXBUFFER_2K 2048
202
+
#define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
203
+
204
+
#if MAX_SKB_FRAGS < 8
205
+
#define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
206
+
#else
207
+
#define WX_RX_BUFSZ WX_RXBUFFER_2K
208
+
#endif
209
+
210
+
#define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
211
+
212
+
#define WX_MAX_DATA_PER_TXD BIT(14)
213
+
/* Tx Descriptors needed, worst case */
214
+
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
215
+
#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
216
+
217
+
/* Ether Types */
218
+
#define WX_ETH_P_CNM 0x22E7
219
+
300
220
#define WX_CFG_PORT_ST 0x14404
221
+
222
+
/******************* Receive Descriptor bit definitions **********************/
223
+
#define WX_RXD_STAT_DD BIT(0) /* Done */
224
+
#define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
225
+
226
+
#define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
227
+
228
+
/*********************** Transmit Descriptor Config Masks ****************/
229
+
#define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
230
+
#define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
231
+
#define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
232
+
#define WX_TXD_EOP BIT(24) /* End of Packet */
233
+
#define WX_TXD_IFCS BIT(25) /* Insert FCS */
234
+
#define WX_TXD_RS BIT(27) /* Report Status */
301
235
302
236
/* Host Interface Command Structures */
303
237
struct wx_hic_hdr {
···
412
270
bool set_lben;
413
271
u8 addr[ETH_ALEN];
414
272
u8 perm_addr[ETH_ALEN];
273
+
u32 mta_shadow[128];
415
274
s32 mc_filter_type;
416
275
u32 mcft_size;
417
276
u32 num_rar_entries;
277
+
u32 rx_pb_size;
278
+
u32 tx_pb_size;
418
279
u32 max_tx_queues;
419
280
u32 max_rx_queues;
420
281
···
457
312
WX_GLOBAL_RESET
458
313
};
459
314
315
+
struct wx_cb {
316
+
dma_addr_t dma;
317
+
u16 append_cnt; /* number of skb's appended */
318
+
bool page_released;
319
+
bool dma_released;
320
+
};
321
+
322
+
#define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
323
+
324
+
/* Transmit Descriptor */
325
+
union wx_tx_desc {
326
+
struct {
327
+
__le64 buffer_addr; /* Address of descriptor's data buf */
328
+
__le32 cmd_type_len;
329
+
__le32 olinfo_status;
330
+
} read;
331
+
struct {
332
+
__le64 rsvd; /* Reserved */
333
+
__le32 nxtseq_seed;
334
+
__le32 status;
335
+
} wb;
336
+
};
337
+
338
+
/* Receive Descriptor */
339
+
union wx_rx_desc {
340
+
struct {
341
+
__le64 pkt_addr; /* Packet buffer address */
342
+
__le64 hdr_addr; /* Header buffer address */
343
+
} read;
344
+
struct {
345
+
struct {
346
+
union {
347
+
__le32 data;
348
+
struct {
349
+
__le16 pkt_info; /* RSS, Pkt type */
350
+
__le16 hdr_info; /* Splithdr, hdrlen */
351
+
} hs_rss;
352
+
} lo_dword;
353
+
union {
354
+
__le32 rss; /* RSS Hash */
355
+
struct {
356
+
__le16 ip_id; /* IP id */
357
+
__le16 csum; /* Packet Checksum */
358
+
} csum_ip;
359
+
} hi_dword;
360
+
} lower;
361
+
struct {
362
+
__le32 status_error; /* ext status/error */
363
+
__le16 length; /* Packet length */
364
+
__le16 vlan; /* VLAN tag */
365
+
} upper;
366
+
} wb; /* writeback */
367
+
};
368
+
369
+
#define WX_RX_DESC(R, i) \
370
+
(&(((union wx_rx_desc *)((R)->desc))[i]))
371
+
#define WX_TX_DESC(R, i) \
372
+
(&(((union wx_tx_desc *)((R)->desc))[i]))
373
+
374
+
/* wrapper around a pointer to a socket buffer,
375
+
* so a DMA handle can be stored along with the buffer
376
+
*/
377
+
struct wx_tx_buffer {
378
+
union wx_tx_desc *next_to_watch;
379
+
struct sk_buff *skb;
380
+
unsigned int bytecount;
381
+
unsigned short gso_segs;
382
+
DEFINE_DMA_UNMAP_ADDR(dma);
383
+
DEFINE_DMA_UNMAP_LEN(len);
384
+
};
385
+
386
+
struct wx_rx_buffer {
387
+
struct sk_buff *skb;
388
+
dma_addr_t dma;
389
+
dma_addr_t page_dma;
390
+
struct page *page;
391
+
unsigned int page_offset;
392
+
u16 pagecnt_bias;
393
+
};
394
+
395
+
struct wx_queue_stats {
396
+
u64 packets;
397
+
u64 bytes;
398
+
};
399
+
400
+
/* iterator for handling rings in ring container */
401
+
#define wx_for_each_ring(posm, headm) \
402
+
for (posm = (headm).ring; posm; posm = posm->next)
403
+
404
+
struct wx_ring_container {
405
+
struct wx_ring *ring; /* pointer to linked list of rings */
406
+
unsigned int total_bytes; /* total bytes processed this int */
407
+
unsigned int total_packets; /* total packets processed this int */
408
+
u8 count; /* total number of rings in vector */
409
+
u8 itr; /* current ITR setting for ring */
410
+
};
411
+
412
+
struct wx_ring {
413
+
struct wx_ring *next; /* pointer to next ring in q_vector */
414
+
struct wx_q_vector *q_vector; /* backpointer to host q_vector */
415
+
struct net_device *netdev; /* netdev ring belongs to */
416
+
struct device *dev; /* device for DMA mapping */
417
+
struct page_pool *page_pool;
418
+
void *desc; /* descriptor ring memory */
419
+
union {
420
+
struct wx_tx_buffer *tx_buffer_info;
421
+
struct wx_rx_buffer *rx_buffer_info;
422
+
};
423
+
u8 __iomem *tail;
424
+
dma_addr_t dma; /* phys. address of descriptor ring */
425
+
unsigned int size; /* length in bytes */
426
+
427
+
u16 count; /* amount of descriptors */
428
+
429
+
u8 queue_index; /* needed for multiqueue queue management */
430
+
u8 reg_idx; /* holds the special value that gets
431
+
* the hardware register offset
432
+
* associated with this ring, which is
433
+
* different for DCB and RSS modes
434
+
*/
435
+
u16 next_to_use;
436
+
u16 next_to_clean;
437
+
u16 next_to_alloc;
438
+
439
+
struct wx_queue_stats stats;
440
+
struct u64_stats_sync syncp;
441
+
} ____cacheline_internodealigned_in_smp;
442
+
443
+
struct wx_q_vector {
444
+
struct wx *wx;
445
+
int cpu; /* CPU for DCA */
446
+
int numa_node;
447
+
u16 v_idx; /* index of q_vector within array, also used for
448
+
* finding the bit in EICR and friends that
449
+
* represents the vector for this ring
450
+
*/
451
+
u16 itr; /* Interrupt throttle rate written to EITR */
452
+
struct wx_ring_container rx, tx;
453
+
struct napi_struct napi;
454
+
struct rcu_head rcu; /* to avoid race with update stats on free */
455
+
456
+
char name[IFNAMSIZ + 17];
457
+
458
+
/* for dynamic allocation of rings associated with this q_vector */
459
+
struct wx_ring ring[0] ____cacheline_internodealigned_in_smp;
460
+
};
461
+
462
+
enum wx_isb_idx {
463
+
WX_ISB_HEADER,
464
+
WX_ISB_MISC,
465
+
WX_ISB_VEC0,
466
+
WX_ISB_VEC1,
467
+
WX_ISB_MAX
468
+
};
469
+
460
470
struct wx {
461
471
u8 __iomem *hw_addr;
462
472
struct pci_dev *pdev;
···
631
331
u16 oem_svid;
632
332
u16 msg_enable;
633
333
bool adapter_stopped;
334
+
u16 tpid[8];
634
335
char eeprom_id[32];
635
336
enum wx_reset_type reset_type;
636
337
···
661
360
u32 tx_ring_count;
662
361
u32 rx_ring_count;
663
362
363
+
struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
364
+
struct wx_ring *rx_ring[64];
365
+
struct wx_q_vector *q_vector[64];
366
+
367
+
unsigned int queues_per_pool;
368
+
struct msix_entry *msix_entries;
369
+
370
+
/* misc interrupt status block */
371
+
dma_addr_t isb_dma;
372
+
u32 *isb_mem;
373
+
u32 isb_tag[WX_ISB_MAX];
374
+
664
375
#define WX_MAX_RETA_ENTRIES 128
665
376
u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
666
377
···
684
371
};
685
372
686
373
#define WX_INTR_ALL (~0ULL)
374
+
#define WX_INTR_Q(i) BIT(i)
687
375
688
376
/* register operations */
689
377
#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
+240
-9
drivers/net/ethernet/wangxun/ngbe/ngbe_main.c
+240
-9
drivers/net/ethernet/wangxun/ngbe/ngbe_main.c
···
13
13
14
14
#include "../libwx/wx_type.h"
15
15
#include "../libwx/wx_hw.h"
16
+
#include "../libwx/wx_lib.h"
16
17
#include "ngbe_type.h"
17
18
#include "ngbe_mdio.h"
18
19
#include "ngbe_hw.h"
···
113
112
wx->mac.num_rar_entries = NGBE_RAR_ENTRIES;
114
113
wx->mac.max_rx_queues = NGBE_MAX_RX_QUEUES;
115
114
wx->mac.max_tx_queues = NGBE_MAX_TX_QUEUES;
115
+
wx->mac.mcft_size = NGBE_MC_TBL_SIZE;
116
+
wx->mac.rx_pb_size = NGBE_RX_PB_SIZE;
117
+
wx->mac.tx_pb_size = NGBE_TDB_PB_SZ;
116
118
117
119
/* PCI config space info */
118
120
err = wx_sw_init(wx);
···
152
148
return 0;
153
149
}
154
150
151
+
/**
152
+
* ngbe_irq_enable - Enable default interrupt generation settings
153
+
* @wx: board private structure
154
+
* @queues: enable all queues interrupts
155
+
**/
156
+
static void ngbe_irq_enable(struct wx *wx, bool queues)
157
+
{
158
+
u32 mask;
159
+
160
+
/* enable misc interrupt */
161
+
mask = NGBE_PX_MISC_IEN_MASK;
162
+
163
+
wr32(wx, WX_GPIO_DDR, WX_GPIO_DDR_0);
164
+
wr32(wx, WX_GPIO_INTEN, WX_GPIO_INTEN_0 | WX_GPIO_INTEN_1);
165
+
wr32(wx, WX_GPIO_INTTYPE_LEVEL, 0x0);
166
+
wr32(wx, WX_GPIO_POLARITY, wx->gpio_ctrl ? 0 : 0x3);
167
+
168
+
wr32(wx, WX_PX_MISC_IEN, mask);
169
+
170
+
/* mask interrupt */
171
+
if (queues)
172
+
wx_intr_enable(wx, NGBE_INTR_ALL);
173
+
else
174
+
wx_intr_enable(wx, NGBE_INTR_MISC(wx));
175
+
}
176
+
177
+
/**
178
+
* ngbe_intr - msi/legacy mode Interrupt Handler
179
+
* @irq: interrupt number
180
+
* @data: pointer to a network interface device structure
181
+
**/
182
+
static irqreturn_t ngbe_intr(int __always_unused irq, void *data)
183
+
{
184
+
struct wx_q_vector *q_vector;
185
+
struct wx *wx = data;
186
+
struct pci_dev *pdev;
187
+
u32 eicr;
188
+
189
+
q_vector = wx->q_vector[0];
190
+
pdev = wx->pdev;
191
+
192
+
eicr = wx_misc_isb(wx, WX_ISB_VEC0);
193
+
if (!eicr) {
194
+
/* shared interrupt alert!
195
+
* the interrupt that we masked before the EICR read.
196
+
*/
197
+
if (netif_running(wx->netdev))
198
+
ngbe_irq_enable(wx, true);
199
+
return IRQ_NONE; /* Not our interrupt */
200
+
}
201
+
wx->isb_mem[WX_ISB_VEC0] = 0;
202
+
if (!(pdev->msi_enabled))
203
+
wr32(wx, WX_PX_INTA, 1);
204
+
205
+
wx->isb_mem[WX_ISB_MISC] = 0;
206
+
/* would disable interrupts here but it is auto disabled */
207
+
napi_schedule_irqoff(&q_vector->napi);
208
+
209
+
if (netif_running(wx->netdev))
210
+
ngbe_irq_enable(wx, false);
211
+
212
+
return IRQ_HANDLED;
213
+
}
214
+
215
+
static irqreturn_t ngbe_msix_other(int __always_unused irq, void *data)
216
+
{
217
+
struct wx *wx = data;
218
+
219
+
/* re-enable the original interrupt state, no lsc, no queues */
220
+
if (netif_running(wx->netdev))
221
+
ngbe_irq_enable(wx, false);
222
+
223
+
return IRQ_HANDLED;
224
+
}
225
+
226
+
/**
227
+
* ngbe_request_msix_irqs - Initialize MSI-X interrupts
228
+
* @wx: board private structure
229
+
*
230
+
* ngbe_request_msix_irqs allocates MSI-X vectors and requests
231
+
* interrupts from the kernel.
232
+
**/
233
+
static int ngbe_request_msix_irqs(struct wx *wx)
234
+
{
235
+
struct net_device *netdev = wx->netdev;
236
+
int vector, err;
237
+
238
+
for (vector = 0; vector < wx->num_q_vectors; vector++) {
239
+
struct wx_q_vector *q_vector = wx->q_vector[vector];
240
+
struct msix_entry *entry = &wx->msix_entries[vector];
241
+
242
+
if (q_vector->tx.ring && q_vector->rx.ring)
243
+
snprintf(q_vector->name, sizeof(q_vector->name) - 1,
244
+
"%s-TxRx-%d", netdev->name, entry->entry);
245
+
else
246
+
/* skip this unused q_vector */
247
+
continue;
248
+
249
+
err = request_irq(entry->vector, wx_msix_clean_rings, 0,
250
+
q_vector->name, q_vector);
251
+
if (err) {
252
+
wx_err(wx, "request_irq failed for MSIX interrupt %s Error: %d\n",
253
+
q_vector->name, err);
254
+
goto free_queue_irqs;
255
+
}
256
+
}
257
+
258
+
err = request_irq(wx->msix_entries[vector].vector,
259
+
ngbe_msix_other, 0, netdev->name, wx);
260
+
261
+
if (err) {
262
+
wx_err(wx, "request_irq for msix_other failed: %d\n", err);
263
+
goto free_queue_irqs;
264
+
}
265
+
266
+
return 0;
267
+
268
+
free_queue_irqs:
269
+
while (vector) {
270
+
vector--;
271
+
free_irq(wx->msix_entries[vector].vector,
272
+
wx->q_vector[vector]);
273
+
}
274
+
wx_reset_interrupt_capability(wx);
275
+
return err;
276
+
}
277
+
278
+
/**
279
+
* ngbe_request_irq - initialize interrupts
280
+
* @wx: board private structure
281
+
*
282
+
* Attempts to configure interrupts using the best available
283
+
* capabilities of the hardware and kernel.
284
+
**/
285
+
static int ngbe_request_irq(struct wx *wx)
286
+
{
287
+
struct net_device *netdev = wx->netdev;
288
+
struct pci_dev *pdev = wx->pdev;
289
+
int err;
290
+
291
+
if (pdev->msix_enabled)
292
+
err = ngbe_request_msix_irqs(wx);
293
+
else if (pdev->msi_enabled)
294
+
err = request_irq(pdev->irq, ngbe_intr, 0,
295
+
netdev->name, wx);
296
+
else
297
+
err = request_irq(pdev->irq, ngbe_intr, IRQF_SHARED,
298
+
netdev->name, wx);
299
+
300
+
if (err)
301
+
wx_err(wx, "request_irq failed, Error %d\n", err);
302
+
303
+
return err;
304
+
}
305
+
155
306
static void ngbe_disable_device(struct wx *wx)
156
307
{
157
308
struct net_device *netdev = wx->netdev;
309
+
u32 i;
158
310
311
+
/* disable all enabled rx queues */
312
+
for (i = 0; i < wx->num_rx_queues; i++)
313
+
/* this call also flushes the previous write */
314
+
wx_disable_rx_queue(wx, wx->rx_ring[i]);
159
315
/* disable receives */
160
316
wx_disable_rx(wx);
317
+
wx_napi_disable_all(wx);
318
+
netif_tx_stop_all_queues(netdev);
161
319
netif_tx_disable(netdev);
162
320
if (wx->gpio_ctrl)
163
321
ngbe_sfp_modules_txrx_powerctl(wx, false);
322
+
wx_irq_disable(wx);
323
+
/* disable transmits in the hardware now that interrupts are off */
324
+
for (i = 0; i < wx->num_tx_queues; i++) {
325
+
u8 reg_idx = wx->tx_ring[i]->reg_idx;
326
+
327
+
wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
328
+
}
164
329
}
165
330
166
331
static void ngbe_down(struct wx *wx)
167
332
{
168
333
phy_stop(wx->phydev);
169
334
ngbe_disable_device(wx);
335
+
wx_clean_all_tx_rings(wx);
336
+
wx_clean_all_rx_rings(wx);
170
337
}
171
338
172
339
static void ngbe_up(struct wx *wx)
173
340
{
341
+
wx_configure_vectors(wx);
342
+
343
+
/* make sure to complete pre-operations */
344
+
smp_mb__before_atomic();
345
+
wx_napi_enable_all(wx);
346
+
/* enable transmits */
347
+
netif_tx_start_all_queues(wx->netdev);
348
+
349
+
/* clear any pending interrupts, may auto mask */
350
+
rd32(wx, WX_PX_IC);
351
+
rd32(wx, WX_PX_MISC_IC);
352
+
ngbe_irq_enable(wx, true);
174
353
if (wx->gpio_ctrl)
175
354
ngbe_sfp_modules_txrx_powerctl(wx, true);
355
+
176
356
phy_start(wx->phydev);
177
357
}
178
358
···
375
187
int err;
376
188
377
189
wx_control_hw(wx, true);
378
-
err = ngbe_phy_connect(wx);
190
+
191
+
err = wx_setup_resources(wx);
379
192
if (err)
380
193
return err;
194
+
195
+
wx_configure(wx);
196
+
197
+
err = ngbe_request_irq(wx);
198
+
if (err)
199
+
goto err_free_resources;
200
+
201
+
err = ngbe_phy_connect(wx);
202
+
if (err)
203
+
goto err_free_irq;
204
+
205
+
err = netif_set_real_num_tx_queues(netdev, wx->num_tx_queues);
206
+
if (err)
207
+
goto err_dis_phy;
208
+
209
+
err = netif_set_real_num_rx_queues(netdev, wx->num_rx_queues);
210
+
if (err)
211
+
goto err_dis_phy;
212
+
381
213
ngbe_up(wx);
382
214
383
215
return 0;
216
+
err_dis_phy:
217
+
phy_disconnect(wx->phydev);
218
+
err_free_irq:
219
+
wx_free_irq(wx);
220
+
err_free_resources:
221
+
wx_free_resources(wx);
222
+
return err;
384
223
}
385
224
386
225
/**
···
426
211
struct wx *wx = netdev_priv(netdev);
427
212
428
213
ngbe_down(wx);
214
+
wx_free_irq(wx);
215
+
wx_free_resources(wx);
429
216
phy_disconnect(wx->phydev);
430
217
wx_control_hw(wx, false);
431
218
432
219
return 0;
433
-
}
434
-
435
-
static netdev_tx_t ngbe_xmit_frame(struct sk_buff *skb,
436
-
struct net_device *netdev)
437
-
{
438
-
return NETDEV_TX_OK;
439
220
}
440
221
441
222
static void ngbe_dev_shutdown(struct pci_dev *pdev, bool *enable_wake)
···
469
258
static const struct net_device_ops ngbe_netdev_ops = {
470
259
.ndo_open = ngbe_open,
471
260
.ndo_stop = ngbe_close,
472
-
.ndo_start_xmit = ngbe_xmit_frame,
261
+
.ndo_start_xmit = wx_xmit_frame,
262
+
.ndo_set_rx_mode = wx_set_rx_mode,
473
263
.ndo_validate_addr = eth_validate_addr,
474
264
.ndo_set_mac_address = wx_set_mac,
265
+
.ndo_get_stats64 = wx_get_stats64,
475
266
};
476
267
477
268
/**
···
549
336
netdev->netdev_ops = &ngbe_netdev_ops;
550
337
551
338
netdev->features |= NETIF_F_HIGHDMA;
339
+
netdev->features = NETIF_F_SG;
340
+
341
+
/* copy netdev features into list of user selectable features */
342
+
netdev->hw_features |= netdev->features |
343
+
NETIF_F_RXALL;
344
+
345
+
netdev->priv_flags |= IFF_UNICAST_FLT;
346
+
netdev->priv_flags |= IFF_SUPP_NOFCS;
347
+
348
+
netdev->min_mtu = ETH_MIN_MTU;
349
+
netdev->max_mtu = NGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
552
350
553
351
wx->bd_number = func_nums;
554
352
/* setup the private structure */
···
635
411
eth_hw_addr_set(netdev, wx->mac.perm_addr);
636
412
wx_mac_set_default_filter(wx, wx->mac.perm_addr);
637
413
414
+
err = wx_init_interrupt_scheme(wx);
415
+
if (err)
416
+
goto err_free_mac_table;
417
+
638
418
/* phy Interface Configuration */
639
419
err = ngbe_mdio_init(wx);
640
420
if (err)
641
-
goto err_free_mac_table;
421
+
goto err_clear_interrupt_scheme;
642
422
643
423
err = register_netdev(netdev);
644
424
if (err)
···
659
431
660
432
err_register:
661
433
wx_control_hw(wx, false);
434
+
err_clear_interrupt_scheme:
435
+
wx_clear_interrupt_scheme(wx);
662
436
err_free_mac_table:
663
437
kfree(wx->mac_table);
664
438
err_pci_release_regions:
···
692
462
pci_select_bars(pdev, IORESOURCE_MEM));
693
463
694
464
kfree(wx->mac_table);
465
+
wx_clear_interrupt_scheme(wx);
695
466
pci_disable_pcie_error_reporting(pdev);
696
467
697
468
pci_disable_device(pdev);
+18
drivers/net/ethernet/wangxun/ngbe/ngbe_type.h
+18
drivers/net/ethernet/wangxun/ngbe/ngbe_type.h
···
90
90
#define NGBE_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
91
91
#define NGBE_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
92
92
93
+
/* Extended Interrupt Enable Set */
94
+
#define NGBE_PX_MISC_IEN_DEV_RST BIT(10)
95
+
#define NGBE_PX_MISC_IEN_ETH_LK BIT(18)
96
+
#define NGBE_PX_MISC_IEN_INT_ERR BIT(20)
97
+
#define NGBE_PX_MISC_IEN_GPIO BIT(26)
98
+
#define NGBE_PX_MISC_IEN_MASK ( \
99
+
NGBE_PX_MISC_IEN_DEV_RST | \
100
+
NGBE_PX_MISC_IEN_ETH_LK | \
101
+
NGBE_PX_MISC_IEN_INT_ERR | \
102
+
NGBE_PX_MISC_IEN_GPIO)
103
+
104
+
#define NGBE_INTR_ALL 0x1FF
105
+
#define NGBE_INTR_MISC(A) BIT((A)->num_q_vectors)
106
+
93
107
#define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4))
94
108
#define NGBE_CFG_LAN_SPEED 0x14440
95
109
#define NGBE_CFG_PORT_ST 0x14404
···
134
120
#define NGBE_ETH_LENGTH_OF_ADDRESS 6
135
121
#define NGBE_MAX_MSIX_VECTORS 0x09
136
122
#define NGBE_RAR_ENTRIES 32
123
+
#define NGBE_RX_PB_SIZE 42
124
+
#define NGBE_MC_TBL_SIZE 128
125
+
#define NGBE_TDB_PB_SZ (20 * 1024) /* 160KB Packet Buffer */
126
+
#define NGBE_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
137
127
138
128
/* TX/RX descriptor defines */
139
129
#define NGBE_DEFAULT_TXD 512 /* default ring size */
+264
-7
drivers/net/ethernet/wangxun/txgbe/txgbe_main.c
+264
-7
drivers/net/ethernet/wangxun/txgbe/txgbe_main.c
···
11
11
#include <net/ip.h>
12
12
13
13
#include "../libwx/wx_type.h"
14
+
#include "../libwx/wx_lib.h"
14
15
#include "../libwx/wx_hw.h"
15
16
#include "txgbe_type.h"
16
17
#include "txgbe_hw.h"
···
73
72
return physfns;
74
73
}
75
74
75
+
/**
76
+
* txgbe_irq_enable - Enable default interrupt generation settings
77
+
* @wx: pointer to private structure
78
+
* @queues: enable irqs for queues
79
+
**/
80
+
static void txgbe_irq_enable(struct wx *wx, bool queues)
81
+
{
82
+
/* unmask interrupt */
83
+
wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
84
+
if (queues)
85
+
wx_intr_enable(wx, TXGBE_INTR_QALL(wx));
86
+
}
87
+
88
+
/**
89
+
* txgbe_intr - msi/legacy mode Interrupt Handler
90
+
* @irq: interrupt number
91
+
* @data: pointer to a network interface device structure
92
+
**/
93
+
static irqreturn_t txgbe_intr(int __always_unused irq, void *data)
94
+
{
95
+
struct wx_q_vector *q_vector;
96
+
struct wx *wx = data;
97
+
struct pci_dev *pdev;
98
+
u32 eicr;
99
+
100
+
q_vector = wx->q_vector[0];
101
+
pdev = wx->pdev;
102
+
103
+
eicr = wx_misc_isb(wx, WX_ISB_VEC0);
104
+
if (!eicr) {
105
+
/* shared interrupt alert!
106
+
* the interrupt that we masked before the ICR read.
107
+
*/
108
+
if (netif_running(wx->netdev))
109
+
txgbe_irq_enable(wx, true);
110
+
return IRQ_NONE; /* Not our interrupt */
111
+
}
112
+
wx->isb_mem[WX_ISB_VEC0] = 0;
113
+
if (!(pdev->msi_enabled))
114
+
wr32(wx, WX_PX_INTA, 1);
115
+
116
+
wx->isb_mem[WX_ISB_MISC] = 0;
117
+
/* would disable interrupts here but it is auto disabled */
118
+
napi_schedule_irqoff(&q_vector->napi);
119
+
120
+
/* re-enable link(maybe) and non-queue interrupts, no flush.
121
+
* txgbe_poll will re-enable the queue interrupts
122
+
*/
123
+
if (netif_running(wx->netdev))
124
+
txgbe_irq_enable(wx, false);
125
+
126
+
return IRQ_HANDLED;
127
+
}
128
+
129
+
static irqreturn_t txgbe_msix_other(int __always_unused irq, void *data)
130
+
{
131
+
struct wx *wx = data;
132
+
133
+
/* re-enable the original interrupt state */
134
+
if (netif_running(wx->netdev))
135
+
txgbe_irq_enable(wx, false);
136
+
137
+
return IRQ_HANDLED;
138
+
}
139
+
140
+
/**
141
+
* txgbe_request_msix_irqs - Initialize MSI-X interrupts
142
+
* @wx: board private structure
143
+
*
144
+
* Allocate MSI-X vectors and request interrupts from the kernel.
145
+
**/
146
+
static int txgbe_request_msix_irqs(struct wx *wx)
147
+
{
148
+
struct net_device *netdev = wx->netdev;
149
+
int vector, err;
150
+
151
+
for (vector = 0; vector < wx->num_q_vectors; vector++) {
152
+
struct wx_q_vector *q_vector = wx->q_vector[vector];
153
+
struct msix_entry *entry = &wx->msix_entries[vector];
154
+
155
+
if (q_vector->tx.ring && q_vector->rx.ring)
156
+
snprintf(q_vector->name, sizeof(q_vector->name) - 1,
157
+
"%s-TxRx-%d", netdev->name, entry->entry);
158
+
else
159
+
/* skip this unused q_vector */
160
+
continue;
161
+
162
+
err = request_irq(entry->vector, wx_msix_clean_rings, 0,
163
+
q_vector->name, q_vector);
164
+
if (err) {
165
+
wx_err(wx, "request_irq failed for MSIX interrupt %s Error: %d\n",
166
+
q_vector->name, err);
167
+
goto free_queue_irqs;
168
+
}
169
+
}
170
+
171
+
err = request_irq(wx->msix_entries[vector].vector,
172
+
txgbe_msix_other, 0, netdev->name, wx);
173
+
if (err) {
174
+
wx_err(wx, "request_irq for msix_other failed: %d\n", err);
175
+
goto free_queue_irqs;
176
+
}
177
+
178
+
return 0;
179
+
180
+
free_queue_irqs:
181
+
while (vector) {
182
+
vector--;
183
+
free_irq(wx->msix_entries[vector].vector,
184
+
wx->q_vector[vector]);
185
+
}
186
+
wx_reset_interrupt_capability(wx);
187
+
return err;
188
+
}
189
+
190
+
/**
191
+
* txgbe_request_irq - initialize interrupts
192
+
* @wx: board private structure
193
+
*
194
+
* Attempt to configure interrupts using the best available
195
+
* capabilities of the hardware and kernel.
196
+
**/
197
+
static int txgbe_request_irq(struct wx *wx)
198
+
{
199
+
struct net_device *netdev = wx->netdev;
200
+
struct pci_dev *pdev = wx->pdev;
201
+
int err;
202
+
203
+
if (pdev->msix_enabled)
204
+
err = txgbe_request_msix_irqs(wx);
205
+
else if (pdev->msi_enabled)
206
+
err = request_irq(wx->pdev->irq, &txgbe_intr, 0,
207
+
netdev->name, wx);
208
+
else
209
+
err = request_irq(wx->pdev->irq, &txgbe_intr, IRQF_SHARED,
210
+
netdev->name, wx);
211
+
212
+
if (err)
213
+
wx_err(wx, "request_irq failed, Error %d\n", err);
214
+
215
+
return err;
216
+
}
217
+
76
218
static void txgbe_up_complete(struct wx *wx)
77
219
{
220
+
u32 reg;
221
+
78
222
wx_control_hw(wx, true);
223
+
wx_configure_vectors(wx);
224
+
225
+
/* make sure to complete pre-operations */
226
+
smp_mb__before_atomic();
227
+
wx_napi_enable_all(wx);
228
+
229
+
/* clear any pending interrupts, may auto mask */
230
+
rd32(wx, WX_PX_IC);
231
+
rd32(wx, WX_PX_MISC_IC);
232
+
txgbe_irq_enable(wx, true);
233
+
234
+
/* Configure MAC Rx and Tx when link is up */
235
+
reg = rd32(wx, WX_MAC_RX_CFG);
236
+
wr32(wx, WX_MAC_RX_CFG, reg);
237
+
wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
238
+
reg = rd32(wx, WX_MAC_WDG_TIMEOUT);
239
+
wr32(wx, WX_MAC_WDG_TIMEOUT, reg);
240
+
reg = rd32(wx, WX_MAC_TX_CFG);
241
+
wr32(wx, WX_MAC_TX_CFG, (reg & ~WX_MAC_TX_CFG_SPEED_MASK) | WX_MAC_TX_CFG_SPEED_10G);
242
+
243
+
/* enable transmits */
244
+
netif_tx_start_all_queues(wx->netdev);
245
+
netif_carrier_on(wx->netdev);
79
246
}
80
247
81
248
static void txgbe_reset(struct wx *wx)
···
265
96
static void txgbe_disable_device(struct wx *wx)
266
97
{
267
98
struct net_device *netdev = wx->netdev;
99
+
u32 i;
268
100
269
101
wx_disable_pcie_master(wx);
270
102
/* disable receives */
271
103
wx_disable_rx(wx);
272
104
105
+
/* disable all enabled rx queues */
106
+
for (i = 0; i < wx->num_rx_queues; i++)
107
+
/* this call also flushes the previous write */
108
+
wx_disable_rx_queue(wx, wx->rx_ring[i]);
109
+
110
+
netif_tx_stop_all_queues(netdev);
273
111
netif_carrier_off(netdev);
274
112
netif_tx_disable(netdev);
113
+
114
+
wx_irq_disable(wx);
115
+
wx_napi_disable_all(wx);
275
116
276
117
if (wx->bus.func < 2)
277
118
wr32m(wx, TXGBE_MIS_PRB_CTL, TXGBE_MIS_PRB_CTL_LAN_UP(wx->bus.func), 0);
···
295
116
wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
296
117
}
297
118
119
+
/* disable transmits in the hardware now that interrupts are off */
120
+
for (i = 0; i < wx->num_tx_queues; i++) {
121
+
u8 reg_idx = wx->tx_ring[i]->reg_idx;
122
+
123
+
wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
124
+
}
125
+
298
126
/* Disable the Tx DMA engine */
299
127
wr32m(wx, WX_TDM_CTL, WX_TDM_CTL_TE, 0);
300
128
}
···
310
124
{
311
125
txgbe_disable_device(wx);
312
126
txgbe_reset(wx);
127
+
128
+
wx_clean_all_tx_rings(wx);
129
+
wx_clean_all_rx_rings(wx);
313
130
}
314
131
315
132
/**
···
321
132
**/
322
133
static int txgbe_sw_init(struct wx *wx)
323
134
{
135
+
u16 msix_count = 0;
324
136
int err;
325
137
326
138
wx->mac.num_rar_entries = TXGBE_SP_RAR_ENTRIES;
327
139
wx->mac.max_tx_queues = TXGBE_SP_MAX_TX_QUEUES;
328
140
wx->mac.max_rx_queues = TXGBE_SP_MAX_RX_QUEUES;
329
141
wx->mac.mcft_size = TXGBE_SP_MC_TBL_SIZE;
142
+
wx->mac.rx_pb_size = TXGBE_SP_RX_PB_SIZE;
143
+
wx->mac.tx_pb_size = TXGBE_SP_TDB_PB_SZ;
330
144
331
145
/* PCI config space info */
332
146
err = wx_sw_init(wx);
···
348
156
break;
349
157
}
350
158
159
+
/* Set common capability flags and settings */
160
+
wx->max_q_vectors = TXGBE_MAX_MSIX_VECTORS;
161
+
err = wx_get_pcie_msix_counts(wx, &msix_count, TXGBE_MAX_MSIX_VECTORS);
162
+
if (err)
163
+
wx_err(wx, "Do not support MSI-X\n");
164
+
wx->mac.max_msix_vectors = msix_count;
165
+
166
+
/* enable itr by default in dynamic mode */
167
+
wx->rx_itr_setting = 1;
168
+
wx->tx_itr_setting = 1;
169
+
170
+
/* set default ring sizes */
171
+
wx->tx_ring_count = TXGBE_DEFAULT_TXD;
172
+
wx->rx_ring_count = TXGBE_DEFAULT_RXD;
173
+
174
+
/* set default work limits */
175
+
wx->tx_work_limit = TXGBE_DEFAULT_TX_WORK;
176
+
wx->rx_work_limit = TXGBE_DEFAULT_RX_WORK;
177
+
351
178
return 0;
352
179
}
353
180
···
382
171
static int txgbe_open(struct net_device *netdev)
383
172
{
384
173
struct wx *wx = netdev_priv(netdev);
174
+
int err;
175
+
176
+
err = wx_setup_resources(wx);
177
+
if (err)
178
+
goto err_reset;
179
+
180
+
wx_configure(wx);
181
+
182
+
err = txgbe_request_irq(wx);
183
+
if (err)
184
+
goto err_free_isb;
185
+
186
+
/* Notify the stack of the actual queue counts. */
187
+
err = netif_set_real_num_tx_queues(netdev, wx->num_tx_queues);
188
+
if (err)
189
+
goto err_free_irq;
190
+
191
+
err = netif_set_real_num_rx_queues(netdev, wx->num_rx_queues);
192
+
if (err)
193
+
goto err_free_irq;
385
194
386
195
txgbe_up_complete(wx);
387
196
388
197
return 0;
198
+
199
+
err_free_irq:
200
+
wx_free_irq(wx);
201
+
err_free_isb:
202
+
wx_free_isb_resources(wx);
203
+
err_reset:
204
+
txgbe_reset(wx);
205
+
206
+
return err;
389
207
}
390
208
391
209
/**
···
427
187
static void txgbe_close_suspend(struct wx *wx)
428
188
{
429
189
txgbe_disable_device(wx);
190
+
wx_free_resources(wx);
430
191
}
431
192
432
193
/**
···
446
205
struct wx *wx = netdev_priv(netdev);
447
206
448
207
txgbe_down(wx);
208
+
wx_free_irq(wx);
209
+
wx_free_resources(wx);
449
210
wx_control_hw(wx, false);
450
211
451
212
return 0;
···
483
240
}
484
241
}
485
242
486
-
static netdev_tx_t txgbe_xmit_frame(struct sk_buff *skb,
487
-
struct net_device *netdev)
488
-
{
489
-
return NETDEV_TX_OK;
490
-
}
491
-
492
243
static const struct net_device_ops txgbe_netdev_ops = {
493
244
.ndo_open = txgbe_open,
494
245
.ndo_stop = txgbe_close,
495
-
.ndo_start_xmit = txgbe_xmit_frame,
246
+
.ndo_start_xmit = wx_xmit_frame,
247
+
.ndo_set_rx_mode = wx_set_rx_mode,
496
248
.ndo_validate_addr = eth_validate_addr,
497
249
.ndo_set_mac_address = wx_set_mac,
250
+
.ndo_get_stats64 = wx_get_stats64,
498
251
};
499
252
500
253
/**
···
593
354
}
594
355
595
356
netdev->features |= NETIF_F_HIGHDMA;
357
+
netdev->features = NETIF_F_SG;
358
+
359
+
/* copy netdev features into list of user selectable features */
360
+
netdev->hw_features |= netdev->features | NETIF_F_RXALL;
361
+
362
+
netdev->priv_flags |= IFF_UNICAST_FLT;
363
+
netdev->priv_flags |= IFF_SUPP_NOFCS;
364
+
365
+
netdev->min_mtu = ETH_MIN_MTU;
366
+
netdev->max_mtu = TXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
596
367
597
368
/* make sure the EEPROM is good */
598
369
err = txgbe_validate_eeprom_checksum(wx, NULL);
···
615
366
616
367
eth_hw_addr_set(netdev, wx->mac.perm_addr);
617
368
wx_mac_set_default_filter(wx, wx->mac.perm_addr);
369
+
370
+
err = wx_init_interrupt_scheme(wx);
371
+
if (err)
372
+
goto err_free_mac_table;
618
373
619
374
/* Save off EEPROM version number and Option Rom version which
620
375
* together make a unique identify for the eeprom
···
664
411
665
412
pci_set_drvdata(pdev, wx);
666
413
414
+
netif_tx_stop_all_queues(netdev);
415
+
667
416
/* calculate the expected PCIe bandwidth required for optimal
668
417
* performance. Note that some older parts will never have enough
669
418
* bandwidth due to being older generation PCIe parts. We clamp these
···
690
435
return 0;
691
436
692
437
err_release_hw:
438
+
wx_clear_interrupt_scheme(wx);
693
439
wx_control_hw(wx, false);
694
440
err_free_mac_table:
695
441
kfree(wx->mac_table);
···
724
468
pci_select_bars(pdev, IORESOURCE_MEM));
725
469
726
470
kfree(wx->mac_table);
471
+
wx_clear_interrupt_scheme(wx);
727
472
728
473
pci_disable_pcie_error_reporting(pdev);
729
474
+21
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
+21
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
···
67
67
#define TXGBE_PBANUM1_PTR 0x06
68
68
#define TXGBE_PBANUM_PTR_GUARD 0xFAFA
69
69
70
+
#define TXGBE_MAX_MSIX_VECTORS 64
70
71
#define TXGBE_MAX_FDIR_INDICES 63
71
72
72
73
#define TXGBE_MAX_RX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1)
···
77
76
#define TXGBE_SP_MAX_RX_QUEUES 128
78
77
#define TXGBE_SP_RAR_ENTRIES 128
79
78
#define TXGBE_SP_MC_TBL_SIZE 128
79
+
#define TXGBE_SP_RX_PB_SIZE 512
80
+
#define TXGBE_SP_TDB_PB_SZ (160 * 1024) /* 160KB Packet Buffer */
81
+
#define TXGBE_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
82
+
83
+
/* TX/RX descriptor defines */
84
+
#define TXGBE_DEFAULT_TXD 512
85
+
#define TXGBE_DEFAULT_TX_WORK 256
86
+
87
+
#if (PAGE_SIZE < 8192)
88
+
#define TXGBE_DEFAULT_RXD 512
89
+
#define TXGBE_DEFAULT_RX_WORK 256
90
+
#else
91
+
#define TXGBE_DEFAULT_RXD 256
92
+
#define TXGBE_DEFAULT_RX_WORK 128
93
+
#endif
94
+
95
+
#define TXGBE_INTR_MISC(A) BIT((A)->num_q_vectors)
96
+
#define TXGBE_INTR_QALL(A) (TXGBE_INTR_MISC(A) - 1)
97
+
98
+
#define TXGBE_MAX_EITR GENMASK(11, 3)
80
99
81
100
extern char txgbe_driver_name[];
82
101