Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'reset-fixes-for-v7.0-2' of https://git.pengutronix.de/git/pza/linux into arm/fixes
Reset controller fixes for v7.0, part 2
* Decouple spacemit K3 reset lines that were incorrectly coupled
together as one, but are in fact separate resets in hardware.
* Fix a double free in the reset_add_gpio_aux_device() error path.
This has already been fixed on reset/next by commit a9b95ce36de4
("reset: gpio: add a devlink between reset-gpio and its consumer").
* Fix the MODULE_AUTHOR string in the rzg2l-usbphy-ctrl driver.
* tag 'reset-fixes-for-v7.0-2' of https://git.pengutronix.de/git/pza/linux:
reset: spacemit: k3: Decouple composite reset lines
reset: gpio: fix double free in reset_add_gpio_aux_device() error path
reset: rzg2l-usbphy-ctrl: Fix malformed MODULE_AUTHOR string
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+73
-38
-1
drivers/reset/core.c
-1
drivers/reset/core.c
+1
-1
drivers/reset/reset-rzg2l-usbphy-ctrl.c
+1
-1
drivers/reset/reset-rzg2l-usbphy-ctrl.c
+36
-24
drivers/reset/spacemit/reset-spacemit-k3.c
+36
-24
drivers/reset/spacemit/reset-spacemit-k3.c
···
112
112
[RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
113
113
[RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
114
114
[RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
115
-
[RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
116
-
BIT(1)|BIT(2)|BIT(3)),
117
-
[RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
118
-
BIT(5)|BIT(6)|BIT(7)),
119
-
[RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
120
-
BIT(9)|BIT(10)|BIT(11)),
121
-
[RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
122
-
BIT(13)|BIT(14)|BIT(15)),
123
-
[RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
124
-
BIT(17)|BIT(18)|BIT(19)),
115
+
[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)),
116
+
[RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)),
117
+
[RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)),
118
+
[RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)),
119
+
[RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)),
120
+
[RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)),
121
+
[RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
122
+
[RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
123
+
[RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
124
+
[RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)),
125
+
[RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)),
126
+
[RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)),
127
+
[RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)),
128
+
[RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)),
129
+
[RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)),
125
130
[RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
126
131
[RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
127
132
[RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
···
156
151
[RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0),
157
152
[RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0),
158
153
[RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0),
159
-
[RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL,
160
-
BIT(1) | BIT(2) | BIT(3), 0),
161
-
[RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0,
162
-
BIT(3) | BIT(2) | BIT(0)),
154
+
[RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0),
155
+
[RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0),
156
+
[RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0),
157
+
[RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)),
158
+
[RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)),
159
+
[RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)),
163
160
[RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)),
164
161
[RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)),
165
162
[RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)),
···
171
164
[RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)),
172
165
[RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)),
173
166
[RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)),
174
-
[RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0,
175
-
BIT(5) | BIT(4) | BIT(3)),
176
-
[RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0,
177
-
BIT(5) | BIT(4) | BIT(3)),
178
-
[RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0,
179
-
BIT(5) | BIT(4) | BIT(3)),
180
-
[RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0,
181
-
BIT(5) | BIT(4) | BIT(3)),
182
-
[RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0,
183
-
BIT(5) | BIT(4) | BIT(3)),
167
+
[RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)),
168
+
[RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)),
169
+
[RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)),
170
+
[RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)),
171
+
[RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)),
172
+
[RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)),
173
+
[RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)),
174
+
[RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)),
175
+
[RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)),
176
+
[RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)),
177
+
[RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)),
178
+
[RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)),
179
+
[RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)),
180
+
[RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)),
181
+
[RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)),
184
182
[RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
185
183
[RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
186
184
[RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),
+36
-12
include/dt-bindings/reset/spacemit,k3-resets.h
+36
-12
include/dt-bindings/reset/spacemit,k3-resets.h
···
97
97
#define RESET_APMU_SDH0 13
98
98
#define RESET_APMU_SDH1 14
99
99
#define RESET_APMU_SDH2 15
100
-
#define RESET_APMU_USB2 16
101
-
#define RESET_APMU_USB3_PORTA 17
102
-
#define RESET_APMU_USB3_PORTB 18
103
-
#define RESET_APMU_USB3_PORTC 19
104
-
#define RESET_APMU_USB3_PORTD 20
100
+
#define RESET_APMU_USB2_AHB 16
101
+
#define RESET_APMU_USB2_VCC 17
102
+
#define RESET_APMU_USB2_PHY 18
103
+
#define RESET_APMU_USB3_A_AHB 19
104
+
#define RESET_APMU_USB3_A_VCC 20
105
105
#define RESET_APMU_QSPI 21
106
106
#define RESET_APMU_QSPI_BUS 22
107
107
#define RESET_APMU_DMA 23
···
132
132
#define RESET_APMU_CPU7_SW 48
133
133
#define RESET_APMU_C1_MPSUB_SW 49
134
134
#define RESET_APMU_MPSUB_DBG 50
135
-
#define RESET_APMU_UCIE 51
136
-
#define RESET_APMU_RCPU 52
135
+
#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
136
+
#define RESET_APMU_USB3_B_AHB 52
137
137
#define RESET_APMU_DSI4LN2_ESCCLK 53
138
138
#define RESET_APMU_DSI4LN2_LCD_SW 54
139
139
#define RESET_APMU_DSI4LN2_LCD_MCLK 55
···
143
143
#define RESET_APMU_UFS_ACLK 59
144
144
#define RESET_APMU_EDP0 60
145
145
#define RESET_APMU_EDP1 61
146
-
#define RESET_APMU_PCIE_PORTA 62
147
-
#define RESET_APMU_PCIE_PORTB 63
148
-
#define RESET_APMU_PCIE_PORTC 64
149
-
#define RESET_APMU_PCIE_PORTD 65
150
-
#define RESET_APMU_PCIE_PORTE 66
146
+
#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
147
+
#define RESET_APMU_USB3_B_PHY 63
148
+
#define RESET_APMU_USB3_C_AHB 64
149
+
#define RESET_APMU_USB3_C_VCC 65
150
+
#define RESET_APMU_USB3_C_PHY 66
151
151
#define RESET_APMU_EMAC0 67
152
152
#define RESET_APMU_EMAC1 68
153
153
#define RESET_APMU_EMAC2 69
154
154
#define RESET_APMU_ESPI_MCLK 70
155
155
#define RESET_APMU_ESPI_SCLK 71
156
+
#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
157
+
#define RESET_APMU_USB3_D_VCC 73
158
+
#define RESET_APMU_USB3_D_PHY 74
159
+
#define RESET_APMU_UCIE_IP 75
160
+
#define RESET_APMU_UCIE_HOT 76
161
+
#define RESET_APMU_UCIE_MON 77
162
+
#define RESET_APMU_RCPU_AUDIO_SYS 78
163
+
#define RESET_APMU_RCPU_MCU_CORE 79
164
+
#define RESET_APMU_RCPU_AUDIO_APMU 80
165
+
#define RESET_APMU_PCIE_A_DBI 81
166
+
#define RESET_APMU_PCIE_A_SLAVE 82
167
+
#define RESET_APMU_PCIE_A_MASTER 83
168
+
#define RESET_APMU_PCIE_B_DBI 84
169
+
#define RESET_APMU_PCIE_B_SLAVE 85
170
+
#define RESET_APMU_PCIE_B_MASTER 86
171
+
#define RESET_APMU_PCIE_C_DBI 87
172
+
#define RESET_APMU_PCIE_C_SLAVE 88
173
+
#define RESET_APMU_PCIE_C_MASTER 89
174
+
#define RESET_APMU_PCIE_D_DBI 90
175
+
#define RESET_APMU_PCIE_D_SLAVE 91
176
+
#define RESET_APMU_PCIE_D_MASTER 92
177
+
#define RESET_APMU_PCIE_E_DBI 93
178
+
#define RESET_APMU_PCIE_E_SLAVE 94
179
+
#define RESET_APMU_PCIE_E_MASTER 95
156
180
157
181
/* DCIU resets*/
158
182
#define RESET_DCIU_HDMA 0