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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dmaengine: dw-edma: Add AMD MDB Endpoint Support
AMD MDB PCIe endpoint support. For AMD specific support
added the following
- AMD supported PCIe Device IDs and Vendor ID (Xilinx).
- AMD MDB specific driver data
- AMD MDB specific VSEC capability to retrieve the device DDR
base address.
Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260318070403.1634706-2-devendra.verma@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Devendra K Verma
and committed by
Vinod Koul
14eb9a1d
132e47b7
+176
-14
+176
-14
drivers/dma/dw-edma/dw-edma-pcie.c
+176
-14
drivers/dma/dw-edma/dw-edma-pcie.c
···
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#include <linux/pci-epf.h>
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#include <linux/msi.h>
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#include <linux/bitfield.h>
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#include <linux/sizes.h>
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#include "dw-edma-core.h"
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#define DW_PCIE_VSEC_DMA_ID 0x6
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#define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8)
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#define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0)
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#define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0)
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#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16)
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/* Synopsys */
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#define DW_PCIE_SYNOPSYS_VSEC_DMA_ID 0x6
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#define DW_PCIE_SYNOPSYS_VSEC_DMA_BAR GENMASK(10, 8)
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#define DW_PCIE_SYNOPSYS_VSEC_DMA_MAP GENMASK(2, 0)
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#define DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH GENMASK(9, 0)
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#define DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH GENMASK(25, 16)
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/* AMD MDB (Xilinx) specific defines */
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#define PCI_DEVICE_ID_XILINX_B054 0xb054
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#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6
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#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20
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#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8)
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#define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0)
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#define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0)
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#define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16)
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#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc
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#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8
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#define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL)
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#define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000
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#define DW_PCIE_XILINX_MDB_LL_SIZE 0x800
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#define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000
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#define DW_PCIE_XILINX_MDB_DT_SIZE 0x800
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#define DW_BLOCK(a, b, c) \
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{ \
···
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u8 irqs;
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u16 wr_ch_cnt;
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u16 rd_ch_cnt;
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u64 devmem_phys_off;
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};
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static const struct dw_edma_pcie_data snps_edda_data = {
···
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.rd_ch_cnt = 2,
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};
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static const struct dw_edma_pcie_data xilinx_mdb_data = {
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/* MDB registers location */
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.rg.bar = BAR_0,
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.rg.off = SZ_4K, /* 4 Kbytes */
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.rg.sz = SZ_8K, /* 8 Kbytes */
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/* Other */
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.mf = EDMA_MF_HDMA_NATIVE,
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.irqs = 1,
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.wr_ch_cnt = 8,
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.rd_ch_cnt = 8,
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};
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static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata,
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enum pci_barno bar, off_t start_off,
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off_t ll_off_gap, size_t ll_size,
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off_t dt_off_gap, size_t dt_size)
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{
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u16 wr_ch = pdata->wr_ch_cnt;
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u16 rd_ch = pdata->rd_ch_cnt;
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off_t off;
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u16 i;
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off = start_off;
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/* Write channel LL region */
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for (i = 0; i < wr_ch; i++) {
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pdata->ll_wr[i].bar = bar;
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pdata->ll_wr[i].off = off;
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pdata->ll_wr[i].sz = ll_size;
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off += ll_off_gap;
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}
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/* Read channel LL region */
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for (i = 0; i < rd_ch; i++) {
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pdata->ll_rd[i].bar = bar;
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pdata->ll_rd[i].off = off;
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pdata->ll_rd[i].sz = ll_size;
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off += ll_off_gap;
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}
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/* Write channel data region */
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for (i = 0; i < wr_ch; i++) {
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pdata->dt_wr[i].bar = bar;
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pdata->dt_wr[i].off = off;
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pdata->dt_wr[i].sz = dt_size;
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off += dt_off_gap;
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}
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/* Read channel data region */
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for (i = 0; i < rd_ch; i++) {
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pdata->dt_rd[i].bar = bar;
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pdata->dt_rd[i].off = off;
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pdata->dt_rd[i].sz = dt_size;
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off += dt_off_gap;
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}
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}
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static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
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{
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return pci_irq_vector(to_pci_dev(dev), nr);
···
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.pci_address = dw_edma_pcie_address,
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};
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static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev,
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struct dw_edma_pcie_data *pdata)
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static void dw_edma_pcie_get_synopsys_dma_data(struct pci_dev *pdev,
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struct dw_edma_pcie_data *pdata)
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{
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u32 val, map;
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u16 vsec;
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u64 off;
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vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS,
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DW_PCIE_VSEC_DMA_ID);
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DW_PCIE_SYNOPSYS_VSEC_DMA_ID);
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if (!vsec)
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return;
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···
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PCI_VNDR_HEADER_LEN(val) != 0x18)
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return;
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pci_dbg(pdev, "Detected PCIe Vendor-Specific Extended Capability DMA\n");
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pci_dbg(pdev, "Detected Synopsys PCIe Vendor-Specific Extended Capability DMA\n");
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pci_read_config_dword(pdev, vsec + 0x8, &val);
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map = FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val);
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map = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_MAP, val);
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if (map != EDMA_MF_EDMA_LEGACY &&
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map != EDMA_MF_EDMA_UNROLL &&
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map != EDMA_MF_HDMA_COMPAT &&
···
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return;
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pdata->mf = map;
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pdata->rg.bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val);
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pdata->rg.bar = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_BAR, val);
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pci_read_config_dword(pdev, vsec + 0xc, &val);
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pdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt,
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FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val));
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FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH, val));
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pdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt,
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FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val));
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FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH, val));
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pci_read_config_dword(pdev, vsec + 0x14, &val);
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off = val;
···
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off <<= 32;
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off |= val;
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pdata->rg.off = off;
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}
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static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev,
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struct dw_edma_pcie_data *pdata)
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{
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u32 val, map;
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u16 vsec;
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u64 off;
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pdata->devmem_phys_off = DW_PCIE_XILINX_MDB_INVALID_ADDR;
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vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX,
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DW_PCIE_XILINX_MDB_VSEC_DMA_ID);
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if (!vsec)
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return;
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pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val);
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if (PCI_VNDR_HEADER_REV(val) != 0x00 ||
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PCI_VNDR_HEADER_LEN(val) != 0x18)
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return;
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pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability DMA\n");
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pci_read_config_dword(pdev, vsec + 0x8, &val);
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map = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val);
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if (map != EDMA_MF_HDMA_NATIVE)
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return;
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pdata->mf = map;
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pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val);
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pci_read_config_dword(pdev, vsec + 0xc, &val);
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pdata->wr_ch_cnt = min(pdata->wr_ch_cnt,
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FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val));
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pdata->rd_ch_cnt = min(pdata->rd_ch_cnt,
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FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val));
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pci_read_config_dword(pdev, vsec + 0x14, &val);
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off = val;
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pci_read_config_dword(pdev, vsec + 0x10, &val);
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off <<= 32;
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off |= val;
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pdata->rg.off = off;
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vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX,
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DW_PCIE_XILINX_MDB_VSEC_ID);
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if (!vsec)
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return;
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pci_read_config_dword(pdev,
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vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH,
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&val);
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off = val;
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pci_read_config_dword(pdev,
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vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW,
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&val);
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off <<= 32;
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off |= val;
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pdata->devmem_phys_off = off;
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}
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static int dw_edma_pcie_probe(struct pci_dev *pdev,
···
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* Tries to find if exists a PCIe Vendor-Specific Extended Capability
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* for the DMA, if one exists, then reconfigures it.
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*/
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dw_edma_pcie_get_vsec_dma_data(pdev, vsec_data);
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dw_edma_pcie_get_synopsys_dma_data(pdev, vsec_data);
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if (pdev->vendor == PCI_VENDOR_ID_XILINX) {
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dw_edma_pcie_get_xilinx_dma_data(pdev, vsec_data);
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/*
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* There is no valid address found for the LL memory
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* space on the device side.
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*/
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if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR)
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return -ENOMEM;
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/*
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* Configure the channel LL and data blocks if number of
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* channels enabled in VSEC capability are more than the
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* channels configured in xilinx_mdb_data.
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*/
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dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,
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DW_PCIE_XILINX_MDB_LL_OFF_GAP,
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DW_PCIE_XILINX_MDB_LL_SIZE,
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DW_PCIE_XILINX_MDB_DT_OFF_GAP,
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DW_PCIE_XILINX_MDB_DT_SIZE);
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}
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/* Mapping PCI BAR regions */
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mask = BIT(vsec_data->rg.bar);
···
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static const struct pci_device_id dw_edma_pcie_id_table[] = {
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{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
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{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),
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(kernel_ulong_t)&xilinx_mdb_data },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);