Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'arm64-fixes-for-6.3' into arm64-for-6.4
Merge the arm64-fixes-for-6.3 branch to avoid merge conflicts with
changes for v6.4.
+106
-72
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
-4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
+26
-2
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
+26
-2
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
···
25
25
gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
26
26
};
27
27
28
+
&mpss {
29
+
pinctrl-0 = <&sim_ctrl_default>;
30
+
pinctrl-names = "default";
31
+
};
32
+
28
33
&button_default {
29
34
pins = "gpio37";
30
35
bias-pull-down;
···
39
34
pins = "gpio20", "gpio21", "gpio22";
40
35
};
41
36
42
-
&sim_ctrl_default {
43
-
pins = "gpio1", "gpio2";
37
+
/* This selects the external SIM card slot by default */
38
+
&msmgpio {
39
+
sim_ctrl_default: sim-ctrl-default-state {
40
+
esim-sel-pins {
41
+
pins = "gpio0", "gpio3";
42
+
bias-disable;
43
+
output-low;
44
+
};
45
+
46
+
sim-en-pins {
47
+
pins = "gpio1";
48
+
bias-disable;
49
+
output-low;
50
+
};
51
+
52
+
sim-sel-pins {
53
+
pins = "gpio2";
54
+
bias-disable;
55
+
output-high;
56
+
};
57
+
};
44
58
};
-10
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
-10
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
···
92
92
};
93
93
94
94
&mpss {
95
-
pinctrl-0 = <&sim_ctrl_default>;
96
-
pinctrl-names = "default";
97
-
98
95
status = "okay";
99
96
};
100
97
···
236
239
function = "gpio";
237
240
drive-strength = <2>;
238
241
bias-disable;
239
-
};
240
-
241
-
sim_ctrl_default: sim-ctrl-default-state {
242
-
function = "gpio";
243
-
drive-strength = <2>;
244
-
bias-disable;
245
-
output-low;
246
242
};
247
243
};
+2
-2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+2
-2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
···
1012
1012
left_spkr: speaker@0,3 {
1013
1013
compatible = "sdw10217211000";
1014
1014
reg = <0 3>;
1015
-
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
1015
+
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
1016
1016
#thermal-sensor-cells = <0>;
1017
1017
sound-name-prefix = "SpkrLeft";
1018
1018
#sound-dai-cells = <0>;
···
1021
1021
right_spkr: speaker@0,4 {
1022
1022
compatible = "sdw10217211000";
1023
1023
reg = <0 4>;
1024
-
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
1024
+
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
1025
1025
#thermal-sensor-cells = <0>;
1026
1026
sound-name-prefix = "SpkrRight";
1027
1027
#sound-dai-cells = <0>;
+1
-1
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+1
-1
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+2
arch/arm64/boot/dts/qcom/sc7280.dtsi
+2
arch/arm64/boot/dts/qcom/sc7280.dtsi
+22
-5
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+22
-5
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
···
374
374
regulator-min-microvolt = <1800000>;
375
375
regulator-max-microvolt = <1800000>;
376
376
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
377
+
regulator-always-on;
377
378
};
378
379
379
380
vreg_s11b: smps11 {
···
382
381
regulator-min-microvolt = <1272000>;
383
382
regulator-max-microvolt = <1272000>;
384
383
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
384
+
regulator-always-on;
385
385
};
386
386
387
387
vreg_s12b: smps12 {
···
390
388
regulator-min-microvolt = <984000>;
391
389
regulator-max-microvolt = <984000>;
392
390
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
391
+
regulator-always-on;
393
392
};
394
393
395
394
vreg_l3b: ldo3 {
···
462
459
regulator-min-microvolt = <3008000>;
463
460
regulator-max-microvolt = <3960000>;
464
461
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
462
+
regulator-always-on;
465
463
};
466
464
};
467
465
···
824
820
pmic-die-temp@3 {
825
821
reg = <PMK8350_ADC7_DIE_TEMP>;
826
822
qcom,pre-scaling = <1 1>;
823
+
label = "pmk8350_die_temp";
827
824
};
828
825
829
826
xo-therm@44 {
830
827
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
831
828
qcom,hw-settle-time = <200>;
832
829
qcom,ratiometric;
830
+
label = "pmk8350_xo_therm";
833
831
};
834
832
835
833
pmic-die-temp@103 {
836
834
reg = <PM8350_ADC7_DIE_TEMP(1)>;
837
835
qcom,pre-scaling = <1 1>;
836
+
label = "pmc8280_1_die_temp";
838
837
};
839
838
840
839
sys-therm@144 {
841
840
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
842
841
qcom,hw-settle-time = <200>;
843
842
qcom,ratiometric;
843
+
label = "sys_therm1";
844
844
};
845
845
846
846
sys-therm@145 {
847
847
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
848
848
qcom,hw-settle-time = <200>;
849
849
qcom,ratiometric;
850
+
label = "sys_therm2";
850
851
};
851
852
852
853
sys-therm@146 {
853
854
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
854
855
qcom,hw-settle-time = <200>;
855
856
qcom,ratiometric;
857
+
label = "sys_therm3";
856
858
};
857
859
858
860
sys-therm@147 {
859
861
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
860
862
qcom,hw-settle-time = <200>;
861
863
qcom,ratiometric;
864
+
label = "sys_therm4";
862
865
};
863
866
864
867
pmic-die-temp@303 {
865
868
reg = <PM8350_ADC7_DIE_TEMP(3)>;
866
869
qcom,pre-scaling = <1 1>;
870
+
label = "pmc8280_2_die_temp";
867
871
};
868
872
869
873
sys-therm@344 {
870
874
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
871
875
qcom,hw-settle-time = <200>;
872
876
qcom,ratiometric;
877
+
label = "sys_therm5";
873
878
};
874
879
875
880
sys-therm@345 {
876
881
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
877
882
qcom,hw-settle-time = <200>;
878
883
qcom,ratiometric;
884
+
label = "sys_therm6";
879
885
};
880
886
881
887
sys-therm@346 {
882
888
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
883
889
qcom,hw-settle-time = <200>;
884
890
qcom,ratiometric;
891
+
label = "sys_therm7";
885
892
};
886
893
887
894
sys-therm@347 {
888
895
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
889
896
qcom,hw-settle-time = <200>;
890
897
qcom,ratiometric;
898
+
label = "sys_therm8";
891
899
};
892
900
893
901
pmic-die-temp@403 {
894
902
reg = <PMR735A_ADC7_DIE_TEMP>;
895
903
qcom,pre-scaling = <1 1>;
904
+
label = "pmr735a_die_temp";
896
905
};
897
906
};
898
907
···
949
932
"VA DMIC0", "MIC BIAS1",
950
933
"VA DMIC1", "MIC BIAS1",
951
934
"VA DMIC2", "MIC BIAS3",
952
-
"TX DMIC0", "MIC BIAS1",
953
-
"TX DMIC1", "MIC BIAS2",
954
-
"TX DMIC2", "MIC BIAS3",
935
+
"VA DMIC0", "VA MIC BIAS1",
936
+
"VA DMIC1", "VA MIC BIAS1",
937
+
"VA DMIC2", "VA MIC BIAS3",
955
938
"TX SWR_ADC1", "ADC2_OUTPUT";
956
939
957
940
wcd-playback-dai-link {
···
1002
985
va-dai-link {
1003
986
link-name = "VA Capture";
1004
987
cpu {
1005
-
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
988
+
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
1006
989
};
1007
990
1008
991
platform {
···
1127
1110
1128
1111
vdd-micb-supply = <&vreg_s10b>;
1129
1112
1130
-
qcom,dmic-sample-rate = <600000>;
1113
+
qcom,dmic-sample-rate = <4800000>;
1131
1114
1132
1115
status = "okay";
1133
1116
};
+9
-9
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+9
-9
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
···
2512
2512
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2513
2513
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2514
2514
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2515
-
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2516
-
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2515
+
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2516
+
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2517
2517
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2518
-
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2518
+
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2519
2519
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2520
-
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2520
+
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2521
2521
2522
2522
#sound-dai-cells = <1>;
2523
2523
#address-cells = <2>;
···
2608
2608
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2609
2609
interrupt-names = "core", "wake";
2610
2610
2611
-
clocks = <&vamacro>;
2611
+
clocks = <&txmacro>;
2612
2612
clock-names = "iface";
2613
2613
label = "TX";
2614
2614
#sound-dai-cells = <1>;
···
2617
2617
2618
2618
qcom,din-ports = <4>;
2619
2619
qcom,dout-ports = <0>;
2620
-
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>;
2621
-
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>;
2620
+
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2621
+
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2622
2622
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2623
2623
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2624
2624
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2625
2625
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2626
-
qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>;
2626
+
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2627
2627
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2628
-
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>;
2628
+
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2629
2629
2630
2630
status = "disabled";
2631
2631
};
+2
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
+2
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
···
753
753
left_spkr: speaker@0,3 {
754
754
compatible = "sdw10217211000";
755
755
reg = <0 3>;
756
-
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
756
+
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>;
757
757
#thermal-sensor-cells = <0>;
758
758
sound-name-prefix = "SpkrLeft";
759
759
#sound-dai-cells = <0>;
···
761
761
762
762
right_spkr: speaker@0,4 {
763
763
compatible = "sdw10217211000";
764
-
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
764
+
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>;
765
765
reg = <0 4>;
766
766
#thermal-sensor-cells = <0>;
767
767
sound-name-prefix = "SpkrRight";
+2
-2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
+2
-2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
···
662
662
left_spkr: speaker@0,3 {
663
663
compatible = "sdw10217211000";
664
664
reg = <0 3>;
665
-
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
665
+
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>;
666
666
#thermal-sensor-cells = <0>;
667
667
sound-name-prefix = "SpkrLeft";
668
668
#sound-dai-cells = <0>;
···
670
670
671
671
right_spkr: speaker@0,4 {
672
672
compatible = "sdw10217211000";
673
-
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
673
+
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>;
674
674
reg = <0 4>;
675
675
#thermal-sensor-cells = <0>;
676
676
sound-name-prefix = "SpkrRight";
+1
arch/arm64/boot/dts/qcom/sm6115.dtsi
+1
arch/arm64/boot/dts/qcom/sm6115.dtsi
+1
arch/arm64/boot/dts/qcom/sm6375.dtsi
+1
arch/arm64/boot/dts/qcom/sm6375.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm8150.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm8150.dtsi
···
1850
1850
"slave_q2a",
1851
1851
"tbu";
1852
1852
1853
-
iommus = <&apps_smmu 0x1d80 0x7f>;
1853
+
iommus = <&apps_smmu 0x1d80 0x3f>;
1854
1854
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1855
1855
<0x100 &apps_smmu 0x1d81 0x1>;
1856
1856
···
1949
1949
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1950
1950
assigned-clock-rates = <19200000>;
1951
1951
1952
-
iommus = <&apps_smmu 0x1e00 0x7f>;
1952
+
iommus = <&apps_smmu 0x1e00 0x3f>;
1953
1953
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1954
1954
<0x100 &apps_smmu 0x1e01 0x1>;
1955
1955
+2
-2
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+2
-2
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
···
764
764
left_spkr: speaker@0,3 {
765
765
compatible = "sdw10217211000";
766
766
reg = <0 3>;
767
-
powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
767
+
powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
768
768
#thermal-sensor-cells = <0>;
769
769
sound-name-prefix = "SpkrLeft";
770
770
#sound-dai-cells = <0>;
···
773
773
right_spkr: speaker@0,4 {
774
774
compatible = "sdw10217211000";
775
775
reg = <0 4>;
776
-
powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>;
776
+
powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_LOW>;
777
777
#thermal-sensor-cells = <0>;
778
778
sound-name-prefix = "SpkrRight";
779
779
#sound-dai-cells = <0>;
+1
-1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts
+1
-1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts
+1
arch/arm64/boot/dts/qcom/sm8350.dtsi
+1
arch/arm64/boot/dts/qcom/sm8350.dtsi
+3
-2
arch/arm64/boot/dts/qcom/sm8450.dtsi
+3
-2
arch/arm64/boot/dts/qcom/sm8450.dtsi
···
2128
2128
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2129
2129
<&vamacro>;
2130
2130
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2131
-
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2132
-
<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2131
+
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2132
+
<&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2133
2133
assigned-clock-rates = <19200000>, <19200000>;
2134
2134
2135
2135
#clock-cells = <0>;
···
4082
4082
power-domains = <&gcc UFS_PHY_GDSC>;
4083
4083
4084
4084
iommus = <&apps_smmu 0xe0 0x0>;
4085
+
dma-coherent;
4085
4086
4086
4087
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4087
4088
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
+25
-24
arch/arm64/boot/dts/qcom/sm8550.dtsi
+25
-24
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
66
66
67
67
CPU0: cpu@0 {
68
68
device_type = "cpu";
69
-
compatible = "qcom,kryo";
69
+
compatible = "arm,cortex-a510";
70
70
reg = <0 0>;
71
71
clocks = <&cpufreq_hw 0>;
72
72
enable-method = "psci";
···
90
90
91
91
CPU1: cpu@100 {
92
92
device_type = "cpu";
93
-
compatible = "qcom,kryo";
93
+
compatible = "arm,cortex-a510";
94
94
reg = <0 0x100>;
95
95
clocks = <&cpufreq_hw 0>;
96
96
enable-method = "psci";
···
110
110
111
111
CPU2: cpu@200 {
112
112
device_type = "cpu";
113
-
compatible = "qcom,kryo";
113
+
compatible = "arm,cortex-a510";
114
114
reg = <0 0x200>;
115
115
clocks = <&cpufreq_hw 0>;
116
116
enable-method = "psci";
···
130
130
131
131
CPU3: cpu@300 {
132
132
device_type = "cpu";
133
-
compatible = "qcom,kryo";
133
+
compatible = "arm,cortex-a715";
134
134
reg = <0 0x300>;
135
135
clocks = <&cpufreq_hw 1>;
136
136
enable-method = "psci";
···
150
150
151
151
CPU4: cpu@400 {
152
152
device_type = "cpu";
153
-
compatible = "qcom,kryo";
153
+
compatible = "arm,cortex-a715";
154
154
reg = <0 0x400>;
155
155
clocks = <&cpufreq_hw 1>;
156
156
enable-method = "psci";
···
170
170
171
171
CPU5: cpu@500 {
172
172
device_type = "cpu";
173
-
compatible = "qcom,kryo";
173
+
compatible = "arm,cortex-a710";
174
174
reg = <0 0x500>;
175
175
clocks = <&cpufreq_hw 1>;
176
176
enable-method = "psci";
···
190
190
191
191
CPU6: cpu@600 {
192
192
device_type = "cpu";
193
-
compatible = "qcom,kryo";
193
+
compatible = "arm,cortex-a710";
194
194
reg = <0 0x600>;
195
195
clocks = <&cpufreq_hw 1>;
196
196
enable-method = "psci";
···
210
210
211
211
CPU7: cpu@700 {
212
212
device_type = "cpu";
213
-
compatible = "qcom,kryo";
213
+
compatible = "arm,cortex-x3";
214
214
reg = <0 0x700>;
215
215
clocks = <&cpufreq_hw 2>;
216
216
enable-method = "psci";
···
1896
1896
required-opps = <&rpmhpd_opp_nom>;
1897
1897
1898
1898
iommus = <&apps_smmu 0x60 0x0>;
1899
+
dma-coherent;
1899
1900
1900
1901
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1901
1902
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
···
1989
1988
lpass_tlmm: pinctrl@6e80000 {
1990
1989
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
1991
1990
reg = <0 0x06e80000 0 0x20000>,
1992
-
<0 0x0725a000 0 0x10000>;
1991
+
<0 0x07250000 0 0x10000>;
1993
1992
gpio-controller;
1994
1993
#gpio-cells = <2>;
1995
1994
gpio-ranges = <&lpass_tlmm 0 0 23>;
···
2705
2704
pins = "gpio28", "gpio29";
2706
2705
function = "qup1_se0";
2707
2706
drive-strength = <2>;
2708
-
bias-pull-up;
2707
+
bias-pull-up = <2200>;
2709
2708
};
2710
2709
2711
2710
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
···
2713
2712
pins = "gpio32", "gpio33";
2714
2713
function = "qup1_se1";
2715
2714
drive-strength = <2>;
2716
-
bias-pull-up;
2715
+
bias-pull-up = <2200>;
2717
2716
};
2718
2717
2719
2718
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
···
2721
2720
pins = "gpio36", "gpio37";
2722
2721
function = "qup1_se2";
2723
2722
drive-strength = <2>;
2724
-
bias-pull-up;
2723
+
bias-pull-up = <2200>;
2725
2724
};
2726
2725
2727
2726
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
···
2729
2728
pins = "gpio40", "gpio41";
2730
2729
function = "qup1_se3";
2731
2730
drive-strength = <2>;
2732
-
bias-pull-up;
2731
+
bias-pull-up = <2200>;
2733
2732
};
2734
2733
2735
2734
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
···
2737
2736
pins = "gpio44", "gpio45";
2738
2737
function = "qup1_se4";
2739
2738
drive-strength = <2>;
2740
-
bias-pull-up;
2739
+
bias-pull-up = <2200>;
2741
2740
};
2742
2741
2743
2742
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
···
2745
2744
pins = "gpio52", "gpio53";
2746
2745
function = "qup1_se5";
2747
2746
drive-strength = <2>;
2748
-
bias-pull-up;
2747
+
bias-pull-up = <2200>;
2749
2748
};
2750
2749
2751
2750
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
···
2753
2752
pins = "gpio48", "gpio49";
2754
2753
function = "qup1_se6";
2755
2754
drive-strength = <2>;
2756
-
bias-pull-up;
2755
+
bias-pull-up = <2200>;
2757
2756
};
2758
2757
2759
2758
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
···
2761
2760
pins = "gpio57";
2762
2761
function = "qup2_se0_l1_mira";
2763
2762
drive-strength = <2>;
2764
-
bias-pull-up;
2763
+
bias-pull-up = <2200>;
2765
2764
};
2766
2765
2767
2766
sda-pins {
2768
2767
pins = "gpio56";
2769
2768
function = "qup2_se0_l0_mira";
2770
2769
drive-strength = <2>;
2771
-
bias-pull-up;
2770
+
bias-pull-up = <2200>;
2772
2771
};
2773
2772
};
2774
2773
···
2777
2776
pins = "gpio60", "gpio61";
2778
2777
function = "qup2_se1";
2779
2778
drive-strength = <2>;
2780
-
bias-pull-up;
2779
+
bias-pull-up = <2200>;
2781
2780
};
2782
2781
2783
2782
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
···
2785
2784
pins = "gpio64", "gpio65";
2786
2785
function = "qup2_se2";
2787
2786
drive-strength = <2>;
2788
-
bias-pull-up;
2787
+
bias-pull-up = <2200>;
2789
2788
};
2790
2789
2791
2790
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
···
2793
2792
pins = "gpio68", "gpio69";
2794
2793
function = "qup2_se3";
2795
2794
drive-strength = <2>;
2796
-
bias-pull-up;
2795
+
bias-pull-up = <2200>;
2797
2796
};
2798
2797
2799
2798
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
···
2801
2800
pins = "gpio2", "gpio3";
2802
2801
function = "qup2_se4";
2803
2802
drive-strength = <2>;
2804
-
bias-pull-up;
2803
+
bias-pull-up = <2200>;
2805
2804
};
2806
2805
2807
2806
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
···
2809
2808
pins = "gpio80", "gpio81";
2810
2809
function = "qup2_se5";
2811
2810
drive-strength = <2>;
2812
-
bias-pull-up;
2811
+
bias-pull-up = <2200>;
2813
2812
};
2814
2813
2815
2814
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
···
2817
2816
pins = "gpio72", "gpio106";
2818
2817
function = "qup2_se7";
2819
2818
drive-strength = <2>;
2820
-
bias-pull-up;
2819
+
bias-pull-up = <2200>;
2821
2820
};
2822
2821
2823
2822
qup_spi0_cs: qup-spi0-cs-state {