Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"A bunch of scattered fixes ati/intel/nouveau, couple of core ones,
nothing too shocking or different."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222S
gma500: Consider CRTC initially active.
drm/radeon: fix dig encoder selection on DCE61
drm/radeon: fix double free in radeon_gpu_reset
drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740
drm/radeon: rework panel mode setup
drm/radeon/atom: powergating fixes for DCE6
drm/radeon/atom: rework DIG modesetting on DCE3+
drm/radeon: don't disable plls that are in use by other crtcs
drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700
drm/radeon: initialize tracked CS state
drm/radeon: fix reading CB_COLORn_MASK from the CS
drm/nvc0/copy: check PUNITS to determine which copy engines are disabled
i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard
drm/i915: Use the correct size of the GTT for placing the per-process entries
drm: Check for invalid cursor flags
drm: Initialize object type when using DRM_MODE() macro
drm/i915: fix color order for BGR formats on IVB
drm/i915: fix wrong order of parameters in port checking functions
+173
-125
+1
-1
drivers/gpu/drm/drm_crtc.c
+1
-1
drivers/gpu/drm/drm_crtc.c
+3
drivers/gpu/drm/drm_edid.c
+3
drivers/gpu/drm/drm_edid.c
+3
drivers/gpu/drm/gma500/psb_intel_display.c
+3
drivers/gpu/drm/gma500/psb_intel_display.c
···
1362
1362
(struct drm_connector **) (psb_intel_crtc + 1);
1363
1363
psb_intel_crtc->mode_set.num_connectors = 0;
1364
1364
psb_intel_cursor_init(dev, psb_intel_crtc);
1365
+
1366
+
/* Set to true so that the pipe is forced off on initial config. */
1367
+
psb_intel_crtc->active = true;
1365
1368
}
1366
1369
1367
1370
int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
+1
-1
drivers/gpu/drm/i915/i915_gem_gtt.c
+1
-1
drivers/gpu/drm/i915/i915_gem_gtt.c
···
72
72
/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
73
73
* entries. For aliasing ppgtt support we just steal them at the end for
74
74
* now. */
75
-
first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
75
+
first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
76
76
77
77
ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
78
78
if (!ppgtt)
+6
-6
drivers/gpu/drm/i915/intel_display.c
+6
-6
drivers/gpu/drm/i915/intel_display.c
···
1384
1384
enum pipe pipe, int reg)
1385
1385
{
1386
1386
u32 val = I915_READ(reg);
1387
-
WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1387
+
WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388
1388
"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389
1389
reg, pipe_name(pipe));
1390
1390
···
1404
1404
1405
1405
reg = PCH_ADPA;
1406
1406
val = I915_READ(reg);
1407
-
WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1407
+
WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408
1408
"PCH VGA enabled on transcoder %c, should be disabled\n",
1409
1409
pipe_name(pipe));
1410
1410
1411
1411
reg = PCH_LVDS;
1412
1412
val = I915_READ(reg);
1413
-
WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1413
+
WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414
1414
"PCH LVDS enabled on transcoder %c, should be disabled\n",
1415
1415
pipe_name(pipe));
1416
1416
···
1872
1872
enum pipe pipe, int reg)
1873
1873
{
1874
1874
u32 val = I915_READ(reg);
1875
-
if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1875
+
if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1876
1876
DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877
1877
reg, pipe);
1878
1878
I915_WRITE(reg, val & ~PORT_ENABLE);
···
1894
1894
1895
1895
reg = PCH_ADPA;
1896
1896
val = I915_READ(reg);
1897
-
if (adpa_pipe_enabled(dev_priv, val, pipe))
1897
+
if (adpa_pipe_enabled(dev_priv, pipe, val))
1898
1898
I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1899
1899
1900
1900
reg = PCH_LVDS;
1901
1901
val = I915_READ(reg);
1902
-
if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1902
+
if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1903
1903
DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1904
1904
I915_WRITE(reg, val & ~LVDS_PORT_EN);
1905
1905
POSTING_READ(reg);
+8
drivers/gpu/drm/i915/intel_lvds.c
+8
drivers/gpu/drm/i915/intel_lvds.c
···
780
780
DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
781
781
},
782
782
},
783
+
{
784
+
.callback = intel_no_lvds_dmi_callback,
785
+
.ident = "Gigabyte GA-D525TUD",
786
+
.matches = {
787
+
DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
788
+
DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
789
+
},
790
+
},
783
791
784
792
{ } /* terminating entry */
785
793
};
+2
-2
drivers/gpu/drm/i915/intel_sprite.c
+2
-2
drivers/gpu/drm/i915/intel_sprite.c
···
60
60
61
61
switch (fb->pixel_format) {
62
62
case DRM_FORMAT_XBGR8888:
63
-
sprctl |= SPRITE_FORMAT_RGBX888;
63
+
sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
64
64
pixel_size = 4;
65
65
break;
66
66
case DRM_FORMAT_XRGB8888:
67
-
sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
67
+
sprctl |= SPRITE_FORMAT_RGBX888;
68
68
pixel_size = 4;
69
69
break;
70
70
case DRM_FORMAT_YUYV:
+4
-2
drivers/gpu/drm/nouveau/nouveau_state.c
+4
-2
drivers/gpu/drm/nouveau/nouveau_state.c
···
736
736
}
737
737
break;
738
738
case NV_C0:
739
-
nvc0_copy_create(dev, 1);
739
+
if (!(nv_rd32(dev, 0x022500) & 0x00000200))
740
+
nvc0_copy_create(dev, 1);
740
741
case NV_D0:
741
-
nvc0_copy_create(dev, 0);
742
+
if (!(nv_rd32(dev, 0x022500) & 0x00000100))
743
+
nvc0_copy_create(dev, 0);
742
744
break;
743
745
default:
744
746
break;
+16
-20
drivers/gpu/drm/radeon/atombios_crtc.c
+16
-20
drivers/gpu/drm/radeon/atombios_crtc.c
···
258
258
radeon_crtc->enabled = true;
259
259
/* adjust pm to dpms changes BEFORE enabling crtcs */
260
260
radeon_pm_compute_clocks(rdev);
261
-
/* disable crtc pair power gating before programming */
262
261
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
263
262
atombios_powergate_crtc(crtc, ATOM_DISABLE);
264
263
atombios_enable_crtc(crtc, ATOM_ENABLE);
···
277
278
atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
278
279
atombios_enable_crtc(crtc, ATOM_DISABLE);
279
280
radeon_crtc->enabled = false;
280
-
/* power gating is per-pair */
281
-
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {
282
-
struct drm_crtc *other_crtc;
283
-
struct radeon_crtc *other_radeon_crtc;
284
-
list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
285
-
other_radeon_crtc = to_radeon_crtc(other_crtc);
286
-
if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
287
-
((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
288
-
((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
289
-
((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
290
-
((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
291
-
((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
292
-
/* if both crtcs in the pair are off, enable power gating */
293
-
if (other_radeon_crtc->enabled == false)
294
-
atombios_powergate_crtc(crtc, ATOM_ENABLE);
295
-
break;
296
-
}
297
-
}
298
-
}
281
+
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
282
+
atombios_powergate_crtc(crtc, ATOM_ENABLE);
299
283
/* adjust pm to dpms changes AFTER disabling crtcs */
300
284
radeon_pm_compute_clocks(rdev);
301
285
break;
···
1664
1682
struct drm_device *dev = crtc->dev;
1665
1683
struct radeon_device *rdev = dev->dev_private;
1666
1684
struct radeon_atom_ss ss;
1685
+
int i;
1667
1686
1668
1687
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1688
+
1689
+
for (i = 0; i < rdev->num_crtc; i++) {
1690
+
if (rdev->mode_info.crtcs[i] &&
1691
+
rdev->mode_info.crtcs[i]->enabled &&
1692
+
i != radeon_crtc->crtc_id &&
1693
+
radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1694
+
/* one other crtc is using this pll don't turn
1695
+
* off the pll
1696
+
*/
1697
+
goto done;
1698
+
}
1699
+
}
1669
1700
1670
1701
switch (radeon_crtc->pll_id) {
1671
1702
case ATOM_PPLL1:
···
1696
1701
default:
1697
1702
break;
1698
1703
}
1704
+
done:
1699
1705
radeon_crtc->pll_id = -1;
1700
1706
}
1701
1707
+12
-17
drivers/gpu/drm/radeon/atombios_dp.c
+12
-17
drivers/gpu/drm/radeon/atombios_dp.c
···
577
577
struct radeon_device *rdev = dev->dev_private;
578
578
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
579
579
int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
580
+
u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
581
+
u8 tmp;
580
582
581
583
if (!ASIC_IS_DCE4(rdev))
582
584
return panel_mode;
583
585
584
-
if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
585
-
ENCODER_OBJECT_ID_NUTMEG)
586
-
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
587
-
else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
588
-
ENCODER_OBJECT_ID_TRAVIS) {
589
-
u8 id[6];
590
-
int i;
591
-
for (i = 0; i < 6; i++)
592
-
id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
593
-
if (id[0] == 0x73 &&
594
-
id[1] == 0x69 &&
595
-
id[2] == 0x76 &&
596
-
id[3] == 0x61 &&
597
-
id[4] == 0x72 &&
598
-
id[5] == 0x54)
586
+
if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
587
+
/* DP bridge chips */
588
+
tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
589
+
if (tmp & 1)
590
+
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
591
+
else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
592
+
(dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
599
593
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
600
594
else
601
-
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
595
+
panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
602
596
} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
603
-
u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
597
+
/* eDP */
598
+
tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
604
599
if (tmp & 1)
605
600
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
606
601
}
+73
-67
drivers/gpu/drm/radeon/atombios_encoders.c
+73
-67
drivers/gpu/drm/radeon/atombios_encoders.c
···
1379
1379
struct drm_device *dev = encoder->dev;
1380
1380
struct radeon_device *rdev = dev->dev_private;
1381
1381
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1382
+
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1383
+
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1382
1384
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1383
1385
struct radeon_connector *radeon_connector = NULL;
1384
1386
struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
···
1392
1390
1393
1391
switch (mode) {
1394
1392
case DRM_MODE_DPMS_ON:
1395
-
/* some early dce3.2 boards have a bug in their transmitter control table */
1396
-
if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
1397
-
ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1398
-
if (ASIC_IS_DCE6(rdev)) {
1399
-
/* It seems we need to call ATOM_ENCODER_CMD_SETUP again
1400
-
* before reenabling encoder on DPMS ON, otherwise we never
1401
-
* get picture
1402
-
*/
1403
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1393
+
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1394
+
if (!connector)
1395
+
dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1396
+
else
1397
+
dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1398
+
1399
+
/* setup and enable the encoder */
1400
+
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1401
+
atombios_dig_encoder_setup(encoder,
1402
+
ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1403
+
dig->panel_mode);
1404
+
if (ext_encoder) {
1405
+
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1406
+
atombios_external_encoder_setup(encoder, ext_encoder,
1407
+
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1404
1408
}
1405
1409
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1406
-
} else {
1410
+
} else if (ASIC_IS_DCE4(rdev)) {
1411
+
/* setup and enable the encoder */
1412
+
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1413
+
/* enable the transmitter */
1414
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1407
1415
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1416
+
} else {
1417
+
/* setup and enable the encoder and transmitter */
1418
+
atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1419
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1420
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1421
+
/* some early dce3.2 boards have a bug in their transmitter control table */
1422
+
if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1423
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1408
1424
}
1409
1425
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1410
1426
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
···
1440
1420
case DRM_MODE_DPMS_STANDBY:
1441
1421
case DRM_MODE_DPMS_SUSPEND:
1442
1422
case DRM_MODE_DPMS_OFF:
1443
-
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1423
+
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1424
+
/* disable the transmitter */
1444
1425
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1445
-
else
1426
+
} else if (ASIC_IS_DCE4(rdev)) {
1427
+
/* disable the transmitter */
1446
1428
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1429
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1430
+
} else {
1431
+
/* disable the encoder and transmitter */
1432
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1433
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1434
+
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1435
+
}
1447
1436
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1448
1437
if (ASIC_IS_DCE4(rdev))
1449
1438
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
···
1769
1740
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1770
1741
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1771
1742
struct drm_encoder *test_encoder;
1772
-
struct radeon_encoder_atom_dig *dig;
1743
+
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1773
1744
uint32_t dig_enc_in_use = 0;
1774
1745
1775
-
/* DCE4/5 */
1776
-
if (ASIC_IS_DCE4(rdev)) {
1777
-
dig = radeon_encoder->enc_priv;
1778
-
if (ASIC_IS_DCE41(rdev)) {
1746
+
if (ASIC_IS_DCE6(rdev)) {
1747
+
/* DCE6 */
1748
+
switch (radeon_encoder->encoder_id) {
1749
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1750
+
if (dig->linkb)
1751
+
return 1;
1752
+
else
1753
+
return 0;
1754
+
break;
1755
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1756
+
if (dig->linkb)
1757
+
return 3;
1758
+
else
1759
+
return 2;
1760
+
break;
1761
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1762
+
if (dig->linkb)
1763
+
return 5;
1764
+
else
1765
+
return 4;
1766
+
break;
1767
+
}
1768
+
} else if (ASIC_IS_DCE4(rdev)) {
1769
+
/* DCE4/5 */
1770
+
if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1779
1771
/* ontario follows DCE4 */
1780
1772
if (rdev->family == CHIP_PALM) {
1781
1773
if (dig->linkb)
···
1898
1848
struct drm_device *dev = encoder->dev;
1899
1849
struct radeon_device *rdev = dev->dev_private;
1900
1850
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1901
-
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1902
1851
1903
1852
radeon_encoder->pixel_clock = adjusted_mode->clock;
1853
+
1854
+
/* need to call this here rather than in prepare() since we need some crtc info */
1855
+
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1904
1856
1905
1857
if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1906
1858
if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
···
1922
1870
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1923
1871
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1924
1872
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1925
-
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1926
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1927
-
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1928
-
1929
-
if (!connector)
1930
-
dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1931
-
else
1932
-
dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1933
-
1934
-
/* setup and enable the encoder */
1935
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1936
-
atombios_dig_encoder_setup(encoder,
1937
-
ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1938
-
dig->panel_mode);
1939
-
} else if (ASIC_IS_DCE4(rdev)) {
1940
-
/* disable the transmitter */
1941
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1942
-
/* setup and enable the encoder */
1943
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1944
-
1945
-
/* enable the transmitter */
1946
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1947
-
} else {
1948
-
/* disable the encoder and transmitter */
1949
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1950
-
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1951
-
1952
-
/* setup and enable the encoder and transmitter */
1953
-
atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1954
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1955
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1956
-
}
1873
+
/* handled in dpms */
1957
1874
break;
1958
1875
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1959
1876
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
···
1941
1920
atombios_tv_setup(encoder, ATOM_DISABLE);
1942
1921
}
1943
1922
break;
1944
-
}
1945
-
1946
-
if (ext_encoder) {
1947
-
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1948
-
atombios_external_encoder_setup(encoder, ext_encoder,
1949
-
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1950
-
else
1951
-
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1952
1923
}
1953
1924
1954
1925
atombios_apply_encoder_quirks(encoder, adjusted_mode);
···
2129
2116
}
2130
2117
2131
2118
radeon_atom_output_lock(encoder, true);
2132
-
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2133
2119
2134
2120
if (connector) {
2135
2121
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
···
2149
2137
2150
2138
static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2151
2139
{
2140
+
/* need to call this here as we need the crtc set up */
2152
2141
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2153
2142
radeon_atom_output_lock(encoder, false);
2154
2143
}
···
2190
2177
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2191
2178
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2192
2179
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2193
-
if (ASIC_IS_DCE4(rdev))
2194
-
/* disable the transmitter */
2195
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2196
-
else {
2197
-
/* disable the encoder and transmitter */
2198
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2199
-
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2200
-
}
2180
+
/* handled in dpms */
2201
2181
break;
2202
2182
case ENCODER_OBJECT_ID_INTERNAL_DDI:
2203
2183
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+25
-3
drivers/gpu/drm/radeon/r600_cs.c
+25
-3
drivers/gpu/drm/radeon/r600_cs.c
···
63
63
u32 cb_color_size_idx[8]; /* unused */
64
64
u32 cb_target_mask;
65
65
u32 cb_shader_mask; /* unused */
66
+
bool is_resolve;
66
67
u32 cb_color_size[8];
67
68
u32 vgt_strmout_en;
68
69
u32 vgt_strmout_buffer_en;
···
316
315
track->cb_color_bo[i] = NULL;
317
316
track->cb_color_bo_offset[i] = 0xFFFFFFFF;
318
317
track->cb_color_bo_mc[i] = 0xFFFFFFFF;
318
+
track->cb_color_frag_bo[i] = NULL;
319
+
track->cb_color_frag_offset[i] = 0xFFFFFFFF;
320
+
track->cb_color_tile_bo[i] = NULL;
321
+
track->cb_color_tile_offset[i] = 0xFFFFFFFF;
322
+
track->cb_color_mask[i] = 0xFFFFFFFF;
319
323
}
324
+
track->is_resolve = false;
325
+
track->nsamples = 16;
326
+
track->log_nsamples = 4;
320
327
track->cb_target_mask = 0xFFFFFFFF;
321
328
track->cb_shader_mask = 0xFFFFFFFF;
322
329
track->cb_dirty = true;
···
361
352
volatile u32 *ib = p->ib.ptr;
362
353
unsigned array_mode;
363
354
u32 format;
355
+
/* When resolve is used, the second colorbuffer has always 1 sample. */
356
+
unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
364
357
365
358
size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
366
359
format = G_0280A0_FORMAT(track->cb_color_info[i]);
···
386
375
array_check.group_size = track->group_size;
387
376
array_check.nbanks = track->nbanks;
388
377
array_check.npipes = track->npipes;
389
-
array_check.nsamples = track->nsamples;
378
+
array_check.nsamples = nsamples;
390
379
array_check.blocksize = r600_fmt_get_blocksize(format);
391
380
if (r600_get_array_mode_alignment(&array_check,
392
381
&pitch_align, &height_align, &depth_align, &base_align)) {
···
432
421
433
422
/* check offset */
434
423
tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
435
-
r600_fmt_get_blocksize(format) * track->nsamples;
424
+
r600_fmt_get_blocksize(format) * nsamples;
436
425
switch (array_mode) {
437
426
default:
438
427
case V_0280A0_ARRAY_LINEAR_GENERAL:
···
803
792
*/
804
793
if (track->cb_dirty) {
805
794
tmp = track->cb_target_mask;
795
+
796
+
/* We must check both colorbuffers for RESOLVE. */
797
+
if (track->is_resolve) {
798
+
tmp |= 0xff;
799
+
}
800
+
806
801
for (i = 0; i < 8; i++) {
807
802
if ((tmp >> (i * 4)) & 0xF) {
808
803
/* at least one component is enabled */
···
1298
1281
track->nsamples = 1 << tmp;
1299
1282
track->cb_dirty = true;
1300
1283
break;
1284
+
case R_028808_CB_COLOR_CONTROL:
1285
+
tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1286
+
track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1287
+
track->cb_dirty = true;
1288
+
break;
1301
1289
case R_0280A0_CB_COLOR0_INFO:
1302
1290
case R_0280A4_CB_COLOR1_INFO:
1303
1291
case R_0280A8_CB_COLOR2_INFO:
···
1438
1416
case R_028118_CB_COLOR6_MASK:
1439
1417
case R_02811C_CB_COLOR7_MASK:
1440
1418
tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1441
-
track->cb_color_mask[tmp] = ib[idx];
1419
+
track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1442
1420
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1443
1421
track->cb_dirty = true;
1444
1422
}
+8
drivers/gpu/drm/radeon/r600d.h
+8
drivers/gpu/drm/radeon/r600d.h
···
66
66
#define CC_RB_BACKEND_DISABLE 0x98F4
67
67
#define BACKEND_DISABLE(x) ((x) << 16)
68
68
69
+
#define R_028808_CB_COLOR_CONTROL 0x28808
70
+
#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
71
+
#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
72
+
#define C_028808_SPECIAL_OP 0xFFFFFF8F
73
+
#define V_028808_SPECIAL_NORMAL 0x00
74
+
#define V_028808_SPECIAL_DISABLE 0x01
75
+
#define V_028808_SPECIAL_RESOLVE_BOX 0x07
76
+
69
77
#define CB_COLOR0_BASE 0x28040
70
78
#define CB_COLOR1_BASE 0x28044
71
79
#define CB_COLOR2_BASE 0x28048
+4
-1
drivers/gpu/drm/radeon/radeon_device.c
+4
-1
drivers/gpu/drm/radeon/radeon_device.c
···
1051
1051
if (rdev->flags & RADEON_IS_AGP)
1052
1052
rdev->need_dma32 = true;
1053
1053
if ((rdev->flags & RADEON_IS_PCI) &&
1054
-
(rdev->family < CHIP_RS400))
1054
+
(rdev->family <= CHIP_RS740))
1055
1055
rdev->need_dma32 = true;
1056
1056
1057
1057
dma_bits = rdev->need_dma32 ? 32 : 40;
···
1346
1346
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1347
1347
radeon_ring_restore(rdev, &rdev->ring[i],
1348
1348
ring_sizes[i], ring_data[i]);
1349
+
ring_sizes[i] = 0;
1350
+
ring_data[i] = NULL;
1349
1351
}
1350
1352
1351
1353
r = radeon_ib_ring_tests(rdev);
1352
1354
if (r) {
1353
1355
dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1354
1356
if (saved) {
1357
+
saved = false;
1355
1358
radeon_suspend(rdev);
1356
1359
goto retry;
1357
1360
}
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
63
63
* 2.19.0 - r600-eg: MSAA textures
64
64
* 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
65
65
* 2.21.0 - r600-r700: FMASK and CMASK
66
+
* 2.22.0 - r600 only: RESOLVE_BOX allowed
66
67
*/
67
68
#define KMS_DRIVER_MAJOR 2
68
-
#define KMS_DRIVER_MINOR 21
69
+
#define KMS_DRIVER_MINOR 22
69
70
#define KMS_DRIVER_PATCHLEVEL 0
70
71
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
71
72
int radeon_driver_unload_kms(struct drm_device *dev);
-1
drivers/gpu/drm/radeon/reg_srcs/r600
-1
drivers/gpu/drm/radeon/reg_srcs/r600
+2
-1
include/drm/drm_crtc.h
+2
-1
include/drm/drm_crtc.h
···
118
118
.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
119
119
.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
120
120
.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
121
-
.vscan = (vs), .flags = (f), .vrefresh = 0
121
+
.vscan = (vs), .flags = (f), .vrefresh = 0, \
122
+
.base.type = DRM_MODE_OBJECT_MODE
122
123
123
124
#define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
124
125
+3
-2
include/drm/drm_mode.h
+3
-2
include/drm/drm_mode.h
···
359
359
struct drm_mode_modeinfo mode;
360
360
};
361
361
362
-
#define DRM_MODE_CURSOR_BO (1<<0)
363
-
#define DRM_MODE_CURSOR_MOVE (1<<1)
362
+
#define DRM_MODE_CURSOR_BO 0x01
363
+
#define DRM_MODE_CURSOR_MOVE 0x02
364
+
#define DRM_MODE_CURSOR_FLAGS 0x03
364
365
365
366
/*
366
367
* depending on the value in flags different members are used.