tjh.dev / kernel
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mfd: rk8xx: Add RK801 support

The RK801 is a Power Management IC (PMIC) for multimedia
and handheld devices. It contains the following components:

- 4 BUCK
- 2 LDO
- 1 SWITCH

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Link: https://patch.msgid.link/20260112124351.17707-3-chenjh@rock-chips.com
Signed-off-by: Lee Jones <lee@kernel.org>

authored by

Joseph Chen and committed by
Lee Jones 156442eb a8a2add7

+234 -4
+3 -3
drivers/mfd/Kconfig
··· 1371 1371 select MFD_CORE 1372 1372 1373 1373 config MFD_RK8XX_I2C 1374 - tristate "Rockchip RK805/RK808/RK809/RK816/RK817/RK818 Power Management Chip" 1374 + tristate "Rockchip RK8xx Power Management Chips" 1375 1375 depends on I2C && OF 1376 1376 select MFD_CORE 1377 1377 select REGMAP_I2C 1378 1378 select REGMAP_IRQ 1379 1379 select MFD_RK8XX 1380 1380 help 1381 - If you say yes here you get support for the RK805, RK808, RK809, 1382 - RK816, RK817 and RK818 Power Management chips. 1381 + If you say yes here you get support for the RK801, RK805, RK808, 1382 + RK809, RK816, RK817 and RK818 Power Management chips. 1383 1383 This driver provides common support for accessing the device 1384 1384 through I2C interface. The device supports multiple sub-devices 1385 1385 including interrupts, RTC, LDO & DCDC regulators, and onkey.
+81
drivers/mfd/rk8xx-core.c
··· 37 37 DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM), 38 38 }; 39 39 40 + static const struct resource rk801_key_resources[] = { 41 + DEFINE_RES_IRQ(RK801_IRQ_PWRON_FALL), 42 + DEFINE_RES_IRQ(RK801_IRQ_PWRON_RISE), 43 + }; 44 + 40 45 static const struct resource rk805_key_resources[] = { 41 46 DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE), 42 47 DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL), ··· 60 55 static const struct resource rk817_charger_resources[] = { 61 56 DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN), 62 57 DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT), 58 + }; 59 + 60 + static const struct mfd_cell rk801s[] = { 61 + { .name = "rk808-regulator", }, 62 + { .name = "rk805-pwrkey", 63 + .num_resources = ARRAY_SIZE(rk801_key_resources), 64 + .resources = &rk801_key_resources[0], 65 + }, 63 66 }; 64 67 65 68 static const struct mfd_cell rk805s[] = { ··· 150 137 .num_resources = ARRAY_SIZE(rtc_resources), 151 138 .resources = rtc_resources, 152 139 }, 140 + }; 141 + 142 + static const struct rk808_reg_data rk801_pre_init_reg[] = { 143 + { RK801_SLEEP_CFG_REG, RK801_SLEEP_FUN_MSK, RK801_NONE_FUN }, 144 + { RK801_SYS_CFG2_REG, RK801_RST_MSK, RK801_RST_RESTART_REG_RESETB }, 145 + { RK801_INT_CONFIG_REG, RK801_INT_POL_MSK, RK801_INT_ACT_L }, 146 + { RK801_POWER_FPWM_EN_REG, RK801_PLDO_HRDEC_EN, RK801_PLDO_HRDEC_EN }, 147 + { RK801_BUCK_DEBUG5_REG, MASK_ALL, 0x54 }, 148 + { RK801_CON_BACK1_REG, MASK_ALL, 0x18 }, 153 149 }; 154 150 155 151 static const struct rk808_reg_data rk805_pre_init_reg[] = { ··· 304 282 { RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN }, 305 283 { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | 306 284 VB_LO_SEL_3500MV }, 285 + }; 286 + 287 + static const struct regmap_irq rk801_irqs[] = { 288 + [RK801_IRQ_PWRON_FALL] = { 289 + .mask = RK801_IRQ_PWRON_FALL_MSK, 290 + .reg_offset = 0, 291 + }, 292 + [RK801_IRQ_PWRON_RISE] = { 293 + .mask = RK801_IRQ_PWRON_RISE_MSK, 294 + .reg_offset = 0, 295 + }, 296 + [RK801_IRQ_PWRON] = { 297 + .mask = RK801_IRQ_PWRON_MSK, 298 + .reg_offset = 0, 299 + }, 300 + [RK801_IRQ_PWRON_LP] = { 301 + .mask = RK801_IRQ_PWRON_LP_MSK, 302 + .reg_offset = 0, 303 + }, 304 + [RK801_IRQ_HOTDIE] = { 305 + .mask = RK801_IRQ_HOTDIE_MSK, 306 + .reg_offset = 0, 307 + }, 308 + [RK801_IRQ_VDC_RISE] = { 309 + .mask = RK801_IRQ_VDC_RISE_MSK, 310 + .reg_offset = 0, 311 + }, 312 + [RK801_IRQ_VDC_FALL] = { 313 + .mask = RK801_IRQ_VDC_FALL_MSK, 314 + .reg_offset = 0, 315 + }, 307 316 }; 308 317 309 318 static const struct regmap_irq rk805_irqs[] = { ··· 585 532 REGMAP_IRQ_REG_LINE(23, 8) 586 533 }; 587 534 535 + static const struct regmap_irq_chip rk801_irq_chip = { 536 + .name = "rk801", 537 + .irqs = rk801_irqs, 538 + .num_irqs = ARRAY_SIZE(rk801_irqs), 539 + .num_regs = 1, 540 + .status_base = RK801_INT_STS0_REG, 541 + .mask_base = RK801_INT_MASK0_REG, 542 + .ack_base = RK801_INT_STS0_REG, 543 + .init_ack_masked = true, 544 + }; 545 + 588 546 static const struct regmap_irq_chip rk805_irq_chip = { 589 547 .name = "rk805", 590 548 .irqs = rk805_irqs, ··· 674 610 unsigned int reg, bit; 675 611 676 612 switch (rk808->variant) { 613 + case RK801_ID: 614 + reg = RK801_SYS_CFG2_REG; 615 + bit = DEV_OFF; 616 + break; 677 617 case RK805_ID: 678 618 reg = RK805_DEV_CTRL_REG; 679 619 bit = DEV_OFF; ··· 782 714 dev_set_drvdata(dev, rk808); 783 715 784 716 switch (rk808->variant) { 717 + case RK801_ID: 718 + rk808->regmap_irq_chip = &rk801_irq_chip; 719 + pre_init_reg = rk801_pre_init_reg; 720 + nr_pre_init_regs = ARRAY_SIZE(rk801_pre_init_reg); 721 + cells = rk801s; 722 + nr_cells = ARRAY_SIZE(rk801s); 723 + break; 785 724 case RK805_ID: 786 725 rk808->regmap_irq_chip = &rk805_irq_chip; 787 726 pre_init_reg = rk805_pre_init_reg; ··· 906 831 int ret = 0; 907 832 908 833 switch (rk808->variant) { 834 + case RK801_ID: 835 + ret = regmap_update_bits(rk808->regmap, 836 + RK801_SLEEP_CFG_REG, 837 + RK801_SLEEP_FUN_MSK, 838 + RK801_SLEEP_FUN); 839 + break; 909 840 case RK805_ID: 910 841 ret = regmap_update_bits(rk808->regmap, 911 842 RK805_GPIO_IO_POL_REG,
+32 -1
drivers/mfd/rk8xx-i2c.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Rockchip RK805/RK808/RK816/RK817/RK818 Core (I2C) driver 3 + * Rockchip RK801/RK805/RK808/RK816/RK817/RK818 Core (I2C) driver 4 4 * 5 5 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 6 6 * Copyright (C) 2016 PHYTEC Messtechnik GmbH ··· 20 20 const struct regmap_config *regmap_cfg; 21 21 int variant; 22 22 }; 23 + 24 + static bool rk801_is_volatile_reg(struct device *dev, unsigned int reg) 25 + { 26 + switch (reg) { 27 + case RK801_SYS_STS_REG: 28 + case RK801_INT_STS0_REG: 29 + case RK801_SYS_CFG0_REG: 30 + case RK801_SYS_CFG1_REG: 31 + case RK801_SYS_CFG2_REG: 32 + case RK801_SYS_CFG3_REG: 33 + case RK801_SYS_CFG4_REG: 34 + case RK801_SLEEP_CFG_REG: 35 + return true; 36 + } 37 + 38 + return false; 39 + } 23 40 24 41 static bool rk806_is_volatile_reg(struct device *dev, unsigned int reg) 25 42 { ··· 141 124 .volatile_reg = rk808_is_volatile_reg, 142 125 }; 143 126 127 + static const struct regmap_config rk801_regmap_config = { 128 + .reg_bits = 8, 129 + .val_bits = 8, 130 + .max_register = RK801_SYS_CFG3_OTP_REG, 131 + .cache_type = REGCACHE_RBTREE, 132 + .volatile_reg = rk801_is_volatile_reg, 133 + }; 134 + 144 135 static const struct regmap_config rk805_regmap_config = { 145 136 .reg_bits = 8, 146 137 .val_bits = 8, ··· 187 162 .max_register = RK817_GPIO_INT_CFG, 188 163 .cache_type = REGCACHE_NONE, 189 164 .volatile_reg = rk817_is_volatile_reg, 165 + }; 166 + 167 + static const struct rk8xx_i2c_platform_data rk801_data = { 168 + .regmap_cfg = &rk801_regmap_config, 169 + .variant = RK801_ID, 190 170 }; 191 171 192 172 static const struct rk8xx_i2c_platform_data rk805_data = { ··· 254 224 static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume); 255 225 256 226 static const struct of_device_id rk8xx_i2c_of_match[] = { 227 + { .compatible = "rockchip,rk801", .data = &rk801_data }, 257 228 { .compatible = "rockchip,rk805", .data = &rk805_data }, 258 229 { .compatible = "rockchip,rk806", .data = &rk806_data }, 259 230 { .compatible = "rockchip,rk808", .data = &rk808_data },
+118
include/linux/mfd/rk808.h
··· 340 340 #define RK818_USB_ILMIN_2000MA 0x7 341 341 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 342 342 343 + /* RK801 */ 344 + enum rk801_reg { 345 + RK801_ID_DCDC1, 346 + RK801_ID_DCDC2, 347 + RK801_ID_DCDC4, 348 + RK801_ID_DCDC3, 349 + RK801_ID_LDO1, 350 + RK801_ID_LDO2, 351 + RK801_ID_SWITCH, 352 + RK801_ID_MAX, 353 + }; 354 + 355 + #define RK801_SLP_REG_OFFSET 5 356 + #define RK801_NUM_REGULATORS 7 357 + 358 + #define RK801_HW_SYNC_US 32 359 + 360 + /* RK801 Register Definitions */ 361 + #define RK801_ID_MSB 0x00 362 + #define RK801_ID_LSB 0x01 363 + #define RK801_OTP_VER_REG 0x02 364 + #define RK801_POWER_EN0_REG 0x03 365 + #define RK801_POWER_EN1_REG 0x04 366 + #define RK801_POWER_SLP_EN_REG 0x05 367 + #define RK801_POWER_FPWM_EN_REG 0x06 368 + #define RK801_SLP_LP_CONFIG_REG 0x07 369 + #define RK801_BUCK_CONFIG_REG 0x08 370 + #define RK801_BUCK1_ON_VSEL_REG 0x09 371 + #define RK801_BUCK2_ON_VSEL_REG 0x0a 372 + #define RK801_BUCK4_ON_VSEL_REG 0x0b 373 + #define RK801_LDO1_ON_VSEL_REG 0x0c 374 + #define RK801_LDO2_ON_VSEL_REG 0x0d 375 + #define RK801_BUCK1_SLP_VSEL_REG 0x0e 376 + #define RK801_BUCK2_SLP_VSEL_REG 0x0f 377 + #define RK801_BUCK4_SLP_VSEL_REG 0x10 378 + #define RK801_LDO1_SLP_VSEL_REG 0x11 379 + #define RK801_LDO2_SLP_VSEL_REG 0x12 380 + #define RK801_LDO_SW_IMAX_REG 0x13 381 + #define RK801_SYS_STS_REG 0x14 382 + #define RK801_SYS_CFG0_REG 0x15 383 + #define RK801_SYS_CFG1_REG 0x16 384 + #define RK801_SYS_CFG2_REG 0x17 385 + #define RK801_SYS_CFG3_REG 0x18 386 + #define RK801_SYS_CFG4_REG 0x19 387 + #define RK801_SLEEP_CFG_REG 0x1a 388 + #define RK801_ON_SOURCE_REG 0x1b 389 + #define RK801_OFF_SOURCE_REG 0x1c 390 + #define RK801_PWRON_KEY_REG 0x1d 391 + #define RK801_INT_STS0_REG 0x1e 392 + #define RK801_INT_MASK0_REG 0x1f 393 + #define RK801_INT_CONFIG_REG 0x20 394 + #define RK801_CON_BACK1_REG 0x21 395 + #define RK801_CON_BACK2_REG 0x22 396 + #define RK801_DATA_CON0_REG 0x23 397 + #define RK801_DATA_CON1_REG 0x24 398 + #define RK801_DATA_CON2_REG 0x25 399 + #define RK801_DATA_CON3_REG 0x26 400 + #define RK801_POWER_EXIT_SLP_SEQ0_REG 0x27 401 + #define RK801_POWER_EXIT_SLP_SEQ1_REG 0x28 402 + #define RK801_POWER_EXIT_SLP_SEQ2_REG 0x29 403 + #define RK801_POWER_EXIT_SLP_SEQ3_REG 0x2a 404 + #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ0_REG 0x2b 405 + #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ1_REG 0x2c 406 + #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ2_REG 0x2d 407 + #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ3_REG 0x2e 408 + #define RK801_BUCK_DEBUG1_REG 0x2f 409 + #define RK801_BUCK_DEBUG2_REG 0x30 410 + #define RK801_BUCK_DEBUG3_REG 0x31 411 + #define RK801_BUCK_DEBUG4_REG 0x32 412 + #define RK801_BUCK_DEBUG5_REG 0x33 413 + #define RK801_BUCK_DEBUG7_REG 0x34 414 + #define RK801_OTP_EN_CON_REG 0x35 415 + #define RK801_TEST_CON_REG 0x36 416 + #define RK801_EFUSE_CONTROL_REG 0x37 417 + #define RK801_SYS_CFG3_OTP_REG 0x38 418 + 419 + /* RK801 IRQ Definitions */ 420 + #define RK801_IRQ_PWRON_FALL 0 421 + #define RK801_IRQ_PWRON_RISE 1 422 + #define RK801_IRQ_PWRON 2 423 + #define RK801_IRQ_PWRON_LP 3 424 + #define RK801_IRQ_HOTDIE 4 425 + #define RK801_IRQ_VDC_RISE 5 426 + #define RK801_IRQ_VDC_FALL 6 427 + #define RK801_IRQ_PWRON_FALL_MSK BIT(0) 428 + #define RK801_IRQ_PWRON_RISE_MSK BIT(1) 429 + #define RK801_IRQ_PWRON_MSK BIT(2) 430 + #define RK801_IRQ_PWRON_LP_MSK BIT(3) 431 + #define RK801_IRQ_HOTDIE_MSK BIT(4) 432 + #define RK801_IRQ_VDC_RISE_MSK BIT(5) 433 + #define RK801_IRQ_VDC_FALL_MSK BIT(6) 434 + /* RK801_SLP_LP_CONFIG_REG */ 435 + #define RK801_BUCK_SLP_LP_EN BIT(3) 436 + #define RK801_PLDO_SLP_LP_EN BIT(1) 437 + #define RK801_SLP_LP_MASK (RK801_PLDO_SLP_LP_EN | RK801_BUCK_SLP_LP_EN) 438 + /* RK801_SLEEP_CFG_REG */ 439 + #define RK801_SLEEP_FUN_MSK 0x3 440 + #define RK801_NONE_FUN 0x0 441 + #define RK801_SLEEP_FUN 0x1 442 + #define RK801_SHUTDOWN_FUN 0x2 443 + #define RK801_RESET_FUN 0x3 444 + /* RK801_SYS_CFG2_REG */ 445 + #define RK801_SLEEP_POL_MSK BIT(1) 446 + #define RK801_SLEEP_ACT_H BIT(1) 447 + #define RK801_SLEEP_ACT_L 0 448 + #define RK801_RST_MSK (0x3 << 4) 449 + #define RK801_RST_RESTART_PMU (0x0 << 4) 450 + #define RK801_RST_RESTART_REG (0x1 << 4) 451 + #define RK801_RST_RESTART_REG_RESETB (0x2 << 4) 452 + /* RK801_INT_CONFIG_REG */ 453 + #define RK801_INT_POL_MSK BIT(1) 454 + #define RK801_INT_ACT_H BIT(1) 455 + #define RK801_INT_ACT_L 0 456 + #define RK801_FPWM_MODE 1 457 + #define RK801_AUTO_PWM_MODE 0 458 + #define RK801_PLDO_HRDEC_EN BIT(6) 459 + 343 460 /* RK805 */ 344 461 enum rk805_reg { 345 462 RK805_ID_DCDC1, ··· 1449 1332 }; 1450 1333 1451 1334 enum { 1335 + RK801_ID = 0x8010, 1452 1336 RK805_ID = 0x8050, 1453 1337 RK806_ID = 0x8060, 1454 1338 RK808_ID = 0x0000,