tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2024-08-10' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly regular fixes, mostly amdgpu with i915/xe having a few each,
and then some misc bits across the board, seems about right for rc3
time.

client:
- fix null ptr deref

bridge:
- connector: fix double free

atomic:
- fix async flip update

panel:
- document panel

omap:
- add config dependency

tests:
- fix gem shmem test

drm buddy:
- Add start address to trim function

amdgpu:
- DMCUB fix
- Fix DET programming on some DCNs
- DCC fixes
- DCN 4.0.1 fixes
- SMU 14.0.x update
- MMHUB fix
- DCN 3.1.4 fix
- GC 12.0 fixes
- Fix soft recovery error propogation
- SDMA 7.0 fixes
- DSC fix

xe:
- Fix off-by-one when processing RTP rules
- Use dma_fence_chain_free in chain fence unused as a sync
- Fix PL1 disable flow in xe_hwmon_power_max_write
- Take ref to VM in delayed dump snapshot

i915:
- correct dual pps handling for MTL_PCH+ [display]
- Adjust vma offset for framebuffer mmap offset [gem]
- Fix Virtual Memory mapping boundaries calculation [gem]
- Allow evicting to use the requested placement
- Attempt to get pages without eviction first"

* tag 'drm-fixes-2024-08-10' of https://gitlab.freedesktop.org/drm/kernel: (31 commits)
drm/xe: Take ref to VM in delayed snapshot
drm/xe/hwmon: Fix PL1 disable flow in xe_hwmon_power_max_write
drm/xe: Use dma_fence_chain_free in chain fence unused as a sync
drm/xe/rtp: Fix off-by-one when processing rules
drm/amdgpu: Add DCC GFX12 flag to enable address alignment
drm/amdgpu: correct sdma7 max dw
drm/amdgpu: Add address alignment support to DCC buffers
drm/amd/display: Skip Recompute DSC Params if no Stream on Link
drm/amdgpu: change non-dcc buffer copy configuration
drm/amdgpu: Forward soft recovery errors to userspace
drm/amdgpu: add golden setting for gc v12
drm/buddy: Add start address support to trim function
drm/amd/display: Add missing program DET segment call to pipe init
drm/amd/display: Add missing DCN314 to the DML Makefile
drm/amdgpu: force to use legacy inv in mmhub
drm/amd/pm: update powerplay structure on smu v14.0.2/3
drm/amd/display: Add missing mcache registers
drm/amd/display: Add dcc propagation value
drm/amd/display: Add missing DET segments programming
drm/amd/display: Replace dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd
...

Linus Torvalds 15833fea afdab700

+287 -56
+6 -3
Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml
··· 17 17 oneOf: 18 18 # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel 19 19 - const: samsung,atna33xc20 20 - # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel 21 20 - items: 22 - - const: samsung,atna45af01 23 - - const: samsung,atna33xc20 21 + - enum: 22 + # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel 23 + - samsung,atna45af01 24 + # Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel 25 + - samsung,atna45dc02 26 + - const: samsung,atna33xc20 24 27 25 28 enable-gpios: true 26 29 port: true
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
··· 156 156 uint64_t addr, uint64_t *flags); 157 157 /* get the amount of memory used by the vbios for pre-OS console */ 158 158 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 159 + /* get the DCC buffer alignment */ 160 + unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 159 161 160 162 enum amdgpu_memory_partition (*query_mem_partition_mode)( 161 163 struct amdgpu_device *adev); ··· 365 363 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 366 364 ((adev), (vm), (addr), (pte_flags)) 367 365 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 366 + #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 367 + typeof(adev) _adev = (adev); \ 368 + _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 369 + }) 368 370 369 371 /** 370 372 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
+1 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
··· 264 264 struct dma_fence *fence = NULL; 265 265 int r; 266 266 267 - /* Ignore soft recovered fences here */ 268 267 r = drm_sched_entity_error(s_entity); 269 - if (r && r != -ENODATA) 268 + if (r) 270 269 goto error; 271 270 272 271 if (!fence && job->gang_submit)
+34 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
··· 456 456 u64 vis_usage = 0, max_bytes, min_block_size; 457 457 struct amdgpu_vram_mgr_resource *vres; 458 458 u64 size, remaining_size, lpfn, fpfn; 459 + unsigned int adjust_dcc_size = 0; 459 460 struct drm_buddy *mm = &mgr->mm; 460 461 struct drm_buddy_block *block; 461 462 unsigned long pages_per_block; ··· 512 511 /* Allocate blocks in desired range */ 513 512 vres->flags |= DRM_BUDDY_RANGE_ALLOCATION; 514 513 514 + if (bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC && 515 + adev->gmc.gmc_funcs->get_dcc_alignment) 516 + adjust_dcc_size = amdgpu_gmc_get_dcc_alignment(adev); 517 + 515 518 remaining_size = (u64)vres->base.size; 519 + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) { 520 + unsigned int dcc_size; 521 + 522 + dcc_size = roundup_pow_of_two(vres->base.size + adjust_dcc_size); 523 + remaining_size = (u64)dcc_size; 524 + 525 + vres->flags |= DRM_BUDDY_TRIM_DISABLE; 526 + } 516 527 517 528 mutex_lock(&mgr->lock); 518 529 while (remaining_size) { ··· 534 521 min_block_size = mgr->default_page_size; 535 522 536 523 size = remaining_size; 537 - if ((size >= (u64)pages_per_block << PAGE_SHIFT) && 538 - !(size & (((u64)pages_per_block << PAGE_SHIFT) - 1))) 524 + 525 + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) 526 + min_block_size = size; 527 + else if ((size >= (u64)pages_per_block << PAGE_SHIFT) && 528 + !(size & (((u64)pages_per_block << PAGE_SHIFT) - 1))) 539 529 min_block_size = (u64)pages_per_block << PAGE_SHIFT; 540 530 541 531 BUG_ON(min_block_size < mm->chunk_size); ··· 568 552 remaining_size -= size; 569 553 } 570 554 mutex_unlock(&mgr->lock); 555 + 556 + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) { 557 + struct drm_buddy_block *dcc_block; 558 + unsigned long dcc_start; 559 + u64 trim_start; 560 + 561 + dcc_block = amdgpu_vram_mgr_first_block(&vres->blocks); 562 + /* Adjust the start address for DCC buffers only */ 563 + dcc_start = 564 + roundup((unsigned long)amdgpu_vram_mgr_block_start(dcc_block), 565 + adjust_dcc_size); 566 + trim_start = (u64)dcc_start; 567 + drm_buddy_block_trim(mm, &trim_start, 568 + (u64)vres->base.size, 569 + &vres->blocks); 570 + } 571 571 572 572 vres->base.start = 0; 573 573 size = max_t(u64, amdgpu_vram_mgr_blocks_size(&vres->blocks),
+27
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 202 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 203 203 }; 204 204 205 + static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 206 + SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 207 + SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 208 + SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 209 + }; 210 + 205 211 #define DEFAULT_SH_MEM_CONFIG \ 206 212 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 207 213 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ ··· 3438 3432 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3439 3433 } 3440 3434 3435 + static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3436 + { 3437 + if (amdgpu_sriov_vf(adev)) 3438 + return; 3439 + 3440 + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3441 + case IP_VERSION(12, 0, 0): 3442 + case IP_VERSION(12, 0, 1): 3443 + if (adev->rev_id == 0) 3444 + soc15_program_register_sequence(adev, 3445 + golden_settings_gc_12_0, 3446 + (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3447 + break; 3448 + default: 3449 + break; 3450 + } 3451 + } 3452 + 3441 3453 static int gfx_v12_0_hw_init(void *handle) 3442 3454 { 3443 3455 int r; ··· 3495 3471 return r; 3496 3472 } 3497 3473 } 3474 + 3475 + if (!amdgpu_emu_mode) 3476 + gfx_v12_0_init_golden_registers(adev); 3498 3477 3499 3478 adev->gfx.is_poweron = true; 3500 3479
+18
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
··· 542 542 return 0; 543 543 } 544 544 545 + static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) 546 + { 547 + unsigned int max_tex_channel_caches, alignment; 548 + 549 + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && 550 + amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) 551 + return 0; 552 + 553 + max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; 554 + if (is_power_of_2(max_tex_channel_caches)) 555 + alignment = (unsigned int)(max_tex_channel_caches / SZ_4); 556 + else 557 + alignment = roundup_pow_of_two(max_tex_channel_caches); 558 + 559 + return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K); 560 + } 561 + 545 562 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 546 563 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 547 564 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, ··· 568 551 .get_vm_pde = gmc_v12_0_get_vm_pde, 569 552 .get_vm_pte = gmc_v12_0_get_vm_pte, 570 553 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 554 + .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, 571 555 }; 572 556 573 557 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev)
+2 -1
drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c
··· 80 80 /* invalidate using legacy mode on vmid*/ 81 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 82 82 PER_VMID_INVALIDATE_REQ, 1 << vmid); 83 - req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 83 + /* Only use legacy inv on mmhub side */ 84 + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 84 85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 85 86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 86 87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+4 -3
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
··· 1575 1575 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1576 1576 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1577 1577 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) | 1578 - SDMA_PKT_COPY_LINEAR_HEADER_CPV((copy_flags & 1579 - (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)) ? 1 : 0); 1578 + SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1580 1579 1581 1580 ib->ptr[ib->length_dw++] = byte_count - 1; 1582 1581 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ ··· 1589 1590 ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) | 1590 1591 ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) | 1591 1592 SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1); 1593 + else 1594 + ib->ptr[ib->length_dw++] = 0; 1592 1595 } 1593 1596 1594 1597 /** ··· 1617 1616 1618 1617 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { 1619 1618 .copy_max_bytes = 0x400000, 1620 - .copy_num_dw = 7, 1619 + .copy_num_dw = 8, 1621 1620 .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, 1622 1621 .fill_max_bytes = 0x400000, 1623 1622 .fill_num_dw = 5,
+3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 1270 1270 } 1271 1271 } 1272 1272 1273 + if (new_stream_on_link_num == 0) 1274 + return false; 1275 + 1273 1276 /* check current_state if there stream on link but it is not in 1274 1277 * new request state 1275 1278 */
+1 -2
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
··· 185 185 else 186 186 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0; 187 187 188 - 189 - dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 188 + dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 190 189 191 190 return true; 192 191 }
+2
drivers/gpu/drm/amd/display/dc/dml/Makefile
··· 83 83 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags) 84 84 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags) 85 85 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags) 86 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn314/display_mode_vba_314.o := $(dml_rcflags) 87 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn314/display_rq_dlg_calc_314.o := $(dml_rcflags) 86 88 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags) 87 89 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags) 88 90 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags)
+2
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
··· 1402 1402 if (hubbub && hubp) { 1403 1403 if (hubbub->funcs->program_det_size) 1404 1404 hubbub->funcs->program_det_size(hubbub, hubp->inst, 0); 1405 + if (hubbub->funcs->program_det_segments) 1406 + hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0); 1405 1407 } 1406 1408 } 1407 1409
+2
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
··· 771 771 if (hubbub && hubp) { 772 772 if (hubbub->funcs->program_det_size) 773 773 hubbub->funcs->program_det_size(hubbub, hubp->inst, 0); 774 + if (hubbub->funcs->program_det_segments) 775 + hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0); 774 776 } 775 777 } 776 778
+1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
··· 723 723 .min_prefetch_in_strobe_ns = 60000, // 60us 724 724 .disable_unbounded_requesting = false, 725 725 .enable_legacy_fast_update = false, 726 + .dcc_meta_propagation_delay_us = 10, 726 727 .fams2_config = { 727 728 .bits = { 728 729 .enable = true,
+3 -1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
··· 138 138 SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ 139 139 SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ 140 140 SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ 141 - HUBP_3DLUT_FL_REG_LIST_DCN401(id) 141 + HUBP_3DLUT_FL_REG_LIST_DCN401(id), \ 142 + SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \ 143 + SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id) 142 144 143 145 /* ABM */ 144 146 #define ABM_DCN401_REG_LIST_RI(id) \
+46 -6
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h
··· 27 27 28 28 #pragma pack(push, 1) 29 29 30 - #define SMU_14_0_2_TABLE_FORMAT_REVISION 3 30 + #define SMU_14_0_2_TABLE_FORMAT_REVISION 23 31 + #define SMU_14_0_2_CUSTOM_TABLE_FORMAT_REVISION 1 31 32 32 33 // POWERPLAYTABLE::ulPlatformCaps 33 34 #define SMU_14_0_2_PP_PLATFORM_CAP_POWERPLAY 0x1 // This cap indicates whether CCC need to show Powerplay page. ··· 44 43 #define SMU_14_0_2_PP_THERMALCONTROLLER_NONE 0 45 44 46 45 #define SMU_14_0_2_PP_OVERDRIVE_VERSION 0x1 // TODO: FIX OverDrive Version TBD 46 + #define SMU_14_0_2_PP_CUSTOM_OVERDRIVE_VERSION 0x1 47 47 #define SMU_14_0_2_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00 48 48 49 49 enum SMU_14_0_2_OD_SW_FEATURE_CAP ··· 109 107 SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_BALANCE, 110 108 SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_TURBO, 111 109 SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_RAGE, 110 + SMU_14_0_2_PMSETTING_COUNT 112 111 }; 113 112 #define SMU_14_0_2_MAX_PMSETTING 32 // Maximum Number of PowerMode Settings 114 113 ··· 130 127 int16_t pm_setting[SMU_14_0_2_MAX_PMSETTING]; // Optimized power mode feature settings 131 128 }; 132 129 130 + enum smu_14_0_3_pptable_source { 131 + PPTABLE_SOURCE_IFWI = 0, 132 + PPTABLE_SOURCE_DRIVER_HARDCODED = 1, 133 + PPTABLE_SOURCE_PPGEN_REGISTRY = 2, 134 + PPTABLE_SOURCE_MAX = PPTABLE_SOURCE_PPGEN_REGISTRY, 135 + }; 136 + 133 137 struct smu_14_0_2_powerplay_table 134 138 { 135 139 struct atom_common_table_header header; // header.format_revision = 3 (HAS TO MATCH SMU_14_0_2_TABLE_FORMAT_REVISION), header.content_revision = ? structuresize is calculated by PPGen. 136 140 uint8_t table_revision; // PPGen use only: table_revision = 3 137 - uint8_t padding; // Padding 1 byte to align table_size offset to 6 bytes (pmfw_start_offset, for PMFW to know the starting offset of PPTable_t). 141 + uint8_t pptable_source; // PPGen UI dropdown box 138 142 uint16_t pmfw_pptable_start_offset; // The start offset of the pmfw portion. i.e. start of PPTable_t (start of SkuTable_t) 139 143 uint16_t pmfw_pptable_size; // The total size of pmfw_pptable, i.e PPTable_t. 140 - uint16_t pmfw_pfe_table_start_offset; // The start offset of the PFE_Settings_t within pmfw_pptable. 141 - uint16_t pmfw_pfe_table_size; // The size of PFE_Settings_t. 142 - uint16_t pmfw_board_table_start_offset; // The start offset of the BoardTable_t within pmfw_pptable. 143 - uint16_t pmfw_board_table_size; // The size of BoardTable_t. 144 + uint16_t pmfw_sku_table_start_offset; // DO NOT CHANGE ORDER; The absolute start offset of the SkuTable_t (within smu_14_0_3_powerplay_table). 145 + uint16_t pmfw_sku_table_size; // DO NOT CHANGE ORDER; The size of SkuTable_t. 146 + uint16_t pmfw_board_table_start_offset; // The start offset of the BoardTable_t 147 + uint16_t pmfw_board_table_size; // The size of BoardTable_t. 144 148 uint16_t pmfw_custom_sku_table_start_offset; // The start offset of the CustomSkuTable_t within pmfw_pptable. 145 149 uint16_t pmfw_custom_sku_table_size; // The size of the CustomSkuTable_t. 146 150 uint32_t golden_pp_id; // PPGen use only: PP Table ID on the Golden Data Base ··· 167 157 struct smu_14_0_2_overdrive_table overdrive_table; 168 158 169 159 PPTable_t smc_pptable; // PPTable_t in driver_if.h -- as requested by PMFW, this offset should start at a 32-byte boundary, and the table_size above should remain at offset=6 bytes 160 + }; 161 + 162 + enum SMU_14_0_2_CUSTOM_OD_SW_FEATURE_CAP { 163 + SMU_14_0_2_CUSTOM_ODCAP_POWER_MODE = 0, 164 + SMU_14_0_2_CUSTOM_ODCAP_COUNT 165 + }; 166 + 167 + enum SMU_14_0_2_CUSTOM_OD_FEATURE_SETTING_ID { 168 + SMU_14_0_2_CUSTOM_ODSETTING_POWER_MODE = 0, 169 + SMU_14_0_2_CUSTOM_ODSETTING_COUNT, 170 + }; 171 + 172 + struct smu_14_0_2_custom_overdrive_table { 173 + uint8_t revision; 174 + uint8_t reserve[3]; 175 + uint8_t cap[SMU_14_0_2_CUSTOM_ODCAP_COUNT]; 176 + int32_t max[SMU_14_0_2_CUSTOM_ODSETTING_COUNT]; 177 + int32_t min[SMU_14_0_2_CUSTOM_ODSETTING_COUNT]; 178 + int16_t pm_setting[SMU_14_0_2_PMSETTING_COUNT]; 179 + }; 180 + 181 + struct smu_14_0_3_custom_powerplay_table { 182 + uint8_t custom_table_revision; 183 + uint16_t custom_table_size; 184 + uint16_t custom_sku_table_offset; 185 + uint32_t custom_platform_caps; 186 + uint16_t software_shutdown_temp; 187 + struct smu_14_0_2_custom_overdrive_table custom_overdrive_table; 188 + uint32_t reserve[8]; 189 + CustomSkuTable_t custom_sku_table_pmfw; 170 190 }; 171 191 172 192 #pragma pack(pop)
+4 -11
drivers/gpu/drm/drm_atomic_uapi.c
··· 1071 1071 } 1072 1072 1073 1073 if (async_flip && 1074 - prop != config->prop_fb_id && 1075 - prop != config->prop_in_fence_fd && 1076 - prop != config->prop_fb_damage_clips) { 1074 + (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY || 1075 + (prop != config->prop_fb_id && 1076 + prop != config->prop_in_fence_fd && 1077 + prop != config->prop_fb_damage_clips))) { 1077 1078 ret = drm_atomic_plane_get_property(plane, plane_state, 1078 1079 prop, &old_val); 1079 1080 ret = drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); 1080 - break; 1081 - } 1082 - 1083 - if (async_flip && plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY) { 1084 - drm_dbg_atomic(prop->dev, 1085 - "[OBJECT:%d] Only primary planes can be changed during async flip\n", 1086 - obj->id); 1087 - ret = -EINVAL; 1088 1081 break; 1089 1082 } 1090 1083
+2 -6
drivers/gpu/drm/drm_bridge_connector.c
··· 443 443 panel_bridge = bridge; 444 444 } 445 445 446 - if (connector_type == DRM_MODE_CONNECTOR_Unknown) { 447 - kfree(bridge_connector); 446 + if (connector_type == DRM_MODE_CONNECTOR_Unknown) 448 447 return ERR_PTR(-EINVAL); 449 - } 450 448 451 449 if (bridge_connector->bridge_hdmi) 452 450 ret = drmm_connector_hdmi_init(drm, connector, ··· 459 461 ret = drmm_connector_init(drm, connector, 460 462 &drm_bridge_connector_funcs, 461 463 connector_type, ddc); 462 - if (ret) { 463 - kfree(bridge_connector); 464 + if (ret) 464 465 return ERR_PTR(ret); 465 - } 466 466 467 467 drm_connector_helper_add(connector, &drm_bridge_connector_helper_funcs); 468 468
+23 -2
drivers/gpu/drm/drm_buddy.c
··· 851 851 * drm_buddy_block_trim - free unused pages 852 852 * 853 853 * @mm: DRM buddy manager 854 + * @start: start address to begin the trimming. 854 855 * @new_size: original size requested 855 856 * @blocks: Input and output list of allocated blocks. 856 857 * MUST contain single block as input to be trimmed. ··· 867 866 * 0 on success, error code on failure. 868 867 */ 869 868 int drm_buddy_block_trim(struct drm_buddy *mm, 869 + u64 *start, 870 870 u64 new_size, 871 871 struct list_head *blocks) 872 872 { 873 873 struct drm_buddy_block *parent; 874 874 struct drm_buddy_block *block; 875 + u64 block_start, block_end; 875 876 LIST_HEAD(dfs); 876 877 u64 new_start; 877 878 int err; ··· 884 881 block = list_first_entry(blocks, 885 882 struct drm_buddy_block, 886 883 link); 884 + 885 + block_start = drm_buddy_block_offset(block); 886 + block_end = block_start + drm_buddy_block_size(mm, block); 887 887 888 888 if (WARN_ON(!drm_buddy_block_is_allocated(block))) 889 889 return -EINVAL; ··· 900 894 if (new_size == drm_buddy_block_size(mm, block)) 901 895 return 0; 902 896 897 + new_start = block_start; 898 + if (start) { 899 + new_start = *start; 900 + 901 + if (new_start < block_start) 902 + return -EINVAL; 903 + 904 + if (!IS_ALIGNED(new_start, mm->chunk_size)) 905 + return -EINVAL; 906 + 907 + if (range_overflows(new_start, new_size, block_end)) 908 + return -EINVAL; 909 + } 910 + 903 911 list_del(&block->link); 904 912 mark_free(mm, block); 905 913 mm->avail += drm_buddy_block_size(mm, block); ··· 924 904 parent = block->parent; 925 905 block->parent = NULL; 926 906 927 - new_start = drm_buddy_block_offset(block); 928 907 list_add(&block->tmp_link, &dfs); 929 908 err = __alloc_range(mm, &dfs, new_start, new_size, blocks, NULL); 930 909 if (err) { ··· 1085 1066 } while (1); 1086 1067 1087 1068 /* Trim the allocated block to the required size */ 1088 - if (original_size != size) { 1069 + if (!(flags & DRM_BUDDY_TRIM_DISABLE) && 1070 + original_size != size) { 1089 1071 struct list_head *trim_list; 1090 1072 LIST_HEAD(temp); 1091 1073 u64 trim_size; ··· 1103 1083 } 1104 1084 1105 1085 drm_buddy_block_trim(mm, 1086 + NULL, 1106 1087 trim_size, 1107 1088 trim_list); 1108 1089
+5
drivers/gpu/drm/drm_client_modeset.c
··· 880 880 881 881 kfree(modeset->mode); 882 882 modeset->mode = drm_mode_duplicate(dev, mode); 883 + if (!modeset->mode) { 884 + ret = -ENOMEM; 885 + break; 886 + } 887 + 883 888 drm_connector_get(connector); 884 889 modeset->connectors[modeset->num_connectors++] = connector; 885 890 modeset->x = offset->x;
+3
drivers/gpu/drm/i915/display/intel_backlight.c
··· 1449 1449 1450 1450 static int cnp_num_backlight_controllers(struct drm_i915_private *i915) 1451 1451 { 1452 + if (INTEL_PCH_TYPE(i915) >= PCH_MTL) 1453 + return 2; 1454 + 1452 1455 if (INTEL_PCH_TYPE(i915) >= PCH_DG1) 1453 1456 return 1; 1454 1457
+3
drivers/gpu/drm/i915/display/intel_pps.c
··· 351 351 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 352 352 return 2; 353 353 354 + if (INTEL_PCH_TYPE(i915) >= PCH_MTL) 355 + return 2; 356 + 354 357 if (INTEL_PCH_TYPE(i915) >= PCH_DG1) 355 358 return 1; 356 359
+49 -6
drivers/gpu/drm/i915/gem/i915_gem_mman.c
··· 290 290 return i915_error_to_vmf_fault(err); 291 291 } 292 292 293 + static void set_address_limits(struct vm_area_struct *area, 294 + struct i915_vma *vma, 295 + unsigned long obj_offset, 296 + unsigned long *start_vaddr, 297 + unsigned long *end_vaddr) 298 + { 299 + unsigned long vm_start, vm_end, vma_size; /* user's memory parameters */ 300 + long start, end; /* memory boundaries */ 301 + 302 + /* 303 + * Let's move into the ">> PAGE_SHIFT" 304 + * domain to be sure not to lose bits 305 + */ 306 + vm_start = area->vm_start >> PAGE_SHIFT; 307 + vm_end = area->vm_end >> PAGE_SHIFT; 308 + vma_size = vma->size >> PAGE_SHIFT; 309 + 310 + /* 311 + * Calculate the memory boundaries by considering the offset 312 + * provided by the user during memory mapping and the offset 313 + * provided for the partial mapping. 314 + */ 315 + start = vm_start; 316 + start -= obj_offset; 317 + start += vma->gtt_view.partial.offset; 318 + end = start + vma_size; 319 + 320 + start = max_t(long, start, vm_start); 321 + end = min_t(long, end, vm_end); 322 + 323 + /* Let's move back into the "<< PAGE_SHIFT" domain */ 324 + *start_vaddr = (unsigned long)start << PAGE_SHIFT; 325 + *end_vaddr = (unsigned long)end << PAGE_SHIFT; 326 + } 327 + 293 328 static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) 294 329 { 295 330 #define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT) ··· 337 302 struct i915_ggtt *ggtt = to_gt(i915)->ggtt; 338 303 bool write = area->vm_flags & VM_WRITE; 339 304 struct i915_gem_ww_ctx ww; 305 + unsigned long obj_offset; 306 + unsigned long start, end; /* memory boundaries */ 340 307 intel_wakeref_t wakeref; 341 308 struct i915_vma *vma; 342 309 pgoff_t page_offset; 310 + unsigned long pfn; 343 311 int srcu; 344 312 int ret; 345 313 346 - /* We don't use vmf->pgoff since that has the fake offset */ 314 + obj_offset = area->vm_pgoff - drm_vma_node_start(&mmo->vma_node); 347 315 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; 316 + page_offset += obj_offset; 348 317 349 318 trace_i915_gem_object_fault(obj, page_offset, true, write); 350 319 ··· 441 402 if (ret) 442 403 goto err_unpin; 443 404 405 + set_address_limits(area, vma, obj_offset, &start, &end); 406 + 407 + pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT; 408 + pfn += (start - area->vm_start) >> PAGE_SHIFT; 409 + pfn += obj_offset - vma->gtt_view.partial.offset; 410 + 444 411 /* Finally, remap it using the new GTT offset */ 445 - ret = remap_io_mapping(area, 446 - area->vm_start + (vma->gtt_view.partial.offset << PAGE_SHIFT), 447 - (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT, 448 - min_t(u64, vma->size, area->vm_end - area->vm_start), 449 - &ggtt->iomap); 412 + ret = remap_io_mapping(area, start, pfn, end - start, &ggtt->iomap); 450 413 if (ret) 451 414 goto err_fence; 452 415 ··· 1125 1084 mmo = mmap_offset_attach(obj, mmap_type, NULL); 1126 1085 if (IS_ERR(mmo)) 1127 1086 return PTR_ERR(mmo); 1087 + 1088 + vma->vm_pgoff += drm_vma_node_start(&mmo->vma_node); 1128 1089 } 1129 1090 1130 1091 /*
+7 -6
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
··· 165 165 i915_ttm_place_from_region(num_allowed ? obj->mm.placements[0] : 166 166 obj->mm.region, &places[0], obj->bo_offset, 167 167 obj->base.size, flags); 168 - places[0].flags |= TTM_PL_FLAG_DESIRED; 169 168 170 169 /* Cache this on object? */ 171 170 for (i = 0; i < num_allowed; ++i) { ··· 778 779 .interruptible = true, 779 780 .no_wait_gpu = false, 780 781 }; 781 - int real_num_busy; 782 + struct ttm_placement initial_placement; 783 + struct ttm_place initial_place; 782 784 int ret; 783 785 784 786 /* First try only the requested placement. No eviction. */ 785 - real_num_busy = placement->num_placement; 786 - placement->num_placement = 1; 787 - ret = ttm_bo_validate(bo, placement, &ctx); 787 + initial_placement.num_placement = 1; 788 + memcpy(&initial_place, placement->placement, sizeof(struct ttm_place)); 789 + initial_place.flags |= TTM_PL_FLAG_DESIRED; 790 + initial_placement.placement = &initial_place; 791 + ret = ttm_bo_validate(bo, &initial_placement, &ctx); 788 792 if (ret) { 789 793 ret = i915_ttm_err_to_gem(ret); 790 794 /* ··· 802 800 * If the initial attempt fails, allow all accepted placements, 803 801 * evicting if necessary. 804 802 */ 805 - placement->num_placement = real_num_busy; 806 803 ret = ttm_bo_validate(bo, placement, &ctx); 807 804 if (ret) 808 805 return i915_ttm_err_to_gem(ret);
+1
drivers/gpu/drm/omapdrm/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 2 config DRM_OMAP 3 3 tristate "OMAP DRM" 4 + depends on MMU 4 5 depends on DRM && OF 5 6 depends on ARCH_OMAP2PLUS || (COMPILE_TEST && PAGE_SIZE_LESS_THAN_64KB) 6 7 select DRM_KMS_HELPER
+11
drivers/gpu/drm/tests/drm_gem_shmem_test.c
··· 102 102 103 103 sg_init_one(sgt->sgl, buf, TEST_SIZE); 104 104 105 + /* 106 + * Set the DMA mask to 64-bits and map the sgtables 107 + * otherwise drm_gem_shmem_free will cause a warning 108 + * on debug kernels. 109 + */ 110 + ret = dma_set_mask(drm_dev->dev, DMA_BIT_MASK(64)); 111 + KUNIT_ASSERT_EQ(test, ret, 0); 112 + 113 + ret = dma_map_sgtable(drm_dev->dev, sgt, DMA_BIDIRECTIONAL, 0); 114 + KUNIT_ASSERT_EQ(test, ret, 0); 115 + 105 116 /* Init a mock DMA-BUF */ 106 117 buf_mock.size = TEST_SIZE; 107 118 attach_mock.dmabuf = &buf_mock;
+2 -1
drivers/gpu/drm/xe/xe_hwmon.c
··· 203 203 reg_val = xe_mmio_rmw32(hwmon->gt, rapl_limit, PKG_PWR_LIM_1_EN, 0); 204 204 reg_val = xe_mmio_read32(hwmon->gt, rapl_limit); 205 205 if (reg_val & PKG_PWR_LIM_1_EN) { 206 + drm_warn(&gt_to_xe(hwmon->gt)->drm, "PL1 disable is not supported!\n"); 206 207 ret = -EOPNOTSUPP; 207 - goto unlock; 208 208 } 209 + goto unlock; 209 210 } 210 211 211 212 /* Computation in 64-bits to avoid overflow. Round to nearest. */
+14 -1
drivers/gpu/drm/xe/xe_lrc.c
··· 1634 1634 if (!snapshot) 1635 1635 return NULL; 1636 1636 1637 + if (lrc->bo && lrc->bo->vm) 1638 + xe_vm_get(lrc->bo->vm); 1639 + 1637 1640 snapshot->context_desc = xe_lrc_ggtt_addr(lrc); 1638 1641 snapshot->indirect_context_desc = xe_lrc_indirect_ring_ggtt_addr(lrc); 1639 1642 snapshot->head = xe_lrc_ring_head(lrc); ··· 1656 1653 void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot) 1657 1654 { 1658 1655 struct xe_bo *bo; 1656 + struct xe_vm *vm; 1659 1657 struct iosys_map src; 1660 1658 1661 1659 if (!snapshot) 1662 1660 return; 1663 1661 1664 1662 bo = snapshot->lrc_bo; 1663 + vm = bo->vm; 1665 1664 snapshot->lrc_bo = NULL; 1666 1665 1667 1666 snapshot->lrc_snapshot = kvmalloc(snapshot->lrc_size, GFP_KERNEL); ··· 1683 1678 xe_bo_unlock(bo); 1684 1679 put_bo: 1685 1680 xe_bo_put(bo); 1681 + if (vm) 1682 + xe_vm_put(vm); 1686 1683 } 1687 1684 1688 1685 void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p) ··· 1734 1727 return; 1735 1728 1736 1729 kvfree(snapshot->lrc_snapshot); 1737 - if (snapshot->lrc_bo) 1730 + if (snapshot->lrc_bo) { 1731 + struct xe_vm *vm; 1732 + 1733 + vm = snapshot->lrc_bo->vm; 1738 1734 xe_bo_put(snapshot->lrc_bo); 1735 + if (vm) 1736 + xe_vm_put(vm); 1737 + } 1739 1738 kfree(snapshot); 1740 1739 } 1741 1740
+1 -1
drivers/gpu/drm/xe/xe_rtp.c
··· 231 231 if (first == last) 232 232 bitmap_set(ctx->active_entries, first, 1); 233 233 else 234 - bitmap_set(ctx->active_entries, first, last - first + 2); 234 + bitmap_set(ctx->active_entries, first, last - first + 1); 235 235 } 236 236 237 237 /**
+1 -1
drivers/gpu/drm/xe/xe_sync.c
··· 263 263 if (sync->fence) 264 264 dma_fence_put(sync->fence); 265 265 if (sync->chain_fence) 266 - dma_fence_put(&sync->chain_fence->base); 266 + dma_fence_chain_free(sync->chain_fence); 267 267 if (sync->ufence) 268 268 user_fence_put(sync->ufence); 269 269 }
+1 -1
drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
··· 150 150 } while (remaining_size); 151 151 152 152 if (place->flags & TTM_PL_FLAG_CONTIGUOUS) { 153 - if (!drm_buddy_block_trim(mm, vres->base.size, &vres->blocks)) 153 + if (!drm_buddy_block_trim(mm, NULL, vres->base.size, &vres->blocks)) 154 154 size = vres->base.size; 155 155 } 156 156
+2
include/drm/drm_buddy.h
··· 27 27 #define DRM_BUDDY_CONTIGUOUS_ALLOCATION BIT(2) 28 28 #define DRM_BUDDY_CLEAR_ALLOCATION BIT(3) 29 29 #define DRM_BUDDY_CLEARED BIT(4) 30 + #define DRM_BUDDY_TRIM_DISABLE BIT(5) 30 31 31 32 struct drm_buddy_block { 32 33 #define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) ··· 156 155 unsigned long flags); 157 156 158 157 int drm_buddy_block_trim(struct drm_buddy *mm, 158 + u64 *start, 159 159 u64 new_size, 160 160 struct list_head *blocks); 161 161