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Merge branch 'ionic-updates-for-v6-11'

Shannon Nelson says:

====================
ionic: updates for v6.11

These are a few minor fixes for the ionic driver to clean
up a some little things that have been waiting for attention.
These were originally sent for net, but now respun for net-next.

v1: https://lore.kernel.org/netdev/20240521013715.12098-1-shannon.nelson@amd.com/
====================

Link: https://lore.kernel.org/r/20240529000259.25775-1-shannon.nelson@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 15a22950 e3bbb994

+201 -77
+1 -1
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
··· 220 220 { 221 221 struct net_device *netdev = seq->private; 222 222 223 - seq_printf(seq, "%s\n", netdev->name); 223 + seq_printf(seq, "%s\n", netdev_name(netdev)); 224 224 225 225 return 0; 226 226 }
+181 -56
drivers/net/ethernet/pensando/ionic/ionic_if.h
··· 71 71 IONIC_CMD_FW_CONTROL_V1 = 255, 72 72 }; 73 73 74 - /** 74 + /* 75 75 * enum ionic_status_code - Device command return codes 76 76 */ 77 77 enum ionic_status_code { ··· 112 112 /** 113 113 * struct ionic_admin_cmd - General admin command format 114 114 * @opcode: Opcode for the command 115 + * @rsvd: reserved byte(s) 115 116 * @lif_index: LIF index 116 117 * @cmd_data: Opcode-specific command bytes 117 118 */ ··· 126 125 /** 127 126 * struct ionic_admin_comp - General admin command completion format 128 127 * @status: Status of the command (enum ionic_status_code) 128 + * @rsvd: reserved byte(s) 129 129 * @comp_index: Index in the descriptor ring for which this is the completion 130 130 * @cmd_data: Command-specific bytes 131 131 * @color: Color bit (Always 0 for commands issued to the ··· 149 147 /** 150 148 * struct ionic_nop_cmd - NOP command 151 149 * @opcode: opcode 150 + * @rsvd: reserved byte(s) 152 151 */ 153 152 struct ionic_nop_cmd { 154 153 u8 opcode; ··· 159 156 /** 160 157 * struct ionic_nop_comp - NOP command completion 161 158 * @status: Status of the command (enum ionic_status_code) 159 + * @rsvd: reserved byte(s) 162 160 */ 163 161 struct ionic_nop_comp { 164 162 u8 status; ··· 170 166 * struct ionic_dev_init_cmd - Device init command 171 167 * @opcode: opcode 172 168 * @type: Device type 169 + * @rsvd: reserved byte(s) 173 170 */ 174 171 struct ionic_dev_init_cmd { 175 172 u8 opcode; ··· 181 176 /** 182 177 * struct ionic_dev_init_comp - Device init command completion 183 178 * @status: Status of the command (enum ionic_status_code) 179 + * @rsvd: reserved byte(s) 184 180 */ 185 181 struct ionic_dev_init_comp { 186 182 u8 status; ··· 191 185 /** 192 186 * struct ionic_dev_reset_cmd - Device reset command 193 187 * @opcode: opcode 188 + * @rsvd: reserved byte(s) 194 189 */ 195 190 struct ionic_dev_reset_cmd { 196 191 u8 opcode; ··· 201 194 /** 202 195 * struct ionic_dev_reset_comp - Reset command completion 203 196 * @status: Status of the command (enum ionic_status_code) 197 + * @rsvd: reserved byte(s) 204 198 */ 205 199 struct ionic_dev_reset_comp { 206 200 u8 status; ··· 215 207 * struct ionic_dev_identify_cmd - Driver/device identify command 216 208 * @opcode: opcode 217 209 * @ver: Highest version of identify supported by driver 210 + * @rsvd: reserved byte(s) 218 211 */ 219 212 struct ionic_dev_identify_cmd { 220 213 u8 opcode; ··· 227 218 * struct ionic_dev_identify_comp - Driver/device identify command completion 228 219 * @status: Status of the command (enum ionic_status_code) 229 220 * @ver: Version of identify returned by device 221 + * @rsvd: reserved byte(s) 230 222 */ 231 223 struct ionic_dev_identify_comp { 232 224 u8 status; ··· 252 242 * @kernel_ver: Kernel version, numeric format 253 243 * @kernel_ver_str: Kernel version, string format 254 244 * @driver_ver_str: Driver version, string format 245 + * @words: word access to struct contents 255 246 */ 256 247 union ionic_drv_identity { 257 248 struct { ··· 278 267 * union ionic_dev_identity - device identity information 279 268 * @version: Version of device identify 280 269 * @type: Identify type (0 for now) 270 + * @rsvd: reserved byte(s) 281 271 * @nports: Number of ports provisioned 272 + * @rsvd2: reserved byte(s) 282 273 * @nlifs: Number of LIFs provisioned 283 274 * @nintrs: Number of interrupts provisioned 284 275 * @ndbpgs_per_lif: Number of doorbell pages per LIF ··· 297 284 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 298 285 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 299 286 * @capabilities: Device capabilities 287 + * @words: word access to struct contents 300 288 */ 301 289 union ionic_dev_identity { 302 290 struct { ··· 331 317 * @opcode: opcode 332 318 * @type: LIF type (enum ionic_lif_type) 333 319 * @ver: Version of identify returned by device 320 + * @rsvd: reserved byte(s) 334 321 */ 335 322 struct ionic_lif_identify_cmd { 336 323 u8 opcode; ··· 344 329 * struct ionic_lif_identify_comp - LIF identify command completion 345 330 * @status: Status of the command (enum ionic_status_code) 346 331 * @ver: Version of identify returned by device 332 + * @rsvd2: reserved byte(s) 347 333 */ 348 334 struct ionic_lif_identify_comp { 349 335 u8 status; ··· 432 416 }; 433 417 434 418 /** 435 - * struct ionic_hwstamp_bits - Hardware timestamp decoding bits 419 + * enum ionic_hwstamp_bits - Hardware timestamp decoding bits 436 420 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 437 421 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 438 422 * from the base cq descriptor. ··· 445 429 /** 446 430 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 447 431 * @qtype: Hardware Queue Type 432 + * @rsvd: reserved byte(s) 448 433 * @qid_count: Number of Queue IDs of the logical type 449 434 * @qid_base: Minimum Queue ID of the logical type 450 435 */ ··· 471 454 /** 472 455 * union ionic_lif_config - LIF configuration 473 456 * @state: LIF state (enum ionic_lif_state) 457 + * @rsvd: reserved byte(s) 474 458 * @name: LIF name 475 459 * @mtu: MTU 476 460 * @mac: Station MAC address 477 461 * @vlan: Default Vlan ID 478 462 * @features: Features (enum ionic_eth_hw_features) 479 463 * @queue_count: Queue counts per queue-type 464 + * @words: word access to struct contents 480 465 */ 481 466 union ionic_lif_config { 482 467 struct { ··· 500 481 * @capabilities: LIF capabilities 501 482 * 502 483 * @eth: Ethernet identify structure 503 - * @version: Ethernet identify structure version 504 - * @max_ucast_filters: Number of perfect unicast addresses supported 505 - * @max_mcast_filters: Number of perfect multicast addresses supported 506 - * @min_frame_size: Minimum size of frames to be sent 507 - * @max_frame_size: Maximum size of frames to be sent 508 - * @hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 509 - * @hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 510 - * @config: LIF config struct with features, mtu, mac, q counts 484 + * @eth.version: Ethernet identify structure version 485 + * @eth.rsvd: reserved byte(s) 486 + * @eth.max_ucast_filters: Number of perfect unicast addresses supported 487 + * @eth.max_mcast_filters: Number of perfect multicast addresses supported 488 + * @eth.min_frame_size: Minimum size of frames to be sent 489 + * @eth.max_frame_size: Maximum size of frames to be sent 490 + * @eth.rsvd2: reserved byte(s) 491 + * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 492 + * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 493 + * @eth.rsvd3: reserved byte(s) 494 + * @eth.config: LIF config struct with features, mtu, mac, q counts 511 495 * 512 496 * @rdma: RDMA identify structure 513 - * @version: RDMA version of opcodes and queue descriptors 514 - * @qp_opcodes: Number of RDMA queue pair opcodes supported 515 - * @admin_opcodes: Number of RDMA admin opcodes supported 516 - * @npts_per_lif: Page table size per LIF 517 - * @nmrs_per_lif: Number of memory regions per LIF 518 - * @nahs_per_lif: Number of address handles per LIF 519 - * @max_stride: Max work request stride 520 - * @cl_stride: Cache line stride 521 - * @pte_stride: Page table entry stride 522 - * @rrq_stride: Remote RQ work request stride 523 - * @rsq_stride: Remote SQ work request stride 524 - * @dcqcn_profiles: Number of DCQCN profiles 525 - * @aq_qtype: RDMA Admin Qtype 526 - * @sq_qtype: RDMA Send Qtype 527 - * @rq_qtype: RDMA Receive Qtype 528 - * @cq_qtype: RDMA Completion Qtype 529 - * @eq_qtype: RDMA Event Qtype 497 + * @rdma.version: RDMA version of opcodes and queue descriptors 498 + * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported 499 + * @rdma.admin_opcodes: Number of RDMA admin opcodes supported 500 + * @rdma.rsvd: reserved byte(s) 501 + * @rdma.npts_per_lif: Page table size per LIF 502 + * @rdma.nmrs_per_lif: Number of memory regions per LIF 503 + * @rdma.nahs_per_lif: Number of address handles per LIF 504 + * @rdma.max_stride: Max work request stride 505 + * @rdma.cl_stride: Cache line stride 506 + * @rdma.pte_stride: Page table entry stride 507 + * @rdma.rrq_stride: Remote RQ work request stride 508 + * @rdma.rsq_stride: Remote SQ work request stride 509 + * @rdma.dcqcn_profiles: Number of DCQCN profiles 510 + * @rdma.rsvd_dimensions: reserved byte(s) 511 + * @rdma.aq_qtype: RDMA Admin Qtype 512 + * @rdma.sq_qtype: RDMA Send Qtype 513 + * @rdma.rq_qtype: RDMA Receive Qtype 514 + * @rdma.cq_qtype: RDMA Completion Qtype 515 + * @rdma.eq_qtype: RDMA Event Qtype 516 + * @words: word access to struct contents 530 517 */ 531 518 union ionic_lif_identity { 532 519 struct { ··· 583 558 * @opcode: Opcode 584 559 * @type: LIF type (enum ionic_lif_type) 585 560 * @index: LIF index 561 + * @rsvd: reserved byte(s) 586 562 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 563 + * @rsvd2: reserved byte(s) 587 564 */ 588 565 struct ionic_lif_init_cmd { 589 566 u8 opcode; ··· 599 572 /** 600 573 * struct ionic_lif_init_comp - LIF init command completion 601 574 * @status: Status of the command (enum ionic_status_code) 575 + * @rsvd: reserved byte(s) 602 576 * @hw_index: Hardware index of the initialized LIF 577 + * @rsvd2: reserved byte(s) 603 578 */ 604 579 struct ionic_lif_init_comp { 605 580 u8 status; ··· 613 584 /** 614 585 * struct ionic_q_identify_cmd - queue identify command 615 586 * @opcode: opcode 587 + * @rsvd: reserved byte(s) 616 588 * @lif_type: LIF type (enum ionic_lif_type) 617 589 * @type: Logical queue type (enum ionic_logical_qtype) 618 590 * @ver: Highest queue type version that the driver supports 591 + * @rsvd2: reserved byte(s) 619 592 */ 620 593 struct ionic_q_identify_cmd { 621 594 u8 opcode; ··· 631 600 /** 632 601 * struct ionic_q_identify_comp - queue identify command completion 633 602 * @status: Status of the command (enum ionic_status_code) 603 + * @rsvd: reserved byte(s) 634 604 * @comp_index: Index in the descriptor ring for which this is the completion 635 605 * @ver: Queue type version that can be used with FW 606 + * @rsvd2: reserved byte(s) 636 607 */ 637 608 struct ionic_q_identify_comp { 638 609 u8 status; ··· 648 615 * union ionic_q_identity - queue identity information 649 616 * @version: Queue type version that can be used with FW 650 617 * @supported: Bitfield of queue versions, first bit = ver 0 618 + * @rsvd: reserved byte(s) 651 619 * @features: Queue features (enum ionic_q_feature, etc) 652 620 * @desc_sz: Descriptor size 653 621 * @comp_sz: Completion descriptor size 654 622 * @sg_desc_sz: Scatter/Gather descriptor size 655 623 * @max_sg_elems: Maximum number of Scatter/Gather elements 656 624 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 625 + * @words: word access to struct contents 657 626 */ 658 627 union ionic_q_identity { 659 628 struct { ··· 675 640 /** 676 641 * struct ionic_q_init_cmd - Queue init command 677 642 * @opcode: opcode 643 + * @rsvd: reserved byte(s) 678 644 * @type: Logical queue type 679 645 * @ver: Queue type version 646 + * @rsvd1: reserved byte(s) 680 647 * @lif_index: LIF index 681 648 * @index: (LIF, qtype) relative admin queue index 682 649 * @intr_index: Interrupt control register index, or Event queue index ··· 704 667 * @ring_base: Queue ring base address 705 668 * @cq_ring_base: Completion queue ring base address 706 669 * @sg_ring_base: Scatter/Gather ring base address 670 + * @rsvd2: reserved byte(s) 707 671 * @features: Mask of queue features to enable, if not in the flags above. 708 672 */ 709 673 struct ionic_q_init_cmd { ··· 736 698 /** 737 699 * struct ionic_q_init_comp - Queue init command completion 738 700 * @status: Status of the command (enum ionic_status_code) 701 + * @rsvd: reserved byte(s) 739 702 * @comp_index: Index in the descriptor ring for which this is the completion 740 703 * @hw_index: Hardware Queue ID 741 704 * @hw_type: Hardware Queue type 705 + * @rsvd2: reserved byte(s) 742 706 * @color: Color 743 707 */ 744 708 struct ionic_q_init_comp { ··· 840 800 * will set CWR flag in the first segment if 841 801 * CWR is set in the template header, and 842 802 * clear CWR in remaining segments. 843 - * @flags: 803 + * flags: 844 804 * vlan: 845 805 * Insert an L2 VLAN header using @vlan_tci 846 806 * encap: ··· 853 813 * TSO start 854 814 * tso_eot: 855 815 * TSO end 856 - * @num_sg_elems: Number of scatter-gather elements in SG 816 + * num_sg_elems: Number of scatter-gather elements in SG 857 817 * descriptor 858 - * @addr: First data buffer's DMA address 818 + * addr: First data buffer's DMA address 859 819 * (Subsequent data buffers are on txq_sg_desc) 860 820 * @len: First data buffer's length, in bytes 861 821 * @vlan_tci: VLAN tag to insert in the packet (if requested 862 822 * by @V-bit). Includes .1p and .1q tags 823 + * @hword0: half word padding 863 824 * @hdr_len: Length of packet headers, including 864 825 * encapsulating outer header, if applicable 865 826 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and ··· 871 830 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 872 831 * inner-most L4 payload, so inclusive of 873 832 * inner-most L4 header. 833 + * @hword1: half word padding 874 834 * @mss: Desired MSS value for TSO; only applicable for 875 835 * IONIC_TXQ_DESC_OPCODE_TSO 876 836 * @csum_start: Offset from packet to first byte checked in L4 checksum 877 837 * @csum_offset: Offset from csum_start to L4 checksum field 838 + * @hword2: half word padding 878 839 */ 879 840 struct ionic_txq_desc { 880 841 __le64 cmd; ··· 944 901 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 945 902 * @addr: DMA address of SG element data buffer 946 903 * @len: Length of SG element data buffer, in bytes 904 + * @rsvd: reserved byte(s) 947 905 */ 948 906 struct ionic_txq_sg_elem { 949 907 __le64 addr; ··· 971 927 /** 972 928 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 973 929 * @status: Status of the command (enum ionic_status_code) 930 + * @rsvd: reserved byte(s) 974 931 * @comp_index: Index in the descriptor ring for which this is the completion 932 + * @rsvd2: reserved byte(s) 975 933 * @color: Color bit 976 934 */ 977 935 struct ionic_txq_comp { ··· 999 953 * receive, including actual bytes received, 1000 954 * are recorded in Rx completion descriptor. 1001 955 * 956 + * @rsvd: reserved byte(s) 1002 957 * @len: Data buffer's length, in bytes 1003 958 * @addr: Data buffer's DMA address 1004 959 */ ··· 1014 967 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 1015 968 * @addr: DMA address of SG element data buffer 1016 969 * @len: Length of SG element data buffer, in bytes 970 + * @rsvd: reserved byte(s) 1017 971 */ 1018 972 struct ionic_rxq_sg_elem { 1019 973 __le64 addr; ··· 1218 1170 * @lif_index: LIF index 1219 1171 * @index: Queue index 1220 1172 * @oper: Operation (enum ionic_q_control_oper) 1173 + * @rsvd: reserved byte(s) 1221 1174 */ 1222 1175 struct ionic_q_control_cmd { 1223 1176 u8 opcode; ··· 1231 1182 1232 1183 typedef struct ionic_admin_comp ionic_q_control_comp; 1233 1184 1234 - enum q_control_oper { 1185 + enum ionic_q_control_oper { 1235 1186 IONIC_Q_DISABLE = 0, 1236 1187 IONIC_Q_ENABLE = 1, 1237 1188 IONIC_Q_HANG_RESET = 2, ··· 1265 1216 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1266 1217 }; 1267 1218 1268 - /** 1219 + /* 1269 1220 * enum ionic_xcvr_pid - Supported link modes 1270 1221 */ 1271 1222 enum ionic_xcvr_pid { ··· 1400 1351 * @fec_type: fec type (enum ionic_port_fec_type) 1401 1352 * @pause_type: pause type (enum ionic_port_pause_type) 1402 1353 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1354 + * @words: word access to struct contents 1403 1355 */ 1404 1356 union ionic_port_config { 1405 1357 struct { ··· 1432 1382 * @speed: link speed (in Mbps) 1433 1383 * @link_down_count: number of times link went from up to down 1434 1384 * @fec_type: fec type (enum ionic_port_fec_type) 1385 + * @rsvd: reserved byte(s) 1435 1386 * @xcvr: transceiver status 1436 1387 */ 1437 1388 struct ionic_port_status { ··· 1450 1399 * @opcode: opcode 1451 1400 * @index: port index 1452 1401 * @ver: Highest version of identify supported by driver 1402 + * @rsvd: reserved byte(s) 1453 1403 */ 1454 1404 struct ionic_port_identify_cmd { 1455 1405 u8 opcode; ··· 1463 1411 * struct ionic_port_identify_comp - Port identify command completion 1464 1412 * @status: Status of the command (enum ionic_status_code) 1465 1413 * @ver: Version of identify returned by device 1414 + * @rsvd: reserved byte(s) 1466 1415 */ 1467 1416 struct ionic_port_identify_comp { 1468 1417 u8 status; ··· 1475 1422 * struct ionic_port_init_cmd - Port initialization command 1476 1423 * @opcode: opcode 1477 1424 * @index: port index 1425 + * @rsvd: reserved byte(s) 1478 1426 * @info_pa: destination address for port info (struct ionic_port_info) 1427 + * @rsvd2: reserved byte(s) 1479 1428 */ 1480 1429 struct ionic_port_init_cmd { 1481 1430 u8 opcode; ··· 1490 1435 /** 1491 1436 * struct ionic_port_init_comp - Port initialization command completion 1492 1437 * @status: Status of the command (enum ionic_status_code) 1438 + * @rsvd: reserved byte(s) 1493 1439 */ 1494 1440 struct ionic_port_init_comp { 1495 1441 u8 status; ··· 1501 1445 * struct ionic_port_reset_cmd - Port reset command 1502 1446 * @opcode: opcode 1503 1447 * @index: port index 1448 + * @rsvd: reserved byte(s) 1504 1449 */ 1505 1450 struct ionic_port_reset_cmd { 1506 1451 u8 opcode; ··· 1512 1455 /** 1513 1456 * struct ionic_port_reset_comp - Port reset command completion 1514 1457 * @status: Status of the command (enum ionic_status_code) 1458 + * @rsvd: reserved byte(s) 1515 1459 */ 1516 1460 struct ionic_port_reset_comp { 1517 1461 u8 status; ··· 1568 1510 * @opcode: Opcode 1569 1511 * @index: Port index 1570 1512 * @attr: Attribute type (enum ionic_port_attr) 1513 + * @rsvd: reserved byte(s) 1571 1514 * @state: Port state 1572 1515 * @speed: Port speed 1573 1516 * @mtu: Port MTU ··· 1577 1518 * @pause_type: Port pause type setting 1578 1519 * @loopback_mode: Port loopback mode 1579 1520 * @stats_ctl: Port stats setting 1521 + * @rsvd2: reserved byte(s) 1580 1522 */ 1581 1523 struct ionic_port_setattr_cmd { 1582 1524 u8 opcode; ··· 1600 1540 /** 1601 1541 * struct ionic_port_setattr_comp - Port set attr command completion 1602 1542 * @status: Status of the command (enum ionic_status_code) 1543 + * @rsvd: reserved byte(s) 1603 1544 * @color: Color bit 1604 1545 */ 1605 1546 struct ionic_port_setattr_comp { ··· 1614 1553 * @opcode: Opcode 1615 1554 * @index: port index 1616 1555 * @attr: Attribute type (enum ionic_port_attr) 1556 + * @rsvd: reserved byte(s) 1617 1557 */ 1618 1558 struct ionic_port_getattr_cmd { 1619 1559 u8 opcode; ··· 1626 1564 /** 1627 1565 * struct ionic_port_getattr_comp - Port get attr command completion 1628 1566 * @status: Status of the command (enum ionic_status_code) 1567 + * @rsvd: reserved byte(s) 1629 1568 * @state: Port state 1630 1569 * @speed: Port speed 1631 1570 * @mtu: Port MTU ··· 1634 1571 * @fec_type: Port FEC type setting 1635 1572 * @pause_type: Port pause type setting 1636 1573 * @loopback_mode: Port loopback mode 1574 + * @rsvd2: reserved byte(s) 1637 1575 * @color: Color bit 1638 1576 */ 1639 1577 struct ionic_port_getattr_comp { ··· 1657 1593 * struct ionic_lif_status - LIF status register 1658 1594 * @eid: most recent NotifyQ event id 1659 1595 * @port_num: port the LIF is connected to 1596 + * @rsvd: reserved byte(s) 1660 1597 * @link_status: port status (enum ionic_port_oper_status) 1661 1598 * @link_speed: speed of link in Mbps 1662 1599 * @link_down_count: number of times link went from up to down 1600 + * @rsvd2: reserved byte(s) 1663 1601 */ 1664 1602 struct ionic_lif_status { 1665 1603 __le64 eid; ··· 1676 1610 /** 1677 1611 * struct ionic_lif_reset_cmd - LIF reset command 1678 1612 * @opcode: opcode 1613 + * @rsvd: reserved byte(s) 1679 1614 * @index: LIF index 1615 + * @rsvd2: reserved byte(s) 1680 1616 */ 1681 1617 struct ionic_lif_reset_cmd { 1682 1618 u8 opcode; ··· 1711 1643 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1712 1644 * @opcode: Opcode 1713 1645 * @attr: Attribute type (enum ionic_dev_attr) 1646 + * @rsvd: reserved byte(s) 1714 1647 * @state: Device state (enum ionic_dev_state) 1715 1648 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1716 1649 * @features: Device features 1650 + * @rsvd2: reserved byte(s) 1717 1651 */ 1718 1652 struct ionic_dev_setattr_cmd { 1719 1653 u8 opcode; ··· 1732 1662 /** 1733 1663 * struct ionic_dev_setattr_comp - Device set attr command completion 1734 1664 * @status: Status of the command (enum ionic_status_code) 1665 + * @rsvd: reserved byte(s) 1735 1666 * @features: Device features 1667 + * @rsvd2: reserved byte(s) 1736 1668 * @color: Color bit 1737 1669 */ 1738 1670 struct ionic_dev_setattr_comp { ··· 1751 1679 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1752 1680 * @opcode: opcode 1753 1681 * @attr: Attribute type (enum ionic_dev_attr) 1682 + * @rsvd: reserved byte(s) 1754 1683 */ 1755 1684 struct ionic_dev_getattr_cmd { 1756 1685 u8 opcode; ··· 1760 1687 }; 1761 1688 1762 1689 /** 1763 - * struct ionic_dev_setattr_comp - Device set attr command completion 1690 + * struct ionic_dev_getattr_comp - Device set attr command completion 1764 1691 * @status: Status of the command (enum ionic_status_code) 1692 + * @rsvd: reserved byte(s) 1765 1693 * @features: Device features 1694 + * @rsvd2: reserved byte(s) 1766 1695 * @color: Color bit 1767 1696 */ 1768 1697 struct ionic_dev_getattr_comp { ··· 1777 1702 u8 color; 1778 1703 }; 1779 1704 1780 - /** 1705 + /* 1781 1706 * RSS parameters 1782 1707 */ 1783 1708 #define IONIC_RSS_HASH_KEY_SIZE 40 ··· 1801 1726 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1802 1727 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1803 1728 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1729 + * @IONIC_LIF_ATTR_MAX: maximum attribute value 1804 1730 */ 1805 1731 enum ionic_lif_attr { 1806 1732 IONIC_LIF_ATTR_STATE = 0, ··· 1812 1736 IONIC_LIF_ATTR_RSS = 5, 1813 1737 IONIC_LIF_ATTR_STATS_CTRL = 6, 1814 1738 IONIC_LIF_ATTR_TXSTAMP = 7, 1739 + IONIC_LIF_ATTR_MAX = 255, 1815 1740 }; 1816 1741 1817 1742 /** ··· 1826 1749 * @mac: Station mac 1827 1750 * @features: Features (enum ionic_eth_hw_features) 1828 1751 * @rss: RSS properties 1829 - * @types: The hash types to enable (see rss_hash_types) 1830 - * @key: The hash secret key 1831 - * @addr: Address for the indirection table shared memory 1752 + * @rss.types: The hash types to enable (see rss_hash_types) 1753 + * @rss.key: The hash secret key 1754 + * @rss.rsvd: reserved byte(s) 1755 + * @rss.addr: Address for the indirection table shared memory 1832 1756 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1833 - * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) 1757 + * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1758 + * @rsvd: reserved byte(s) 1834 1759 */ 1835 1760 struct ionic_lif_setattr_cmd { 1836 1761 u8 opcode; ··· 1851 1772 __le64 addr; 1852 1773 } rss; 1853 1774 u8 stats_ctl; 1854 - __le16 txstamp_mode; 1775 + __le16 txstamp_mode; 1855 1776 u8 rsvd[60]; 1856 1777 } __packed; 1857 1778 }; ··· 1859 1780 /** 1860 1781 * struct ionic_lif_setattr_comp - LIF set attr command completion 1861 1782 * @status: Status of the command (enum ionic_status_code) 1783 + * @rsvd: reserved byte(s) 1862 1784 * @comp_index: Index in the descriptor ring for which this is the completion 1863 1785 * @features: features (enum ionic_eth_hw_features) 1786 + * @rsvd2: reserved byte(s) 1864 1787 * @color: Color bit 1865 1788 */ 1866 1789 struct ionic_lif_setattr_comp { ··· 1881 1800 * @opcode: Opcode 1882 1801 * @attr: Attribute type (enum ionic_lif_attr) 1883 1802 * @index: LIF index 1803 + * @rsvd: reserved byte(s) 1884 1804 */ 1885 1805 struct ionic_lif_getattr_cmd { 1886 1806 u8 opcode; ··· 1893 1811 /** 1894 1812 * struct ionic_lif_getattr_comp - LIF get attr command completion 1895 1813 * @status: Status of the command (enum ionic_status_code) 1814 + * @rsvd: reserved byte(s) 1896 1815 * @comp_index: Index in the descriptor ring for which this is the completion 1897 1816 * @state: LIF state (enum ionic_lif_state) 1898 - * @name: The netdev name string, 0 terminated 1899 1817 * @mtu: Mtu 1900 1818 * @mac: Station mac 1901 1819 * @features: Features (enum ionic_eth_hw_features) 1902 - * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) 1820 + * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1821 + * @rsvd2: reserved byte(s) 1903 1822 * @color: Color bit 1904 1823 */ 1905 1824 struct ionic_lif_getattr_comp { ··· 1921 1838 /** 1922 1839 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 1923 1840 * @opcode: Opcode 1841 + * @rsvd1: reserved byte(s) 1924 1842 * @lif_index: LIF index 1843 + * @rsvd2: reserved byte(s) 1925 1844 * @tick: Hardware stamp tick of an instant in time. 1926 1845 * @nsec: Nanosecond stamp of the same instant. 1927 1846 * @frac: Fractional nanoseconds at the same instant. 1928 1847 * @mult: Cycle to nanosecond multiplier. 1929 1848 * @shift: Cycle to nanosecond divisor (power of two). 1849 + * @rsvd3: reserved byte(s) 1930 1850 */ 1931 1851 struct ionic_lif_setphc_cmd { 1932 1852 u8 opcode; ··· 1956 1870 /** 1957 1871 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1958 1872 * @opcode: opcode 1873 + * @rsvd: reserved byte(s) 1959 1874 * @lif_index: LIF index 1960 1875 * @rx_mode: Rx mode flags: 1961 1876 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets ··· 1965 1878 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1966 1879 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1967 1880 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1881 + * @rsvd2: reserved byte(s) 1968 1882 */ 1969 1883 struct ionic_rx_mode_set_cmd { 1970 1884 u8 opcode; ··· 1992 1904 * @qid: Queue ID 1993 1905 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1994 1906 * @vlan: VLAN filter 1995 - * @vlan: VLAN ID 1907 + * @vlan.vlan: VLAN ID 1996 1908 * @mac: MAC filter 1997 - * @addr: MAC address (network-byte order) 1909 + * @mac.addr: MAC address (network-byte order) 1998 1910 * @mac_vlan: MACVLAN filter 1999 - * @vlan: VLAN ID 2000 - * @addr: MAC address (network-byte order) 1911 + * @mac_vlan.vlan: VLAN ID 1912 + * @mac_vlan.addr: MAC address (network-byte order) 2001 1913 * @pkt_class: Packet classification filter 1914 + * @rsvd: reserved byte(s) 2002 1915 */ 2003 1916 struct ionic_rx_filter_add_cmd { 2004 1917 u8 opcode; ··· 2026 1937 /** 2027 1938 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 2028 1939 * @status: Status of the command (enum ionic_status_code) 1940 + * @rsvd: reserved byte(s) 2029 1941 * @comp_index: Index in the descriptor ring for which this is the completion 2030 1942 * @filter_id: Filter ID 1943 + * @rsvd2: reserved byte(s) 2031 1944 * @color: Color bit 2032 1945 */ 2033 1946 struct ionic_rx_filter_add_comp { ··· 2044 1953 /** 2045 1954 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 2046 1955 * @opcode: opcode 1956 + * @rsvd: reserved byte(s) 2047 1957 * @lif_index: LIF index 2048 1958 * @filter_id: Filter ID 1959 + * @rsvd2: reserved byte(s) 2049 1960 */ 2050 1961 struct ionic_rx_filter_del_cmd { 2051 1962 u8 opcode; ··· 2093 2000 * @trust: enable VF trust 2094 2001 * @linkstate: set link up or down 2095 2002 * @stats_pa: set DMA address for VF stats 2003 + * @pad: reserved byte(s) 2096 2004 */ 2097 2005 struct ionic_vf_setattr_cmd { 2098 2006 u8 opcode; ··· 2125 2031 * @opcode: Opcode 2126 2032 * @attr: Attribute type (enum ionic_vf_attr) 2127 2033 * @vf_index: VF index 2034 + * @rsvd: reserved byte(s) 2128 2035 */ 2129 2036 struct ionic_vf_getattr_cmd { 2130 2037 u8 opcode; ··· 2159 2064 /** 2160 2065 * struct ionic_vf_ctrl_cmd - VF control command 2161 2066 * @opcode: Opcode for the command 2162 - * @vf_index: VF Index. It is unused if op START_ALL is used. 2163 2067 * @ctrl_opcode: VF control operation type 2068 + * @vf_index: VF Index. It is unused if op START_ALL is used. 2164 2069 */ 2165 2070 struct ionic_vf_ctrl_cmd { 2166 2071 u8 opcode; ··· 2184 2089 * struct ionic_qos_identify_cmd - QoS identify command 2185 2090 * @opcode: opcode 2186 2091 * @ver: Highest version of identify supported by driver 2187 - * 2092 + * @rsvd: reserved byte(s) 2188 2093 */ 2189 2094 struct ionic_qos_identify_cmd { 2190 2095 u8 opcode; ··· 2196 2101 * struct ionic_qos_identify_comp - QoS identify command completion 2197 2102 * @status: Status of the command (enum ionic_status_code) 2198 2103 * @ver: Version of identify returned by device 2104 + * @rsvd: reserved byte(s) 2199 2105 */ 2200 2106 struct ionic_qos_identify_comp { 2201 2107 u8 status; ··· 2214 2118 #define IONIC_QOS_ALL_PCP 0xFF 2215 2119 #define IONIC_DSCP_BLOCK_SIZE 8 2216 2120 2217 - /** 2121 + /* 2218 2122 * enum ionic_qos_class 2219 2123 */ 2220 2124 enum ionic_qos_class { ··· 2270 2174 * @dot1q_pcp: Dot1q pcp value 2271 2175 * @ndscp: Number of valid dscp values in the ip_dscp field 2272 2176 * @ip_dscp: IP dscp values 2177 + * @words: word access to struct contents 2273 2178 */ 2274 2179 union ionic_qos_config { 2275 2180 struct { ··· 2316 2219 * union ionic_qos_identity - QoS identity structure 2317 2220 * @version: Version of the identify structure 2318 2221 * @type: QoS system type 2319 - * @nclasses: Number of usable QoS classes 2222 + * @rsvd: reserved byte(s) 2320 2223 * @config: Current configuration of classes 2224 + * @words: word access to struct contents 2321 2225 */ 2322 2226 union ionic_qos_identity { 2323 2227 struct { ··· 2334 2236 * struct ionic_qos_init_cmd - QoS config init command 2335 2237 * @opcode: Opcode 2336 2238 * @group: QoS class id 2239 + * @rsvd: reserved byte(s) 2337 2240 * @info_pa: destination address for qos info 2241 + * @rsvd1: reserved byte(s) 2338 2242 */ 2339 2243 struct ionic_qos_init_cmd { 2340 2244 u8 opcode; ··· 2352 2252 * struct ionic_qos_reset_cmd - QoS config reset command 2353 2253 * @opcode: Opcode 2354 2254 * @group: QoS class id 2255 + * @rsvd: reserved byte(s) 2355 2256 */ 2356 2257 struct ionic_qos_reset_cmd { 2357 2258 u8 opcode; ··· 2361 2260 }; 2362 2261 2363 2262 /** 2364 - * struct ionic_qos_clear_port_stats_cmd - Qos config reset command 2263 + * struct ionic_qos_clear_stats_cmd - Qos config reset command 2365 2264 * @opcode: Opcode 2265 + * @group_bitmap: bitmap of groups to be cleared 2266 + * @rsvd: reserved byte(s) 2366 2267 */ 2367 2268 struct ionic_qos_clear_stats_cmd { 2368 2269 u8 opcode; ··· 2377 2274 /** 2378 2275 * struct ionic_fw_download_cmd - Firmware download command 2379 2276 * @opcode: opcode 2277 + * @rsvd: reserved byte(s) 2380 2278 * @addr: dma address of the firmware buffer 2381 2279 * @offset: offset of the firmware buffer within the full image 2382 2280 * @length: number of valid bytes in the firmware buffer ··· 2401 2297 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2402 2298 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2403 2299 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2300 + * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update 2404 2301 */ 2405 2302 enum ionic_fw_control_oper { 2406 2303 IONIC_FW_RESET = 0, ··· 2417 2312 /** 2418 2313 * struct ionic_fw_control_cmd - Firmware control command 2419 2314 * @opcode: opcode 2315 + * @rsvd: reserved byte(s) 2420 2316 * @oper: firmware control operation (enum ionic_fw_control_oper) 2421 2317 * @slot: slot to activate 2318 + * @rsvd1: reserved byte(s) 2422 2319 */ 2423 2320 struct ionic_fw_control_cmd { 2424 2321 u8 opcode; ··· 2433 2326 /** 2434 2327 * struct ionic_fw_control_comp - Firmware control copletion 2435 2328 * @status: Status of the command (enum ionic_status_code) 2329 + * @rsvd: reserved byte(s) 2436 2330 * @comp_index: Index in the descriptor ring for which this is the completion 2437 2331 * @slot: Slot where the firmware was installed 2332 + * @rsvd1: reserved byte(s) 2438 2333 * @color: Color bit 2439 2334 */ 2440 2335 struct ionic_fw_control_comp { ··· 2455 2346 /** 2456 2347 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2457 2348 * @opcode: opcode 2349 + * @rsvd: reserved byte(s) 2458 2350 * @lif_index: LIF index 2351 + * @rsvd2: reserved byte(s) 2459 2352 * 2460 2353 * There is no RDMA specific dev command completion struct. Completion uses 2461 2354 * the common struct ionic_admin_comp. Only the status is indicated. ··· 2473 2362 /** 2474 2363 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2475 2364 * @opcode: opcode, 52, 53 2365 + * @rsvd: reserved byte(s) 2476 2366 * @lif_index: LIF index 2477 2367 * @qid_ver: (qid | (RDMA version << 24)) 2478 2368 * @cid: intr, eq_id, or cq_id ··· 2481 2369 * @depth_log2: log base two of queue depth 2482 2370 * @stride_log2: log base two of queue stride 2483 2371 * @dma_addr: address of the queue memory 2372 + * @rsvd2: reserved byte(s) 2484 2373 * 2485 2374 * The same command struct is used to create an RDMA event queue, completion 2486 2375 * queue, or RDMA admin queue. The cid is an interrupt number for an event ··· 2538 2425 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2539 2426 * @link_status: link up/down, with error bits (enum ionic_port_status) 2540 2427 * @link_speed: speed of the network link 2428 + * @rsvd: reserved byte(s) 2541 2429 * 2542 2430 * Sent when the network link state changes between UP and DOWN 2543 2431 */ ··· 2556 2442 * @ecode: event code = IONIC_EVENT_RESET 2557 2443 * @reset_code: reset type 2558 2444 * @state: 0=pending, 1=complete, 2=error 2445 + * @rsvd: reserved byte(s) 2559 2446 * 2560 2447 * Sent when the NIC or some subsystem is going to be or 2561 2448 * has been reset. ··· 2573 2458 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2574 2459 * @eid: event number 2575 2460 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2461 + * @rsvd: reserved byte(s) 2576 2462 */ 2577 2463 struct ionic_heartbeat_event { 2578 2464 __le64 eid; ··· 2597 2481 * struct ionic_xcvr_event - Transceiver change event 2598 2482 * @eid: event number 2599 2483 * @ecode: event code = IONIC_EVENT_XCVR 2484 + * @rsvd: reserved byte(s) 2600 2485 */ 2601 2486 struct ionic_xcvr_event { 2602 2487 __le64 eid; ··· 2605 2488 u8 rsvd[54]; 2606 2489 }; 2607 2490 2608 - /** 2491 + /* 2609 2492 * struct ionic_port_stats - Port statistics structure 2610 2493 */ 2611 2494 struct ionic_port_stats { ··· 2763 2646 IONIC_OFLOW_DROP_MAX, 2764 2647 }; 2765 2648 2766 - /** 2767 - * struct port_pb_stats - packet buffers system stats 2649 + /* struct ionic_port_pb_stats - packet buffers system stats 2768 2650 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2769 2651 */ 2770 2652 struct ionic_port_pb_stats { ··· 2797 2681 * @pause_type: supported pause types 2798 2682 * @loopback_mode: supported loopback mode 2799 2683 * @speeds: supported speeds 2684 + * @rsvd2: reserved byte(s) 2800 2685 * @config: current port configuration 2686 + * @words: word access to struct contents 2801 2687 */ 2802 2688 union ionic_port_identity { 2803 2689 struct { ··· 2825 2707 * @status: Port status data 2826 2708 * @stats: Port statistics data 2827 2709 * @mgmt_stats: Port management statistics data 2828 - * @port_pb_drop_stats: uplink pb drop stats 2710 + * @rsvd: reserved byte(s) 2711 + * @pb_stats: uplink pb drop stats 2829 2712 */ 2830 2713 struct ionic_port_info { 2831 2714 union ionic_port_config config; ··· 2840 2721 struct ionic_port_pb_stats pb_stats; 2841 2722 }; 2842 2723 2843 - /** 2724 + /* 2844 2725 * struct ionic_lif_stats - LIF statistics structure 2845 2726 */ 2846 2727 struct ionic_lif_stats { ··· 3102 2983 * bit 4-7 - 4 bit generation number, changes on fw restart 3103 2984 * @fw_heartbeat: Firmware heartbeat counter 3104 2985 * @serial_num: Serial number 2986 + * @rsvd_pad1024: reserved byte(s) 3105 2987 * @fw_version: Firmware version 3106 - * @hwstamp_regs: Hardware current timestamp registers 2988 + * @hwstamp: Hardware current timestamp registers 2989 + * @words: word access to struct contents 3107 2990 */ 3108 2991 union ionic_dev_info_regs { 3109 2992 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 ··· 3135 3014 * @done: Done indicator, bit 0 == 1 when command is complete 3136 3015 * @cmd: Opcode-specific command bytes 3137 3016 * @comp: Opcode-specific response bytes 3017 + * @rsvd: reserved byte(s) 3138 3018 * @data: Opcode-specific side-data 3019 + * @words: word access to struct contents 3139 3020 */ 3140 3021 union ionic_dev_cmd_regs { 3141 3022 struct { ··· 3155 3032 * union ionic_dev_regs - Device register format for bar 0 page 0 3156 3033 * @info: Device info registers 3157 3034 * @devcmd: Device command registers 3035 + * @words: word access to struct contents 3158 3036 */ 3159 3037 union ionic_dev_regs { 3160 3038 struct { ··· 3222 3098 * interrupts when armed. 3223 3099 * @qid_lo: Queue destination for the producer index and flags (low bits) 3224 3100 * @qid_hi: Queue destination for the producer index and flags (high bits) 3101 + * @rsvd2: reserved byte(s) 3225 3102 */ 3226 3103 struct ionic_doorbell { 3227 3104 __le16 p_index;
+4 -3
drivers/net/ethernet/pensando/ionic/ionic_lif.c
··· 237 237 const char *name; 238 238 239 239 if (lif->registered) 240 - name = lif->netdev->name; 240 + name = netdev_name(lif->netdev); 241 241 else 242 242 name = dev_name(dev); 243 243 244 244 snprintf(intr->name, sizeof(intr->name), 245 - "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 245 + "%.5s-%.16s-%.8s", IONIC_DRV_NAME, name, q->name); 246 246 247 247 return devm_request_irq(dev, intr->vector, ionic_isr, 248 248 0, intr->name, &qcq->napi); ··· 3388 3388 * just need to reanimate it. 3389 3389 */ 3390 3390 ionic_init_devinfo(ionic); 3391 + ionic_reset(ionic); 3391 3392 err = ionic_identify(ionic); 3392 3393 if (err) 3393 3394 goto err_out; ··· 3732 3731 }, 3733 3732 }; 3734 3733 3735 - strscpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3734 + strscpy(ctx.cmd.lif_setattr.name, netdev_name(lif->netdev), 3736 3735 sizeof(ctx.cmd.lif_setattr.name)); 3737 3736 3738 3737 ionic_adminq_post_wait(lif, &ctx);
+15 -17
drivers/net/ethernet/pensando/ionic/ionic_txrx.c
··· 502 502 XDP_PACKET_HEADROOM, frag_len, false); 503 503 504 504 dma_sync_single_range_for_cpu(rxq->dev, ionic_rx_buf_pa(buf_info), 505 - XDP_PACKET_HEADROOM, len, 505 + XDP_PACKET_HEADROOM, frag_len, 506 506 DMA_FROM_DEVICE); 507 507 508 508 prefetchw(&xdp_buf.data_hard_start); ··· 582 582 buf_info->page_offset, 583 583 true); 584 584 __netif_tx_unlock(nq); 585 - if (err) { 585 + if (unlikely(err)) { 586 586 netdev_dbg(netdev, "tx ionic_xdp_post_frame err %d\n", err); 587 587 goto out_xdp_abort; 588 588 } ··· 597 597 IONIC_PAGE_SIZE, DMA_FROM_DEVICE); 598 598 599 599 err = xdp_do_redirect(netdev, &xdp_buf, xdp_prog); 600 - if (err) { 600 + if (unlikely(err)) { 601 601 netdev_dbg(netdev, "xdp_do_redirect err %d\n", err); 602 602 goto out_xdp_abort; 603 603 } ··· 1058 1058 dma_addr_t dma_addr; 1059 1059 1060 1060 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE); 1061 - if (dma_mapping_error(dev, dma_addr)) { 1061 + if (unlikely(dma_mapping_error(dev, dma_addr))) { 1062 1062 net_warn_ratelimited("%s: DMA single map failed on %s!\n", 1063 1063 dev_name(dev), q->name); 1064 1064 q_to_tx_stats(q)->dma_map_err++; ··· 1075 1075 dma_addr_t dma_addr; 1076 1076 1077 1077 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE); 1078 - if (dma_mapping_error(dev, dma_addr)) { 1078 + if (unlikely(dma_mapping_error(dev, dma_addr))) { 1079 1079 net_warn_ratelimited("%s: DMA frag map failed on %s!\n", 1080 1080 dev_name(dev), q->name); 1081 1081 q_to_tx_stats(q)->dma_map_err++; ··· 1316 1316 int err; 1317 1317 1318 1318 err = skb_cow_head(skb, 0); 1319 - if (err) 1319 + if (unlikely(err)) 1320 1320 return err; 1321 1321 1322 1322 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { ··· 1340 1340 int err; 1341 1341 1342 1342 err = skb_cow_head(skb, 0); 1343 - if (err) 1343 + if (unlikely(err)) 1344 1344 return err; 1345 1345 1346 1346 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { ··· 1357 1357 } 1358 1358 1359 1359 static void ionic_tx_tso_post(struct net_device *netdev, struct ionic_queue *q, 1360 - struct ionic_tx_desc_info *desc_info, 1360 + struct ionic_txq_desc *desc, 1361 1361 struct sk_buff *skb, 1362 1362 dma_addr_t addr, u8 nsge, u16 len, 1363 1363 unsigned int hdrlen, unsigned int mss, ··· 1365 1365 u16 vlan_tci, bool has_vlan, 1366 1366 bool start, bool done) 1367 1367 { 1368 - struct ionic_txq_desc *desc = &q->txq[q->head_idx]; 1369 1368 u8 flags = 0; 1370 1369 u64 cmd; 1371 1370 ··· 1444 1445 err = ionic_tx_tcp_inner_pseudo_csum(skb); 1445 1446 else 1446 1447 err = ionic_tx_tcp_pseudo_csum(skb); 1447 - if (err) { 1448 + if (unlikely(err)) { 1448 1449 /* clean up mapping from ionic_tx_map_skb */ 1449 1450 ionic_tx_desc_unmap_bufs(q, desc_info); 1450 1451 return err; ··· 1502 1503 seg_rem = min(tso_rem, mss); 1503 1504 done = (tso_rem == 0); 1504 1505 /* post descriptor */ 1505 - ionic_tx_tso_post(netdev, q, desc_info, skb, 1506 - desc_addr, desc_nsge, desc_len, 1507 - hdrlen, mss, outer_csum, vlan_tci, has_vlan, 1508 - start, done); 1506 + ionic_tx_tso_post(netdev, q, desc, skb, desc_addr, desc_nsge, 1507 + desc_len, hdrlen, mss, outer_csum, vlan_tci, 1508 + has_vlan, start, done); 1509 1509 start = false; 1510 1510 /* Buffer information is stored with the first tso descriptor */ 1511 1511 desc_info = &q->tx_info[q->head_idx]; ··· 1729 1731 linearize: 1730 1732 if (too_many_frags) { 1731 1733 err = skb_linearize(skb); 1732 - if (err) 1734 + if (unlikely(err)) 1733 1735 return err; 1734 1736 q_to_tx_stats(q)->linearize++; 1735 1737 } ··· 1763 1765 else 1764 1766 err = ionic_tx(netdev, q, skb); 1765 1767 1766 - if (err) 1768 + if (unlikely(err)) 1767 1769 goto err_out_drop; 1768 1770 1769 1771 return NETDEV_TX_OK; ··· 1809 1811 else 1810 1812 err = ionic_tx(netdev, q, skb); 1811 1813 1812 - if (err) 1814 + if (unlikely(err)) 1813 1815 goto err_out_drop; 1814 1816 1815 1817 return NETDEV_TX_OK;