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drm/amd/display: avoid dig reg access timeout on usb4 link training fail

[Why]
When usb4 link training fails, the dpia sym clock will be disabled and SYMCLK
source should be changed back to phy clock. In enable_streams, it is
assumed that link training succeeded and will switch from refclk to
phy clock. But phy clk here might not be on. Dig reg access timeout
will occur.

[How]
When enable_stream is hit, check if link training failed for usb4.
If it did, fall back to the ref clock to avoid reg access timeout.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Zhongwei <Zhongwei.Zhang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Zhongwei and committed by
Alex Deucher
15b1d7b7 c37084e2

+10 -2
+10 -2
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
··· 3058 3058 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 3059 3059 } 3060 3060 } else { 3061 - if (dccg->funcs->enable_symclk_se) 3062 - dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, 3061 + if (dccg->funcs->enable_symclk_se && link_enc) { 3062 + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA 3063 + && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN 3064 + && !link->link_status.link_active) { 3065 + if (dccg->funcs->disable_symclk_se) 3066 + dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 3063 3067 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 3068 + } else 3069 + dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, 3070 + link_enc->transmitter - TRANSMITTER_UNIPHY_A); 3071 + } 3064 3072 } 3065 3073 3066 3074 if (dc->res_pool->dccg->funcs->set_pixel_rate_div)