Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'irq-drivers-2025-11-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq driver updates from Thomas Gleixner:
"Boring updates for interrupt drivers:
- Support for a couple of new ARM64 and RISCV SoC variants and their
magic interrupt controllers which either can reuse existing code or
require quirks due to a botched hardware implementation
- More section mismatch fixes
- The usual cleanups and fixes all over the place"
* tag 'irq-drivers-2025-11-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (32 commits)
irqchip/meson-gpio: Add support for Amlogic S6 S7 and S7D SoCs
dt-bindings: interrupt-controller: Add support for Amlogic S6 S7 and S7D SoCs
dt-bindings: interrupt-controller: aspeed,ast2700: Correct #interrupt-cells and interrupts count
irqchip/aclint-sswi: Add Nuclei UX900 support
dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
irqchip/irq-bcm7038-l1: Remove unused reg_mask_status()
irqchip/sifive-plic: Fix call to __plic_toggle() in M-Mode code path
irqchip/sifive-plic: Add support for UltraRISC DP1000 PLIC
irqchip/sifive-plic: Cache the interrupt enable state
dt-bindings: interrupt-controller: Add UltraRISC DP1000 PLIC
dt-bindings: vendor-prefixes: Add UltraRISC
irqchip/qcom-irq-combiner: Rename driver structure
irqchip/riscv-imsic: Inline imsic_vector_from_local_id()
irqchip/riscv-imsic: Embed the vector array in lpriv
irqchip/riscv-imsic: Remove redundant irq_data lookups
irqchip/ts4800: Drop unused module alias
irqchip/mvebu-pic: Drop unused module alias
irqchip/meson-gpio: Drop unused module alias
...
+264
-223
+3
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
+3
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
+9
-4
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
+9
-4
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
···
25
25
interrupt-controller: true
26
26
27
27
'#interrupt-cells':
28
-
const: 2
28
+
const: 1
29
29
description:
30
30
The first cell is the IRQ number, the second cell is the trigger
31
31
type as defined in interrupt.txt in this directory.
32
32
33
33
interrupts:
34
-
maxItems: 6
34
+
minItems: 1
35
+
maxItems: 10
35
36
description: |
36
37
Depend to which INTC0 or INTC1 used.
37
38
INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
···
75
74
interrupt-controller@12101b00 {
76
75
compatible = "aspeed,ast2700-intc-ic";
77
76
reg = <0 0x12101b00 0 0x10>;
78
-
#interrupt-cells = <2>;
77
+
#interrupt-cells = <1>;
79
78
interrupt-controller;
80
79
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
81
80
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
82
81
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
83
82
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
84
83
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
85
-
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
84
+
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
85
+
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
86
+
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
87
+
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
88
+
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
86
89
};
87
90
};
+4
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+4
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
···
58
58
- const: andestech,nceplic100
59
59
- items:
60
60
- enum:
61
+
- anlogic,dr1v90-plic
61
62
- canaan,k210-plic
62
63
- eswin,eic7700-plic
63
64
- sifive,fu540-c000-plic
···
76
75
- sophgo,sg2044-plic
77
76
- thead,th1520-plic
78
77
- const: thead,c900-plic
78
+
- items:
79
+
- const: ultrarisc,dp1000-plic
80
+
- const: ultrarisc,cp100-plic
79
81
- items:
80
82
- const: sifive,plic-1.0.0
81
83
- const: riscv,plic0
+11
-6
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
+11
-6
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
···
4
4
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
7
+
title: ACLINT Machine-level Software Interrupt Device
8
8
9
9
maintainers:
10
10
- Inochi Amaoto <inochiama@outlook.com>
11
11
12
12
properties:
13
13
compatible:
14
-
items:
15
-
- enum:
16
-
- sophgo,sg2042-aclint-mswi
17
-
- sophgo,sg2044-aclint-mswi
18
-
- const: thead,c900-aclint-mswi
14
+
oneOf:
15
+
- items:
16
+
- enum:
17
+
- sophgo,sg2042-aclint-mswi
18
+
- sophgo,sg2044-aclint-mswi
19
+
- const: thead,c900-aclint-mswi
20
+
- items:
21
+
- enum:
22
+
- anlogic,dr1v90-aclint-mswi
23
+
- const: nuclei,ux900-aclint-mswi
19
24
20
25
reg:
21
26
maxItems: 1
+4
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
+4
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
1705
1705
description: Universal Scientific Industrial Co., Ltd.
1706
1706
"^usr,.*":
1707
1707
description: U.S. Robotics Corporation
1708
+
"^ultrarisc,.*":
1709
+
description: UltraRISC Technology Co., Ltd.
1708
1710
"^ultratronik,.*":
1709
1711
description: Ultratronik GmbH
1710
1712
"^utoo,.*":
+3
-3
drivers/irqchip/Kconfig
+3
-3
drivers/irqchip/Kconfig
···
150
150
151
151
config BCM7038_L1_IRQ
152
152
tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
153
-
depends on ARCH_BRCMSTB || BMIPS_GENERIC
153
+
depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
154
154
default ARCH_BRCMSTB || BMIPS_GENERIC
155
155
select GENERIC_IRQ_CHIP
156
156
select IRQ_DOMAIN
···
158
158
159
159
config BCM7120_L2_IRQ
160
160
tristate "Broadcom STB 7120-style L2 interrupt controller driver"
161
-
depends on ARCH_BRCMSTB || BMIPS_GENERIC
161
+
depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
162
162
default ARCH_BRCMSTB || BMIPS_GENERIC
163
163
select GENERIC_IRQ_CHIP
164
164
select IRQ_DOMAIN
165
165
166
166
config BRCMSTB_L2_IRQ
167
167
tristate "Broadcom STB generic L2 interrupt controller driver"
168
-
depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
168
+
depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
169
169
default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
170
170
select GENERIC_IRQ_CHIP
171
171
select IRQ_DOMAIN
+2
-1
drivers/irqchip/irq-aclint-sswi.c
+2
-1
drivers/irqchip/irq-aclint-sswi.c
···
175
175
{
176
176
return generic_aclint_sswi_probe(&node->fwnode);
177
177
}
178
-
IRQCHIP_DECLARE(generic_aclint_sswi, "mips,p8700-aclint-sswi", generic_aclint_sswi_early_probe);
178
+
IRQCHIP_DECLARE(mips_p8700_sswi, "mips,p8700-aclint-sswi", generic_aclint_sswi_early_probe);
179
+
IRQCHIP_DECLARE(nuclei_ux900_sswi, "nuclei,ux900-aclint-sswi", generic_aclint_sswi_early_probe);
179
180
180
181
/* THEAD variant */
181
182
#define THEAD_C9XX_CSR_SXSTATUS 0x5c0
+3
-8
drivers/irqchip/irq-bcm2712-mip.c
+3
-8
drivers/irqchip/irq-bcm2712-mip.c
···
232
232
return ret;
233
233
}
234
234
235
-
static int __init mip_of_msi_init(struct device_node *node, struct device_node *parent)
235
+
static int mip_msi_probe(struct platform_device *pdev, struct device_node *parent)
236
236
{
237
-
struct platform_device *pdev;
237
+
struct device_node *node = pdev->dev.of_node;
238
238
struct mip_priv *mip;
239
239
int ret;
240
-
241
-
pdev = of_find_device_by_node(node);
242
-
of_node_put(node);
243
-
if (!pdev)
244
-
return -EPROBE_DEFER;
245
240
246
241
mip = kzalloc(sizeof(*mip), GFP_KERNEL);
247
242
if (!mip)
···
280
285
}
281
286
282
287
IRQCHIP_PLATFORM_DRIVER_BEGIN(mip_msi)
283
-
IRQCHIP_MATCH("brcm,bcm2712-mip", mip_of_msi_init)
288
+
IRQCHIP_MATCH("brcm,bcm2712-mip", mip_msi_probe)
284
289
IRQCHIP_PLATFORM_DRIVER_END(mip_msi)
285
290
MODULE_DESCRIPTION("Broadcom BCM2712 MSI-X interrupt controller");
286
291
MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
+5
-12
drivers/irqchip/irq-bcm7038-l1.c
+5
-12
drivers/irqchip/irq-bcm7038-l1.c
···
82
82
return (0 * intc->n_words + word) * sizeof(u32);
83
83
}
84
84
85
-
static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
86
-
unsigned int word)
87
-
{
88
-
return (1 * intc->n_words + word) * sizeof(u32);
89
-
}
90
-
91
85
static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
92
86
unsigned int word)
93
87
{
···
213
219
}
214
220
#endif
215
221
216
-
static int __init bcm7038_l1_init_one(struct device_node *dn,
217
-
unsigned int idx,
218
-
struct bcm7038_l1_chip *intc)
222
+
static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx,
223
+
struct bcm7038_l1_chip *intc)
219
224
{
220
225
struct resource res;
221
226
resource_size_t sz;
···
388
395
.map = bcm7038_l1_map,
389
396
};
390
397
391
-
static int __init bcm7038_l1_of_init(struct device_node *dn,
392
-
struct device_node *parent)
398
+
static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *parent)
393
399
{
400
+
struct device_node *dn = pdev->dev.of_node;
394
401
struct bcm7038_l1_chip *intc;
395
402
int idx, ret;
396
403
···
448
455
}
449
456
450
457
IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1)
451
-
IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_of_init)
458
+
IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_probe)
452
459
IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1)
453
460
MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller");
454
461
MODULE_LICENSE("GPL v2");
+9
-22
drivers/irqchip/irq-bcm7120-l2.c
+9
-22
drivers/irqchip/irq-bcm7120-l2.c
···
143
143
return 0;
144
144
}
145
145
146
-
static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
147
-
struct bcm7120_l2_intc_data *data)
146
+
static int bcm7120_l2_intc_iomap_7120(struct device_node *dn, struct bcm7120_l2_intc_data *data)
148
147
{
149
148
int ret;
150
149
···
176
177
return 0;
177
178
}
178
179
179
-
static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
180
-
struct bcm7120_l2_intc_data *data)
180
+
static int bcm7120_l2_intc_iomap_3380(struct device_node *dn, struct bcm7120_l2_intc_data *data)
181
181
{
182
182
unsigned int gc_idx;
183
183
···
206
208
return 0;
207
209
}
208
210
209
-
static int __init bcm7120_l2_intc_probe(struct device_node *dn,
210
-
struct device_node *parent,
211
+
static int bcm7120_l2_intc_probe(struct platform_device *pdev, struct device_node *parent,
211
212
int (*iomap_regs_fn)(struct device_node *,
212
-
struct bcm7120_l2_intc_data *),
213
+
struct bcm7120_l2_intc_data *),
213
214
const char *intc_name)
214
215
{
215
216
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
217
+
struct device_node *dn = pdev->dev.of_node;
216
218
struct bcm7120_l2_intc_data *data;
217
-
struct platform_device *pdev;
218
219
struct irq_chip_generic *gc;
219
220
struct irq_chip_type *ct;
220
221
int ret = 0;
···
224
227
if (!data)
225
228
return -ENOMEM;
226
229
227
-
pdev = of_find_device_by_node(dn);
228
-
if (!pdev) {
229
-
ret = -ENODEV;
230
-
goto out_free_data;
231
-
}
232
-
233
230
data->num_parent_irqs = platform_irq_count(pdev);
234
-
put_device(&pdev->dev);
235
231
if (data->num_parent_irqs <= 0) {
236
232
pr_err("invalid number of parent interrupts\n");
237
233
ret = -ENOMEM;
···
324
334
if (data->map_base[idx])
325
335
iounmap(data->map_base[idx]);
326
336
}
327
-
out_free_data:
328
337
kfree(data);
329
338
return ret;
330
339
}
331
340
332
-
static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
333
-
struct device_node *parent)
341
+
static int bcm7120_l2_intc_probe_7120(struct platform_device *pdev, struct device_node *parent)
334
342
{
335
-
return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
343
+
return bcm7120_l2_intc_probe(pdev, parent, bcm7120_l2_intc_iomap_7120,
336
344
"BCM7120 L2");
337
345
}
338
346
339
-
static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
340
-
struct device_node *parent)
347
+
static int bcm7120_l2_intc_probe_3380(struct platform_device *pdev, struct device_node *parent)
341
348
{
342
-
return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
349
+
return bcm7120_l2_intc_probe(pdev, parent, bcm7120_l2_intc_iomap_3380,
343
350
"BCM3380 L2");
344
351
}
345
352
+11
-14
drivers/irqchip/irq-brcmstb-l2.c
+11
-14
drivers/irqchip/irq-brcmstb-l2.c
···
138
138
irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
139
139
}
140
140
141
-
static int __init brcmstb_l2_intc_of_init(struct device_node *np,
142
-
struct device_node *parent,
143
-
const struct brcmstb_intc_init_params
144
-
*init_params)
141
+
static int brcmstb_l2_intc_probe(struct platform_device *pdev, struct device_node *parent,
142
+
const struct brcmstb_intc_init_params *init_params)
145
143
{
146
144
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
147
145
unsigned int set = 0;
146
+
struct device_node *np = pdev->dev.of_node;
148
147
struct brcmstb_l2_intc_data *data;
149
148
struct irq_chip_type *ct;
150
149
int ret;
···
256
257
return ret;
257
258
}
258
259
259
-
static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
260
-
struct device_node *parent)
260
+
static int brcmstb_l2_edge_intc_probe(struct platform_device *pdev, struct device_node *parent)
261
261
{
262
-
return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
262
+
return brcmstb_l2_intc_probe(pdev, parent, &l2_edge_intc_init);
263
263
}
264
264
265
-
static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
266
-
struct device_node *parent)
265
+
static int brcmstb_l2_lvl_intc_probe(struct platform_device *pdev, struct device_node *parent)
267
266
{
268
-
return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
267
+
return brcmstb_l2_intc_probe(pdev, parent, &l2_lvl_intc_init);
269
268
}
270
269
271
270
IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
272
-
IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
273
-
IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
274
-
IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
275
-
IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
271
+
IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_probe)
272
+
IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_probe)
273
+
IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_probe)
274
+
IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_probe)
276
275
IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
277
276
MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
278
277
MODULE_LICENSE("GPL v2");
+11
-17
drivers/irqchip/irq-imx-mu-msi.c
+11
-17
drivers/irqchip/irq-imx-mu-msi.c
···
296
296
},
297
297
};
298
298
299
-
static int __init imx_mu_of_init(struct device_node *dn,
300
-
struct device_node *parent,
301
-
const struct imx_mu_dcfg *cfg)
299
+
static int imx_mu_probe(struct platform_device *pdev, struct device_node *parent,
300
+
const struct imx_mu_dcfg *cfg)
302
301
{
303
-
struct platform_device *pdev = of_find_device_by_node(dn);
304
302
struct device_link *pd_link_a;
305
303
struct device_link *pd_link_b;
306
304
struct imx_mu_msi *msi_data;
···
414
416
imx_mu_runtime_resume, NULL)
415
417
};
416
418
417
-
static int __init imx_mu_imx7ulp_of_init(struct device_node *dn,
418
-
struct device_node *parent)
419
+
static int imx_mu_imx7ulp_probe(struct platform_device *pdev, struct device_node *parent)
419
420
{
420
-
return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp);
421
+
return imx_mu_probe(pdev, parent, &imx_mu_cfg_imx7ulp);
421
422
}
422
423
423
-
static int __init imx_mu_imx6sx_of_init(struct device_node *dn,
424
-
struct device_node *parent)
424
+
static int imx_mu_imx6sx_probe(struct platform_device *pdev, struct device_node *parent)
425
425
{
426
-
return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx);
426
+
return imx_mu_probe(pdev, parent, &imx_mu_cfg_imx6sx);
427
427
}
428
428
429
-
static int __init imx_mu_imx8ulp_of_init(struct device_node *dn,
430
-
struct device_node *parent)
429
+
static int imx_mu_imx8ulp_probe(struct platform_device *pdev, struct device_node *parent)
431
430
{
432
-
return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp);
431
+
return imx_mu_probe(pdev, parent, &imx_mu_cfg_imx8ulp);
433
432
}
434
433
435
434
IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi)
436
-
IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
437
-
IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
438
-
IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
435
+
IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_probe)
436
+
IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_probe)
437
+
IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_probe)
439
438
IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops)
440
-
441
439
442
440
MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>");
443
441
MODULE_DESCRIPTION("Freescale MU MSI controller driver");
+3
-2
drivers/irqchip/irq-mchp-eic.c
+3
-2
drivers/irqchip/irq-mchp-eic.c
···
199
199
.free = irq_domain_free_irqs_common,
200
200
};
201
201
202
-
static int mchp_eic_init(struct device_node *node, struct device_node *parent)
202
+
static int mchp_eic_probe(struct platform_device *pdev, struct device_node *parent)
203
203
{
204
+
struct device_node *node = pdev->dev.of_node;
204
205
struct irq_domain *parent_domain = NULL;
205
206
int ret, i;
206
207
···
274
273
}
275
274
276
275
IRQCHIP_PLATFORM_DRIVER_BEGIN(mchp_eic)
277
-
IRQCHIP_MATCH("microchip,sama7g5-eic", mchp_eic_init)
276
+
IRQCHIP_MATCH("microchip,sama7g5-eic", mchp_eic_probe)
278
277
IRQCHIP_PLATFORM_DRIVER_END(mchp_eic)
279
278
280
279
MODULE_DESCRIPTION("Microchip External Interrupt Controller");
+14
-3
drivers/irqchip/irq-meson-gpio.c
+14
-3
drivers/irqchip/irq-meson-gpio.c
···
174
174
INIT_MESON_S4_COMMON_DATA(82)
175
175
};
176
176
177
+
static const struct meson_gpio_irq_params s6_params = {
178
+
INIT_MESON_S4_COMMON_DATA(100)
179
+
};
180
+
181
+
static const struct meson_gpio_irq_params s7_params = {
182
+
INIT_MESON_S4_COMMON_DATA(84)
183
+
};
184
+
177
185
static const struct meson_gpio_irq_params c3_params = {
178
186
INIT_MESON_S4_COMMON_DATA(55)
179
187
};
···
203
195
{ .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
204
196
{ .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
205
197
{ .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
198
+
{ .compatible = "amlogic,s6-gpio-intc", .data = &s6_params },
199
+
{ .compatible = "amlogic,s7-gpio-intc", .data = &s7_params },
200
+
{ .compatible = "amlogic,s7d-gpio-intc", .data = &s7_params },
206
201
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
207
202
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
208
203
{ }
···
583
572
return 0;
584
573
}
585
574
586
-
static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *parent)
575
+
static int meson_gpio_irq_probe(struct platform_device *pdev, struct device_node *parent)
587
576
{
577
+
struct device_node *node = pdev->dev.of_node;
588
578
struct irq_domain *domain, *parent_domain;
589
579
struct meson_gpio_irq_controller *ctl;
590
580
int ret;
···
642
630
}
643
631
644
632
IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc)
645
-
IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_of_init)
633
+
IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_probe)
646
634
IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc)
647
635
648
636
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
649
637
MODULE_DESCRIPTION("Meson GPIO Interrupt Multiplexer driver");
650
638
MODULE_LICENSE("GPL v2");
651
-
MODULE_ALIAS("platform:meson-gpio-intc");
-2
drivers/irqchip/irq-mvebu-pic.c
-2
drivers/irqchip/irq-mvebu-pic.c
+3
-3
drivers/irqchip/irq-qcom-mpm.c
+3
-3
drivers/irqchip/irq-qcom-mpm.c
···
320
320
return false;
321
321
}
322
322
323
-
static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
323
+
static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *parent)
324
324
{
325
-
struct platform_device *pdev = of_find_device_by_node(np);
325
+
struct device_node *np = pdev->dev.of_node;
326
326
struct device *dev = &pdev->dev;
327
327
struct irq_domain *parent_domain;
328
328
struct generic_pm_domain *genpd;
···
478
478
}
479
479
480
480
IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_mpm)
481
-
IRQCHIP_MATCH("qcom,mpm", qcom_mpm_init)
481
+
IRQCHIP_MATCH("qcom,mpm", qcom_mpm_probe)
482
482
IRQCHIP_PLATFORM_DRIVER_END(qcom_mpm)
483
483
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. MSM Power Manager");
484
484
MODULE_LICENSE("GPL v2");
+10
-27
drivers/irqchip/irq-renesas-rzg2l.c
+10
-27
drivers/irqchip/irq-renesas-rzg2l.c
···
8
8
*/
9
9
10
10
#include <linux/bitfield.h>
11
-
#include <linux/cleanup.h>
12
11
#include <linux/clk.h>
13
12
#include <linux/err.h>
14
13
#include <linux/io.h>
···
527
528
return 0;
528
529
}
529
530
530
-
static int rzg2l_irqc_common_init(struct device_node *node, struct device_node *parent,
531
-
const struct irq_chip *irq_chip)
531
+
static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_node *parent,
532
+
const struct irq_chip *irq_chip)
532
533
{
533
-
struct platform_device *pdev = of_find_device_by_node(node);
534
-
struct device *dev __free(put_device) = pdev ? &pdev->dev : NULL;
535
534
struct irq_domain *irq_domain, *parent_domain;
535
+
struct device_node *node = pdev->dev.of_node;
536
+
struct device *dev = &pdev->dev;
536
537
struct reset_control *resetn;
537
538
int ret;
538
-
539
-
if (!pdev)
540
-
return -ENODEV;
541
539
542
540
parent_domain = irq_find_host(parent);
543
541
if (!parent_domain)
···
579
583
580
584
register_syscore_ops(&rzg2l_irqc_syscore_ops);
581
585
582
-
/*
583
-
* Prevent the cleanup function from invoking put_device by assigning
584
-
* NULL to dev.
585
-
*
586
-
* make coccicheck will complain about missing put_device calls, but
587
-
* those are false positives, as dev will be automatically "put" via
588
-
* __free_put_device on the failing path.
589
-
* On the successful path we don't actually want to "put" dev.
590
-
*/
591
-
dev = NULL;
592
-
593
586
return 0;
594
587
}
595
588
596
-
static int __init rzg2l_irqc_init(struct device_node *node,
597
-
struct device_node *parent)
589
+
static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_node *parent)
598
590
{
599
-
return rzg2l_irqc_common_init(node, parent, &rzg2l_irqc_chip);
591
+
return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip);
600
592
}
601
593
602
-
static int __init rzfive_irqc_init(struct device_node *node,
603
-
struct device_node *parent)
594
+
static int rzfive_irqc_probe(struct platform_device *pdev, struct device_node *parent)
604
595
{
605
-
return rzg2l_irqc_common_init(node, parent, &rzfive_irqc_chip);
596
+
return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip);
606
597
}
607
598
608
599
IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
609
-
IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
610
-
IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_init)
600
+
IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_probe)
601
+
IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_probe)
611
602
IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
612
603
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
613
604
MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
+9
-23
drivers/irqchip/irq-renesas-rzv2h.c
+9
-23
drivers/irqchip/irq-renesas-rzv2h.c
···
490
490
return 0;
491
491
}
492
492
493
-
static void rzv2h_icu_put_device(void *data)
494
-
{
495
-
put_device(data);
496
-
}
497
-
498
-
static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent,
499
-
const struct rzv2h_hw_info *hw_info)
493
+
static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_node *parent,
494
+
const struct rzv2h_hw_info *hw_info)
500
495
{
501
496
struct irq_domain *irq_domain, *parent_domain;
497
+
struct device_node *node = pdev->dev.of_node;
502
498
struct rzv2h_icu_priv *rzv2h_icu_data;
503
-
struct platform_device *pdev;
504
499
struct reset_control *resetn;
505
500
int ret;
506
-
507
-
pdev = of_find_device_by_node(node);
508
-
if (!pdev)
509
-
return -ENODEV;
510
-
511
-
ret = devm_add_action_or_reset(&pdev->dev, rzv2h_icu_put_device,
512
-
&pdev->dev);
513
-
if (ret < 0)
514
-
return ret;
515
501
516
502
parent_domain = irq_find_host(parent);
517
503
if (!parent_domain) {
···
604
618
.field_width = 8,
605
619
};
606
620
607
-
static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
621
+
static int rzg3e_icu_probe(struct platform_device *pdev, struct device_node *parent)
608
622
{
609
-
return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
623
+
return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params);
610
624
}
611
625
612
-
static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
626
+
static int rzv2h_icu_probe(struct platform_device *pdev, struct device_node *parent)
613
627
{
614
-
return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
628
+
return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params);
615
629
}
616
630
617
631
IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
618
-
IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
619
-
IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
632
+
IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe)
633
+
IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe)
620
634
IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
621
635
MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
622
636
MODULE_DESCRIPTION("Renesas RZ/V2H(P) ICU Driver");
+3
-8
drivers/irqchip/irq-riscv-imsic-early.c
+3
-8
drivers/irqchip/irq-riscv-imsic-early.c
···
91
91
*/
92
92
static void imsic_handle_irq(struct irq_desc *desc)
93
93
{
94
+
struct imsic_local_priv *lpriv = this_cpu_ptr(imsic->lpriv);
94
95
struct irq_chip *chip = irq_desc_get_chip(desc);
95
-
int cpu = smp_processor_id();
96
-
struct imsic_vector *vec;
97
96
unsigned long local_id;
98
97
99
98
/*
···
112
113
continue;
113
114
}
114
115
115
-
if (unlikely(!imsic->base_domain))
116
-
continue;
117
-
118
-
vec = imsic_vector_from_local_id(cpu, local_id);
119
-
if (!vec) {
116
+
if (unlikely(local_id > imsic->global.nr_ids)) {
120
117
pr_warn_ratelimited("vector not found for local ID 0x%lx\n", local_id);
121
118
continue;
122
119
}
123
120
124
-
generic_handle_irq(vec->irq);
121
+
generic_handle_irq(lpriv->vectors[local_id].irq);
125
122
}
126
123
127
124
chained_irq_exit(chip, desc);
+2
-2
drivers/irqchip/irq-riscv-imsic-platform.c
+2
-2
drivers/irqchip/irq-riscv-imsic-platform.c
···
158
158
tmp_vec.local_id = new_vec->local_id;
159
159
160
160
/* Point device to the temporary vector */
161
-
imsic_msi_update_msg(irq_get_irq_data(d->irq), &tmp_vec);
161
+
imsic_msi_update_msg(d, &tmp_vec);
162
162
}
163
163
164
164
/* Point device to the new vector */
165
-
imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec);
165
+
imsic_msi_update_msg(d, new_vec);
166
166
167
167
/* Update irq descriptors with the new vector */
168
168
d->chip_data = new_vec;
+2
-18
drivers/irqchip/irq-riscv-imsic-state.c
+2
-18
drivers/irqchip/irq-riscv-imsic-state.c
···
434
434
}
435
435
#endif
436
436
437
-
struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, unsigned int local_id)
438
-
{
439
-
struct imsic_local_priv *lpriv = per_cpu_ptr(imsic->lpriv, cpu);
440
-
441
-
if (!lpriv || imsic->global.nr_ids < local_id)
442
-
return NULL;
443
-
444
-
return &lpriv->vectors[local_id];
445
-
}
446
-
447
437
struct imsic_vector *imsic_vector_alloc(unsigned int irq, const struct cpumask *mask)
448
438
{
449
439
struct imsic_vector *vec = NULL;
···
477
487
lpriv = per_cpu_ptr(imsic->lpriv, cpu);
478
488
479
489
bitmap_free(lpriv->dirty_bitmap);
480
-
kfree(lpriv->vectors);
481
490
}
482
491
483
492
free_percpu(imsic->lpriv);
···
490
501
int cpu, i;
491
502
492
503
/* Allocate per-CPU private state */
493
-
imsic->lpriv = alloc_percpu(typeof(*imsic->lpriv));
504
+
imsic->lpriv = __alloc_percpu(struct_size(imsic->lpriv, vectors, global->nr_ids + 1),
505
+
__alignof__(*imsic->lpriv));
494
506
if (!imsic->lpriv)
495
507
return -ENOMEM;
496
508
···
510
520
/* Setup lazy timer for synchronization */
511
521
timer_setup(&lpriv->timer, imsic_local_timer_callback, TIMER_PINNED);
512
522
#endif
513
-
514
-
/* Allocate vector array */
515
-
lpriv->vectors = kcalloc(global->nr_ids + 1, sizeof(*lpriv->vectors),
516
-
GFP_KERNEL);
517
-
if (!lpriv->vectors)
518
-
goto fail_local_cleanup;
519
523
520
524
/* Setup vector array */
521
525
for (i = 0; i <= global->nr_ids; i++) {
+1
-3
drivers/irqchip/irq-riscv-imsic-state.h
+1
-3
drivers/irqchip/irq-riscv-imsic-state.h
···
40
40
#endif
41
41
42
42
/* Local vector table */
43
-
struct imsic_vector *vectors;
43
+
struct imsic_vector vectors[];
44
44
};
45
45
46
46
struct imsic_priv {
···
94
94
95
95
void imsic_vector_force_move_cleanup(struct imsic_vector *vec);
96
96
void imsic_vector_move(struct imsic_vector *old_vec, struct imsic_vector *new_vec);
97
-
98
-
struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, unsigned int local_id);
99
97
100
98
struct imsic_vector *imsic_vector_alloc(unsigned int irq, const struct cpumask *mask);
101
99
void imsic_vector_free(struct imsic_vector *vector);
+120
-29
drivers/irqchip/irq-sifive-plic.c
+120
-29
drivers/irqchip/irq-sifive-plic.c
···
49
49
#define CONTEXT_ENABLE_BASE 0x2000
50
50
#define CONTEXT_ENABLE_SIZE 0x80
51
51
52
+
#define PENDING_BASE 0x1000
53
+
52
54
/*
53
55
* Each hart context has a set of control registers associated with it. Right
54
56
* now there's only two: a source priority threshold over which the hart will
···
65
63
#define PLIC_ENABLE_THRESHOLD 0
66
64
67
65
#define PLIC_QUIRK_EDGE_INTERRUPT 0
66
+
#define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM 1
68
67
69
68
struct plic_priv {
70
69
struct fwnode_handle *fwnode;
···
97
94
98
95
static int plic_irq_set_type(struct irq_data *d, unsigned int type);
99
96
100
-
static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
97
+
static void __plic_toggle(struct plic_handler *handler, int hwirq, int enable)
101
98
{
102
-
u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
99
+
u32 __iomem *base = handler->enable_base;
103
100
u32 hwirq_mask = 1 << (hwirq % 32);
101
+
int group = hwirq / 32;
102
+
u32 value;
103
+
104
+
value = readl(base + group);
104
105
105
106
if (enable)
106
-
writel(readl(reg) | hwirq_mask, reg);
107
+
value |= hwirq_mask;
107
108
else
108
-
writel(readl(reg) & ~hwirq_mask, reg);
109
+
value &= ~hwirq_mask;
110
+
111
+
handler->enable_save[group] = value;
112
+
writel(value, base + group);
109
113
}
110
114
111
115
static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
···
120
110
unsigned long flags;
121
111
122
112
raw_spin_lock_irqsave(&handler->enable_lock, flags);
123
-
__plic_toggle(handler->enable_base, hwirq, enable);
113
+
__plic_toggle(handler, hwirq, enable);
124
114
raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
125
115
}
126
116
···
257
247
258
248
static int plic_irq_suspend(void)
259
249
{
260
-
unsigned int i, cpu;
261
-
unsigned long flags;
262
-
u32 __iomem *reg;
263
250
struct plic_priv *priv;
264
251
265
252
priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;
266
253
267
254
/* irq ID 0 is reserved */
268
-
for (i = 1; i < priv->nr_irqs; i++) {
255
+
for (unsigned int i = 1; i < priv->nr_irqs; i++) {
269
256
__assign_bit(i, priv->prio_save,
270
257
readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID));
271
-
}
272
-
273
-
for_each_present_cpu(cpu) {
274
-
struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
275
-
276
-
if (!handler->present)
277
-
continue;
278
-
279
-
raw_spin_lock_irqsave(&handler->enable_lock, flags);
280
-
for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
281
-
reg = handler->enable_base + i * sizeof(u32);
282
-
handler->enable_save[i] = readl(reg);
283
-
}
284
-
raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
285
258
}
286
259
287
260
return 0;
···
391
398
chained_irq_exit(chip, desc);
392
399
}
393
400
401
+
static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *handler)
402
+
{
403
+
u32 __iomem *pending = handler->priv->regs + PENDING_BASE;
404
+
u32 __iomem *enable = handler->enable_base;
405
+
u32 pending_irqs = 0;
406
+
int i, j;
407
+
408
+
/* Look for first pending interrupt */
409
+
for (i = 0; i < nr_irq_groups; i++) {
410
+
/* Any pending interrupts would be annihilated, so skip checking them */
411
+
if (!handler->enable_save[i])
412
+
continue;
413
+
414
+
pending_irqs = handler->enable_save[i] & readl_relaxed(pending + i);
415
+
if (pending_irqs)
416
+
break;
417
+
}
418
+
419
+
if (!pending_irqs)
420
+
return 0;
421
+
422
+
/* Isolate lowest set bit */
423
+
pending_irqs &= -pending_irqs;
424
+
425
+
/* Disable all interrupts but the first pending one */
426
+
for (j = 0; j < nr_irq_groups; j++) {
427
+
u32 new_mask = j == i ? pending_irqs : 0;
428
+
429
+
if (new_mask != handler->enable_save[j])
430
+
writel_relaxed(new_mask, enable + j);
431
+
}
432
+
return pending_irqs;
433
+
}
434
+
435
+
static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void __iomem *claim)
436
+
{
437
+
int nr_irq_groups = DIV_ROUND_UP(handler->priv->nr_irqs, 32);
438
+
u32 __iomem *enable = handler->enable_base;
439
+
irq_hw_number_t hwirq = 0;
440
+
u32 iso_mask;
441
+
int i;
442
+
443
+
guard(raw_spinlock)(&handler->enable_lock);
444
+
445
+
/* Existing enable state is already cached in enable_save */
446
+
iso_mask = cp100_isolate_pending_irq(nr_irq_groups, handler);
447
+
if (!iso_mask)
448
+
return 0;
449
+
450
+
/*
451
+
* Interrupts delievered to hardware still become pending, but only
452
+
* interrupts that are both pending and enabled can be claimed.
453
+
* Clearing the enable bit for all interrupts but the first pending
454
+
* one avoids a hardware bug that occurs during read from the claim
455
+
* register with more than one eligible interrupt.
456
+
*/
457
+
hwirq = readl(claim);
458
+
459
+
/* Restore previous state */
460
+
for (i = 0; i < nr_irq_groups; i++) {
461
+
u32 written = i == hwirq / 32 ? iso_mask : 0;
462
+
u32 stored = handler->enable_save[i];
463
+
464
+
if (stored != written)
465
+
writel_relaxed(stored, enable + i);
466
+
}
467
+
return hwirq;
468
+
}
469
+
470
+
static void plic_handle_irq_cp100(struct irq_desc *desc)
471
+
{
472
+
struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
473
+
struct irq_chip *chip = irq_desc_get_chip(desc);
474
+
void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
475
+
irq_hw_number_t hwirq;
476
+
477
+
WARN_ON_ONCE(!handler->present);
478
+
479
+
chained_irq_enter(chip, desc);
480
+
481
+
while ((hwirq = cp100_get_hwirq(handler, claim))) {
482
+
int err = generic_handle_domain_irq(handler->priv->irqdomain, hwirq);
483
+
484
+
if (unlikely(err)) {
485
+
pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
486
+
handler->priv->fwnode, hwirq);
487
+
}
488
+
}
489
+
490
+
chained_irq_exit(chip, desc);
491
+
}
492
+
394
493
static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
395
494
{
396
495
/* priority must be > threshold to trigger an interrupt */
···
519
434
.data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
520
435
{ .compatible = "thead,c900-plic",
521
436
.data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
437
+
{ .compatible = "ultrarisc,cp100-plic",
438
+
.data = (const void *)BIT(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM) },
522
439
{}
523
440
};
524
441
···
679
592
if (parent_hwirq != RV_IRQ_EXT) {
680
593
/* Disable S-mode enable bits if running in M-mode. */
681
594
if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
682
-
void __iomem *enable_base = priv->regs +
683
-
CONTEXT_ENABLE_BASE +
684
-
i * CONTEXT_ENABLE_SIZE;
595
+
u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE +
596
+
i * CONTEXT_ENABLE_SIZE;
685
597
686
-
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
687
-
__plic_toggle(enable_base, hwirq, 0);
598
+
for (int j = 0; j <= nr_irqs / 32; j++)
599
+
writel(0, enable_base + j);
688
600
}
689
601
continue;
690
602
}
···
754
668
}
755
669
756
670
if (global_setup) {
671
+
void (*handler_fn)(struct irq_desc *) = plic_handle_irq;
672
+
673
+
if (test_bit(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM, &handler->priv->plic_quirks))
674
+
handler_fn = plic_handle_irq_cp100;
675
+
757
676
/* Find parent domain and register chained handler */
758
677
domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
759
678
if (domain)
760
679
plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
761
680
if (plic_parent_irq)
762
-
irq_set_chained_handler(plic_parent_irq, plic_handle_irq);
681
+
irq_set_chained_handler(plic_parent_irq, handler_fn);
763
682
764
683
cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
765
684
"irqchip/sifive/plic:starting",
+3
-3
drivers/irqchip/irq-starfive-jh8100-intc.c
+3
-3
drivers/irqchip/irq-starfive-jh8100-intc.c
···
114
114
chained_irq_exit(chip, desc);
115
115
}
116
116
117
-
static int __init starfive_intc_init(struct device_node *intc,
118
-
struct device_node *parent)
117
+
static int starfive_intc_probe(struct platform_device *pdev, struct device_node *parent)
119
118
{
119
+
struct device_node *intc = pdev->dev.of_node;
120
120
struct starfive_irq_chip *irqc;
121
121
struct reset_control *rst;
122
122
struct clk *clk;
···
199
199
}
200
200
201
201
IRQCHIP_PLATFORM_DRIVER_BEGIN(starfive_intc)
202
-
IRQCHIP_MATCH("starfive,jh8100-intc", starfive_intc_init)
202
+
IRQCHIP_MATCH("starfive,jh8100-intc", starfive_intc_probe)
203
203
IRQCHIP_PLATFORM_DRIVER_END(starfive_intc)
204
204
205
205
MODULE_DESCRIPTION("StarFive JH8100 External Interrupt Controller");
-1
drivers/irqchip/irq-ts4800.c
-1
drivers/irqchip/irq-ts4800.c
+4
-6
drivers/irqchip/irqchip.c
+4
-6
drivers/irqchip/irqchip.c
···
36
36
{
37
37
struct device_node *np = pdev->dev.of_node;
38
38
struct device_node *par_np __free(device_node) = of_irq_find_parent(np);
39
-
of_irq_init_cb_t irq_init_cb = of_device_get_match_data(&pdev->dev);
39
+
platform_irq_probe_t irq_probe = of_device_get_match_data(&pdev->dev);
40
40
41
-
if (!irq_init_cb) {
41
+
if (!irq_probe)
42
42
return -EINVAL;
43
-
}
44
43
45
44
if (par_np == np)
46
45
par_np = NULL;
···
52
53
* interrupt controller. The actual initialization callback of this
53
54
* interrupt controller can check for specific domains as necessary.
54
55
*/
55
-
if (par_np && !irq_find_matching_host(par_np, DOMAIN_BUS_ANY)) {
56
+
if (par_np && !irq_find_matching_host(par_np, DOMAIN_BUS_ANY))
56
57
return -EPROBE_DEFER;
57
-
}
58
58
59
-
return irq_init_cb(np, par_np);
59
+
return irq_probe(pdev, par_np);
60
60
}
61
61
EXPORT_SYMBOL_GPL(platform_irqchip_probe);
+3
-3
drivers/irqchip/qcom-irq-combiner.c
+3
-3
drivers/irqchip/qcom-irq-combiner.c
···
222
222
return 0;
223
223
}
224
224
225
-
static int __init combiner_probe(struct platform_device *pdev)
225
+
static int combiner_probe(struct platform_device *pdev)
226
226
{
227
227
struct combiner *combiner;
228
228
int nregs;
···
266
266
{ }
267
267
};
268
268
269
-
static struct platform_driver qcom_irq_combiner_probe = {
269
+
static struct platform_driver qcom_irq_combiner_driver = {
270
270
.driver = {
271
271
.name = "qcom-irq-combiner",
272
272
.acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
273
273
},
274
274
.probe = combiner_probe,
275
275
};
276
-
builtin_platform_driver(qcom_irq_combiner_probe);
276
+
builtin_platform_driver(qcom_irq_combiner_driver);
+3
-2
drivers/irqchip/qcom-pdc.c
+3
-2
drivers/irqchip/qcom-pdc.c
···
350
350
351
351
#define QCOM_PDC_SIZE 0x30000
352
352
353
-
static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
353
+
static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *parent)
354
354
{
355
355
struct irq_domain *parent_domain, *pdc_domain;
356
+
struct device_node *node = pdev->dev.of_node;
356
357
resource_size_t res_size;
357
358
struct resource res;
358
359
int ret;
···
429
428
}
430
429
431
430
IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
432
-
IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
431
+
IRQCHIP_MATCH("qcom,pdc", qcom_pdc_probe)
433
432
IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
434
433
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
435
434
MODULE_LICENSE("GPL v2");
+7
-1
include/linux/irqchip.h
+7
-1
include/linux/irqchip.h
···
17
17
#include <linux/of_irq.h>
18
18
#include <linux/platform_device.h>
19
19
20
+
typedef int (*platform_irq_probe_t)(struct platform_device *, struct device_node *);
21
+
20
22
/* Undefined on purpose */
21
23
extern of_irq_init_cb_t typecheck_irq_init_cb;
24
+
extern platform_irq_probe_t typecheck_irq_probe;
22
25
23
26
#define typecheck_irq_init_cb(fn) \
24
27
(__typecheck(typecheck_irq_init_cb, &fn) ? fn : fn)
28
+
29
+
#define typecheck_irq_probe(fn) \
30
+
(__typecheck(typecheck_irq_probe, &fn) ? fn : fn)
25
31
26
32
/*
27
33
* This macro must be used by the different irqchip drivers to declare
···
48
42
static const struct of_device_id drv_name##_irqchip_match_table[] = {
49
43
50
44
#define IRQCHIP_MATCH(compat, fn) { .compatible = compat, \
51
-
.data = typecheck_irq_init_cb(fn), },
45
+
.data = typecheck_irq_probe(fn), },
52
46
53
47
54
48
#define IRQCHIP_PLATFORM_DRIVER_END(drv_name, ...) \