tjh.dev / kernel
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drm/amd/display: add seamless pipe topology transition check

[why]
We have a few cases where we need to perform update topology update
in dc update interface. However some of the updates are not seamless
This could cause user noticible glitches. To enforce seamless transition
we are adding a checking condition and error logging so the corruption
as result of non seamless transition can be easily spotted.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Wenjing Liu and committed by
Alex Deucher 15c6798a c8b249a7

+68
+8
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 4363 4363 update_type, 4364 4364 context); 4365 4365 } else { 4366 + if (!stream_update && 4367 + dc->hwss.is_pipe_topology_transition_seamless && 4368 + !dc->hwss.is_pipe_topology_transition_seamless( 4369 + dc, dc->current_state, context)) { 4370 + 4371 + DC_LOG_ERROR("performing non-seamless pipe topology transition with surface only update!\n"); 4372 + BREAK_TO_DEBUGGER(); 4373 + } 4366 4374 commit_planes_for_stream( 4367 4375 dc, 4368 4376 srf_updates,
+52
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
··· 1619 1619 if (tg->funcs->is_tg_enabled(tg)) 1620 1620 hws->funcs.wait_for_blank_complete(opp); 1621 1621 } 1622 + 1623 + bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, 1624 + const struct dc_state *cur_ctx, 1625 + const struct dc_state *new_ctx) 1626 + { 1627 + int i; 1628 + const struct pipe_ctx *cur_pipe, *new_pipe; 1629 + bool is_seamless = true; 1630 + 1631 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 1632 + cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i]; 1633 + new_pipe = &new_ctx->res_ctx.pipe_ctx[i]; 1634 + 1635 + if (resource_is_pipe_type(cur_pipe, FREE_PIPE) || 1636 + resource_is_pipe_type(new_pipe, FREE_PIPE)) 1637 + /* adding or removing free pipes is always seamless */ 1638 + continue; 1639 + else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) { 1640 + if (resource_is_pipe_type(new_pipe, OTG_MASTER)) 1641 + if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id) 1642 + /* OTG master with the same stream is seamless */ 1643 + continue; 1644 + } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) { 1645 + if (resource_is_pipe_type(new_pipe, OPP_HEAD)) { 1646 + if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg) 1647 + /* 1648 + * OPP heads sharing the same timing 1649 + * generator is seamless 1650 + */ 1651 + continue; 1652 + } 1653 + } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) { 1654 + if (resource_is_pipe_type(new_pipe, DPP_PIPE)) { 1655 + if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp) 1656 + /* 1657 + * DPP pipes sharing the same OPP head is 1658 + * seamless 1659 + */ 1660 + continue; 1661 + } 1662 + } 1663 + 1664 + /* 1665 + * This pipe's transition doesn't fall under any seamless 1666 + * conditions 1667 + */ 1668 + is_seamless = false; 1669 + break; 1670 + } 1671 + 1672 + return is_seamless; 1673 + }
+4
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
··· 120 120 int width, 121 121 int height); 122 122 123 + bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, 124 + const struct dc_state *cur_ctx, 125 + const struct dc_state *new_ctx); 126 + 123 127 #endif /* __DC_HWSS_DCN32_H__ */
+1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
··· 116 116 .update_dsc_pg = dcn32_update_dsc_pg, 117 117 .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, 118 118 .blank_phantom = dcn32_blank_phantom, 119 + .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, 119 120 }; 120 121 121 122 static const struct hwseq_private_funcs dcn32_private_funcs = {
+3
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
··· 410 410 struct dc_state *context, 411 411 struct pipe_ctx *phantom_pipe); 412 412 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 413 + bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 414 + const struct dc_state *cur_ctx, 415 + const struct dc_state *new_ctx); 413 416 414 417 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 415 418 struct pg_block_update *update_state);