Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'staging-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging / IIO driver fixes from Greg KH:
"Here are some small staging and IIO driver fixes for 5.3-rc4.
Nothing major, just resolutions for a number of small reported issues,
full details in the shortlog.
All have been in linux-next for a while with no reported issues"
* tag 'staging-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
iio: adc: gyroadc: fix uninitialized return code
docs: generic-counter.rst: fix broken references for ABI file
staging: android: ion: Bail out upon SIGKILL when allocating memory.
Staging: fbtft: Fix GPIO handling
staging: unisys: visornic: Update the description of 'poll_for_irq()'
staging: wilc1000: flush the workqueue before deinit the host
staging: gasket: apex: fix copy-paste typo
Staging: fbtft: Fix reset assertion when using gpio descriptor
Staging: fbtft: Fix probing of gpio descriptor
iio: imu: mpu6050: add missing available scan masks
iio: cros_ec_accel_legacy: Fix incorrect channel setting
IIO: Ingenic JZ47xx: Set clock divider on probe
iio: adc: max9611: Fix misuse of GENMASK macro
+138
-40
-1
drivers/iio/accel/cros_ec_accel_legacy.c
-1
drivers/iio/accel/cros_ec_accel_legacy.c
+54
drivers/iio/adc/ingenic-adc.c
+54
drivers/iio/adc/ingenic-adc.c
···
11
11
#include <linux/iio/iio.h>
12
12
#include <linux/io.h>
13
13
#include <linux/iopoll.h>
14
+
#include <linux/kernel.h>
14
15
#include <linux/module.h>
15
16
#include <linux/mutex.h>
16
17
#include <linux/platform_device.h>
···
23
22
#define JZ_ADC_REG_ADTCH 0x18
24
23
#define JZ_ADC_REG_ADBDAT 0x1c
25
24
#define JZ_ADC_REG_ADSDAT 0x20
25
+
#define JZ_ADC_REG_ADCLK 0x28
26
26
27
27
#define JZ_ADC_REG_CFG_BAT_MD BIT(4)
28
+
#define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
29
+
#define JZ_ADC_REG_ADCLK_CLKDIV10US_LSB 16
28
30
29
31
#define JZ_ADC_AUX_VREF 3300
30
32
#define JZ_ADC_AUX_VREF_BITS 12
···
38
34
#define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
39
35
#define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
40
36
37
+
struct ingenic_adc;
38
+
41
39
struct ingenic_adc_soc_data {
42
40
unsigned int battery_high_vref;
43
41
unsigned int battery_high_vref_bits;
···
47
41
size_t battery_raw_avail_size;
48
42
const int *battery_scale_avail;
49
43
size_t battery_scale_avail_size;
44
+
int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
50
45
};
51
46
52
47
struct ingenic_adc {
···
158
151
JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
159
152
};
160
153
154
+
static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
155
+
{
156
+
struct clk *parent_clk;
157
+
unsigned long parent_rate, rate;
158
+
unsigned int div_main, div_10us;
159
+
160
+
parent_clk = clk_get_parent(adc->clk);
161
+
if (!parent_clk) {
162
+
dev_err(dev, "ADC clock has no parent\n");
163
+
return -ENODEV;
164
+
}
165
+
parent_rate = clk_get_rate(parent_clk);
166
+
167
+
/*
168
+
* The JZ4725B ADC works at 500 kHz to 8 MHz.
169
+
* We pick the highest rate possible.
170
+
* In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
171
+
*/
172
+
div_main = DIV_ROUND_UP(parent_rate, 8000000);
173
+
div_main = clamp(div_main, 1u, 64u);
174
+
rate = parent_rate / div_main;
175
+
if (rate < 500000 || rate > 8000000) {
176
+
dev_err(dev, "No valid divider for ADC main clock\n");
177
+
return -EINVAL;
178
+
}
179
+
180
+
/* We also need a divider that produces a 10us clock. */
181
+
div_10us = DIV_ROUND_UP(rate, 100000);
182
+
183
+
writel(((div_10us - 1) << JZ_ADC_REG_ADCLK_CLKDIV10US_LSB) |
184
+
(div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
185
+
adc->base + JZ_ADC_REG_ADCLK);
186
+
187
+
return 0;
188
+
}
189
+
161
190
static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
162
191
.battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
163
192
.battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
···
201
158
.battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
202
159
.battery_scale_avail = jz4725b_adc_battery_scale_avail,
203
160
.battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
161
+
.init_clk_div = jz4725b_adc_init_clk_div,
204
162
};
205
163
206
164
static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
···
211
167
.battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
212
168
.battery_scale_avail = jz4740_adc_battery_scale_avail,
213
169
.battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
170
+
.init_clk_div = NULL, /* no ADCLK register on JZ4740 */
214
171
};
215
172
216
173
static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
···
360
315
if (ret) {
361
316
dev_err(dev, "Failed to enable clock\n");
362
317
return ret;
318
+
}
319
+
320
+
/* Set clock dividers. */
321
+
if (soc_data->init_clk_div) {
322
+
ret = soc_data->init_clk_div(dev, adc);
323
+
if (ret) {
324
+
clk_disable_unprepare(adc->clk);
325
+
return ret;
326
+
}
363
327
}
364
328
365
329
/* Put hardware in a known passive state. */
+1
-1
drivers/iio/adc/max9611.c
+1
-1
drivers/iio/adc/max9611.c
···
83
83
#define MAX9611_TEMP_MAX_POS 0x7f80
84
84
#define MAX9611_TEMP_MAX_NEG 0xff80
85
85
#define MAX9611_TEMP_MIN_NEG 0xd980
86
-
#define MAX9611_TEMP_MASK GENMASK(7, 15)
86
+
#define MAX9611_TEMP_MASK GENMASK(15, 7)
87
87
#define MAX9611_TEMP_SHIFT 0x07
88
88
#define MAX9611_TEMP_RAW(_r) ((_r) >> MAX9611_TEMP_SHIFT)
89
89
#define MAX9611_TEMP_SCALE_NUM 1000000
+2
-2
drivers/iio/adc/rcar-gyroadc.c
+2
-2
drivers/iio/adc/rcar-gyroadc.c
···
382
382
dev_err(dev,
383
383
"Only %i channels supported with %pOFn, but reg = <%i>.\n",
384
384
num_channels, child, reg);
385
-
return ret;
385
+
return -EINVAL;
386
386
}
387
387
}
388
388
···
391
391
dev_err(dev,
392
392
"Channel %i uses different ADC mode than the rest.\n",
393
393
reg);
394
-
return ret;
394
+
return -EINVAL;
395
395
}
396
396
397
397
/* Channel is valid, grab the regulator. */
+43
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
+43
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
···
845
845
INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
846
846
};
847
847
848
+
static const unsigned long inv_mpu_scan_masks[] = {
849
+
/* 3-axis accel */
850
+
BIT(INV_MPU6050_SCAN_ACCL_X)
851
+
| BIT(INV_MPU6050_SCAN_ACCL_Y)
852
+
| BIT(INV_MPU6050_SCAN_ACCL_Z),
853
+
/* 3-axis gyro */
854
+
BIT(INV_MPU6050_SCAN_GYRO_X)
855
+
| BIT(INV_MPU6050_SCAN_GYRO_Y)
856
+
| BIT(INV_MPU6050_SCAN_GYRO_Z),
857
+
/* 6-axis accel + gyro */
858
+
BIT(INV_MPU6050_SCAN_ACCL_X)
859
+
| BIT(INV_MPU6050_SCAN_ACCL_Y)
860
+
| BIT(INV_MPU6050_SCAN_ACCL_Z)
861
+
| BIT(INV_MPU6050_SCAN_GYRO_X)
862
+
| BIT(INV_MPU6050_SCAN_GYRO_Y)
863
+
| BIT(INV_MPU6050_SCAN_GYRO_Z),
864
+
0,
865
+
};
866
+
848
867
static const struct iio_chan_spec inv_icm20602_channels[] = {
849
868
IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP),
850
869
{
···
888
869
INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_ICM20602_SCAN_ACCL_Y),
889
870
INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_ICM20602_SCAN_ACCL_X),
890
871
INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z),
872
+
};
873
+
874
+
static const unsigned long inv_icm20602_scan_masks[] = {
875
+
/* 3-axis accel + temp (mandatory) */
876
+
BIT(INV_ICM20602_SCAN_ACCL_X)
877
+
| BIT(INV_ICM20602_SCAN_ACCL_Y)
878
+
| BIT(INV_ICM20602_SCAN_ACCL_Z)
879
+
| BIT(INV_ICM20602_SCAN_TEMP),
880
+
/* 3-axis gyro + temp (mandatory) */
881
+
BIT(INV_ICM20602_SCAN_GYRO_X)
882
+
| BIT(INV_ICM20602_SCAN_GYRO_Y)
883
+
| BIT(INV_ICM20602_SCAN_GYRO_Z)
884
+
| BIT(INV_ICM20602_SCAN_TEMP),
885
+
/* 6-axis accel + gyro + temp (mandatory) */
886
+
BIT(INV_ICM20602_SCAN_ACCL_X)
887
+
| BIT(INV_ICM20602_SCAN_ACCL_Y)
888
+
| BIT(INV_ICM20602_SCAN_ACCL_Z)
889
+
| BIT(INV_ICM20602_SCAN_GYRO_X)
890
+
| BIT(INV_ICM20602_SCAN_GYRO_Y)
891
+
| BIT(INV_ICM20602_SCAN_GYRO_Z)
892
+
| BIT(INV_ICM20602_SCAN_TEMP),
893
+
0,
891
894
};
892
895
893
896
/*
···
1171
1130
if (chip_type == INV_ICM20602) {
1172
1131
indio_dev->channels = inv_icm20602_channels;
1173
1132
indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels);
1133
+
indio_dev->available_scan_masks = inv_icm20602_scan_masks;
1174
1134
} else {
1175
1135
indio_dev->channels = inv_mpu_channels;
1176
1136
indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1137
+
indio_dev->available_scan_masks = inv_mpu_scan_masks;
1177
1138
}
1178
1139
1179
1140
indio_dev->info = &mpu_info;
+3
drivers/staging/android/ion/ion_page_pool.c
+3
drivers/staging/android/ion/ion_page_pool.c
···
8
8
#include <linux/list.h>
9
9
#include <linux/slab.h>
10
10
#include <linux/swap.h>
11
+
#include <linux/sched/signal.h>
11
12
12
13
#include "ion.h"
13
14
14
15
static inline struct page *ion_page_pool_alloc_pages(struct ion_page_pool *pool)
15
16
{
17
+
if (fatal_signal_pending(current))
18
+
return NULL;
16
19
return alloc_pages(pool->gfp_mask, pool->order);
17
20
}
18
21
+1
-1
drivers/staging/fbtft/fb_bd663474.c
+1
-1
drivers/staging/fbtft/fb_bd663474.c
+1
-1
drivers/staging/fbtft/fb_ili9163.c
+1
-1
drivers/staging/fbtft/fb_ili9163.c
+1
-1
drivers/staging/fbtft/fb_ili9325.c
+1
-1
drivers/staging/fbtft/fb_ili9325.c
+1
-1
drivers/staging/fbtft/fb_s6d1121.c
+1
-1
drivers/staging/fbtft/fb_s6d1121.c
+1
-1
drivers/staging/fbtft/fb_ssd1289.c
+1
-1
drivers/staging/fbtft/fb_ssd1289.c
+2
-2
drivers/staging/fbtft/fb_ssd1331.c
+2
-2
drivers/staging/fbtft/fb_ssd1331.c
···
81
81
va_start(args, len);
82
82
83
83
*buf = (u8)va_arg(args, unsigned int);
84
-
if (!par->gpio.dc)
84
+
if (par->gpio.dc)
85
85
gpiod_set_value(par->gpio.dc, 0);
86
86
ret = par->fbtftops.write(par, par->buf, sizeof(u8));
87
87
if (ret < 0) {
···
104
104
return;
105
105
}
106
106
}
107
-
if (!par->gpio.dc)
107
+
if (par->gpio.dc)
108
108
gpiod_set_value(par->gpio.dc, 1);
109
109
va_end(args);
110
110
}
+1
-1
drivers/staging/fbtft/fb_upd161704.c
+1
-1
drivers/staging/fbtft/fb_upd161704.c
+1
-1
drivers/staging/fbtft/fbtft-bus.c
+1
-1
drivers/staging/fbtft/fbtft-bus.c
+22
-25
drivers/staging/fbtft/fbtft-core.c
+22
-25
drivers/staging/fbtft/fbtft-core.c
···
76
76
struct gpio_desc **gpiop)
77
77
{
78
78
struct device *dev = par->info->device;
79
-
struct device_node *node = dev->of_node;
80
79
int ret = 0;
81
80
82
-
if (of_find_property(node, name, NULL)) {
83
-
*gpiop = devm_gpiod_get_index(dev, dev->driver->name, index,
84
-
GPIOD_OUT_HIGH);
85
-
if (IS_ERR(*gpiop)) {
86
-
ret = PTR_ERR(*gpiop);
87
-
dev_err(dev,
88
-
"Failed to request %s GPIO:%d\n", name, ret);
89
-
return ret;
90
-
}
91
-
fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par, "%s: '%s' GPIO\n",
92
-
__func__, name);
81
+
*gpiop = devm_gpiod_get_index_optional(dev, name, index,
82
+
GPIOD_OUT_HIGH);
83
+
if (IS_ERR(*gpiop)) {
84
+
ret = PTR_ERR(*gpiop);
85
+
dev_err(dev,
86
+
"Failed to request %s GPIO: %d\n", name, ret);
87
+
return ret;
93
88
}
89
+
fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par, "%s: '%s' GPIO\n",
90
+
__func__, name);
94
91
95
92
return ret;
96
93
}
···
100
103
if (!par->info->device->of_node)
101
104
return -EINVAL;
102
105
103
-
ret = fbtft_request_one_gpio(par, "reset-gpios", 0, &par->gpio.reset);
106
+
ret = fbtft_request_one_gpio(par, "reset", 0, &par->gpio.reset);
104
107
if (ret)
105
108
return ret;
106
-
ret = fbtft_request_one_gpio(par, "dc-gpios", 0, &par->gpio.dc);
109
+
ret = fbtft_request_one_gpio(par, "dc", 0, &par->gpio.dc);
107
110
if (ret)
108
111
return ret;
109
-
ret = fbtft_request_one_gpio(par, "rd-gpios", 0, &par->gpio.rd);
112
+
ret = fbtft_request_one_gpio(par, "rd", 0, &par->gpio.rd);
110
113
if (ret)
111
114
return ret;
112
-
ret = fbtft_request_one_gpio(par, "wr-gpios", 0, &par->gpio.wr);
115
+
ret = fbtft_request_one_gpio(par, "wr", 0, &par->gpio.wr);
113
116
if (ret)
114
117
return ret;
115
-
ret = fbtft_request_one_gpio(par, "cs-gpios", 0, &par->gpio.cs);
118
+
ret = fbtft_request_one_gpio(par, "cs", 0, &par->gpio.cs);
116
119
if (ret)
117
120
return ret;
118
-
ret = fbtft_request_one_gpio(par, "latch-gpios", 0, &par->gpio.latch);
121
+
ret = fbtft_request_one_gpio(par, "latch", 0, &par->gpio.latch);
119
122
if (ret)
120
123
return ret;
121
124
for (i = 0; i < 16; i++) {
122
-
ret = fbtft_request_one_gpio(par, "db-gpios", i,
125
+
ret = fbtft_request_one_gpio(par, "db", i,
123
126
&par->gpio.db[i]);
124
127
if (ret)
125
128
return ret;
126
-
ret = fbtft_request_one_gpio(par, "led-gpios", i,
129
+
ret = fbtft_request_one_gpio(par, "led", i,
127
130
&par->gpio.led[i]);
128
131
if (ret)
129
132
return ret;
130
-
ret = fbtft_request_one_gpio(par, "aux-gpios", i,
133
+
ret = fbtft_request_one_gpio(par, "aux", i,
131
134
&par->gpio.aux[i]);
132
135
if (ret)
133
136
return ret;
···
231
234
if (!par->gpio.reset)
232
235
return;
233
236
fbtft_par_dbg(DEBUG_RESET, par, "%s()\n", __func__);
234
-
gpiod_set_value_cansleep(par->gpio.reset, 0);
235
-
usleep_range(20, 40);
236
237
gpiod_set_value_cansleep(par->gpio.reset, 1);
238
+
usleep_range(20, 40);
239
+
gpiod_set_value_cansleep(par->gpio.reset, 0);
237
240
msleep(120);
238
241
}
239
242
···
918
921
return -EINVAL;
919
922
920
923
par->fbtftops.reset(par);
921
-
if (!par->gpio.cs)
924
+
if (par->gpio.cs)
922
925
gpiod_set_value(par->gpio.cs, 0); /* Activate chip */
923
926
924
927
while (p) {
···
1009
1012
}
1010
1013
1011
1014
par->fbtftops.reset(par);
1012
-
if (!par->gpio.cs)
1015
+
if (par->gpio.cs)
1013
1016
gpiod_set_value(par->gpio.cs, 0); /* Activate chip */
1014
1017
1015
1018
i = 0;
+1
-1
drivers/staging/gasket/apex_driver.c
+1
-1
drivers/staging/gasket/apex_driver.c
+2
-1
drivers/staging/unisys/visornic/visornic_main.c
+2
-1
drivers/staging/unisys/visornic/visornic_main.c
···
1750
1750
}
1751
1751
1752
1752
/* poll_for_irq - checks the status of the response queue
1753
-
* @v: Void pointer to the visronic devdata struct.
1753
+
* @t: pointer to the 'struct timer_list' from which we can retrieve the
1754
+
* the visornic devdata struct.
1754
1755
*
1755
1756
* Main function of the vnic_incoming thread. Periodically check the response
1756
1757
* queue and drain it if needed.