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drm/msm/adreno: Support AQE engine

AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides
in Raytracing related workloads. Add support for loading the AQE firmware
and initialize the necessary registers.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689020/
Message-ID: <20251118-kaana-gpu-support-v4-15-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark 16201a1e 288a9320

+28
+22
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 1118 1118 } 1119 1119 } 1120 1120 1121 + if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) { 1122 + a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu, 1123 + adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova); 1124 + 1125 + if (IS_ERR(a6xx_gpu->aqe_bo)) { 1126 + int ret = PTR_ERR(a6xx_gpu->aqe_bo); 1127 + 1128 + a6xx_gpu->aqe_bo = NULL; 1129 + DRM_DEV_ERROR(&gpu->pdev->dev, 1130 + "Could not allocate AQE ucode: %d\n", ret); 1131 + 1132 + return ret; 1133 + } 1134 + 1135 + msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw"); 1136 + } 1137 + 1121 1138 /* 1122 1139 * Expanded APRIV and targets that support WHERE_AM_I both need a 1123 1140 * privileged buffer to store the RPTR shadow ··· 2415 2398 if (a6xx_gpu->sqe_bo) { 2416 2399 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm); 2417 2400 drm_gem_object_put(a6xx_gpu->sqe_bo); 2401 + } 2402 + 2403 + if (a6xx_gpu->aqe_bo) { 2404 + msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm); 2405 + drm_gem_object_put(a6xx_gpu->aqe_bo); 2418 2406 } 2419 2407 2420 2408 if (a6xx_gpu->shadow_bo) {
+2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
··· 59 59 60 60 struct drm_gem_object *sqe_bo; 61 61 uint64_t sqe_iova; 62 + struct drm_gem_object *aqe_bo; 63 + uint64_t aqe_iova; 62 64 63 65 struct msm_ringbuffer *cur_ring; 64 66 struct msm_ringbuffer *next_ring;
+3
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
··· 627 627 goto out; 628 628 629 629 gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 630 + if (a6xx_gpu->aqe_iova) 631 + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova); 632 + 630 633 /* Set the ringbuffer address */ 631 634 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 632 635 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
+1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
··· 27 27 ADRENO_FW_PFP = 1, 28 28 ADRENO_FW_GMU = 1, /* a6xx */ 29 29 ADRENO_FW_GPMU = 2, 30 + ADRENO_FW_AQE = 3, 30 31 ADRENO_FW_MAX, 31 32 }; 32 33