tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2023-06-17' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"A bunch of misc fixes across the board.

amdgpu is the usual bulk with a revert and other fixes, nouveau has a
race fix that was causing a UAF that was hard hanging systems,
otherwise some qaic, bridge and radeon.

amdgpu:
- GFX9 preemption fixes
- Add missing radeon secondary PCI ID
- vblflash fixes
- SMU 13 fix
- VCN 4.0 fix
- Re-enable TOPDOWN flag for large BAR systems to fix regression
- eDP fix
- PSR hang fix
- DPIA fix

radeon:
- fbdev client warning fix

qaic:
- leak fix
- null ptr deref fix

nouveau:
- use-after-free caused by fence race fix
- runtime pm fix
- NULL ptr checks

bridge:
- ti-sn65dsi86: Avoid possible buffer overflow"

* tag 'drm-fixes-2023-06-17' of git://anongit.freedesktop.org/drm/drm: (21 commits)
nouveau: fix client work fence deletion race
drm/amd/display: limit DPIA link rate to HBR3
drm/amd/display: fix the system hang while disable PSR
drm/amd/display: edp do not add non-edid timings
Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM in large bar system"
drm/amdgpu: vcn_4_0 set instance 0 init sched score to 1
drm/radeon: Disable outputs when releasing fbdev client
drm/amd/pm: workaround for compute workload type on some skus
drm/amd: Tighten permissions on VBIOS flashing attributes
drm/amd: Make sure image is written to trigger VBIOS image update flow
drm/amdgpu: add missing radeon secondary PCI ID
drm/amdgpu: Implement gfx9 patch functions for resubmission
drm/amdgpu: Modify indirect buffer packages for resubmission
drm/amdgpu: Program gds backup address as zero if no gds allocated
drm/nouveau: add nv_encoder pointer check for NULL
drm/amdgpu: Reset CP_VMID_PREEMPT after trailing fence signaled
drm/nouveau/dp: check for NULL nv_connector->native_mode
drm/bridge: ti-sn65dsi86: Avoid possible buffer overflow
drm/nouveau: don't detect DSM for non-NVIDIA device
accel/qaic: Fix NULL pointer deref in qaic_destroy_drm_device()
...

Linus Torvalds 1639fae5 ba00b190

+281 -27
+4
drivers/accel/qaic/qaic_drv.c
··· 97 97 98 98 cleanup_usr: 99 99 cleanup_srcu_struct(&usr->qddev_lock); 100 + ida_free(&qaic_usrs, usr->handle); 100 101 free_usr: 101 102 kfree(usr); 102 103 dev_unlock: ··· 225 224 struct qaic_user *usr; 226 225 227 226 qddev = qdev->qddev; 227 + qdev->qddev = NULL; 228 + if (!qddev) 229 + return; 228 230 229 231 /* 230 232 * Existing users get unresolvable errors till they close FDs.
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 1615 1615 0x5874, 1616 1616 0x5940, 1617 1617 0x5941, 1618 + 0x5b70, 1618 1619 0x5b72, 1619 1620 0x5b73, 1620 1621 0x5b74,
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 140 140 141 141 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 142 142 places[c].lpfn = visible_pfn; 143 - else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) 143 + else 144 144 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 145 145 146 146 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+5 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 3548 3548 void *fw_pri_cpu_addr; 3549 3549 int ret; 3550 3550 3551 + if (adev->psp.vbflash_image_size == 0) 3552 + return -EINVAL; 3553 + 3551 3554 dev_info(adev->dev, "VBIOS flash to PSP started"); 3552 3555 3553 3556 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, ··· 3602 3599 } 3603 3600 3604 3601 static const struct bin_attribute psp_vbflash_bin_attr = { 3605 - .attr = {.name = "psp_vbflash", .mode = 0664}, 3602 + .attr = {.name = "psp_vbflash", .mode = 0660}, 3606 3603 .size = 0, 3607 3604 .write = amdgpu_psp_vbflash_write, 3608 3605 .read = amdgpu_psp_vbflash_read, 3609 3606 }; 3610 3607 3611 - static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3608 + static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3612 3609 3613 3610 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3614 3611 {
+18
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
··· 581 581 if (ring->is_sw_ring) 582 582 amdgpu_sw_ring_ib_end(ring); 583 583 } 584 + 585 + void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring) 586 + { 587 + if (ring->is_sw_ring) 588 + amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL); 589 + } 590 + 591 + void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring) 592 + { 593 + if (ring->is_sw_ring) 594 + amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE); 595 + } 596 + 597 + void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring) 598 + { 599 + if (ring->is_sw_ring) 600 + amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); 601 + }
+9
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
··· 227 227 int (*preempt_ib)(struct amdgpu_ring *ring); 228 228 void (*emit_mem_sync)(struct amdgpu_ring *ring); 229 229 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 230 + void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 231 + void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 232 + void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 230 233 }; 231 234 232 235 struct amdgpu_ring { ··· 321 318 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 322 319 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 323 320 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 321 + #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 322 + #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 323 + #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 324 324 325 325 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 326 326 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 327 327 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 328 + void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 329 + void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 330 + void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 328 331 329 332 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 330 333 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
+60
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
··· 105 105 amdgpu_fence_update_start_timestamp(e->ring, 106 106 chunk->sync_seq, 107 107 ktime_get()); 108 + if (chunk->sync_seq == 109 + le32_to_cpu(*(e->ring->fence_drv.cpu_addr + 2))) { 110 + if (chunk->cntl_offset <= e->ring->buf_mask) 111 + amdgpu_ring_patch_cntl(e->ring, 112 + chunk->cntl_offset); 113 + if (chunk->ce_offset <= e->ring->buf_mask) 114 + amdgpu_ring_patch_ce(e->ring, chunk->ce_offset); 115 + if (chunk->de_offset <= e->ring->buf_mask) 116 + amdgpu_ring_patch_de(e->ring, chunk->de_offset); 117 + } 108 118 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, e->ring, 109 119 chunk->start, 110 120 chunk->end); ··· 417 407 amdgpu_ring_mux_end_ib(mux, ring); 418 408 } 419 409 410 + void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type) 411 + { 412 + struct amdgpu_device *adev = ring->adev; 413 + struct amdgpu_ring_mux *mux = &adev->gfx.muxer; 414 + unsigned offset; 415 + 416 + offset = ring->wptr & ring->buf_mask; 417 + 418 + amdgpu_ring_mux_ib_mark_offset(mux, ring, offset, type); 419 + } 420 + 420 421 void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring) 421 422 { 422 423 struct amdgpu_mux_entry *e; ··· 450 429 } 451 430 452 431 chunk->start = ring->wptr; 432 + /* the initialized value used to check if they are set by the ib submission*/ 433 + chunk->cntl_offset = ring->buf_mask + 1; 434 + chunk->de_offset = ring->buf_mask + 1; 435 + chunk->ce_offset = ring->buf_mask + 1; 453 436 list_add_tail(&chunk->entry, &e->list); 454 437 } 455 438 ··· 476 451 list_del(&chunk->entry); 477 452 kmem_cache_free(amdgpu_mux_chunk_slab, chunk); 478 453 } 454 + } 455 + } 456 + 457 + void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux, 458 + struct amdgpu_ring *ring, u64 offset, 459 + enum amdgpu_ring_mux_offset_type type) 460 + { 461 + struct amdgpu_mux_entry *e; 462 + struct amdgpu_mux_chunk *chunk; 463 + 464 + e = amdgpu_ring_mux_sw_entry(mux, ring); 465 + if (!e) { 466 + DRM_ERROR("cannot find entry!\n"); 467 + return; 468 + } 469 + 470 + chunk = list_last_entry(&e->list, struct amdgpu_mux_chunk, entry); 471 + if (!chunk) { 472 + DRM_ERROR("cannot find chunk!\n"); 473 + return; 474 + } 475 + 476 + switch (type) { 477 + case AMDGPU_MUX_OFFSET_TYPE_CONTROL: 478 + chunk->cntl_offset = offset; 479 + break; 480 + case AMDGPU_MUX_OFFSET_TYPE_DE: 481 + chunk->de_offset = offset; 482 + break; 483 + case AMDGPU_MUX_OFFSET_TYPE_CE: 484 + chunk->ce_offset = offset; 485 + break; 486 + default: 487 + DRM_ERROR("invalid type (%d)\n", type); 488 + break; 479 489 } 480 490 } 481 491
+15
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
··· 50 50 struct list_head list; 51 51 }; 52 52 53 + enum amdgpu_ring_mux_offset_type { 54 + AMDGPU_MUX_OFFSET_TYPE_CONTROL, 55 + AMDGPU_MUX_OFFSET_TYPE_DE, 56 + AMDGPU_MUX_OFFSET_TYPE_CE, 57 + }; 58 + 53 59 struct amdgpu_ring_mux { 54 60 struct amdgpu_ring *real_ring; 55 61 ··· 78 72 * @sync_seq: the fence seqno related with the saved IB. 79 73 * @start:- start location on the software ring. 80 74 * @end:- end location on the software ring. 75 + * @control_offset:- the PRE_RESUME bit position used for resubmission. 76 + * @de_offset:- the anchor in write_data for de meta of resubmission. 77 + * @ce_offset:- the anchor in write_data for ce meta of resubmission. 81 78 */ 82 79 struct amdgpu_mux_chunk { 83 80 struct list_head entry; 84 81 uint32_t sync_seq; 85 82 u64 start; 86 83 u64 end; 84 + u64 cntl_offset; 85 + u64 de_offset; 86 + u64 ce_offset; 87 87 }; 88 88 89 89 int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, ··· 101 89 u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring); 102 90 void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring); 103 91 void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring); 92 + void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, 93 + u64 offset, enum amdgpu_ring_mux_offset_type type); 104 94 bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux); 105 95 106 96 u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring); ··· 111 97 void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 112 98 void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring); 113 99 void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring); 100 + void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type); 114 101 const char *amdgpu_sw_ring_name(int idx); 115 102 unsigned int amdgpu_sw_ring_priority(int idx); 116 103
+92 -9
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 755 755 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 756 756 struct amdgpu_cu_info *cu_info); 757 757 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 758 - static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 758 + static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds); 759 759 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 760 760 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 761 761 void *ras_error_status); ··· 5127 5127 gfx_v9_0_ring_emit_de_meta(ring, 5128 5128 (!amdgpu_sriov_vf(ring->adev) && 5129 5129 flags & AMDGPU_IB_PREEMPTED) ? 5130 - true : false); 5130 + true : false, 5131 + job->gds_size > 0 && job->gds_base != 0); 5131 5132 } 5132 5133 5133 5134 amdgpu_ring_write(ring, header); ··· 5139 5138 #endif 5140 5139 lower_32_bits(ib->gpu_addr)); 5141 5140 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5141 + amdgpu_ring_ib_on_emit_cntl(ring); 5142 5142 amdgpu_ring_write(ring, control); 5143 + } 5144 + 5145 + static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring, 5146 + unsigned offset) 5147 + { 5148 + u32 control = ring->ring[offset]; 5149 + 5150 + control |= INDIRECT_BUFFER_PRE_RESUME(1); 5151 + ring->ring[offset] = control; 5152 + } 5153 + 5154 + static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring, 5155 + unsigned offset) 5156 + { 5157 + struct amdgpu_device *adev = ring->adev; 5158 + void *ce_payload_cpu_addr; 5159 + uint64_t payload_offset, payload_size; 5160 + 5161 + payload_size = sizeof(struct v9_ce_ib_state); 5162 + 5163 + if (ring->is_mes_queue) { 5164 + payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5165 + gfx[0].gfx_meta_data) + 5166 + offsetof(struct v9_gfx_meta_data, ce_payload); 5167 + ce_payload_cpu_addr = 5168 + amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset); 5169 + } else { 5170 + payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5171 + ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset; 5172 + } 5173 + 5174 + if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { 5175 + memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size); 5176 + } else { 5177 + memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, 5178 + (ring->buf_mask + 1 - offset) << 2); 5179 + payload_size -= (ring->buf_mask + 1 - offset) << 2; 5180 + memcpy((void *)&ring->ring[0], 5181 + ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), 5182 + payload_size); 5183 + } 5184 + } 5185 + 5186 + static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring, 5187 + unsigned offset) 5188 + { 5189 + struct amdgpu_device *adev = ring->adev; 5190 + void *de_payload_cpu_addr; 5191 + uint64_t payload_offset, payload_size; 5192 + 5193 + payload_size = sizeof(struct v9_de_ib_state); 5194 + 5195 + if (ring->is_mes_queue) { 5196 + payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5197 + gfx[0].gfx_meta_data) + 5198 + offsetof(struct v9_gfx_meta_data, de_payload); 5199 + de_payload_cpu_addr = 5200 + amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset); 5201 + } else { 5202 + payload_offset = offsetof(struct v9_gfx_meta_data, de_payload); 5203 + de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset; 5204 + } 5205 + 5206 + if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { 5207 + memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size); 5208 + } else { 5209 + memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, 5210 + (ring->buf_mask + 1 - offset) << 2); 5211 + payload_size -= (ring->buf_mask + 1 - offset) << 2; 5212 + memcpy((void *)&ring->ring[0], 5213 + de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), 5214 + payload_size); 5215 + } 5143 5216 } 5144 5217 5145 5218 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, ··· 5411 5336 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 5412 5337 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 5413 5338 5339 + amdgpu_ring_ib_on_emit_ce(ring); 5340 + 5414 5341 if (resume) 5415 5342 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 5416 5343 sizeof(ce_payload) >> 2); ··· 5446 5369 amdgpu_ring_alloc(ring, 13); 5447 5370 gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 5448 5371 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); 5449 - /*reset the CP_VMID_PREEMPT after trailing fence*/ 5450 - amdgpu_ring_emit_wreg(ring, 5451 - SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5452 - 0x0); 5453 5372 5454 5373 /* assert IB preemption, emit the trailing fence */ 5455 5374 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, ··· 5468 5395 DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); 5469 5396 } 5470 5397 5398 + /*reset the CP_VMID_PREEMPT after trailing fence*/ 5399 + amdgpu_ring_emit_wreg(ring, 5400 + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5401 + 0x0); 5471 5402 amdgpu_ring_commit(ring); 5472 5403 5473 5404 /* deassert preemption condition */ ··· 5479 5402 return r; 5480 5403 } 5481 5404 5482 - static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5405 + static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds) 5483 5406 { 5484 5407 struct amdgpu_device *adev = ring->adev; 5485 5408 struct v9_de_ib_state de_payload = {0}; ··· 5510 5433 PAGE_SIZE); 5511 5434 } 5512 5435 5513 - de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5514 - de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5436 + if (usegds) { 5437 + de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5438 + de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5439 + } 5515 5440 5516 5441 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5517 5442 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); ··· 5524 5445 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5525 5446 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5526 5447 5448 + amdgpu_ring_ib_on_emit_de(ring); 5527 5449 if (resume) 5528 5450 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5529 5451 sizeof(de_payload) >> 2); ··· 6935 6855 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6936 6856 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6937 6857 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6858 + .patch_cntl = gfx_v9_0_ring_patch_cntl, 6859 + .patch_de = gfx_v9_0_ring_patch_de_meta, 6860 + .patch_ce = gfx_v9_0_ring_patch_ce_meta, 6938 6861 }; 6939 6862 6940 6863 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
+5 -1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
··· 129 129 if (adev->vcn.harvest_config & (1 << i)) 130 130 continue; 131 131 132 - atomic_set(&adev->vcn.inst[i].sched_score, 0); 132 + /* Init instance 0 sched_score to 1, so it's scheduled after other instances */ 133 + if (i == 0) 134 + atomic_set(&adev->vcn.inst[i].sched_score, 1); 135 + else 136 + atomic_set(&adev->vcn.inst[i].sched_score, 0); 133 137 134 138 /* VCN UNIFIED TRAP */ 135 139 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
+13 -5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 7196 7196 drm_add_modes_noedid(connector, 1920, 1080); 7197 7197 } else { 7198 7198 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7199 - amdgpu_dm_connector_add_common_modes(encoder, connector); 7199 + /* most eDP supports only timings from its edid, 7200 + * usually only detailed timings are available 7201 + * from eDP edid. timings which are not from edid 7202 + * may damage eDP 7203 + */ 7204 + if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 7205 + amdgpu_dm_connector_add_common_modes(encoder, connector); 7200 7206 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7201 7207 } 7202 7208 amdgpu_dm_fbc_init(connector); ··· 8204 8198 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8205 8199 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8206 8200 8201 + mutex_lock(&dm->dc_lock); 8202 + if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8203 + acrtc_state->stream->link->psr_settings.psr_allow_active) 8204 + amdgpu_dm_psr_disable(acrtc_state->stream); 8205 + mutex_unlock(&dm->dc_lock); 8206 + 8207 8207 /* 8208 8208 * If FreeSync state on the stream has changed then we need to 8209 8209 * re-adjust the min/max bounds now that DC doesn't handle this ··· 8223 8211 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8224 8212 } 8225 8213 mutex_lock(&dm->dc_lock); 8226 - if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8227 - acrtc_state->stream->link->psr_settings.psr_allow_active) 8228 - amdgpu_dm_psr_disable(acrtc_state->stream); 8229 - 8230 8214 update_planes_and_stream_adapter(dm->dc, 8231 8215 acrtc_state->update_type, 8232 8216 planes_count,
+31 -2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
··· 1696 1696 } 1697 1697 } 1698 1698 1699 - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1700 - workload_type = smu_cmn_to_asic_specific_index(smu, 1699 + if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE && 1700 + (((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) || 1701 + ((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) { 1702 + ret = smu_cmn_update_table(smu, 1703 + SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1704 + WORKLOAD_PPLIB_COMPUTE_BIT, 1705 + (void *)(&activity_monitor_external), 1706 + false); 1707 + if (ret) { 1708 + dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1709 + return ret; 1710 + } 1711 + 1712 + ret = smu_cmn_update_table(smu, 1713 + SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1714 + WORKLOAD_PPLIB_CUSTOM_BIT, 1715 + (void *)(&activity_monitor_external), 1716 + true); 1717 + if (ret) { 1718 + dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1719 + return ret; 1720 + } 1721 + 1722 + workload_type = smu_cmn_to_asic_specific_index(smu, 1723 + CMN2ASIC_MAPPING_WORKLOAD, 1724 + PP_SMC_POWER_PROFILE_CUSTOM); 1725 + } else { 1726 + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1727 + workload_type = smu_cmn_to_asic_specific_index(smu, 1701 1728 CMN2ASIC_MAPPING_WORKLOAD, 1702 1729 smu->power_profile_mode); 1730 + } 1731 + 1703 1732 if (workload_type < 0) 1704 1733 return -EINVAL; 1705 1734
+4
drivers/gpu/drm/bridge/ti-sn65dsi86.c
··· 298 298 if (refclk_lut[i] == refclk_rate) 299 299 break; 300 300 301 + /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 302 + if (i >= refclk_lut_size) 303 + i = 1; 304 + 301 305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 302 306 REFCLK_FREQ(i)); 303 307
+3
drivers/gpu/drm/nouveau/nouveau_acpi.c
··· 220 220 int optimus_funcs; 221 221 struct pci_dev *parent_pdev; 222 222 223 + if (pdev->vendor != PCI_VENDOR_ID_NVIDIA) 224 + return; 225 + 223 226 *has_pr3 = false; 224 227 parent_pdev = pci_upstream_bridge(pdev); 225 228 if (parent_pdev) {
+4 -3
drivers/gpu/drm/nouveau/nouveau_connector.c
··· 730 730 #endif 731 731 732 732 nouveau_connector_set_edid(nv_connector, edid); 733 - nouveau_connector_set_encoder(connector, nv_encoder); 733 + if (nv_encoder) 734 + nouveau_connector_set_encoder(connector, nv_encoder); 734 735 return status; 735 736 } 736 737 ··· 967 966 /* Determine display colour depth for everything except LVDS now, 968 967 * DP requires this before mode_valid() is called. 969 968 */ 970 - if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 969 + if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode) 971 970 nouveau_connector_detect_depth(connector); 972 971 973 972 /* Find the native mode if this is a digital panel, if we didn't ··· 988 987 * "native" mode as some VBIOS tables require us to use the 989 988 * pixel clock as part of the lookup... 990 989 */ 991 - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 990 + if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode) 992 991 nouveau_connector_detect_depth(connector); 993 992 994 993 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
+10 -4
drivers/gpu/drm/nouveau/nouveau_drm.c
··· 137 137 static inline bool 138 138 nouveau_cli_work_ready(struct dma_fence *fence) 139 139 { 140 - if (!dma_fence_is_signaled(fence)) 141 - return false; 142 - dma_fence_put(fence); 143 - return true; 140 + bool ret = true; 141 + 142 + spin_lock_irq(fence->lock); 143 + if (!dma_fence_is_signaled_locked(fence)) 144 + ret = false; 145 + spin_unlock_irq(fence->lock); 146 + 147 + if (ret == true) 148 + dma_fence_put(fence); 149 + return ret; 144 150 } 145 151 146 152 static void
+1
drivers/gpu/drm/radeon/radeon_fbdev.c
··· 307 307 308 308 if (fb_helper->info) { 309 309 vga_switcheroo_client_fb_set(rdev->pdev, NULL); 310 + drm_helper_force_disable_all(dev); 310 311 drm_fb_helper_unregister_info(fb_helper); 311 312 } else { 312 313 drm_client_release(&fb_helper->client);