+11 -18

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

reviewed

··· 69 69 /* don't do anything if sink is not display port, i.e., 70 70 * passive dp->(dvi|hdmi) adaptor 71 71 */ 72 72 - if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73 73 - int saved_dpms = connector->dpms; 74 74 - /* Only turn off the display if it's physically disconnected */ 75 75 - if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76 76 - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77 77 - } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 78 - /* Don't try to start link training before we 79 79 - * have the dpcd */ 80 80 - if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 81 - return; 72 72 + if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 73 73 + amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 74 74 + amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 75 75 + /* Don't start link training before we have the DPCD */ 76 76 + if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 77 77 + return; 82 78 83 83 - /* set it to OFF so that drm_helper_connector_dpms() 84 84 - * won't return immediately since the current state 85 85 - * is ON at this point. 86 86 - */ 87 87 - connector->dpms = DRM_MODE_DPMS_OFF; 88 88 - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89 89 - } 90 90 - connector->dpms = saved_dpms; 79 79 + /* Turn the connector off and back on immediately, which 80 80 + * will trigger link training 81 81 + */ 82 82 + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 83 83 + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 91 84 } 92 85 } 93 86 }

-2

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

reviewed

··· 36 36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 37 37 38 38 if (robj) { 39 39 - if (robj->gem_base.import_attach) 40 40 - drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 41 39 amdgpu_mn_unregister(robj); 42 40 amdgpu_bo_unref(&robj); 43 41 }

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

reviewed

··· 352 352 u16 firmware_flags; 353 353 /* pointer to backlight encoder */ 354 354 struct amdgpu_encoder *bl_encoder; 355 355 + u8 bl_level; /* saved backlight level */ 355 356 struct amdgpu_audio audio; /* audio stuff */ 356 357 int num_crtc; /* number of crtcs */ 357 358 int num_hpd; /* number of hpd pins */

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

reviewed

··· 56 56 57 57 amdgpu_bo_kunmap(bo); 58 58 59 59 + if (bo->gem_base.import_attach) 60 60 + drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 59 61 drm_gem_object_release(&bo->gem_base); 60 62 amdgpu_bo_unref(&bo->parent); 61 63 if (!list_empty(&bo->shadow_list)) {

+2 -2

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

reviewed

··· 34 34 #include <linux/backlight.h> 35 35 #include "bif/bif_4_1_d.h" 36 36 37 37 - static u8 37 37 + u8 38 38 amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev) 39 39 { 40 40 u8 backlight_level; ··· 48 48 return backlight_level; 49 49 } 50 50 51 51 - static void 51 51 + void 52 52 amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, 53 53 u8 backlight_level) 54 54 {

+5

drivers/gpu/drm/amd/amdgpu/atombios_encoders.h

reviewed

··· 25 25 #define __ATOMBIOS_ENCODER_H__ 26 26 27 27 u8 28 28 + amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev); 29 29 + void 30 30 + amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, 31 31 + u8 backlight_level); 32 32 + u8 28 33 amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder); 29 34 void 30 35 amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,

+8

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

reviewed

··· 2921 2921 2922 2922 static int dce_v10_0_suspend(void *handle) 2923 2923 { 2924 2924 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2925 2925 + 2926 2926 + adev->mode_info.bl_level = 2927 2927 + amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2928 2928 + 2924 2929 return dce_v10_0_hw_fini(handle); 2925 2930 } 2926 2931 ··· 2933 2928 { 2934 2929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2935 2930 int ret; 2931 2931 + 2932 2932 + amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2933 2933 + adev->mode_info.bl_level); 2936 2934 2937 2935 ret = dce_v10_0_hw_init(handle); 2938 2936

+8

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

reviewed

··· 3047 3047 3048 3048 static int dce_v11_0_suspend(void *handle) 3049 3049 { 3050 3050 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3051 3051 + 3052 3052 + adev->mode_info.bl_level = 3053 3053 + amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 3054 3054 + 3050 3055 return dce_v11_0_hw_fini(handle); 3051 3056 } 3052 3057 ··· 3059 3054 { 3060 3055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3061 3056 int ret; 3057 3057 + 3058 3058 + amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 3059 3059 + adev->mode_info.bl_level); 3062 3060 3063 3061 ret = dce_v11_0_hw_init(handle); 3064 3062

+8

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

reviewed

··· 2787 2787 2788 2788 static int dce_v6_0_suspend(void *handle) 2789 2789 { 2790 2790 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2791 2791 + 2792 2792 + adev->mode_info.bl_level = 2793 2793 + amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2794 2794 + 2790 2795 return dce_v6_0_hw_fini(handle); 2791 2796 } 2792 2797 ··· 2799 2794 { 2800 2795 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2801 2796 int ret; 2797 2797 + 2798 2798 + amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2799 2799 + adev->mode_info.bl_level); 2802 2800 2803 2801 ret = dce_v6_0_hw_init(handle); 2804 2802

+8

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

reviewed

··· 2819 2819 2820 2820 static int dce_v8_0_suspend(void *handle) 2821 2821 { 2822 2822 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2823 2823 + 2824 2824 + adev->mode_info.bl_level = 2825 2825 + amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2826 2826 + 2822 2827 return dce_v8_0_hw_fini(handle); 2823 2828 } 2824 2829 ··· 2831 2826 { 2832 2827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2833 2828 int ret; 2829 2829 + 2830 2830 + amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2831 2831 + adev->mode_info.bl_level); 2834 2832 2835 2833 ret = dce_v8_0_hw_init(handle); 2836 2834

+8

drivers/gpu/drm/i915/gvt/cmd_parser.c

reviewed

··· 471 471 * used when ret from 2nd level batch buffer 472 472 */ 473 473 int saved_buf_addr_type; 474 474 + bool is_ctx_wa; 474 475 475 476 struct cmd_info *info; 476 477 ··· 1716 1715 bb->accessing = true; 1717 1716 bb->bb_start_cmd_va = s->ip_va; 1718 1717 1718 1718 + if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) 1719 1719 + bb->bb_offset = s->ip_va - s->rb_va; 1720 1720 + else 1721 1721 + bb->bb_offset = 0; 1722 1722 + 1719 1723 /* 1720 1724 * ip_va saves the virtual address of the shadow batch buffer, while 1721 1725 * ip_gma saves the graphics address of the original batch buffer. ··· 2577 2571 s.ring_tail = gma_tail; 2578 2572 s.rb_va = workload->shadow_ring_buffer_va; 2579 2573 s.workload = workload; 2574 2574 + s.is_ctx_wa = false; 2580 2575 2581 2576 if ((bypass_scan_mask & (1 << workload->ring_id)) || 2582 2577 gma_head == gma_tail) ··· 2631 2624 s.ring_tail = gma_tail; 2632 2625 s.rb_va = wa_ctx->indirect_ctx.shadow_va; 2633 2626 s.workload = workload; 2627 2627 + s.is_ctx_wa = true; 2634 2628 2635 2629 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { 2636 2630 ret = -EINVAL;

+2

drivers/gpu/drm/i915/gvt/mmio_context.c

reviewed

··· 394 394 * performace for batch mmio read/write, so we need 395 395 * handle forcewake mannually. 396 396 */ 397 397 + intel_runtime_pm_get(dev_priv); 397 398 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 398 399 switch_mmio(pre, next, ring_id); 399 400 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 401 401 + intel_runtime_pm_put(dev_priv); 400 402 } 401 403 402 404 /**

+67 -4

drivers/gpu/drm/i915/gvt/scheduler.c

reviewed

··· 52 52 pdp_pair[i].val = pdp[7 - i]; 53 53 } 54 54 55 55 + /* 56 56 + * when populating shadow ctx from guest, we should not overrride oa related 57 57 + * registers, so that they will not be overlapped by guest oa configs. Thus 58 58 + * made it possible to capture oa data from host for both host and guests. 59 59 + */ 60 60 + static void sr_oa_regs(struct intel_vgpu_workload *workload, 61 61 + u32 *reg_state, bool save) 62 62 + { 63 63 + struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; 64 64 + u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; 65 65 + u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset; 66 66 + int i = 0; 67 67 + u32 flex_mmio[] = { 68 68 + i915_mmio_reg_offset(EU_PERF_CNTL0), 69 69 + i915_mmio_reg_offset(EU_PERF_CNTL1), 70 70 + i915_mmio_reg_offset(EU_PERF_CNTL2), 71 71 + i915_mmio_reg_offset(EU_PERF_CNTL3), 72 72 + i915_mmio_reg_offset(EU_PERF_CNTL4), 73 73 + i915_mmio_reg_offset(EU_PERF_CNTL5), 74 74 + i915_mmio_reg_offset(EU_PERF_CNTL6), 75 75 + }; 76 76 + 77 77 + if (!workload || !reg_state || workload->ring_id != RCS) 78 78 + return; 79 79 + 80 80 + if (save) { 81 81 + workload->oactxctrl = reg_state[ctx_oactxctrl + 1]; 82 82 + 83 83 + for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 84 84 + u32 state_offset = ctx_flexeu0 + i * 2; 85 85 + 86 86 + workload->flex_mmio[i] = reg_state[state_offset + 1]; 87 87 + } 88 88 + } else { 89 89 + reg_state[ctx_oactxctrl] = 90 90 + i915_mmio_reg_offset(GEN8_OACTXCONTROL); 91 91 + reg_state[ctx_oactxctrl + 1] = workload->oactxctrl; 92 92 + 93 93 + for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 94 94 + u32 state_offset = ctx_flexeu0 + i * 2; 95 95 + u32 mmio = flex_mmio[i]; 96 96 + 97 97 + reg_state[state_offset] = mmio; 98 98 + reg_state[state_offset + 1] = workload->flex_mmio[i]; 99 99 + } 100 100 + } 101 101 + } 102 102 + 55 103 static int populate_shadow_context(struct intel_vgpu_workload *workload) 56 104 { 57 105 struct intel_vgpu *vgpu = workload->vgpu; ··· 146 98 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 147 99 shadow_ring_context = kmap(page); 148 100 101 101 + sr_oa_regs(workload, (u32 *)shadow_ring_context, true); 149 102 #define COPY_REG(name) \ 150 103 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 151 104 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) ··· 171 122 sizeof(*shadow_ring_context), 172 123 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 173 124 125 125 + sr_oa_regs(workload, (u32 *)shadow_ring_context, false); 174 126 kunmap(page); 175 127 return 0; 176 128 } ··· 425 375 ret = PTR_ERR(bb->vma); 426 376 goto err; 427 377 } 378 378 + 379 379 + /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va 380 380 + * is only updated into ring_scan_buffer, not real ring address 381 381 + * allocated in later copy_workload_to_ring_buffer. pls be noted 382 382 + * shadow_ring_buffer_va is now pointed to real ring buffer va 383 383 + * in copy_workload_to_ring_buffer. 384 384 + */ 385 385 + 386 386 + if (bb->bb_offset) 387 387 + bb->bb_start_cmd_va = workload->shadow_ring_buffer_va 388 388 + + bb->bb_offset; 428 389 429 390 /* relocate shadow batch buffer */ 430 391 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); ··· 1105 1044 1106 1045 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); 1107 1046 1108 1108 - s->workloads = kmem_cache_create("gvt-g_vgpu_workload", 1109 1109 - sizeof(struct intel_vgpu_workload), 0, 1110 1110 - SLAB_HWCACHE_ALIGN, 1111 1111 - NULL); 1047 1047 + s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", 1048 1048 + sizeof(struct intel_vgpu_workload), 0, 1049 1049 + SLAB_HWCACHE_ALIGN, 1050 1050 + offsetof(struct intel_vgpu_workload, rb_tail), 1051 1051 + sizeof_field(struct intel_vgpu_workload, rb_tail), 1052 1052 + NULL); 1112 1053 1113 1054 if (!s->workloads) { 1114 1055 ret = -ENOMEM;

+5

drivers/gpu/drm/i915/gvt/scheduler.h

reviewed

··· 110 110 /* shadow batch buffer */ 111 111 struct list_head shadow_bb; 112 112 struct intel_shadow_wa_ctx wa_ctx; 113 113 + 114 114 + /* oa registers */ 115 115 + u32 oactxctrl; 116 116 + u32 flex_mmio[7]; 113 117 }; 114 118 115 119 struct intel_vgpu_shadow_bb { ··· 124 120 u32 *bb_start_cmd_va; 125 121 unsigned int clflush; 126 122 bool accessing; 123 123 + unsigned long bb_offset; 127 124 }; 128 125 129 126 #define workload_q_head(vgpu, ring_id) \

+12 -4

drivers/gpu/drm/i915/i915_gem.c

reviewed

··· 434 434 dma_fence_put(shared[i]); 435 435 kfree(shared); 436 436 437 437 + /* 438 438 + * If both shared fences and an exclusive fence exist, 439 439 + * then by construction the shared fences must be later 440 440 + * than the exclusive fence. If we successfully wait for 441 441 + * all the shared fences, we know that the exclusive fence 442 442 + * must all be signaled. If all the shared fences are 443 443 + * signaled, we can prune the array and recover the 444 444 + * floating references on the fences/requests. 445 445 + */ 437 446 prune_fences = count && timeout >= 0; 438 447 } else { 439 448 excl = reservation_object_get_excl_rcu(resv); 440 449 } 441 450 442 442 - if (excl && timeout >= 0) { 451 451 + if (excl && timeout >= 0) 443 452 timeout = i915_gem_object_wait_fence(excl, flags, timeout, 444 453 rps_client); 445 445 - prune_fences = timeout >= 0; 446 446 - } 447 454 448 455 dma_fence_put(excl); 449 456 450 450 - /* Oportunistically prune the fences iff we know they have *all* been 457 457 + /* 458 458 + * Opportunistically prune the fences iff we know they have *all* been 451 459 * signaled and that the reservation object has not been changed (i.e. 452 460 * no new fences have been added). 453 461 */

+8 -2

drivers/gpu/drm/i915/i915_sysfs.c

reviewed

··· 304 304 { 305 305 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 306 306 struct intel_rps *rps = &dev_priv->gt_pm.rps; 307 307 - u32 val; 307 307 + bool boost = false; 308 308 ssize_t ret; 309 309 + u32 val; 309 310 310 311 ret = kstrtou32(buf, 0, &val); 311 312 if (ret) ··· 318 317 return -EINVAL; 319 318 320 319 mutex_lock(&dev_priv->pcu_lock); 321 321 - rps->boost_freq = val; 320 320 + if (val != rps->boost_freq) { 321 321 + rps->boost_freq = val; 322 322 + boost = atomic_read(&rps->num_waiters); 323 323 + } 322 324 mutex_unlock(&dev_priv->pcu_lock); 325 325 + if (boost) 326 326 + schedule_work(&rps->work); 323 327 324 328 return count; 325 329 }

+3 -7

drivers/gpu/drm/i915/intel_dp.c

reviewed

··· 620 620 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 621 621 { 622 622 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 623 623 + int backlight_controller = dev_priv->vbt.backlight.controller; 623 624 624 625 lockdep_assert_held(&dev_priv->pps_mutex); 625 626 626 627 /* We should never land here with regular DP ports */ 627 628 WARN_ON(!intel_dp_is_edp(intel_dp)); 628 629 629 629 - /* 630 630 - * TODO: BXT has 2 PPS instances. The correct port->PPS instance 631 631 - * mapping needs to be retrieved from VBT, for now just hard-code to 632 632 - * use instance #0 always. 633 633 - */ 634 630 if (!intel_dp->pps_reset) 635 635 - return 0; 631 631 + return backlight_controller; 636 632 637 633 intel_dp->pps_reset = false; 638 634 ··· 638 642 */ 639 643 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 640 644 641 641 - return 0; 645 645 + return backlight_controller; 642 646 } 643 647 644 648 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,

+7 -7

drivers/gpu/drm/nouveau/nouveau_backlight.c

reviewed

··· 134 134 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 135 135 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 136 136 struct nvif_object *device = &drm->client.device.object; 137 137 - int or = nv_encoder->or; 137 137 + int or = ffs(nv_encoder->dcb->or) - 1; 138 138 u32 div = 1025; 139 139 u32 val; 140 140 ··· 149 149 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 150 150 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 151 151 struct nvif_object *device = &drm->client.device.object; 152 152 - int or = nv_encoder->or; 152 152 + int or = ffs(nv_encoder->dcb->or) - 1; 153 153 u32 div = 1025; 154 154 u32 val = (bd->props.brightness * div) / 100; 155 155 ··· 170 170 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 171 171 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 172 172 struct nvif_object *device = &drm->client.device.object; 173 173 - int or = nv_encoder->or; 173 173 + int or = ffs(nv_encoder->dcb->or) - 1; 174 174 u32 div, val; 175 175 176 176 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); ··· 188 188 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 189 189 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 190 190 struct nvif_object *device = &drm->client.device.object; 191 191 - int or = nv_encoder->or; 191 191 + int or = ffs(nv_encoder->dcb->or) - 1; 192 192 u32 div, val; 193 193 194 194 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); ··· 228 228 return -ENODEV; 229 229 } 230 230 231 231 - if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or))) 231 231 + if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1))) 232 232 return 0; 233 233 234 234 if (drm->client.device.info.chipset <= 0xa0 || ··· 268 268 struct nvif_device *device = &drm->client.device; 269 269 struct drm_connector *connector; 270 270 271 271 + INIT_LIST_HEAD(&drm->bl_connectors); 272 272 + 271 273 if (apple_gmux_present()) { 272 274 NV_INFO(drm, "Apple GMUX detected: not registering Nouveau backlight interface\n"); 273 275 return 0; 274 276 } 275 275 - 276 276 - INIT_LIST_HEAD(&drm->bl_connectors); 277 277 278 278 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 279 279 if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&

+1 -1

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c

reviewed

··· 1354 1354 1355 1355 tail = this->addr + this->size; 1356 1356 if (vmm->func->page_block && next && next->page != p) 1357 1357 - tail = ALIGN_DOWN(addr, vmm->func->page_block); 1357 1357 + tail = ALIGN_DOWN(tail, vmm->func->page_block); 1358 1358 1359 1359 if (addr <= tail && tail - addr >= size) { 1360 1360 rb_erase(&this->tree, &vmm->free);

-2

drivers/gpu/drm/radeon/radeon_gem.c

reviewed

··· 34 34 struct radeon_bo *robj = gem_to_radeon_bo(gobj); 35 35 36 36 if (robj) { 37 37 - if (robj->gem_base.import_attach) 38 38 - drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 39 37 radeon_mn_unregister(robj); 40 38 radeon_bo_unref(&robj); 41 39 }

+2

drivers/gpu/drm/radeon/radeon_object.c

reviewed

··· 82 82 mutex_unlock(&bo->rdev->gem.mutex); 83 83 radeon_bo_clear_surface_reg(bo); 84 84 WARN_ON_ONCE(!list_empty(&bo->va)); 85 85 + if (bo->gem_base.import_attach) 86 86 + drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 85 87 drm_gem_object_release(&bo->gem_base); 86 88 kfree(bo); 87 89 }