Merge tag 'mtk-dts64-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

+2

Documentation/devicetree/bindings/arm/mediatek.yaml

··· 438 438 - const: mediatek,mt8365 439 439 - items: 440 440 - enum: 441 + - ezurio,mt8370-tungsten-smarc 441 442 - grinn,genio-510-sbc 442 443 - mediatek,mt8370-evk 443 444 - const: mediatek,mt8370 444 445 - const: mediatek,mt8188 445 446 - items: 446 447 - enum: 448 + - ezurio,mt8390-tungsten-smarc 447 449 - grinn,genio-700-sbc 448 450 - mediatek,mt8390-evk 449 451 - const: mediatek,mt8390

+33 -13

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml

··· 48 48 - compatible 49 49 - '#clock-cells' 50 50 51 - if: 52 - properties: 53 - compatible: 54 - contains: 55 - const: mediatek,mt8183-audiosys 56 - then: 57 - properties: 58 - audio-controller: 59 - $ref: /schemas/sound/mediatek,mt8183-audio.yaml# 60 - else: 61 - properties: 62 - audio-controller: 63 - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# 51 + allOf: 52 + - if: 53 + properties: 54 + compatible: 55 + contains: 56 + enum: 57 + - mediatek,mt2701-audsys 58 + - mediatek,mt7622-audsys 59 + then: 60 + properties: 61 + audio-controller: 62 + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# 63 + 64 + - if: 65 + properties: 66 + compatible: 67 + contains: 68 + const: mediatek,mt8183-audiosys 69 + then: 70 + properties: 71 + audio-controller: 72 + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# 73 + 74 + - if: 75 + properties: 76 + compatible: 77 + contains: 78 + const: mediatek,mt8192-audsys 79 + then: 80 + properties: 81 + audio-controller: 82 + $ref: /schemas/sound/mt8192-afe-pcm.yaml# 83 + 64 84 65 85 additionalProperties: false 66 86

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 557 557 description: Exegin Technologies Limited 558 558 "^ezchip,.*": 559 559 description: EZchip Semiconductor 560 + "^ezurio,.*": 561 + description: Ezurio LLC 560 562 "^facebook,.*": 561 563 description: Facebook 562 564 "^fairchild,.*":

+3 -3

arch/arm64/boot/dts/airoha/en7581-evb.dts

··· 47 47 reg = <0x00600000 0x03200000>; 48 48 }; 49 49 50 - tclinux_slave@3800000 { 50 + tclinux-slave@3800000 { 51 51 label = "tclinux_alt"; 52 52 reg = <0x03800000 0x03200000>; 53 53 }; 54 54 55 - rootfs_data@6a00000 { 55 + rootfs-data@6a00000 { 56 56 label = "rootfs_data"; 57 57 reg = <0x06a00000 0x01400000>; 58 58 }; 59 59 60 - reserved_bmt@7e00000 { 60 + reserved-bmt@7e00000 { 61 61 label = "reserved_bmt"; 62 62 reg = <0x07e00000 0x00200000>; 63 63 read-only;

+2

arch/arm64/boot/dts/mediatek/Makefile

··· 159 159 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb 160 160 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb 161 161 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb 162 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-tungsten-smarc.dtb 162 163 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb 163 164 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb 164 165 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb 165 166 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb 167 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb 166 168 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb 167 169 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb 168 170 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo

+1 -1

arch/arm64/boot/dts/mediatek/mt6331.dtsi

··· 217 217 }; 218 218 219 219 mt6331_vcamio_reg: ldo-vcamio { 220 - regulator-name = "vcam_io"; 220 + regulator-name = "vcamio"; 221 221 regulator-min-microvolt = <1200000>; 222 222 regulator-max-microvolt = <1800000>; 223 223 regulator-ramp-delay = <0>;

+47 -3

arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts

··· 227 227 228 228 &mmc1 { 229 229 /* MicroSD card slot */ 230 - pinctrl-names = "default"; 230 + pinctrl-names = "default", "state_uhs"; 231 231 pinctrl-0 = <&mmc1_pins_default>; 232 + pinctrl-1 = <&mmc1_pins_uhs>; 232 233 vmmc-supply = <&mt6331_vmc_reg>; 233 234 vqmmc-supply = <&mt6331_vmch_reg>; 234 235 status = "okay"; ··· 237 236 238 237 &mmc2 { 239 238 /* SDIO WiFi on MMC2 */ 240 - pinctrl-names = "default"; 239 + pinctrl-names = "default", "state_uhs"; 241 240 pinctrl-0 = <&mmc2_pins_default>; 241 + pinctrl-1 = <&mmc2_pins_uhs>; 242 242 vmmc-supply = <&mt6331_vmc_reg>; 243 243 vqmmc-supply = <&mt6331_vmch_reg>; 244 244 status = "okay"; ··· 326 324 <PINMUX_GPIO170__FUNC_MSDC1_CMD>; 327 325 input-enable; 328 326 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 327 + drive-strength = <4>; 329 328 }; 330 329 331 330 pins-clk { 332 331 pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>; 333 332 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 333 + drive-strength = <4>; 334 + }; 335 + }; 336 + 337 + mmc1_pins_uhs: microsd-uhs-pins { 338 + pins-cmd-dat { 339 + pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>, 340 + <PINMUX_GPIO172__FUNC_MSDC1_DAT1>, 341 + <PINMUX_GPIO173__FUNC_MSDC1_DAT2>, 342 + <PINMUX_GPIO174__FUNC_MSDC1_DAT3>, 343 + <PINMUX_GPIO170__FUNC_MSDC1_CMD>; 344 + input-enable; 345 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 346 + drive-strength = <6>; 347 + }; 348 + 349 + pins-clk { 350 + pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>; 351 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 352 + drive-strength = <8>; 334 353 }; 335 354 }; 336 355 ··· 364 341 <PINMUX_GPIO105__FUNC_MSDC2_CMD>; 365 342 input-enable; 366 343 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 344 + drive-strength = <4>; 367 345 }; 368 346 369 347 pins-clk { 370 348 pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>; 371 349 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 350 + drive-strength = <4>; 351 + }; 352 + }; 353 + 354 + mmc2_pins_uhs: sdio-uhs-pins { 355 + pins-cmd-dat { 356 + pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>, 357 + <PINMUX_GPIO101__FUNC_MSDC2_DAT1>, 358 + <PINMUX_GPIO102__FUNC_MSDC2_DAT2>, 359 + <PINMUX_GPIO103__FUNC_MSDC2_DAT3>, 360 + <PINMUX_GPIO105__FUNC_MSDC2_CMD>; 361 + input-enable; 362 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 363 + drive-strength = <8>; 364 + }; 365 + 366 + pins-clk { 367 + pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>; 368 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 369 + drive-strength = <8>; 372 370 }; 373 371 }; 374 372 ··· 507 463 */ 508 464 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 509 465 510 - mt6332-led { 466 + leds { 511 467 compatible = "mediatek,mt6332-led"; 512 468 #address-cells = <1>; 513 469 #size-cells = <0>;

+1 -2

arch/arm64/boot/dts/mediatek/mt6795.dtsi

··· 287 287 }; 288 288 289 289 scpsys: syscon@10006000 { 290 - compatible = "syscon", "simple-mfd"; 290 + compatible = "mediatek,mt6795-scpsys", "syscon", "simple-mfd"; 291 291 reg = <0 0x10006000 0 0x1000>; 292 - #power-domain-cells = <1>; 293 292 294 293 /* System Power Manager */ 295 294 spm: power-controller {

+127 -2

arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts

··· 12 12 model = "OpenWrt One"; 13 13 14 14 aliases { 15 + ethernet0 = &gmac1; 16 + ethernet1 = &gmac0; 15 17 serial0 = &uart0; 16 18 }; 17 19 ··· 69 67 linux,default-trigger = "netdev"; 70 68 }; 71 69 }; 70 + 71 + reg_3p3v: regulator-3p3v { 72 + compatible = "regulator-fixed"; 73 + regulator-name = "fixed-3.3V"; 74 + regulator-min-microvolt = <3300000>; 75 + regulator-max-microvolt = <3300000>; 76 + regulator-boot-on; 77 + regulator-always-on; 78 + }; 79 + 80 + reg_5v: regulator-5v { 81 + compatible = "regulator-fixed"; 82 + regulator-name = "fixed-5V"; 83 + regulator-min-microvolt = <5000000>; 84 + regulator-max-microvolt = <5000000>; 85 + regulator-boot-on; 86 + regulator-always-on; 87 + }; 88 + }; 89 + 90 + &eth { 91 + #address-cells = <1>; 92 + #size-cells = <0>; 93 + status = "okay"; 94 + 95 + /* WAN interface */ 96 + gmac0: mac@0 { 97 + compatible = "mediatek,eth-mac"; 98 + reg = <0>; 99 + nvmem-cells = <&wan_factory_mac 0>; 100 + nvmem-cell-names = "mac-address"; 101 + phy-mode = "2500base-x"; 102 + phy-handle = <&phy15>; 103 + }; 104 + 105 + /* LAN interface */ 106 + gmac1: mac@1 { 107 + compatible = "mediatek,eth-mac"; 108 + reg = <1>; 109 + phy-mode = "gmii"; 110 + phy-handle = <&int_gbe_phy>; 111 + }; 112 + }; 113 + 114 + &mdio_bus { 115 + phy15: ethernet-phy@f { 116 + compatible = "ethernet-phy-id03a2.a411"; 117 + reg = <0xf>; 118 + interrupt-parent = <&pio>; 119 + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; 120 + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; 121 + reset-assert-us = <10000>; 122 + reset-deassert-us = <20000>; 123 + airoha,pnswap-rx; 124 + 125 + leds { 126 + #address-cells = <1>; 127 + #size-cells = <0>; 128 + 129 + led@0 { 130 + reg = <0>; 131 + function = LED_FUNCTION_WAN; 132 + color = <LED_COLOR_ID_AMBER>; 133 + }; 134 + 135 + led@1 { 136 + reg = <1>; 137 + function = LED_FUNCTION_WAN; 138 + color = <LED_COLOR_ID_GREEN>; 139 + }; 140 + }; 141 + }; 142 + }; 143 + 144 + &pcie { 145 + pinctrl-names = "default"; 146 + pinctrl-0 = <&pcie_pins>; 147 + status = "okay"; 72 148 }; 73 149 74 150 &pio { 151 + pcie_pins: pcie-pins { 152 + mux { 153 + function = "pcie"; 154 + groups = "pcie_pereset"; 155 + }; 156 + }; 157 + 75 158 pwm_pins: pwm-pins { 76 159 mux { 77 160 function = "pwm"; ··· 182 95 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; 183 96 }; 184 97 }; 98 + 99 + wifi_dbdc_pins: wifi-dbdc-pins { 100 + mux { 101 + function = "eth"; 102 + groups = "wf0_mode1"; 103 + }; 104 + 105 + conf { 106 + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", 107 + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", 108 + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", 109 + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", 110 + "WF_CBA_RESETB", "WF_DIG_RESETB"; 111 + drive-strength = <4>; 112 + }; 113 + }; 185 114 }; 186 115 187 116 &pwm { ··· 215 112 compatible = "jedec,spi-nor"; 216 113 reg = <0>; 217 114 spi-max-frequency = <40000000>; 218 - #address-cells = <1>; 219 - #size-cells = <1>; 220 115 221 116 partitions { 222 117 compatible = "fixed-partitions"; ··· 261 160 }; 262 161 }; 263 162 163 + &sgmiisys0 { 164 + mediatek,pnswap; 165 + }; 166 + 264 167 &uart0 { 168 + status = "okay"; 169 + }; 170 + 171 + &usb_phy { 172 + status = "okay"; 173 + }; 174 + 175 + &wifi { 176 + nvmem-cells = <&wifi_factory_calibration>; 177 + nvmem-cell-names = "eeprom"; 178 + pinctrl-names = "dbdc"; 179 + pinctrl-0 = <&wifi_dbdc_pins>; 180 + status = "okay"; 181 + }; 182 + 183 + &xhci { 184 + phys = <&u2port0 PHY_TYPE_USB2>; 185 + vusb33-supply = <&reg_3p3v>; 186 + vbus-supply = <&reg_5v>; 187 + mediatek,u3p-dis-msk = <0x01>; 265 188 status = "okay"; 266 189 };

+218 -2

arch/arm64/boot/dts/mediatek/mt7981b.dtsi

··· 2 2 3 3 #include <dt-bindings/clock/mediatek,mt7981-clk.h> 4 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 + #include <dt-bindings/leds/common.h> 6 + #include <dt-bindings/phy/phy.h> 5 7 #include <dt-bindings/reset/mt7986-resets.h> 6 8 7 9 / { ··· 48 46 #size-cells = <2>; 49 47 ranges; 50 48 49 + wo_boot: wo-boot@15194000 { 50 + reg = <0 0x15194000 0 0x1000>; 51 + no-map; 52 + }; 53 + 54 + wo_ilm0: wo-ilm@151e0000 { 55 + reg = <0 0x151e0000 0 0x8000>; 56 + no-map; 57 + }; 58 + 59 + wo_dlm0: wo-dlm@151e8000 { 60 + reg = <0 0x151e8000 0 0x2000>; 61 + no-map; 62 + }; 63 + 51 64 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 52 65 secmon_reserved: secmon@43000000 { 53 66 reg = <0 0x43000000 0 0x30000>; 67 + no-map; 68 + }; 69 + 70 + wmcpu_emi: wmcpu-reserved@47c80000 { 71 + reg = <0 0x47c80000 0 0x100000>; 72 + no-map; 73 + }; 74 + 75 + wo_emi0: wo-emi@47d80000 { 76 + reg = <0 0x47d80000 0 0x40000>; 77 + no-map; 78 + }; 79 + 80 + wo_data: wo-data@47dc0000 { 81 + reg = <0 0x47dc0000 0 0x240000>; 54 82 no-map; 55 83 }; 56 84 }; ··· 136 104 <&infracfg CLK_INFRA_PWM3_CK>; 137 105 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 138 106 #pwm-cells = <2>; 107 + }; 108 + 109 + sgmiisys0: syscon@10060000 { 110 + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; 111 + reg = <0 0x10060000 0 0x1000>; 112 + #clock-cells = <1>; 113 + }; 114 + 115 + sgmiisys1: syscon@10070000 { 116 + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; 117 + reg = <0 0x10070000 0 0x1000>; 118 + #clock-cells = <1>; 139 119 }; 140 120 141 121 uart0: serial@11002000 { ··· 267 223 status = "disabled"; 268 224 }; 269 225 226 + xhci: usb@11200000 { 227 + compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; 228 + reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 229 + reg-names = "mac", "ippc"; 230 + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, 231 + <&infracfg CLK_INFRA_IUSB_CK>, 232 + <&infracfg CLK_INFRA_IUSB_133_CK>, 233 + <&infracfg CLK_INFRA_IUSB_66M_CK>, 234 + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; 235 + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 236 + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 237 + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 238 + status = "disabled"; 239 + }; 240 + 241 + pcie: pcie@11280000 { 242 + compatible = "mediatek,mt7981-pcie", 243 + "mediatek,mt8192-pcie"; 244 + reg = <0 0x11280000 0 0x4000>; 245 + reg-names = "pcie-mac"; 246 + ranges = <0x82000000 0 0x20000000 247 + 0x0 0x20000000 0 0x10000000>; 248 + bus-range = <0x00 0xff>; 249 + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, 250 + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, 251 + <&infracfg CLK_INFRA_IPCIER_CK>, 252 + <&infracfg CLK_INFRA_IPCIEB_CK>; 253 + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; 254 + device_type = "pci"; 255 + phys = <&u3port0 PHY_TYPE_PCIE>; 256 + phy-names = "pcie-phy"; 257 + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 258 + interrupt-map-mask = <0 0 0 7>; 259 + interrupt-map = <0 0 0 1 &pcie_intc 0>, 260 + <0 0 0 2 &pcie_intc 1>, 261 + <0 0 0 3 &pcie_intc 2>, 262 + <0 0 0 4 &pcie_intc 3>; 263 + #address-cells = <3>; 264 + #interrupt-cells = <1>; 265 + #size-cells = <2>; 266 + status = "disabled"; 267 + 268 + pcie_intc: interrupt-controller { 269 + interrupt-controller; 270 + #address-cells = <0>; 271 + #interrupt-cells = <1>; 272 + }; 273 + }; 274 + 270 275 pio: pinctrl@11d00000 { 271 276 compatible = "mediatek,mt7981-pinctrl"; 272 277 reg = <0 0x11d00000 0 0x1000>, ··· 345 252 }; 346 253 }; 347 254 255 + topmisc: topmisc@11d10000 { 256 + compatible = "mediatek,mt7981-topmisc", "syscon"; 257 + reg = <0 0x11d10000 0 0x10000>; 258 + #clock-cells = <1>; 259 + }; 260 + 261 + usb_phy: t-phy@11e10000 { 262 + compatible = "mediatek,mt7981-tphy", 263 + "mediatek,generic-tphy-v2"; 264 + ranges = <0 0 0x11e10000 0x1700>; 265 + #address-cells = <1>; 266 + #size-cells = <1>; 267 + status = "disabled"; 268 + 269 + u2port0: usb-phy@0 { 270 + reg = <0x0 0x700>; 271 + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; 272 + clock-names = "ref"; 273 + #phy-cells = <1>; 274 + }; 275 + 276 + u3port0: usb-phy@700 { 277 + reg = <0x700 0x900>; 278 + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; 279 + clock-names = "ref"; 280 + #phy-cells = <1>; 281 + mediatek,syscon-type = <&topmisc 0x218 0>; 282 + }; 283 + }; 284 + 348 285 efuse@11f20000 { 349 286 compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; 350 287 reg = <0 0x11f20000 0 0x1000>; ··· 388 265 thermal_calibration: thermal-calib@274 { 389 266 reg = <0x274 0xc>; 390 267 }; 268 + 269 + phy_calibration: phy-calib@8dc { 270 + reg = <0x8dc 0x10>; 271 + }; 391 272 }; 392 273 393 - clock-controller@15000000 { 274 + ethsys: clock-controller@15000000 { 394 275 compatible = "mediatek,mt7981-ethsys", "syscon"; 395 276 reg = <0 0x15000000 0 0x1000>; 396 277 #clock-cells = <1>; 397 278 #reset-cells = <1>; 398 279 }; 399 280 400 - wifi@18000000 { 281 + wed: wed@15010000 { 282 + compatible = "mediatek,mt7981-wed", 283 + "syscon"; 284 + reg = <0 0x15010000 0 0x1000>; 285 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 286 + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, 287 + <&wo_data>, <&wo_boot>; 288 + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 289 + "wo-data", "wo-boot"; 290 + mediatek,wo-ccif = <&wo_ccif0>; 291 + }; 292 + 293 + eth: ethernet@15100000 { 294 + compatible = "mediatek,mt7981-eth"; 295 + reg = <0 0x15100000 0 0x40000>; 296 + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 297 + <&topckgen CLK_TOP_SGM_325M_SEL>; 298 + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, 299 + <&topckgen CLK_TOP_CB_SGM_325M>; 300 + clocks = <&ethsys CLK_ETH_FE_EN>, 301 + <&ethsys CLK_ETH_GP2_EN>, 302 + <&ethsys CLK_ETH_GP1_EN>, 303 + <&ethsys CLK_ETH_WOCPU0_EN>, 304 + <&topckgen CLK_TOP_SGM_REG>, 305 + <&sgmiisys0 CLK_SGM0_TX_EN>, 306 + <&sgmiisys0 CLK_SGM0_RX_EN>, 307 + <&sgmiisys0 CLK_SGM0_CK0_EN>, 308 + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, 309 + <&sgmiisys1 CLK_SGM1_TX_EN>, 310 + <&sgmiisys1 CLK_SGM1_RX_EN>, 311 + <&sgmiisys1 CLK_SGM1_CK1_EN>, 312 + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, 313 + <&topckgen CLK_TOP_NETSYS_SEL>, 314 + <&topckgen CLK_TOP_NETSYS_500M_SEL>; 315 + clock-names = "fe", "gp2", "gp1", "wocpu0", 316 + "sgmii_ck", 317 + "sgmii_tx250m", "sgmii_rx250m", 318 + "sgmii_cdr_ref", "sgmii_cdr_fb", 319 + "sgmii2_tx250m", "sgmii2_rx250m", 320 + "sgmii2_cdr_ref", "sgmii2_cdr_fb", 321 + "netsys0", "netsys1"; 322 + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 323 + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 324 + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 325 + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 326 + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 327 + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 328 + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 329 + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 330 + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", 331 + "pdma1", "pdma2", "pdma3"; 332 + sram = <&eth_sram>; 333 + mediatek,ethsys = <&ethsys>; 334 + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 335 + mediatek,infracfg = <&topmisc>; 336 + mediatek,wed = <&wed>; 337 + status = "disabled"; 338 + 339 + mdio_bus: mdio-bus { 340 + #address-cells = <1>; 341 + #size-cells = <0>; 342 + 343 + int_gbe_phy: ethernet-phy@0 { 344 + compatible = "ethernet-phy-ieee802.3-c22"; 345 + reg = <0>; 346 + phy-mode = "gmii"; 347 + phy-is-integrated; 348 + nvmem-cells = <&phy_calibration>; 349 + nvmem-cell-names = "phy-cal-data"; 350 + }; 351 + }; 352 + }; 353 + 354 + eth_sram: sram@15140000 { 355 + compatible = "mmio-sram"; 356 + reg = <0 0x15140000 0 0x40000>; 357 + ranges = <0 0x15140000 0 0x40000>; 358 + #address-cells = <1>; 359 + #size-cells = <1>; 360 + }; 361 + 362 + wo_ccif0: syscon@151a5000 { 363 + compatible = "mediatek,mt7986-wo-ccif", "syscon"; 364 + reg = <0 0x151a5000 0 0x1000>; 365 + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 366 + }; 367 + 368 + wifi: wifi@18000000 { 401 369 compatible = "mediatek,mt7981-wmac"; 402 370 reg = <0 0x18000000 0 0x1000000>, 403 371 <0 0x10003000 0 0x1000>, ··· 500 286 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, 501 287 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 502 288 clock-names = "mcu", "ap2conn"; 289 + memory-region = <&wmcpu_emi>; 503 290 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 504 291 reset-names = "consys"; 292 + status = "disabled"; 505 293 }; 506 294 }; 507 295

+1 -1

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

··· 231 231 }; 232 232 233 233 crypto: crypto@10320000 { 234 - compatible = "inside-secure,safexcel-eip97"; 234 + compatible = "mediatek,mt7986-crypto", "inside-secure,safexcel-eip97ies"; 235 235 reg = <0 0x10320000 0 0x40000>; 236 236 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 237 237 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

+14 -14

arch/arm64/boot/dts/mediatek/mt7988a.dtsi

··· 629 629 tphy: t-phy@11c50000 { 630 630 compatible = "mediatek,mt7986-tphy", 631 631 "mediatek,generic-tphy-v2"; 632 - #address-cells = <2>; 633 - #size-cells = <2>; 634 - ranges; 632 + #address-cells = <1>; 633 + #size-cells = <1>; 634 + ranges = <0 0 0x11c50000 0x1000>; 635 635 status = "disabled"; 636 636 637 - tphyu2port0: usb-phy@11c50000 { 638 - reg = <0 0x11c50000 0 0x700>; 637 + tphyu2port0: usb-phy@0 { 638 + reg = <0 0x700>; 639 639 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; 640 640 clock-names = "ref"; 641 641 #phy-cells = <1>; 642 642 }; 643 643 644 - tphyu3port0: usb-phy@11c50700 { 645 - reg = <0 0x11c50700 0 0x900>; 644 + tphyu3port0: usb-phy@700 { 645 + reg = <0x700 0x900>; 646 646 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; 647 647 clock-names = "ref"; 648 648 #phy-cells = <1>; ··· 659 659 xsphy: xs-phy@11e10000 { 660 660 compatible = "mediatek,mt7988-xsphy", 661 661 "mediatek,xsphy"; 662 - #address-cells = <2>; 663 - #size-cells = <2>; 664 - ranges; 662 + #address-cells = <1>; 663 + #size-cells = <1>; 664 + ranges = <0 0 0x11e10000 0x3900>; 665 665 status = "disabled"; 666 666 667 - xphyu2port0: usb-phy@11e10000 { 668 - reg = <0 0x11e10000 0 0x400>; 667 + xphyu2port0: usb-phy@0 { 668 + reg = <0 0x400>; 669 669 clocks = <&infracfg CLK_INFRA_USB_UTMI>; 670 670 clock-names = "ref"; 671 671 #phy-cells = <1>; 672 672 }; 673 673 674 - xphyu3port0: usb-phy@11e13000 { 675 - reg = <0 0x11e13400 0 0x500>; 674 + xphyu3port0: usb-phy@3400 { 675 + reg = <0x3400 0x500>; 676 676 clocks = <&infracfg CLK_INFRA_USB_PIPE>; 677 677 clock-names = "ref"; 678 678 #phy-cells = <1>;

+16 -18

arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi

··· 5 5 6 6 #include "mt8173-elm.dtsi" 7 7 8 + &hdmi_mux_pins { 9 + pins-mux { 10 + pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>; 11 + bias-pull-up; 12 + output-high; 13 + }; 14 + }; 15 + 8 16 &i2c0 { 9 17 clock-frequency = <200000>; 10 18 }; ··· 75 67 }; 76 68 }; 77 69 78 - &mmc1 { 79 - wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 70 + &mmc1_pins_default { 71 + pins-wp { 72 + pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>; 73 + input-enable; 74 + bias-pull-up; 75 + }; 80 76 }; 81 77 82 - &pio { 83 - hdmi_mux_pins: hdmi_mux_pins { 84 - pins2 { 85 - pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>; 86 - bias-pull-up; 87 - output-high; 88 - }; 89 - }; 90 - 91 - mmc1_pins_default: mmc1default { 92 - pins_wp { 93 - pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>; 94 - input-enable; 95 - bias-pull-up; 96 - }; 97 - }; 78 + &mmc1 { 79 + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 98 80 }; 99 81 100 82 &touchscreen {

+80 -87

arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi

··· 206 206 207 207 &dsi0 { 208 208 status = "okay"; 209 - ports { 210 - port { 211 - dsi0_out: endpoint { 212 - remote-endpoint = <&ps8640_in>; 213 - }; 209 + port { 210 + dsi0_out: endpoint { 211 + remote-endpoint = <&ps8640_in>; 214 212 }; 215 213 }; 216 214 }; ··· 430 432 #address-cells = <1>; 431 433 #size-cells = <0>; 432 434 433 - btmrvl: btmrvl@2 { 435 + mwifiex: wifi@1 { 436 + compatible = "marvell,sd8897"; 437 + reg = <1>; 438 + interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; 439 + marvell,wakeup-pin = <3>; 440 + }; 441 + 442 + btmrvl: bluetooth@2 { 434 443 compatible = "marvell,sd8897-bt"; 435 444 reg = <2>; 436 445 interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>; 437 446 marvell,wakeup-pin = /bits/ 16 <0x0d>; 438 447 marvell,wakeup-gap-ms = /bits/ 16 <0x64>; 439 - }; 440 - 441 - mwifiex: mwifiex@1 { 442 - compatible = "marvell,sd8897"; 443 - reg = <1>; 444 - interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; 445 - marvell,wakeup-pin = <3>; 446 448 }; 447 449 }; 448 450 ··· 599 601 "SOC_I2C4_1V8_SDA_400K", 600 602 "SOC_I2C4_1V8_SCL_400K"; 601 603 602 - aud_i2s2: aud_i2s2 { 603 - pins1 { 604 + aud_i2s2: aud-i2s2-pins { 605 + pins-bus { 604 606 pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>, 605 607 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>, 606 608 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>, ··· 612 614 }; 613 615 }; 614 616 615 - bl_fixed_pins: bl_fixed_pins { 616 - pins1 { 617 + bl_fixed_pins: backlight-pins { 618 + pins-blon { 617 619 pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>; 618 620 output-low; 619 621 }; 620 622 }; 621 623 622 - bt_wake_pins: bt_wake_pins { 623 - pins1 { 624 + bt_wake_pins: bt-pins { 625 + pins-wake { 624 626 pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>; 625 627 bias-pull-up; 626 628 }; 627 629 }; 628 630 629 - disp_pwm0_pins: disp_pwm0_pins { 631 + disp_pwm0_pins: disp-pwm0-pins { 630 632 pins1 { 631 633 pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; 632 634 output-low; 633 635 }; 634 636 }; 635 637 636 - gpio_keys_pins: gpio_keys_pins { 637 - volume_pins { 638 + gpio_keys_pins: gpio-keys-pins { 639 + pins-volumeupdn { 638 640 pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>, 639 641 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>; 640 642 bias-pull-up; 641 643 }; 642 644 643 - tablet_mode_pins { 645 + pins-tabletmode { 644 646 pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>; 645 647 bias-pull-up; 646 648 }; 647 649 }; 648 650 649 - hdmi_mux_pins: hdmi_mux_pins { 650 - pins1 { 651 + hdmi_mux_pins: hdmi-pins { 652 + pins-mux { 651 653 pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>; 652 654 }; 653 655 }; 654 656 655 - i2c1_pins_a: i2c1 { 656 - da9211_pins { 657 + i2c1_pins_a: i2c1-pins { 658 + pins-da9211 { 657 659 pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; 658 660 bias-pull-up; 659 661 }; 660 662 }; 661 663 662 - mmc0_pins_default: mmc0default { 663 - pins_cmd_dat { 664 + mmc0_pins_default: mmc0-default-pins { 665 + pins-cmd-dat { 664 666 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 665 667 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 666 668 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, ··· 673 675 bias-pull-up; 674 676 }; 675 677 676 - pins_clk { 678 + pins-clk { 677 679 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 678 680 bias-pull-down; 679 681 }; 680 682 681 - pins_rst { 683 + pins-rst { 682 684 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 683 685 bias-pull-up; 684 686 }; 685 687 }; 686 688 687 - mmc1_pins_default: mmc1default { 688 - pins_cmd_dat { 689 + mmc1_pins_default: mmc1-default-pins { 690 + pins-cmd-dat { 689 691 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 690 692 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 691 693 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 692 694 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 693 695 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; 694 696 input-enable; 695 - drive-strength = <MTK_DRIVE_4mA>; 697 + drive-strength = <4>; 696 698 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 697 699 }; 698 700 699 - pins_clk { 701 + pins-clk { 700 702 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 701 703 bias-pull-down; 702 - drive-strength = <MTK_DRIVE_4mA>; 704 + drive-strength = <4>; 703 705 }; 704 706 705 - pins_insert { 707 + pins-insert { 706 708 pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>; 707 709 bias-pull-up; 708 710 }; 709 711 }; 710 712 711 - mmc3_pins_default: mmc3default { 712 - pins_dat { 713 + mmc3_pins_default: mmc3-default-pins { 714 + pins-dat { 713 715 pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, 714 716 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, 715 717 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, 716 718 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; 717 719 input-enable; 718 - drive-strength = <MTK_DRIVE_8mA>; 720 + drive-strength = <8>; 719 721 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 720 722 }; 721 723 722 - pins_cmd { 724 + pins-cmd { 723 725 pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; 724 726 input-enable; 725 - drive-strength = <MTK_DRIVE_8mA>; 727 + drive-strength = <8>; 726 728 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 727 729 }; 728 730 729 - pins_clk { 731 + pins-clk { 730 732 pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; 731 733 bias-pull-down; 732 - drive-strength = <MTK_DRIVE_8mA>; 734 + drive-strength = <8>; 733 735 }; 734 736 }; 735 737 736 - mmc0_pins_uhs: mmc0 { 737 - pins_cmd_dat { 738 + mmc0_pins_uhs: mmc0-uhs-pins { 739 + pins-cmd-dat { 738 740 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 739 741 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 740 742 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, ··· 745 747 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 746 748 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; 747 749 input-enable; 748 - drive-strength = <MTK_DRIVE_6mA>; 750 + drive-strength = <6>; 749 751 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 750 752 }; 751 753 752 - pins_clk { 754 + pins-clk { 753 755 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 754 - drive-strength = <MTK_DRIVE_6mA>; 756 + drive-strength = <6>; 755 757 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 756 758 }; 757 759 758 - pins_ds { 760 + pins-ds { 759 761 pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>; 760 762 drive-strength = <MTK_DRIVE_10mA>; 761 763 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 762 764 }; 763 765 764 - pins_rst { 766 + pins-rst { 765 767 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 766 768 bias-pull-up; 767 769 }; 768 770 }; 769 771 770 - mmc1_pins_uhs: mmc1 { 771 - pins_cmd_dat { 772 + mmc1_pins_uhs: mmc1-pins { 773 + pins-cmd-dat { 772 774 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 773 775 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 774 776 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 775 777 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 776 778 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; 777 779 input-enable; 778 - drive-strength = <MTK_DRIVE_6mA>; 780 + drive-strength = <6>; 779 781 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 780 782 }; 781 783 782 - pins_clk { 784 + pins-clk { 783 785 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 784 - drive-strength = <MTK_DRIVE_8mA>; 786 + drive-strength = <8>; 785 787 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 786 788 }; 787 789 }; 788 790 789 - mmc3_pins_uhs: mmc3 { 790 - pins_dat { 791 + mmc3_pins_uhs: mmc3-pins { 792 + pins-dat { 791 793 pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, 792 794 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, 793 795 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, 794 796 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; 795 797 input-enable; 796 - drive-strength = <MTK_DRIVE_8mA>; 798 + drive-strength = <8>; 797 799 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 798 800 }; 799 801 800 - pins_cmd { 802 + pins-cmd { 801 803 pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; 802 804 input-enable; 803 - drive-strength = <MTK_DRIVE_8mA>; 805 + drive-strength = <8>; 804 806 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 805 807 }; 806 808 807 - pins_clk { 809 + pins-clk { 808 810 pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; 809 - drive-strength = <MTK_DRIVE_8mA>; 811 + drive-strength = <8>; 810 812 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 811 813 }; 812 814 }; 813 815 814 - nor_gpio1_pins: nor { 816 + nor_gpio1_pins: nor-pins { 815 817 pins1 { 816 818 pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>, 817 819 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>, 818 820 <MT8173_PIN_8_EINT8__FUNC_SFIN>; 819 821 input-enable; 820 - drive-strength = <MTK_DRIVE_4mA>; 822 + drive-strength = <4>; 821 823 bias-pull-up; 822 824 }; 823 825 824 826 pins2 { 825 827 pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>; 826 - drive-strength = <MTK_DRIVE_4mA>; 828 + drive-strength = <4>; 827 829 bias-pull-up; 828 830 }; 829 831 830 - pins_clk { 832 + pins-clk { 831 833 pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>; 832 834 input-enable; 833 - drive-strength = <MTK_DRIVE_4mA>; 835 + drive-strength = <4>; 834 836 bias-pull-up; 835 837 }; 836 838 }; 837 839 838 - panel_backlight_en_pins: panel_backlight_en_pins { 840 + panel_backlight_en_pins: panel-backlight-en-pins { 839 841 pins1 { 840 842 pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>; 841 843 }; 842 844 }; 843 845 844 - panel_fixed_pins: panel_fixed_pins { 846 + panel_fixed_pins: panel-fixed-pins { 845 847 pins1 { 846 848 pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>; 847 849 }; 848 850 }; 849 851 850 - ps8640_pins: ps8640_pins { 852 + ps8640_pins: ps8640-pins { 851 853 pins1 { 852 854 pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>, 853 855 <MT8173_PIN_115_URTS0__FUNC_GPIO115>, ··· 855 857 }; 856 858 }; 857 859 858 - ps8640_fixed_pins: ps8640_fixed_pins { 860 + ps8640_fixed_pins: ps8640-fixed-pins { 859 861 pins1 { 860 862 pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>; 861 863 }; 862 864 }; 863 865 864 - rt5650_irq: rt5650_irq { 865 - pins1 { 866 + rt5650_irq: rt5650-pins { 867 + pins-intn { 866 868 pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>; 867 869 bias-pull-down; 868 870 }; 869 871 }; 870 872 871 - sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { 873 + sdio_fixed_3v3_pins: sdio-vreg-3v3-pins { 872 874 pins1 { 873 875 pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>; 874 876 output-low; 875 877 }; 876 878 }; 877 879 878 - spi_pins_a: spi1 { 880 + spi_pins_a: spi1-pins { 879 881 pins1 { 880 882 pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>; 881 883 bias-pull-up; 882 884 }; 883 885 884 - pins_spi { 886 + pins-spi { 885 887 pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>, 886 888 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>, 887 889 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>, ··· 890 892 }; 891 893 }; 892 894 893 - trackpad_irq: trackpad_irq { 894 - pins1 { 895 + trackpad_irq: trackpad-pins { 896 + pins-intn { 895 897 pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>; 896 898 input-enable; 897 899 bias-pull-up; 898 900 }; 899 901 }; 900 902 901 - usb_pins: usb { 903 + usb_pins: usb-pins { 902 904 pins1 { 903 905 pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>; 904 906 output-high; ··· 906 908 }; 907 909 }; 908 910 909 - wifi_wake_pins: wifi_wake_pins { 910 - pins1 { 911 + wifi_wake_pins: wifi-pins { 912 + pins-wake { 911 913 pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>; 912 914 bias-pull-up; 913 915 }; ··· 1145 1147 wakeup-source; 1146 1148 vusb33-supply = <&mt6397_vusb_reg>; 1147 1149 status = "okay"; 1148 - }; 1149 - 1150 - &thermal { 1151 - bank0-supply = <&mt6397_vpca15_reg>; 1152 - bank1-supply = <&da9211_vcpu_reg>; 1153 1150 }; 1154 1151 1155 1152 &uart0 {

+37 -31

arch/arm64/boot/dts/mediatek/mt8173-evb.dts

··· 117 117 buck: da9211@68 { 118 118 compatible = "dlg,da9211"; 119 119 reg = <0x68>; 120 + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 120 121 121 122 regulators { 122 123 da9211_vcpu_reg: BUCKA { ··· 173 172 }; 174 173 175 174 &pio { 176 - disp_pwm0_pins: disp_pwm0_pins { 175 + disp_pwm0_pins: disp-pwm0-pins { 177 176 pins1 { 178 177 pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; 179 178 output-low; 180 179 }; 181 180 }; 182 181 183 - mmc0_pins_default: mmc0default { 184 - pins_cmd_dat { 182 + i2c1_pins_a: i2c1-pins { 183 + pins-da9211 { 184 + pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; 185 + bias-pull-up; 186 + }; 187 + }; 188 + 189 + mmc0_pins_default: mmc0-default-pins { 190 + pins-cmd-dat { 185 191 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 186 192 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 187 193 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, ··· 202 194 bias-pull-up; 203 195 }; 204 196 205 - pins_clk { 197 + pins-clk { 206 198 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 207 199 bias-pull-down; 208 200 }; 209 201 210 - pins_rst { 202 + pins-rst { 211 203 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 212 204 bias-pull-up; 213 205 }; 214 206 }; 215 207 216 - mmc1_pins_default: mmc1default { 217 - pins_cmd_dat { 208 + mmc1_pins_default: mmc1-default-pins { 209 + pins-cmd-dat { 218 210 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 219 211 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 220 212 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, ··· 225 217 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 226 218 }; 227 219 228 - pins_clk { 220 + pins-clk { 229 221 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 230 222 bias-pull-down; 231 223 drive-strength = <4>; 232 224 }; 233 225 234 - pins_insert { 226 + pins-insert { 235 227 pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>; 236 228 bias-pull-up; 237 229 }; 238 230 }; 239 231 240 - mmc0_pins_uhs: mmc0 { 241 - pins_cmd_dat { 232 + mmc0_pins_uhs: mmc0-uhs-pins { 233 + pins-cmd-dat { 242 234 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 243 235 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 244 236 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, ··· 253 245 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 254 246 }; 255 247 256 - pins_clk { 248 + pins-clk { 257 249 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 258 250 drive-strength = <2>; 259 251 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 260 252 }; 261 253 262 - pins_rst { 254 + pins-rst { 263 255 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 264 256 bias-pull-up; 265 257 }; 266 258 }; 267 259 268 - mmc1_pins_uhs: mmc1 { 269 - pins_cmd_dat { 260 + spi_pins_a: spi0-pins { 261 + pins-bus { 262 + pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>, 263 + <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>, 264 + <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>, 265 + <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>; 266 + }; 267 + }; 268 + 269 + mmc1_pins_uhs: mmc1-uhs-pins { 270 + pins-cmd-dat { 270 271 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 271 272 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 272 273 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, ··· 286 269 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 287 270 }; 288 271 289 - pins_clk { 272 + pins-clk { 290 273 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 291 274 drive-strength = <4>; 292 275 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 293 276 }; 294 277 }; 295 278 296 - usb_id_pins_float: usb_iddig_pull_up { 297 - pins_iddig { 279 + usb_id_pins_float: usb-iddig-pu-pins { 280 + pins-iddig-pu { 298 281 pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>; 299 282 bias-pull-up; 300 283 }; 301 284 }; 302 285 303 - usb_id_pins_ground: usb_iddig_pull_down { 304 - pins_iddig { 286 + usb_id_pins_ground: usb-iddig-pd-pins { 287 + pins-iddig-pd { 305 288 pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>; 306 289 bias-pull-down; 307 290 }; ··· 486 469 regulator-max-microvolt = <3300000>; 487 470 regulator-enable-ramp-delay = <218>; 488 471 }; 489 - }; 490 - }; 491 - }; 492 - 493 - &pio { 494 - spi_pins_a: spi0 { 495 - pins_spi { 496 - pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>, 497 - <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>, 498 - <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>, 499 - <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>; 500 472 }; 501 473 }; 502 474 };

+14 -14

arch/arm64/boot/dts/mediatek/mt8173.dtsi

··· 391 391 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 392 392 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 393 393 394 - hdmi_pin: xxx { 394 + hdmi_pin: hdmi-hotplug-pins { 395 395 396 396 /*hdmi htplg pin*/ 397 - pins1 { 397 + pins-htplg { 398 398 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 399 399 input-enable; 400 400 bias-pull-down; 401 401 }; 402 402 }; 403 403 404 - i2c0_pins_a: i2c0 { 405 - pins1 { 404 + i2c0_pins_a: i2c0-pins { 405 + pins-bus { 406 406 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 407 407 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 408 408 bias-disable; 409 409 }; 410 410 }; 411 411 412 - i2c1_pins_a: i2c1 { 413 - pins1 { 412 + i2c1_pins_a: i2c1-pins { 413 + pins-bus { 414 414 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 415 415 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 416 416 bias-disable; 417 417 }; 418 418 }; 419 419 420 - i2c2_pins_a: i2c2 { 421 - pins1 { 420 + i2c2_pins_a: i2c2-pins { 421 + pins-bus { 422 422 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 423 423 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 424 424 bias-disable; 425 425 }; 426 426 }; 427 427 428 - i2c3_pins_a: i2c3 { 429 - pins1 { 428 + i2c3_pins_a: i2c3-pins { 429 + pins-bus { 430 430 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 431 431 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 432 432 bias-disable; 433 433 }; 434 434 }; 435 435 436 - i2c4_pins_a: i2c4 { 437 - pins1 { 436 + i2c4_pins_a: i2c4-pins { 437 + pins-bus { 438 438 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 439 439 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 440 440 bias-disable; 441 441 }; 442 442 }; 443 443 444 - i2c6_pins_a: i2c6 { 445 - pins1 { 444 + i2c6_pins_a: i2c6-pins { 445 + pins-bus { 446 446 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 447 447 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 448 448 bias-disable;

+18 -18

arch/arm64/boot/dts/mediatek/mt8183-evb.dts

··· 38 38 }; 39 39 }; 40 40 41 - thermal-sensor { 41 + thermistor { 42 42 compatible = "murata,ncp03wf104"; 43 43 pullup-uv = <1800000>; 44 44 pullup-ohm = <390000>; ··· 155 155 }; 156 156 157 157 &pio { 158 - i2c_pins_0: i2c0 { 158 + i2c_pins_0: i2c0-pins { 159 159 pins_i2c { 160 160 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 161 161 <PINMUX_GPIO83__FUNC_SCL0>; ··· 163 163 }; 164 164 }; 165 165 166 - i2c_pins_1: i2c1 { 166 + i2c_pins_1: i2c1-pins { 167 167 pins_i2c { 168 168 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 169 169 <PINMUX_GPIO84__FUNC_SCL1>; ··· 171 171 }; 172 172 }; 173 173 174 - i2c_pins_2: i2c2 { 174 + i2c_pins_2: i2c2-pins { 175 175 pins_i2c { 176 176 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 177 177 <PINMUX_GPIO104__FUNC_SDA2>; ··· 179 179 }; 180 180 }; 181 181 182 - i2c_pins_3: i2c3 { 182 + i2c_pins_3: i2c3-pins { 183 183 pins_i2c { 184 184 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 185 185 <PINMUX_GPIO51__FUNC_SDA3>; ··· 187 187 }; 188 188 }; 189 189 190 - i2c_pins_4: i2c4 { 190 + i2c_pins_4: i2c4-pins { 191 191 pins_i2c { 192 192 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 193 193 <PINMUX_GPIO106__FUNC_SDA4>; ··· 195 195 }; 196 196 }; 197 197 198 - i2c_pins_5: i2c5 { 198 + i2c_pins_5: i2c5-pins { 199 199 pins_i2c { 200 200 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 201 201 <PINMUX_GPIO49__FUNC_SDA5>; ··· 203 203 }; 204 204 }; 205 205 206 - spi_pins_0: spi0 { 206 + spi_pins_0: spi0-pins { 207 207 pins_spi { 208 208 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 209 209 <PINMUX_GPIO86__FUNC_SPI0_CSB>, ··· 213 213 }; 214 214 }; 215 215 216 - mmc0_pins_default: mmc0default { 216 + mmc0_pins_default: mmc0-default-pins { 217 217 pins_cmd_dat { 218 218 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 219 219 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, ··· 239 239 }; 240 240 }; 241 241 242 - mmc0_pins_uhs: mmc0 { 242 + mmc0_pins_uhs: mmc0-uhs-pins { 243 243 pins_cmd_dat { 244 244 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 245 245 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, ··· 274 274 }; 275 275 }; 276 276 277 - mmc1_pins_default: mmc1default { 277 + mmc1_pins_default: mmc1-default-pins { 278 278 pins_cmd_dat { 279 279 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 280 280 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, ··· 298 298 }; 299 299 }; 300 300 301 - mmc1_pins_uhs: mmc1 { 301 + mmc1_pins_uhs: mmc1-pins { 302 302 pins_cmd_dat { 303 303 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 304 304 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, ··· 318 318 }; 319 319 }; 320 320 321 - spi_pins_1: spi1 { 321 + spi_pins_1: spi1-pins { 322 322 pins_spi { 323 323 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 324 324 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, ··· 328 328 }; 329 329 }; 330 330 331 - spi_pins_2: spi2 { 331 + spi_pins_2: spi2-pins { 332 332 pins_spi { 333 333 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 334 334 <PINMUX_GPIO1__FUNC_SPI2_MO>, ··· 338 338 }; 339 339 }; 340 340 341 - spi_pins_3: spi3 { 341 + spi_pins_3: spi3-pins { 342 342 pins_spi { 343 343 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 344 344 <PINMUX_GPIO22__FUNC_SPI3_CSB>, ··· 348 348 }; 349 349 }; 350 350 351 - spi_pins_4: spi4 { 351 + spi_pins_4: spi4-pins { 352 352 pins_spi { 353 353 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 354 354 <PINMUX_GPIO18__FUNC_SPI4_CSB>, ··· 358 358 }; 359 359 }; 360 360 361 - spi_pins_5: spi5 { 361 + spi_pins_5: spi5-pins { 362 362 pins_spi { 363 363 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 364 364 <PINMUX_GPIO14__FUNC_SPI5_CSB>, ··· 368 368 }; 369 369 }; 370 370 371 - pwm_pins_1: pwm1 { 371 + pwm_pins_1: pwm1-pins { 372 372 pins_pwm { 373 373 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>; 374 374 };

+1 -1

arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts

··· 91 91 92 92 &pio { 93 93 bt_pins_wakeup: bt-pins-wakeup { 94 - piins-bt-wakeup { 94 + pins-bt-wakeup { 95 95 pinmux = <PINMUX_GPIO42__FUNC_GPIO42>; 96 96 input-enable; 97 97 };

+3 -3

arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi

··· 44 44 clock-output-names = "clk32k"; 45 45 }; 46 46 47 - it6505_pp18_reg: regulator0 { 47 + pp1800_it6505: regulator0 { 48 48 compatible = "regulator-fixed"; 49 - regulator-name = "it6505_pp18"; 50 - gpio = <&pio 178 0>; 49 + regulator-name = "pp1800_it6505"; 50 + gpios = <&pio 178 GPIO_ACTIVE_HIGH>; 51 51 enable-active-high; 52 52 vin-supply = <&pp1800_alw>; 53 53 };

+8 -8

arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts

··· 241 241 }; 242 242 243 243 &pio { 244 - i2c_pins_0: i2c0 { 244 + i2c_pins_0: i2c0-pins { 245 245 pins_i2c { 246 246 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 247 247 <PINMUX_GPIO83__FUNC_SCL0>; ··· 249 249 }; 250 250 }; 251 251 252 - i2c_pins_1: i2c1 { 252 + i2c_pins_1: i2c1-pins { 253 253 pins_i2c { 254 254 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 255 255 <PINMUX_GPIO84__FUNC_SCL1>; ··· 257 257 }; 258 258 }; 259 259 260 - i2c_pins_2: i2c2 { 260 + i2c_pins_2: i2c2-pins { 261 261 pins_i2c { 262 262 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 263 263 <PINMUX_GPIO104__FUNC_SDA2>; ··· 265 265 }; 266 266 }; 267 267 268 - i2c_pins_3: i2c3 { 268 + i2c_pins_3: i2c3-pins { 269 269 pins_i2c { 270 270 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 271 271 <PINMUX_GPIO51__FUNC_SDA3>; ··· 273 273 }; 274 274 }; 275 275 276 - i2c_pins_4: i2c4 { 276 + i2c_pins_4: i2c4-pins { 277 277 pins_i2c { 278 278 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 279 279 <PINMUX_GPIO106__FUNC_SDA4>; ··· 281 281 }; 282 282 }; 283 283 284 - i2c_pins_5: i2c5 { 284 + i2c_pins_5: i2c5-pins { 285 285 pins_i2c { 286 286 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 287 287 <PINMUX_GPIO49__FUNC_SDA5>; ··· 289 289 }; 290 290 }; 291 291 292 - i2c6_pins: i2c6 { 292 + i2c6_pins: i2c6-pins { 293 293 pins_cmd_dat { 294 294 pinmux = <PINMUX_GPIO113__FUNC_SCL6>, 295 295 <PINMUX_GPIO114__FUNC_SDA6>; ··· 297 297 }; 298 298 }; 299 299 300 - keyboard_pins: keyboard { 300 + keyboard_pins: keyboard-pins { 301 301 pins_keyboard { 302 302 pinmux = <PINMUX_GPIO91__FUNC_KPROW1>, 303 303 <PINMUX_GPIO92__FUNC_KPROW0>,

+31 -6

arch/arm64/boot/dts/mediatek/mt8183.dtsi

··· 1812 1812 #size-cells = <0>; 1813 1813 1814 1814 port@0 { 1815 + #address-cells = <1>; 1816 + #size-cells = <0>; 1815 1817 reg = <0>; 1816 - ovl_2l1_in: endpoint { 1818 + 1819 + ovl_2l1_in: endpoint@1 { 1820 + reg = <1>; 1817 1821 remote-endpoint = <&mmsys_ep_ext>; 1818 1822 }; 1819 1823 }; 1820 1824 1821 1825 port@1 { 1826 + #address-cells = <1>; 1827 + #size-cells = <0>; 1822 1828 reg = <1>; 1823 - ovl_2l1_out: endpoint { 1829 + 1830 + ovl_2l1_out: endpoint@1 { 1831 + reg = <1>; 1824 1832 remote-endpoint = <&rdma1_in>; 1825 1833 }; 1826 1834 }; ··· 1880 1872 #size-cells = <0>; 1881 1873 1882 1874 port@0 { 1875 + #address-cells = <1>; 1876 + #size-cells = <0>; 1883 1877 reg = <0>; 1884 - rdma1_in: endpoint { 1878 + 1879 + rdma1_in: endpoint@1 { 1880 + reg = <1>; 1885 1881 remote-endpoint = <&ovl_2l1_out>; 1886 1882 }; 1887 1883 }; 1888 1884 1889 1885 port@1 { 1886 + #address-cells = <1>; 1887 + #size-cells = <0>; 1890 1888 reg = <1>; 1891 - rdma1_out: endpoint { 1889 + 1890 + rdma1_out: endpoint@1 { 1891 + reg = <1>; 1892 1892 remote-endpoint = <&dpi_in>; 1893 1893 }; 1894 1894 }; ··· 2092 2076 #size-cells = <0>; 2093 2077 2094 2078 port@0 { 2079 + #address-cells = <1>; 2080 + #size-cells = <0>; 2095 2081 reg = <0>; 2096 - dpi_in: endpoint { 2082 + 2083 + dpi_in: endpoint@1 { 2084 + reg = <1>; 2097 2085 remote-endpoint = <&rdma1_out>; 2098 2086 }; 2099 2087 }; 2100 2088 2101 2089 port@1 { 2090 + #address-cells = <1>; 2091 + #size-cells = <0>; 2102 2092 reg = <1>; 2103 - dpi_out: endpoint { }; 2093 + 2094 + dpi_out: endpoint@1 { 2095 + reg = <1>; 2096 + }; 2104 2097 }; 2105 2098 }; 2106 2099 };

+13

arch/arm64/boot/dts/mediatek/mt8186-evb.dts

··· 22 22 device_type = "memory"; 23 23 reg = <0 0x40000000 0 0x80000000>; 24 24 }; 25 + 26 + vproc: regulator-vproc12 { 27 + compatible = "regulator-fixed"; 28 + regulator-name = "vproc12"; 29 + regulator-always-on; 30 + regulator-boot-on; 31 + regulator-min-microvolt = <1200000>; 32 + regulator-max-microvolt = <1200000>; 33 + }; 34 + }; 35 + 36 + &cci { 37 + proc-supply = <&vproc>; 25 38 }; 26 39 27 40 &i2c0 {

-1

arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi

··· 1166 1166 &scp_c0 { 1167 1167 pinctrl-names = "default"; 1168 1168 pinctrl-0 = <&scp_pins>; 1169 - firmware-name = "mediatek/mt8188/scp.img"; 1170 1169 memory-region = <&scp_mem_reserved>; 1171 1170 status = "okay"; 1172 1171 };

+85 -3

arch/arm64/boot/dts/mediatek/mt8188.dtsi

··· 26 26 aliases { 27 27 dp-intf0 = &dp_intf0; 28 28 dp-intf1 = &dp_intf1; 29 + dpi1 = &dpi1; 29 30 dsc0 = &dsc0; 30 31 ethdr0 = &ethdr0; 31 32 gce0 = &gce0; ··· 1801 1800 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1802 1801 reg = <0 0x11230000 0 0x10000>, 1803 1802 <0 0x11f50000 0 0x1000>; 1804 - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1803 + interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1805 1804 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1806 1805 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1807 1806 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, ··· 1814 1813 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1815 1814 reg = <0 0x11240000 0 0x1000>, 1816 1815 <0 0x11eb0000 0 0x1000>; 1817 - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1816 + interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1818 1817 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1819 1818 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1820 1819 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; ··· 1828 1827 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1829 1828 reg = <0 0x11250000 0 0x1000>, 1830 1829 <0 0x11e60000 0 0x1000>; 1831 - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1830 + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1832 1831 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1833 1832 <&infracfg_ao CLK_INFRA_AO_MSDC2>, 1834 1833 <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; ··· 2037 2036 clock-names = "ref"; 2038 2037 #phy-cells = <1>; 2039 2038 }; 2039 + }; 2040 + 2041 + hdmi_phy: hdmi-phy@11d5f000 { 2042 + compatible = "mediatek,mt8188-hdmi-phy", "mediatek,mt8195-hdmi-phy"; 2043 + reg = <0 0x11d5f000 0 0x100>; 2044 + clocks = <&infracfg_ao CLK_INFRA_AO_HDMI_26M>; 2045 + clock-names = "pll_ref"; 2046 + clock-output-names = "hdmi_txpll"; 2047 + #clock-cells = <0>; 2048 + #phy-cells = <0>; 2049 + mediatek,ibias = <0xa>; 2050 + mediatek,ibias_up = <0x1c>; 2051 + status = "disabled"; 2040 2052 }; 2041 2053 2042 2054 mipi_tx_config0: dsi-phy@11c80000 { ··· 3420 3406 mediatek,merge-fifo-en; 3421 3407 }; 3422 3408 3409 + dpi1: dpi@1c112000 { 3410 + compatible = "mediatek,mt8188-dpi", "mediatek,mt8195-dpi"; 3411 + reg = <0 0x1c112000 0 0x1000>; 3412 + clocks = <&vdosys1 CLK_VDO1_DPI1>, 3413 + <&vdosys1 CLK_VDO1_DPI1_MM>, 3414 + <&vdosys1 CLK_VDO1_DPI1_HDMI>; 3415 + clock-names = "pixel", "engine", "pll"; 3416 + interrupts = <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>; 3417 + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3418 + resets = <&vdosys1 MT8188_VDO1_RST_DPI1_MM_CK>; 3419 + status = "disabled"; 3420 + 3421 + ports { 3422 + #address-cells = <1>; 3423 + #size-cells = <0>; 3424 + 3425 + port@0 { 3426 + reg = <0>; 3427 + dpi1_in: endpoint { }; 3428 + }; 3429 + 3430 + port@1 { 3431 + reg = <1>; 3432 + dpi1_out: endpoint { }; 3433 + }; 3434 + }; 3435 + }; 3436 + 3423 3437 dp_intf1: dp-intf@1c113000 { 3424 3438 compatible = "mediatek,mt8188-dp-intf"; 3425 3439 reg = <0 0x1c113000 0 0x1000>; ··· 3571 3529 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3572 3530 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; 3573 3531 }; 3532 + 3533 + hdmi: hdmi@1c300000 { 3534 + compatible = "mediatek,mt8188-hdmi-tx"; 3535 + #sound-dai-cells = <1>; 3536 + reg = <0 0x1c300000 0 0x1000>; 3537 + clocks = <&topckgen CLK_TOP_HDMI_APB>, 3538 + <&topckgen CLK_TOP_HDCP>, 3539 + <&topckgen CLK_TOP_HDCP_24M>, 3540 + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 3541 + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; 3542 + assigned-clocks = <&topckgen CLK_TOP_HDCP>; 3543 + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; 3544 + interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; 3545 + power-domains = <&spm MT8188_POWER_DOMAIN_HDMI_TX>; 3546 + phys = <&hdmi_phy>; 3547 + phy-names = "hdmi"; 3548 + status = "disabled"; 3549 + 3550 + hdmi_ddc: i2c { 3551 + compatible = "mediatek,mt8188-hdmi-ddc", 3552 + "mediatek,mt8195-hdmi-ddc"; 3553 + clocks = <&clk26m>; 3554 + }; 3555 + 3556 + ports { 3557 + #address-cells = <1>; 3558 + #size-cells = <0>; 3559 + 3560 + port@0 { 3561 + reg = <0>; 3562 + hdmi0_in: endpoint { }; 3563 + }; 3564 + 3565 + port@1 { 3566 + reg = <1>; 3567 + hdmi0_out: endpoint { }; 3568 + }; 3569 + }; 3570 + }; 3571 + 3574 3572 3575 3573 edp_tx: edp-tx@1c500000 { 3576 3574 compatible = "mediatek,mt8188-edp-tx";

-1

arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

··· 344 344 status = "okay"; 345 345 346 346 clock-frequency = <400000>; 347 - clock-stretch-ns = <12600>; 348 347 pinctrl-names = "default"; 349 348 pinctrl-0 = <&i2c2_pins>; 350 349

+1 -1

arch/arm64/boot/dts/mediatek/mt8192.dtsi

··· 973 973 reg = <0 0x11210000 0 0x2000>; 974 974 #clock-cells = <1>; 975 975 976 - afe: mt8192-afe-pcm { 976 + afe: audio-controller { 977 977 compatible = "mediatek,mt8192-audio"; 978 978 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 979 979 resets = <&watchdog 17>;

+85

arch/arm64/boot/dts/mediatek/mt8195.dtsi

··· 26 26 aliases { 27 27 dp-intf0 = &dp_intf0; 28 28 dp-intf1 = &dp_intf1; 29 + dpi1 = &dpi1; 29 30 gce0 = &gce0; 30 31 gce1 = &gce1; 32 + hdmi0 = &hdmi; 31 33 ethdr0 = &ethdr0; 32 34 mutex0 = &mutex; 33 35 mutex1 = &mutex1; ··· 1859 1857 #clock-cells = <1>; 1860 1858 }; 1861 1859 1860 + hdmi_phy: hdmi-phy@11d5f000 { 1861 + compatible = "mediatek,mt8195-hdmi-phy"; 1862 + reg = <0 0x11d5f000 0 0x100>; 1863 + clocks = <&topckgen CLK_TOP_HDMI_XTAL>, 1864 + <&infracfg_ao CLK_INFRA_AO_HDMI_26M>, 1865 + <&apmixedsys CLK_APMIXED_HDMIPLL1>, 1866 + <&apmixedsys CLK_APMIXED_HDMIPLL2>; 1867 + clock-names = "pll_ref", "26m", "pll1", "pll2"; 1868 + clock-output-names = "hdmi_txpll"; 1869 + 1870 + #clock-cells = <0>; 1871 + #phy-cells = <0>; 1872 + mediatek,ibias = <0xa>; 1873 + mediatek,ibias_up = <0x1c>; 1874 + status = "disabled"; 1875 + }; 1876 + 1862 1877 i2c0: i2c@11e00000 { 1863 1878 compatible = "mediatek,mt8195-i2c", 1864 1879 "mediatek,mt8192-i2c"; ··· 3689 3670 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3690 3671 }; 3691 3672 3673 + dpi1: dpi@1c112000 { 3674 + compatible = "mediatek,mt8195-dpi"; 3675 + reg = <0 0x1c112000 0 0x1000>; 3676 + clocks = <&vdosys1 CLK_VDO1_DPI1>, 3677 + <&vdosys1 CLK_VDO1_DPI1_MM>, 3678 + <&vdosys1 CLK_VDO1_DPI1_HDMI>; 3679 + clock-names = "pixel", "engine", "pll"; 3680 + interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>; 3681 + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3682 + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_DPI1>; 3683 + status = "disabled"; 3684 + 3685 + ports { 3686 + #address-cells = <1>; 3687 + #size-cells = <0>; 3688 + 3689 + port@0 { 3690 + reg = <0>; 3691 + dpi1_in: endpoint { }; 3692 + }; 3693 + 3694 + port@1 { 3695 + reg = <1>; 3696 + dpi1_out: endpoint { }; 3697 + }; 3698 + }; 3699 + }; 3700 + 3692 3701 dp_intf1: dp-intf@1c113000 { 3693 3702 compatible = "mediatek,mt8195-dp-intf"; 3694 3703 reg = <0 0x1c113000 0 0x1000>; ··· 3775 3728 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3776 3729 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3777 3730 "gfx_fe1_async", "vdo_be_async"; 3731 + }; 3732 + 3733 + hdmi: hdmi-tx@1c300000 { 3734 + compatible = "mediatek,mt8195-hdmi-tx"; 3735 + #sound-dai-cells = <1>; 3736 + reg = <0 0x1c300000 0 0x1000>; 3737 + clocks = <&topckgen CLK_TOP_HDMI_APB>, 3738 + <&topckgen CLK_TOP_HDCP>, 3739 + <&topckgen CLK_TOP_HDCP_24M>, 3740 + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 3741 + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; 3742 + assigned-clocks = <&topckgen CLK_TOP_HDCP>; 3743 + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; 3744 + interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>; 3745 + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; 3746 + phys = <&hdmi_phy>; 3747 + phy-names = "hdmi"; 3748 + status = "disabled"; 3749 + 3750 + hdmitx_ddc: i2c { 3751 + compatible = "mediatek,mt8195-hdmi-ddc"; 3752 + clocks = <&clk26m>; 3753 + }; 3754 + 3755 + ports { 3756 + #address-cells = <1>; 3757 + #size-cells = <0>; 3758 + 3759 + port@0 { 3760 + reg = <0>; 3761 + hdmi0_in: endpoint { }; 3762 + }; 3763 + 3764 + port@1 { 3765 + reg = <1>; 3766 + hdmi0_out: endpoint { }; 3767 + }; 3768 + }; 3778 3769 }; 3779 3770 3780 3771 edp_tx: edp-tx@1c500000 {

+14

arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2025 Ezurio LLC 4 + * Author: Gary Bisson <bisson.gary@gmail.com> 5 + */ 6 + /dts-v1/; 7 + #include "mt8370.dtsi" 8 + #include "mt8390-tungsten-smarc.dtsi" 9 + 10 + / { 11 + model = "Ezurio Tungsten510 SMARC (MT8370)"; 12 + compatible = "ezurio,mt8370-tungsten-smarc", "mediatek,mt8370", 13 + "mediatek,mt8188"; 14 + };

+150

arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi

··· 55 55 wakeup-delay-ms = <30>; 56 56 }; 57 57 58 + connector { 59 + compatible = "hdmi-connector"; 60 + label = "hdmi"; 61 + type = "a"; 62 + ddc-i2c-bus = <&hdmi_ddc>; 63 + hdmi-pwr-supply = <&hdmi_phy>; 64 + 65 + port { 66 + hdmi_connector_in: endpoint { 67 + remote-endpoint = <&hdmi0_out>; 68 + }; 69 + }; 70 + }; 71 + 58 72 firmware { 59 73 optee { 60 74 compatible = "linaro,optee-tz"; ··· 342 328 remote-endpoint = <&dsi0_in>; 343 329 }; 344 330 331 + &dpi1 { 332 + status = "okay"; 333 + }; 334 + 335 + &dpi1_in { 336 + remote-endpoint = <&merge5_out>; 337 + }; 338 + 339 + &dpi1_out { 340 + remote-endpoint = <&hdmi0_in>; 341 + }; 342 + 345 343 &gamma0_out { 346 344 remote-endpoint = <&postmask0_in>; 347 345 }; 348 346 349 347 &gpu { 350 348 mali-supply = <&mt6359_vproc2_buck_reg>; 349 + status = "okay"; 350 + }; 351 + 352 + &ethdr0 { 353 + ports { 354 + #address-cells = <1>; 355 + #size-cells = <0>; 356 + 357 + port@0 { 358 + #address-cells = <1>; 359 + #size-cells = <0>; 360 + reg = <0>; 361 + 362 + ethdr0_in: endpoint@1 { 363 + reg = <1>; 364 + remote-endpoint = <&vdosys1_ep_ext>; 365 + }; 366 + }; 367 + 368 + port@1 { 369 + #address-cells = <1>; 370 + #size-cells = <0>; 371 + reg = <1>; 372 + 373 + ethdr0_out: endpoint@1 { 374 + reg = <1>; 375 + remote-endpoint = <&merge5_in>; 376 + }; 377 + }; 378 + }; 379 + }; 380 + 381 + &hdmi { 382 + pinctrl-names = "default"; 383 + pinctrl-0 = <&hdmi_pins>; 384 + status = "okay"; 385 + }; 386 + 387 + &hdmi0_in { 388 + remote-endpoint = <&dpi1_out>; 389 + }; 390 + 391 + &hdmi0_out { 392 + remote-endpoint = <&hdmi_connector_in>; 393 + }; 394 + 395 + &hdmi_phy { 396 + pinctrl-names = "default"; 397 + pinctrl-0 = <&hdmi_vreg_pins>; 351 398 status = "okay"; 352 399 }; 353 400 ··· 548 473 pinctrl-0 = <&i2c6_pins>; 549 474 clock-frequency = <400000>; 550 475 status = "okay"; 476 + }; 477 + 478 + &merge5 { 479 + ports { 480 + #address-cells = <1>; 481 + #size-cells = <0>; 482 + 483 + port@0 { 484 + #address-cells = <1>; 485 + #size-cells = <0>; 486 + reg = <0>; 487 + 488 + merge5_in: endpoint@1 { 489 + reg = <1>; 490 + remote-endpoint = <&ethdr0_out>; 491 + }; 492 + }; 493 + 494 + port@1 { 495 + #address-cells = <1>; 496 + #size-cells = <0>; 497 + reg = <1>; 498 + 499 + merge5_out: endpoint@1 { 500 + reg = <1>; 501 + remote-endpoint = <&dpi1_in>; 502 + }; 503 + }; 504 + }; 551 505 }; 552 506 553 507 &mfg0 { ··· 828 724 <PINMUX_GPIO132__FUNC_B_GPIO132>, 829 725 <PINMUX_GPIO133__FUNC_B_GPIO133>, 830 726 <PINMUX_GPIO134__FUNC_B_GPIO134>; 727 + }; 728 + }; 729 + 730 + hdmi_vreg_pins: hdmi-vreg-pins { 731 + pins-pwr { 732 + pinmux = <PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V>; 733 + bias-disable; 734 + }; 735 + }; 736 + 737 + hdmi_pins: hdmi-pins { 738 + pins-hotplug { 739 + pinmux = <PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG>; 740 + bias-pull-down; 741 + }; 742 + 743 + pins-cec { 744 + pinmux = <PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC>; 745 + bias-disable; 746 + }; 747 + 748 + pins-ddc { 749 + pinmux = <PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL>, 750 + <PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA>; 751 + drive-strength = <10>; 831 752 }; 832 753 }; 833 754 ··· 1344 1215 sound-dai = <&dmic_codec>; 1345 1216 }; 1346 1217 }; 1218 + 1219 + dai-link-2 { 1220 + link-name = "ETDM3_OUT_BE"; 1221 + 1222 + codec { 1223 + sound-dai = <&hdmi 0>; 1224 + }; 1225 + }; 1226 + 1347 1227 }; 1348 1228 1349 1229 &spi2 { ··· 1421 1283 type = "micro"; 1422 1284 id-gpios = <&pio 83 GPIO_ACTIVE_HIGH>; 1423 1285 vbus-supply = <&usb_p0_vbus>; 1286 + }; 1287 + }; 1288 + 1289 + &vdosys1 { 1290 + port { 1291 + #address-cells = <1>; 1292 + #size-cells = <0>; 1293 + 1294 + vdosys1_ep_ext: endpoint@1 { 1295 + reg = <1>; 1296 + remote-endpoint = <&ethdr0_in>; 1297 + }; 1424 1298 }; 1425 1299 }; 1426 1300

+22

arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2025 Ezurio LLC 4 + * Author: Gary Bisson <bisson.gary@gmail.com> 5 + */ 6 + /dts-v1/; 7 + #include "mt8188.dtsi" 8 + #include "mt8390-tungsten-smarc.dtsi" 9 + 10 + / { 11 + model = "Ezurio Tungsten700 SMARC (MT8390)"; 12 + compatible = "ezurio,mt8390-tungsten-smarc", "mediatek,mt8390", 13 + "mediatek,mt8188"; 14 + }; 15 + 16 + &cpu4 { 17 + cpu-supply = <&mt6359_vcore_buck_reg>; 18 + }; 19 + 20 + &cpu5 { 21 + cpu-supply = <&mt6359_vcore_buck_reg>; 22 + };

+1489

arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2025 Ezurio LLC 4 + * Author: Gary Bisson <bisson.gary@gmail.com> 5 + */ 6 + 7 + #include "mt6359.dtsi" 8 + #include <dt-bindings/gpio/gpio.h> 9 + #include <dt-bindings/input/input.h> 10 + #include <dt-bindings/input/linux-event-codes.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + #include <dt-bindings/net/microchip-lan78xx.h> 13 + #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 14 + #include <dt-bindings/spmi/spmi.h> 15 + #include <dt-bindings/usb/pd.h> 16 + 17 + / { 18 + aliases { 19 + dsi0 = &disp_dsi0; 20 + ethernet0 = ð 21 + i2c0 = &i2c0; 22 + i2c1 = &i2c1; 23 + i2c2 = &i2c2; 24 + i2c3 = &i2c3; 25 + i2c4 = &i2c4; 26 + i2c5 = &i2c5; 27 + i2c6 = &i2c6; 28 + mmc0 = &mmc0; 29 + mmc1 = &mmc1; 30 + mmc2 = &mmc2; 31 + rtc0 = &rv3028; 32 + rtc1 = &mt6359rtc; 33 + serial0 = &uart0; 34 + }; 35 + 36 + backlight_lcd0: backlight-lcd0 { 37 + compatible = "pwm-backlight"; 38 + brightness-levels = <0 1023>; 39 + default-brightness-level = <768>; 40 + num-interpolated-steps = <1023>; 41 + enable-gpios = <&pio 30 GPIO_ACTIVE_HIGH>; 42 + pwms = <&disp_pwm0 0 30000>; 43 + }; 44 + 45 + chosen { 46 + stdout-path = "serial0:115200n8"; 47 + }; 48 + 49 + firmware { 50 + optee { 51 + compatible = "linaro,optee-tz"; 52 + method = "smc"; 53 + }; 54 + }; 55 + 56 + memory@40000000 { 57 + device_type = "memory"; 58 + reg = <0 0x40000000 0x1 0x00000000>; 59 + }; 60 + 61 + panel-dsi0 { 62 + compatible = "tianma,tm070jdhg30"; 63 + backlight = <&backlight_lcd0>; 64 + power-supply = <&reg_5v>; 65 + 66 + port { 67 + dsi0_panel_in: endpoint { 68 + remote-endpoint = <&sn65dsi84_bridge_out>; 69 + }; 70 + }; 71 + }; 72 + 73 + reserved-memory { 74 + #address-cells = <2>; 75 + #size-cells = <2>; 76 + ranges; 77 + 78 + /* 79 + * 12 MiB reserved for OP-TEE (BL32) 80 + * +-----------------------+ 0x43e0_0000 81 + * | SHMEM 2MiB | 82 + * +-----------------------+ 0x43c0_0000 83 + * | | TA_RAM 8MiB | 84 + * + TZDRAM +--------------+ 0x4340_0000 85 + * | | TEE_RAM 2MiB | 86 + * +-----------------------+ 0x4320_0000 87 + */ 88 + optee_reserved: optee@43200000 { 89 + no-map; 90 + reg = <0 0x43200000 0 0x00c00000>; 91 + }; 92 + 93 + scp_mem: memory@50000000 { 94 + compatible = "shared-dma-pool"; 95 + reg = <0 0x50000000 0 0x2900000>; 96 + no-map; 97 + }; 98 + 99 + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 100 + bl31_secmon_reserved: memory@54600000 { 101 + no-map; 102 + reg = <0 0x54600000 0x0 0x200000>; 103 + }; 104 + 105 + apu_mem: memory@55000000 { 106 + compatible = "shared-dma-pool"; 107 + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ 108 + }; 109 + 110 + vpu_mem: memory@57000000 { 111 + compatible = "shared-dma-pool"; 112 + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ 113 + }; 114 + 115 + adsp_mem: memory@60000000 { 116 + compatible = "shared-dma-pool"; 117 + reg = <0 0x60000000 0 0xf00000>; 118 + no-map; 119 + }; 120 + 121 + afe_dma_mem: memory@60f00000 { 122 + compatible = "shared-dma-pool"; 123 + reg = <0 0x60f00000 0 0x100000>; 124 + no-map; 125 + }; 126 + 127 + adsp_dma_mem: memory@61000000 { 128 + compatible = "shared-dma-pool"; 129 + reg = <0 0x61000000 0 0x100000>; 130 + no-map; 131 + }; 132 + }; 133 + 134 + regulator-efuse { 135 + compatible = "regulator-output"; 136 + vout-supply = <&mt6359_vefuse_ldo_reg>; 137 + }; 138 + 139 + reg_1v8: regulator-1v8 { 140 + compatible = "regulator-fixed"; 141 + regulator-name = "reg_1v8"; 142 + regulator-min-microvolt = <1800000>; 143 + regulator-max-microvolt = <1800000>; 144 + regulator-always-on; 145 + }; 146 + 147 + reg_3v3: regulator-3v3 { 148 + compatible = "regulator-fixed"; 149 + regulator-name = "reg_3v3"; 150 + regulator-min-microvolt = <3300000>; 151 + regulator-max-microvolt = <3300000>; 152 + regulator-always-on; 153 + }; 154 + 155 + reg_5v: regulator-5v { 156 + compatible = "regulator-fixed"; 157 + regulator-name = "reg_5v"; 158 + regulator-min-microvolt = <5000000>; 159 + regulator-max-microvolt = <5000000>; 160 + regulator-always-on; 161 + }; 162 + 163 + sdcard_en_3v3: regulator-sdcard-en { 164 + compatible = "regulator-fixed"; 165 + regulator-always-on; 166 + regulator-name = "sdcard_en_3v3"; 167 + regulator-min-microvolt = <3300000>; 168 + regulator-max-microvolt = <3300000>; 169 + gpio = <&pio 111 GPIO_ACTIVE_HIGH>; 170 + enable-active-high; 171 + }; 172 + 173 + usb_p0_vbus: regulator-usb-p0-vbus { 174 + compatible = "regulator-fixed"; 175 + regulator-name = "vbus_p0"; 176 + regulator-min-microvolt = <5000000>; 177 + regulator-max-microvolt = <5000000>; 178 + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; 179 + enable-active-high; 180 + }; 181 + 182 + usb_p1_vbus: regulator-usb-p1-vbus { 183 + compatible = "regulator-fixed"; 184 + pinctrl-names = "default"; 185 + pinctrl-0 = <&usb1_hub_pins>; 186 + regulator-name = "vbus_p1"; 187 + regulator-min-microvolt = <1800000>; 188 + regulator-max-microvolt = <1800000>; 189 + gpio = <&pio 147 GPIO_ACTIVE_HIGH>; 190 + enable-active-high; 191 + }; 192 + 193 + usb_p2_vbus: regulator-usb-p2-vbus { 194 + compatible = "regulator-fixed"; 195 + pinctrl-names = "default"; 196 + pinctrl-0 = <&usb2_eth_pins>; 197 + regulator-name = "vbus_p2"; 198 + regulator-min-microvolt = <1800000>; 199 + regulator-max-microvolt = <1800000>; 200 + gpio = <&pio 80 GPIO_ACTIVE_HIGH>; 201 + enable-active-high; 202 + }; 203 + 204 + wifi_pwrseq: wifi-pwrseq { 205 + compatible = "mmc-pwrseq-simple"; 206 + pinctrl-names = "default"; 207 + pinctrl-0 = <&wifi_pwrseq_pins>; 208 + post-power-on-delay-ms = <200>; 209 + reset-gpios = <&pio 89 GPIO_ACTIVE_LOW>; 210 + }; 211 + }; 212 + 213 + &adsp { 214 + memory-region = <&adsp_dma_mem>, <&adsp_mem>; 215 + status = "okay"; 216 + }; 217 + 218 + &afe { 219 + memory-region = <&afe_dma_mem>; 220 + status = "okay"; 221 + }; 222 + 223 + &cpu0 { 224 + cpu-supply = <&mt6359_vcore_buck_reg>; 225 + }; 226 + 227 + &cpu1 { 228 + cpu-supply = <&mt6359_vcore_buck_reg>; 229 + }; 230 + 231 + &cpu2 { 232 + cpu-supply = <&mt6359_vcore_buck_reg>; 233 + }; 234 + 235 + &cpu3 { 236 + cpu-supply = <&mt6359_vcore_buck_reg>; 237 + }; 238 + 239 + &cpu6 { 240 + cpu-supply = <&mt6315_6_vbuck1>; 241 + }; 242 + 243 + &cpu7 { 244 + cpu-supply = <&mt6315_6_vbuck1>; 245 + }; 246 + 247 + &disp_pwm0 { 248 + pinctrl-names = "default"; 249 + pinctrl-0 = <&disp_pwm0_pins>; 250 + status = "okay"; 251 + }; 252 + 253 + &disp_dsi0 { 254 + #address-cells = <1>; 255 + #size-cells = <0>; 256 + status = "okay"; 257 + 258 + ports { 259 + #address-cells = <1>; 260 + #size-cells = <0>; 261 + 262 + port@0 { 263 + reg = <0>; 264 + dsi0_in: endpoint { 265 + remote-endpoint = <&dither0_out>; 266 + }; 267 + }; 268 + 269 + port@1 { 270 + reg = <1>; 271 + dsi0_out: endpoint { 272 + remote-endpoint = <&sn65dsi84_bridge_in>; 273 + }; 274 + }; 275 + }; 276 + }; 277 + 278 + &dither0_in { 279 + remote-endpoint = <&postmask0_out>; 280 + }; 281 + 282 + &dither0_out { 283 + remote-endpoint = <&dsi0_in>; 284 + }; 285 + 286 + &eth { 287 + phy-mode ="rgmii-id"; 288 + phy-handle = <&ethernet_phy0>; 289 + pinctrl-names = "default", "sleep"; 290 + pinctrl-0 = <&eth_default_pins>; 291 + pinctrl-1 = <&eth_sleep_pins>; 292 + mediatek,mac-wol; 293 + snps,reset-gpio = <&pio 27 GPIO_ACTIVE_LOW>; 294 + snps,reset-active-low; 295 + snps,reset-delays-us = <0 11000 1000>; 296 + status = "okay"; 297 + }; 298 + 299 + &eth_mdio { 300 + ethernet_phy0: ethernet-phy@7 { 301 + compatible = "ethernet-phy-ieee802.3-c22"; 302 + reg = <0x7>; 303 + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; 304 + }; 305 + }; 306 + 307 + &gamma0_out { 308 + remote-endpoint = <&postmask0_in>; 309 + }; 310 + 311 + &gpu { 312 + mali-supply = <&mt6359_vproc2_buck_reg>; 313 + status = "okay"; 314 + }; 315 + 316 + &i2c0 { 317 + pinctrl-names = "default"; 318 + pinctrl-0 = <&i2c0_pins>; 319 + clock-frequency = <100000>; 320 + status = "okay"; 321 + 322 + i2c-mux@73 { 323 + compatible = "nxp,pca9546"; 324 + reg = <0x73>; 325 + pinctrl-names = "default"; 326 + pinctrl-0 = <&i2c0_mux_pins>; 327 + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; 328 + #address-cells = <1>; 329 + #size-cells = <0>; 330 + 331 + i2c_mux_gp_0: i2c@0 { 332 + reg = <0>; 333 + clock-frequency = <100000>; 334 + #address-cells = <1>; 335 + #size-cells = <0>; 336 + }; 337 + 338 + i2c_mux_gp_1: i2c@1 { 339 + reg = <1>; 340 + clock-frequency = <100000>; 341 + #address-cells = <1>; 342 + #size-cells = <0>; 343 + }; 344 + 345 + i2c_mux_gp_2: i2c@2 { 346 + reg = <2>; 347 + clock-frequency = <100000>; 348 + #address-cells = <1>; 349 + #size-cells = <0>; 350 + }; 351 + 352 + i2c_mux_gp_3: i2c@3 { 353 + reg = <3>; 354 + clock-frequency = <100000>; 355 + #address-cells = <1>; 356 + #size-cells = <0>; 357 + }; 358 + }; 359 + }; 360 + 361 + &i2c1 { 362 + pinctrl-names = "default"; 363 + pinctrl-0 = <&i2c1_pins>; 364 + clock-frequency = <400000>; 365 + status = "okay"; 366 + }; 367 + 368 + &i2c2 { 369 + pinctrl-names = "default"; 370 + pinctrl-0 = <&i2c2_pins>; 371 + clock-frequency = <400000>; 372 + status = "okay"; 373 + 374 + i2c-mux@73 { 375 + compatible = "nxp,pca9546"; 376 + reg = <0x73>; 377 + pinctrl-names = "default"; 378 + pinctrl-0 = <&i2c_mux_smarc_lcd_pins>; 379 + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; 380 + #address-cells = <1>; 381 + #size-cells = <0>; 382 + 383 + i2c_mux_lcd_0: i2c@0 { 384 + reg = <0>; 385 + clock-frequency = <100000>; 386 + #address-cells = <1>; 387 + #size-cells = <0>; 388 + }; 389 + 390 + i2c_mux_lcd_1: i2c@1 { 391 + reg = <1>; 392 + clock-frequency = <100000>; 393 + #address-cells = <1>; 394 + #size-cells = <0>; 395 + }; 396 + 397 + i2c_mux_lcd_2: i2c@2 { 398 + reg = <2>; 399 + clock-frequency = <100000>; 400 + #address-cells = <1>; 401 + #size-cells = <0>; 402 + }; 403 + 404 + i2c_mux_lcd_3: i2c@3 { 405 + reg = <3>; 406 + clock-frequency = <100000>; 407 + #address-cells = <1>; 408 + #size-cells = <0>; 409 + }; 410 + }; 411 + }; 412 + 413 + &i2c3 { 414 + pinctrl-names = "default"; 415 + pinctrl-0 = <&i2c3_pins>; 416 + clock-frequency = <400000>; 417 + status = "okay"; 418 + }; 419 + 420 + &i2c4 { 421 + pinctrl-names = "default"; 422 + pinctrl-0 = <&i2c4_pins>; 423 + clock-frequency = <400000>; 424 + status = "okay"; 425 + }; 426 + 427 + &i2c_mux_gp_0 { 428 + rv3028: rtc@52 { 429 + compatible = "microcrystal,rv3028"; 430 + reg = <0x52>; 431 + interrupts-extended = <&pio 42 IRQ_TYPE_LEVEL_LOW>; 432 + pinctrl-names = "default"; 433 + pinctrl-0 = <&rv3028_pins>; 434 + #clock-cells = <0>; 435 + wakeup-source; 436 + }; 437 + }; 438 + 439 + &i2c_mux_gp_1 { 440 + usb-typec@60 { 441 + compatible = "ti,hd3ss3220"; 442 + reg = <0x60>; 443 + interrupts-extended = <&pio 45 IRQ_TYPE_LEVEL_LOW>; 444 + pinctrl-names = "default"; 445 + pinctrl-0 = <&hd3ss3220_pins>; 446 + 447 + ports { 448 + #address-cells = <1>; 449 + #size-cells = <0>; 450 + 451 + port@0 { 452 + reg = <0>; 453 + hd3ss3220_in_ep: endpoint { 454 + remote-endpoint = <&ss_ep>; 455 + }; 456 + }; 457 + 458 + port@1 { 459 + reg = <1>; 460 + hd3ss3220_out_ep: endpoint { 461 + remote-endpoint = <&usb_role_switch>; 462 + }; 463 + }; 464 + }; 465 + }; 466 + }; 467 + 468 + &i2c_mux_gp_2 { 469 + codec@1a { 470 + compatible = "wlf,wm8962"; 471 + reg = <0x1a>; 472 + clocks = <&topckgen CLK_TOP_I2SO1>; 473 + AVDD-supply = <&reg_1v8>; 474 + CPVDD-supply = <&reg_1v8>; 475 + DBVDD-supply = <&reg_3v3>; 476 + DCVDD-supply = <&reg_1v8>; 477 + MICVDD-supply = <&reg_3v3>; 478 + PLLVDD-supply = <&reg_1v8>; 479 + SPKVDD1-supply = <&reg_5v>; 480 + SPKVDD2-supply = <&reg_5v>; 481 + gpio-cfg = < 482 + 0x0000 /* n/c */ 483 + 0x0000 /* gpio2: */ 484 + 0x0000 /* gpio3: */ 485 + 0x0000 /* n/c */ 486 + 0x8081 /* gpio5:HP detect */ 487 + 0x8095 /* gpio6:Mic detect */ 488 + >; 489 + }; 490 + }; 491 + 492 + &i2c_mux_lcd_2 { 493 + bridge@2c { 494 + compatible = "ti,sn65dsi84"; 495 + reg = <0x2c>; 496 + pinctrl-names = "default"; 497 + pinctrl-0 = <&dsi0_sn65dsi84_pins>; 498 + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; 499 + 500 + ports { 501 + #address-cells = <1>; 502 + #size-cells = <0>; 503 + 504 + port@0 { 505 + reg = <0>; 506 + 507 + sn65dsi84_bridge_in: endpoint { 508 + remote-endpoint = <&dsi0_out>; 509 + data-lanes = <1 2 3 4>; 510 + }; 511 + }; 512 + 513 + port@2 { 514 + reg = <2>; 515 + 516 + sn65dsi84_bridge_out: endpoint { 517 + remote-endpoint = <&dsi0_panel_in>; 518 + }; 519 + }; 520 + }; 521 + }; 522 + 523 + touchscren@5d { 524 + compatible = "goodix,gt911"; 525 + reg = <0x5d>; 526 + pinctrl-names = "default"; 527 + pinctrl-0 = <&ts_dsi0_goodix_pins>; 528 + interrupts-extended = <&pio 146 IRQ_TYPE_LEVEL_HIGH>; 529 + irq-gpios = <&pio 146 GPIO_ACTIVE_HIGH>; 530 + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; 531 + }; 532 + }; 533 + 534 + &mfg0 { 535 + domain-supply = <&mt6359_vproc2_buck_reg>; 536 + }; 537 + 538 + &mfg1 { 539 + domain-supply = <&mt6359_vsram_others_ldo_reg>; 540 + }; 541 + 542 + &mmc0 { 543 + bus-width = <8>; 544 + cap-mmc-highspeed; 545 + cap-mmc-hw-reset; 546 + hs400-ds-delay = <0x1481b>; 547 + max-frequency = <200000000>; 548 + mmc-hs200-1_8v; 549 + mmc-hs400-1_8v; 550 + non-removable; 551 + no-sd; 552 + no-sdio; 553 + supports-cqe; 554 + pinctrl-names = "default", "state_uhs"; 555 + pinctrl-0 = <&mmc0_default_pins>; 556 + pinctrl-1 = <&mmc0_uhs_pins>; 557 + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 558 + vqmmc-supply = <&mt6359_vufs_ldo_reg>; 559 + status = "okay"; 560 + }; 561 + 562 + &mmc1 { 563 + bus-width = <4>; 564 + cap-sd-highspeed; 565 + max-frequency = <200000000>; 566 + sd-uhs-sdr104; 567 + sd-uhs-sdr50; 568 + pinctrl-names = "default", "state_uhs"; 569 + pinctrl-0 = <&mmc1_default_pins>; 570 + pinctrl-1 = <&mmc1_uhs_pins>; 571 + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; 572 + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; 573 + vmmc-supply = <&sdcard_en_3v3>; 574 + status = "okay"; 575 + }; 576 + 577 + &mmc2 { 578 + bus-width = <4>; 579 + cap-sd-highspeed; 580 + cap-sdio-irq; 581 + keep-power-in-suspend; 582 + max-frequency = <200000000>; 583 + no-mmc; 584 + non-removable; 585 + no-sd; 586 + sd-uhs-sdr104; 587 + wakeup-source; 588 + pinctrl-names = "default", "state_uhs", "state_eint"; 589 + pinctrl-0 = <&mmc2_default_pins>; 590 + pinctrl-1 = <&mmc2_uhs_pins>; 591 + pinctrl-2 = <&mmc2_eint_pins>; 592 + interrupt-names = "msdc", "sdio_wakeup"; 593 + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, 594 + <&pio 172 IRQ_TYPE_LEVEL_LOW>; 595 + vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 596 + vqmmc-supply = <&mt6359_vcn18_ldo_reg>; 597 + mmc-pwrseq = <&wifi_pwrseq>; 598 + status = "okay"; 599 + }; 600 + 601 + &mipi_tx_config0 { 602 + status = "okay"; 603 + }; 604 + 605 + &mt6359codec { 606 + mediatek,mic-type-0 = <1>; 607 + mediatek,mic-type-1 = <3>; 608 + }; 609 + 610 + &mt6359_vbbck_ldo_reg { 611 + regulator-always-on; 612 + }; 613 + 614 + &mt6359_vcn18_ldo_reg { 615 + regulator-name = "vcn18_pmu"; 616 + regulator-always-on; 617 + regulator-boot-on; 618 + }; 619 + 620 + &mt6359_vcn33_1_bt_ldo_reg { 621 + regulator-name = "vcn33_1_pmu"; 622 + regulator-always-on; 623 + }; 624 + 625 + &mt6359_vcn33_2_bt_ldo_reg { 626 + regulator-name = "vcn33_2_pmu"; 627 + regulator-min-microvolt = <3300000>; 628 + regulator-max-microvolt = <3300000>; 629 + regulator-always-on; 630 + regulator-boot-on; 631 + }; 632 + 633 + &mt6359_vcore_buck_reg { 634 + regulator-name = "dvdd_proc_l"; 635 + regulator-always-on; 636 + }; 637 + 638 + &mt6359_vemc_1_ldo_reg { 639 + regulator-always-on; 640 + }; 641 + 642 + &mt6359_vgpu11_buck_reg { 643 + regulator-name = "dvdd_core"; 644 + regulator-always-on; 645 + }; 646 + 647 + &mt6359_vmodem_buck_reg { 648 + regulator-always-on; 649 + }; 650 + 651 + &mt6359_vpa_buck_reg { 652 + regulator-name = "vpa_pmu"; 653 + regulator-always-on; 654 + }; 655 + 656 + &mt6359_vproc2_buck_reg { 657 + /* The name "vgpu" is required by mtk-regulator-coupler */ 658 + regulator-name = "vgpu"; 659 + regulator-min-microvolt = <550000>; 660 + regulator-max-microvolt = <800000>; 661 + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 662 + regulator-coupled-max-spread = <225000>; 663 + }; 664 + 665 + &mt6359_vs2_buck_reg { 666 + regulator-min-microvolt = <1600000>; 667 + regulator-boot-on; 668 + }; 669 + 670 + &mt6359_vpu_buck_reg { 671 + regulator-name = "dvdd_adsp"; 672 + regulator-always-on; 673 + }; 674 + 675 + &mt6359_vrf12_ldo_reg { 676 + regulator-name = "va12_abb2_pmu"; 677 + regulator-always-on; 678 + }; 679 + 680 + &mt6359_vsram_md_ldo_reg { 681 + regulator-always-on; 682 + }; 683 + 684 + &mt6359_vsram_others_ldo_reg { 685 + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ 686 + regulator-name = "vsram_gpu"; 687 + regulator-min-microvolt = <750000>; 688 + regulator-max-microvolt = <800000>; 689 + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; 690 + regulator-coupled-max-spread = <225000>; 691 + }; 692 + 693 + &mt6359_vsim1_ldo_reg { 694 + regulator-name = "vsim1_pmu"; 695 + regulator-max-microvolt = <1800000>; 696 + regulator-enable-ramp-delay = <480>; 697 + }; 698 + 699 + &mt6359_vufs_ldo_reg { 700 + regulator-name = "vufs18_pmu"; 701 + regulator-always-on; 702 + }; 703 + 704 + &ovl0_in { 705 + remote-endpoint = <&vdosys0_ep_main>; 706 + }; 707 + 708 + &pcie { 709 + pinctrl-names = "default"; 710 + pinctrl-0 = <&pcie_default_pins>; 711 + status = "okay"; 712 + }; 713 + 714 + &pciephy { 715 + status = "okay"; 716 + }; 717 + 718 + &pmic { 719 + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 720 + 721 + keys { 722 + compatible = "mediatek,mt6359-keys"; 723 + mediatek,long-press-mode = <1>; 724 + power-off-time-sec = <0>; 725 + 726 + power-key { 727 + linux,keycodes = <KEY_POWER>; 728 + wakeup-source; 729 + }; 730 + }; 731 + }; 732 + 733 + &postmask0_in { 734 + remote-endpoint = <&gamma0_out>; 735 + }; 736 + 737 + &postmask0_out { 738 + remote-endpoint = <&dither0_in>; 739 + }; 740 + 741 + &scp_cluster { 742 + status = "okay"; 743 + }; 744 + 745 + &scp_c0 { 746 + memory-region = <&scp_mem>; 747 + status = "okay"; 748 + }; 749 + 750 + &spi0 { 751 + pinctrl-0 = <&spi0_pins>; 752 + pinctrl-names = "default"; 753 + mediatek,pad-select = <0>; 754 + status = "okay"; 755 + }; 756 + 757 + &spi1 { 758 + pinctrl-0 = <&spi1_pins>; 759 + pinctrl-names = "default"; 760 + mediatek,pad-select = <0>; 761 + status = "okay"; 762 + }; 763 + 764 + &spmi { 765 + #address-cells = <2>; 766 + #size-cells = <0>; 767 + 768 + mt6315_6: pmic@6 { 769 + compatible = "mediatek,mt6315-regulator"; 770 + reg = <0x6 SPMI_USID>; 771 + 772 + regulators { 773 + mt6315_6_vbuck1: vbuck1 { 774 + regulator-name = "vbuck1"; 775 + regulator-min-microvolt = <300000>; 776 + regulator-max-microvolt = <1193750>; 777 + regulator-enable-ramp-delay = <256>; 778 + regulator-allowed-modes = <0 1 2>; 779 + regulator-always-on; 780 + }; 781 + 782 + mt6315_6_vbuck3: vbuck3 { 783 + regulator-name = "vbuck3"; 784 + regulator-min-microvolt = <300000>; 785 + regulator-max-microvolt = <1193750>; 786 + regulator-enable-ramp-delay = <256>; 787 + regulator-allowed-modes = <0 1 2>; 788 + regulator-always-on; 789 + }; 790 + 791 + mt6315_6_vbuck4: vbuck4 { 792 + regulator-name = "vbuck4"; 793 + regulator-min-microvolt = <1193750>; 794 + regulator-max-microvolt = <1193750>; 795 + regulator-enable-ramp-delay = <256>; 796 + regulator-allowed-modes = <0 1 2>; 797 + regulator-always-on; 798 + 799 + regulator-state-mem { 800 + regulator-on-in-suspend; 801 + regulator-suspend-microvolt = <1193750>; 802 + }; 803 + }; 804 + }; 805 + }; 806 + }; 807 + 808 + &uart0 { 809 + pinctrl-0 = <&uart0_pins>; 810 + pinctrl-names = "default"; 811 + status = "okay"; 812 + }; 813 + 814 + &uart1 { 815 + pinctrl-0 = <&uart1_pins>; 816 + pinctrl-names = "default"; 817 + status = "okay"; 818 + }; 819 + 820 + &uart2 { 821 + pinctrl-0 = <&uart2_pins>; 822 + pinctrl-names = "default"; 823 + status = "okay"; 824 + }; 825 + 826 + &ssusb0 { 827 + dr_mode = "otg"; 828 + maximum-speed = "high-speed"; 829 + usb-role-switch; 830 + wakeup-source; 831 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 832 + pinctrl-0 = <&usbotg_pins>; 833 + pinctrl-names = "default"; 834 + status = "okay"; 835 + 836 + connector { 837 + compatible = "usb-c-connector"; 838 + label = "USB-C"; 839 + data-role = "dual"; 840 + 841 + ports { 842 + #address-cells = <1>; 843 + #size-cells = <0>; 844 + 845 + port@0 { 846 + reg = <0>; 847 + hs_ep: endpoint { 848 + remote-endpoint = <&usb_hs_ep>; 849 + }; 850 + }; 851 + 852 + port@1 { 853 + reg = <1>; 854 + ss_ep: endpoint { 855 + remote-endpoint = <&hd3ss3220_in_ep>; 856 + }; 857 + }; 858 + }; 859 + }; 860 + 861 + ports { 862 + #address-cells = <1>; 863 + #size-cells = <0>; 864 + 865 + port@0 { 866 + reg = <0>; 867 + usb_hs_ep: endpoint { 868 + remote-endpoint = <&hs_ep>; 869 + }; 870 + }; 871 + 872 + port@1 { 873 + reg = <1>; 874 + usb_role_switch: endpoint { 875 + remote-endpoint = <&hd3ss3220_out_ep>; 876 + }; 877 + }; 878 + }; 879 + }; 880 + 881 + &u2port0 { 882 + status = "okay"; 883 + }; 884 + 885 + &u3phy0 { 886 + status = "okay"; 887 + }; 888 + 889 + &xhci0 { 890 + vbus-supply = <&usb_p0_vbus>; 891 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 892 + status = "okay"; 893 + }; 894 + 895 + &ssusb1 { 896 + dr_mode = "host"; 897 + wakeup-source; 898 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 899 + pinctrl-0 = <&usb1_pins>; 900 + pinctrl-names = "default"; 901 + status = "okay"; 902 + }; 903 + 904 + &u2port1 { 905 + status = "okay"; 906 + }; 907 + 908 + &u3port1 { 909 + status = "okay"; 910 + }; 911 + 912 + &u3phy1 { 913 + status = "okay"; 914 + }; 915 + 916 + &xhci1 { 917 + vbus-supply = <&usb_p1_vbus>; 918 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 919 + status = "okay"; 920 + }; 921 + 922 + &ssusb2 { 923 + dr_mode = "host"; 924 + maximum-speed = "high-speed"; 925 + wakeup-source; 926 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 927 + status = "okay"; 928 + }; 929 + 930 + &u2port2 { 931 + status = "okay"; 932 + }; 933 + 934 + &u3phy2 { 935 + status = "okay"; 936 + }; 937 + 938 + &xhci2 { 939 + vbus-supply = <&usb_p2_vbus>; 940 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 941 + #address-cells = <1>; 942 + #size-cells = <0>; 943 + status = "okay"; 944 + 945 + ethernet@1 { 946 + compatible = "usb424,7850"; 947 + reg = <1>; 948 + #address-cells = <1>; 949 + #size-cells = <0>; 950 + 951 + mdio { 952 + #address-cells = <1>; 953 + #size-cells = <0>; 954 + 955 + ethernet-phy@1 { 956 + reg = <1>; 957 + microchip,led-modes = < 958 + LAN78XX_LINK_1000_ACTIVITY 959 + LAN78XX_LINK_10_ACTIVITY 960 + LAN78XX_LINK_10_100_ACTIVITY 961 + LAN78XX_LINK_ACTIVITY 962 + >; 963 + }; 964 + }; 965 + }; 966 + }; 967 + 968 + &vdosys0 { 969 + port { 970 + #address-cells = <1>; 971 + #size-cells = <0>; 972 + 973 + vdosys0_ep_main: endpoint@0 { 974 + reg = <0>; 975 + remote-endpoint = <&ovl0_in>; 976 + }; 977 + }; 978 + }; 979 + 980 + &watchdog { 981 + pinctrl-names = "default"; 982 + pinctrl-0 = <&watchdog_pins>; 983 + }; 984 + 985 + &pio { 986 + audio_pins: audio-pins { 987 + pins-aud-pmic { 988 + pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI 989 + PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI 990 + PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0 991 + PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1 992 + PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0 993 + PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>; 994 + }; 995 + 996 + pins-pcm-wifi { 997 + pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK 998 + PINMUX_GPIO122__FUNC_B0_PCM_SYNC 999 + PINMUX_GPIO123__FUNC_O_PCM_DO 1000 + PINMUX_GPIO124__FUNC_I0_PCM_DI>; 1001 + }; 1002 + 1003 + pins-i2s { 1004 + pinmux = <PINMUX_GPIO119__FUNC_O_I2SO1_MCK 1005 + PINMUX_GPIO112__FUNC_O_I2SO1_WS 1006 + PINMUX_GPIO120__FUNC_O_I2SO1_BCK 1007 + PINMUX_GPIO113__FUNC_O_I2SO1_D0 1008 + PINMUX_GPIO110__FUNC_I0_I2SIN_D0>; 1009 + }; 1010 + }; 1011 + 1012 + disp_pwm0_pins: disp-pwm0-pins { 1013 + pins { 1014 + pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>; 1015 + bias-pull-down; 1016 + }; 1017 + }; 1018 + 1019 + dsi0_sn65dsi84_pins: dsi0-sn65dsi84-pins { 1020 + pins-irq { 1021 + pinmux = <PINMUX_GPIO128__FUNC_B_GPIO128>; 1022 + bias-pull-down; 1023 + input-enable; 1024 + }; 1025 + 1026 + pins-enable { 1027 + pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>; 1028 + bias-pull-down; 1029 + }; 1030 + }; 1031 + 1032 + eth_default_pins: eth-default-pins { 1033 + pins-txd { 1034 + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, 1035 + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, 1036 + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, 1037 + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; 1038 + drive-strength = <8>; 1039 + }; 1040 + pins-cc { 1041 + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, 1042 + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>, 1043 + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>; 1044 + drive-strength = <8>; 1045 + }; 1046 + pins-rxd { 1047 + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, 1048 + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, 1049 + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, 1050 + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>, 1051 + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>; 1052 + drive-strength = <8>; 1053 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1054 + }; 1055 + pins-mdio { 1056 + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, 1057 + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; 1058 + drive-strength = <8>; 1059 + input-enable; 1060 + }; 1061 + pins-power { 1062 + pinmux = <PINMUX_GPIO27__FUNC_B_GPIO27>; /* GP_EQOS_RESET */ 1063 + output-high; 1064 + }; 1065 + pins-intr { 1066 + pinmux = <PINMUX_GPIO148__FUNC_B_GPIO148>; /* GPIRQ_EQOS_PHY */ 1067 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1068 + input-enable; 1069 + }; 1070 + }; 1071 + 1072 + eth_sleep_pins: eth-sleep-pins { 1073 + pins-txd { 1074 + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, 1075 + <PINMUX_GPIO132__FUNC_B_GPIO132>, 1076 + <PINMUX_GPIO133__FUNC_B_GPIO133>, 1077 + <PINMUX_GPIO134__FUNC_B_GPIO134>; 1078 + }; 1079 + pins-cc { 1080 + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, 1081 + <PINMUX_GPIO142__FUNC_B_GPIO142>, 1082 + <PINMUX_GPIO141__FUNC_B_GPIO141>, 1083 + <PINMUX_GPIO140__FUNC_B_GPIO140>; 1084 + }; 1085 + pins-rxd { 1086 + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, 1087 + <PINMUX_GPIO136__FUNC_B_GPIO136>, 1088 + <PINMUX_GPIO137__FUNC_B_GPIO137>, 1089 + <PINMUX_GPIO138__FUNC_B_GPIO138>; 1090 + }; 1091 + pins-mdio { 1092 + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, 1093 + <PINMUX_GPIO144__FUNC_B_GPIO144>; 1094 + input-disable; 1095 + bias-disable; 1096 + }; 1097 + }; 1098 + 1099 + gpio_keys_pins: gpio-keys-pins { 1100 + pins-keys { 1101 + pinmux = <PINMUX_GPIO129__FUNC_B_GPIO129>, 1102 + <PINMUX_GPIO65__FUNC_B_GPIO65>, 1103 + <PINMUX_GPIO66__FUNC_B_GPIO66>; 1104 + bias-pull-up; 1105 + }; 1106 + }; 1107 + 1108 + hd3ss3220_pins: hd3ss3320-pins { 1109 + pins-irq { 1110 + pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>; 1111 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1112 + input-enable; 1113 + }; 1114 + }; 1115 + 1116 + hdmi_vreg_pins: hdmi-vreg-pins { 1117 + pins-pwr { 1118 + pinmux = <PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V>; 1119 + bias-disable; 1120 + }; 1121 + }; 1122 + 1123 + hdmi_pins: hdmi-pins { 1124 + pins-hotplug { 1125 + pinmux = <PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG>; 1126 + bias-pull-down; 1127 + }; 1128 + 1129 + pins-cec { 1130 + pinmux = <PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC>; 1131 + bias-disable; 1132 + }; 1133 + 1134 + pins-ddc { 1135 + pinmux = <PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL>, 1136 + <PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA>; 1137 + drive-strength = <10>; 1138 + }; 1139 + }; 1140 + 1141 + i2c0_pins: i2c0-pins { 1142 + pins-bus { 1143 + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, 1144 + <PINMUX_GPIO55__FUNC_B1_SCL0>; 1145 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 1146 + drive-strength-microamp = <1000>; 1147 + }; 1148 + }; 1149 + 1150 + i2c0_mux_pins: i2c0-mux-pins { 1151 + pins-reset { 1152 + pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>; 1153 + bias-pull-up; 1154 + }; 1155 + }; 1156 + 1157 + i2c1_pins: i2c1-pins { 1158 + pins-bus { 1159 + pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, 1160 + <PINMUX_GPIO57__FUNC_B1_SCL1>; 1161 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 1162 + drive-strength-microamp = <1000>; 1163 + }; 1164 + }; 1165 + 1166 + i2c2_pins: i2c2-pins { 1167 + pins-bus { 1168 + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, 1169 + <PINMUX_GPIO59__FUNC_B1_SCL2>; 1170 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 1171 + drive-strength-microamp = <1000>; 1172 + }; 1173 + }; 1174 + 1175 + i2c3_pins: i2c3-pins { 1176 + pins-bus { 1177 + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, 1178 + <PINMUX_GPIO61__FUNC_B1_SCL3>; 1179 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 1180 + drive-strength-microamp = <1000>; 1181 + }; 1182 + }; 1183 + 1184 + i2c4_pins: i2c4-pins { 1185 + pins-bus { 1186 + pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, 1187 + <PINMUX_GPIO63__FUNC_B1_SCL4>; 1188 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 1189 + drive-strength-microamp = <1000>; 1190 + }; 1191 + }; 1192 + 1193 + i2c_mux_smarc_lcd_pins: i2c-mux-smarc-lcd-pins { 1194 + pins-reset { 1195 + pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>; 1196 + bias-pull-down; 1197 + }; 1198 + }; 1199 + 1200 + mmc0_default_pins: mmc0-default-pins { 1201 + pins-cmd-dat { 1202 + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, 1203 + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, 1204 + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, 1205 + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, 1206 + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, 1207 + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, 1208 + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, 1209 + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, 1210 + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; 1211 + input-enable; 1212 + drive-strength = <6>; 1213 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1214 + }; 1215 + 1216 + pins-clk { 1217 + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; 1218 + drive-strength = <6>; 1219 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1220 + }; 1221 + 1222 + pins-rst { 1223 + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; 1224 + drive-strength = <6>; 1225 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1226 + }; 1227 + }; 1228 + 1229 + mmc0_uhs_pins: mmc0-uhs-pins { 1230 + pins-cmd-dat { 1231 + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, 1232 + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, 1233 + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, 1234 + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, 1235 + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, 1236 + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, 1237 + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, 1238 + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, 1239 + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; 1240 + input-enable; 1241 + drive-strength = <8>; 1242 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1243 + }; 1244 + 1245 + pins-clk { 1246 + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; 1247 + drive-strength = <8>; 1248 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1249 + }; 1250 + 1251 + pins-ds { 1252 + pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; 1253 + drive-strength = <8>; 1254 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1255 + }; 1256 + 1257 + pins-rst { 1258 + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; 1259 + drive-strength = <8>; 1260 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1261 + }; 1262 + }; 1263 + 1264 + mmc1_default_pins: mmc1-default-pins { 1265 + pins-cmd-dat { 1266 + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, 1267 + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, 1268 + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, 1269 + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, 1270 + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; 1271 + input-enable; 1272 + drive-strength = <6>; 1273 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1274 + }; 1275 + 1276 + pins-pwr { 1277 + pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>; 1278 + bias-pull-down; 1279 + }; 1280 + 1281 + pins-pullup { 1282 + pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>; 1283 + bias-pull-up; 1284 + }; 1285 + 1286 + pins-clk { 1287 + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; 1288 + drive-strength = <6>; 1289 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1290 + }; 1291 + 1292 + pins-insert { 1293 + pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>; 1294 + bias-pull-up; 1295 + }; 1296 + }; 1297 + 1298 + mmc1_uhs_pins: mmc1-uhs-pins { 1299 + pins-cmd-dat { 1300 + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, 1301 + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, 1302 + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, 1303 + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, 1304 + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; 1305 + input-enable; 1306 + drive-strength = <6>; 1307 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1308 + }; 1309 + 1310 + pins-clk { 1311 + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; 1312 + drive-strength = <6>; 1313 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1314 + }; 1315 + }; 1316 + 1317 + mmc2_default_pins: mmc2-default-pins { 1318 + pins-clk { 1319 + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; 1320 + drive-strength = <4>; 1321 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1322 + }; 1323 + 1324 + pins-cmd-dat { 1325 + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, 1326 + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, 1327 + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, 1328 + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, 1329 + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; 1330 + input-enable; 1331 + drive-strength = <6>; 1332 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1333 + }; 1334 + }; 1335 + 1336 + mmc2_uhs_pins: mmc2-uhs-pins { 1337 + pins-clk { 1338 + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; 1339 + drive-strength = <4>; 1340 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1341 + }; 1342 + 1343 + pins-cmd-dat { 1344 + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, 1345 + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, 1346 + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, 1347 + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, 1348 + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; 1349 + input-enable; 1350 + drive-strength = <6>; 1351 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1352 + }; 1353 + }; 1354 + 1355 + mmc2_eint_pins: mmc2-eint-pins { 1356 + pins-dat1 { 1357 + pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>; 1358 + input-enable; 1359 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1360 + }; 1361 + }; 1362 + 1363 + rv3028_pins: rv3028-pins { 1364 + pins-irq { 1365 + pinmux = <PINMUX_GPIO42__FUNC_B_GPIO42>; 1366 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1367 + input-enable; 1368 + }; 1369 + }; 1370 + 1371 + spi0_pins: spi0-pins { 1372 + pins-spi { 1373 + pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, 1374 + <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, 1375 + <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, 1376 + <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; 1377 + bias-disable; 1378 + }; 1379 + }; 1380 + 1381 + spi1_pins: spi1-pins { 1382 + pins-spi { 1383 + pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, 1384 + <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, 1385 + <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, 1386 + <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; 1387 + bias-disable; 1388 + }; 1389 + }; 1390 + 1391 + pcie_default_pins: pcie-default-pins { 1392 + pins { 1393 + pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, 1394 + <PINMUX_GPIO48__FUNC_O_PERSTN>, 1395 + <PINMUX_GPIO49__FUNC_B1_CLKREQN>; 1396 + bias-pull-up; 1397 + }; 1398 + }; 1399 + 1400 + ts_dsi0_goodix_pins: ts-dsi0-goodix-pins { 1401 + pins-irq { 1402 + pinmux = <PINMUX_GPIO146__FUNC_B_GPIO146>; 1403 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1404 + input-enable; 1405 + }; 1406 + 1407 + pins-reset { 1408 + pinmux = <PINMUX_GPIO7__FUNC_B_GPIO7>; 1409 + bias-pull-down; 1410 + }; 1411 + }; 1412 + 1413 + uart0_pins: uart0-pins { 1414 + pins { 1415 + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, 1416 + <PINMUX_GPIO32__FUNC_I1_URXD0>; 1417 + bias-pull-up; 1418 + }; 1419 + }; 1420 + 1421 + uart1_pins: uart1-pins { 1422 + pins { 1423 + pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>, 1424 + <PINMUX_GPIO34__FUNC_I1_URXD1>; 1425 + bias-pull-up; 1426 + }; 1427 + }; 1428 + 1429 + uart2_pins: uart2-pins { 1430 + pins { 1431 + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, 1432 + <PINMUX_GPIO36__FUNC_I1_URXD2>; 1433 + bias-pull-up; 1434 + }; 1435 + }; 1436 + 1437 + usbotg_pins: usbotg-pins { 1438 + pins-iddig { 1439 + pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>; 1440 + input-enable; 1441 + bias-pull-up; 1442 + }; 1443 + 1444 + pins-valid { 1445 + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; 1446 + input-enable; 1447 + }; 1448 + 1449 + pins-vbus { 1450 + pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>; 1451 + output-high; 1452 + }; 1453 + }; 1454 + 1455 + usb1_hub_pins: usb1-hub-pins { 1456 + pins { 1457 + pinmux = <PINMUX_GPIO147__FUNC_B_GPIO147>; 1458 + output-low; 1459 + }; 1460 + }; 1461 + 1462 + usb1_pins: usb1-pins { 1463 + pins { 1464 + pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>; 1465 + input-enable; 1466 + }; 1467 + }; 1468 + 1469 + usb2_eth_pins: usb2-eth-pins { 1470 + pins { 1471 + pinmux = <PINMUX_GPIO80__FUNC_B_GPIO80>; 1472 + output-low; 1473 + }; 1474 + }; 1475 + 1476 + wifi_pwrseq_pins: wifi-pwrseq-pins { 1477 + pins { 1478 + pinmux = <PINMUX_GPIO89__FUNC_B_GPIO89>; 1479 + output-low; 1480 + }; 1481 + }; 1482 + 1483 + watchdog_pins: watchdog-pins { 1484 + pins { 1485 + pinmux = <PINMUX_GPIO100__FUNC_O_WATCHDOG>; 1486 + bias-pull-up; 1487 + }; 1488 + }; 1489 + };

+150

arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi

··· 26 26 stdout-path = "serial0:921600n8"; 27 27 }; 28 28 29 + connector { 30 + compatible = "hdmi-connector"; 31 + label = "hdmi"; 32 + type = "a"; 33 + ddc-i2c-bus = <&hdmitx_ddc>; 34 + hdmi-pwr-supply = <&hdmi_phy>; 35 + 36 + port { 37 + hdmi_connector_in: endpoint { 38 + remote-endpoint = <&hdmi0_out>; 39 + }; 40 + }; 41 + }; 42 + 29 43 firmware { 30 44 optee { 31 45 compatible = "linaro,optee-tz"; ··· 261 247 wakeup-delay-ms = <200>; 262 248 }; 263 249 250 + &dpi1 { 251 + status = "okay"; 252 + }; 253 + 254 + &dpi1_in { 255 + remote-endpoint = <&merge5_out>; 256 + }; 257 + 258 + &dpi1_out { 259 + remote-endpoint = <&hdmi0_in>; 260 + }; 261 + 264 262 &dsi0 { 265 263 #address-cells = <1>; 266 264 #size-cells = <0>; ··· 339 313 }; 340 314 }; 341 315 316 + &ethdr0 { 317 + ports { 318 + #address-cells = <1>; 319 + #size-cells = <0>; 320 + 321 + port@0 { 322 + #address-cells = <1>; 323 + #size-cells = <0>; 324 + reg = <0>; 325 + 326 + ethdr0_in: endpoint@1 { 327 + reg = <1>; 328 + remote-endpoint = <&vdosys1_ep_ext>; 329 + }; 330 + }; 331 + 332 + port@1 { 333 + #address-cells = <1>; 334 + #size-cells = <0>; 335 + reg = <1>; 336 + 337 + ethdr0_out: endpoint@1 { 338 + reg = <1>; 339 + remote-endpoint = <&merge5_in>; 340 + }; 341 + }; 342 + }; 343 + }; 344 + 342 345 &gamma0_out { 343 346 remote-endpoint = <&dither0_in>; 344 347 }; ··· 381 326 clock-frequency = <400000>; 382 327 pinctrl-0 = <&i2c0_pins>; 383 328 pinctrl-names = "default"; 329 + status = "okay"; 330 + }; 331 + 332 + &hdmi { 333 + pinctrl-names = "default"; 334 + pinctrl-0 = <&hdmi_pins>; 335 + status = "okay"; 336 + }; 337 + 338 + &hdmi0_in { 339 + remote-endpoint = <&dpi1_out>; 340 + }; 341 + 342 + &hdmi0_out { 343 + remote-endpoint = <&hdmi_connector_in>; 344 + }; 345 + 346 + &hdmi_phy { 347 + pinctrl-names = "default"; 348 + pinctrl-0 = <&hdmi_vreg_pins>; 349 + 384 350 status = "okay"; 385 351 }; 386 352 ··· 604 528 }; 605 529 }; 606 530 }; 531 + }; 532 + }; 533 + }; 534 + }; 535 + 536 + &merge5 { 537 + ports { 538 + #address-cells = <1>; 539 + #size-cells = <0>; 540 + 541 + port@0 { 542 + #address-cells = <1>; 543 + #size-cells = <0>; 544 + reg = <0>; 545 + 546 + merge5_in: endpoint@1 { 547 + reg = <1>; 548 + remote-endpoint = <&ethdr0_out>; 549 + }; 550 + }; 551 + 552 + port@1 { 553 + #address-cells = <1>; 554 + #size-cells = <0>; 555 + reg = <1>; 556 + 557 + merge5_out: endpoint@1 { 558 + reg = <1>; 559 + remote-endpoint = <&dpi1_in>; 607 560 }; 608 561 }; 609 562 }; ··· 864 759 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 865 760 bias-pull-up; 866 761 input-enable; 762 + }; 763 + }; 764 + 765 + hdmi_vreg_pins: hdmi-vreg-pins { 766 + pins-pwr { 767 + pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>; 768 + bias-disable; 769 + }; 770 + }; 771 + 772 + hdmi_pins: hdmi-pins { 773 + pins-hotplug { 774 + pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>; 775 + bias-pull-down; 776 + }; 777 + 778 + pins-ddc { 779 + pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>, 780 + <PINMUX_GPIO35__FUNC_HDMITX20_SDA>; 781 + drive-strength = <10>; 782 + }; 783 + 784 + pins-cec { 785 + pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>; 786 + bias-disable; 867 787 }; 868 788 }; 869 789 ··· 1189 1059 sound-dai = <&pmic 0>; 1190 1060 }; 1191 1061 }; 1062 + 1063 + hdmi-dai-link { 1064 + link-name = "ETDM3_OUT_BE"; 1065 + 1066 + codec { 1067 + sound-dai = <&hdmi 0>; 1068 + }; 1069 + }; 1192 1070 }; 1193 1071 1194 1072 &spi1 { ··· 1346 1208 vdosys0_ep_main: endpoint@0 { 1347 1209 reg = <0>; 1348 1210 remote-endpoint = <&ovl0_in>; 1211 + }; 1212 + }; 1213 + }; 1214 + 1215 + &vdosys1 { 1216 + port { 1217 + #address-cells = <1>; 1218 + #size-cells = <0>; 1219 + 1220 + vdosys1_ep_ext: endpoint@1 { 1221 + reg = <1>; 1222 + remote-endpoint = <&ethdr0_in>; 1349 1223 }; 1350 1224 }; 1351 1225 };

+150

arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts

··· 37 37 stdout-path = "serial0:921600n8"; 38 38 }; 39 39 40 + connector { 41 + compatible = "hdmi-connector"; 42 + label = "hdmi"; 43 + type = "a"; 44 + ddc-i2c-bus = <&hdmitx_ddc>; 45 + hdmi-pwr-supply = <&hdmi_phy>; 46 + 47 + port { 48 + hdmi_connector_in: endpoint { 49 + remote-endpoint = <&hdmi0_out>; 50 + }; 51 + }; 52 + }; 53 + 40 54 firmware { 41 55 optee { 42 56 compatible = "linaro,optee-tz"; ··· 259 245 }; 260 246 }; 261 247 248 + &dpi1 { 249 + status = "okay"; 250 + }; 251 + 252 + &dpi1_in { 253 + remote-endpoint = <&merge5_out>; 254 + }; 255 + 256 + &dpi1_out { 257 + remote-endpoint = <&hdmi0_in>; 258 + }; 259 + 262 260 &eth { 263 261 phy-mode = "rgmii-rxid"; 264 262 phy-handle = <&rgmii_phy>; ··· 291 265 }; 292 266 }; 293 267 268 + &ethdr0 { 269 + ports { 270 + #address-cells = <1>; 271 + #size-cells = <0>; 272 + 273 + port@0 { 274 + #address-cells = <1>; 275 + #size-cells = <0>; 276 + reg = <0>; 277 + 278 + ethdr0_in: endpoint@1 { 279 + reg = <1>; 280 + remote-endpoint = <&vdosys1_ep_ext>; 281 + }; 282 + }; 283 + 284 + port@1 { 285 + #address-cells = <1>; 286 + #size-cells = <0>; 287 + reg = <1>; 288 + 289 + ethdr0_out: endpoint@1 { 290 + reg = <1>; 291 + remote-endpoint = <&merge5_in>; 292 + }; 293 + }; 294 + }; 295 + }; 296 + 294 297 &gpu { 295 298 mali-supply = <&mt6315_7_vbuck1>; 299 + status = "okay"; 300 + }; 301 + 302 + &hdmi { 303 + pinctrl-names = "default"; 304 + pinctrl-0 = <&hdmi_pins>; 305 + status = "okay"; 306 + }; 307 + 308 + &hdmi0_in { 309 + remote-endpoint = <&dpi1_out>; 310 + }; 311 + 312 + &hdmi0_out { 313 + remote-endpoint = <&hdmi_connector_in>; 314 + }; 315 + 316 + &hdmi_phy { 317 + pinctrl-names = "default"; 318 + pinctrl-0 = <&hdmi_vreg_pins>; 319 + 296 320 status = "okay"; 297 321 }; 298 322 ··· 519 443 }; 520 444 }; 521 445 }; 446 + }; 447 + }; 448 + }; 449 + }; 450 + 451 + &merge5 { 452 + ports { 453 + #address-cells = <1>; 454 + #size-cells = <0>; 455 + 456 + port@0 { 457 + #address-cells = <1>; 458 + #size-cells = <0>; 459 + reg = <0>; 460 + 461 + merge5_in: endpoint@1 { 462 + reg = <1>; 463 + remote-endpoint = <&ethdr0_out>; 464 + }; 465 + }; 466 + 467 + port@1 { 468 + #address-cells = <1>; 469 + #size-cells = <0>; 470 + reg = <1>; 471 + 472 + merge5_out: endpoint@1 { 473 + reg = <1>; 474 + remote-endpoint = <&dpi1_in>; 522 475 }; 523 476 }; 524 477 }; ··· 749 644 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 750 645 bias-pull-up; 751 646 input-enable; 647 + }; 648 + }; 649 + 650 + hdmi_vreg_pins: hdmi-vreg-pins { 651 + pins-pwr { 652 + pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>; 653 + bias-disable; 654 + }; 655 + }; 656 + 657 + hdmi_pins: hdmi-pins { 658 + pins-hotplug { 659 + pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>; 660 + bias-pull-down; 661 + }; 662 + 663 + pins-ddc { 664 + pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>, 665 + <PINMUX_GPIO35__FUNC_HDMITX20_SDA>; 666 + drive-strength = <10>; 667 + }; 668 + 669 + pins-cec { 670 + pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>; 671 + bias-disable; 752 672 }; 753 673 }; 754 674 ··· 1072 942 sound-dai = <&pmic 0>; 1073 943 }; 1074 944 }; 945 + 946 + hdmi-dai-link { 947 + link-name = "ETDM3_OUT_BE"; 948 + 949 + codec { 950 + sound-dai = <&hdmi 0>; 951 + }; 952 + }; 1075 953 }; 1076 954 1077 955 &spi1 { ··· 1194 1056 pinctrl-0 = <&usb2_port0_pins>; 1195 1057 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1196 1058 status = "okay"; 1059 + }; 1060 + 1061 + &vdosys1 { 1062 + port { 1063 + #address-cells = <1>; 1064 + #size-cells = <0>; 1065 + 1066 + vdosys1_ep_ext: endpoint@1 { 1067 + reg = <1>; 1068 + remote-endpoint = <&ethdr0_in>; 1069 + }; 1070 + }; 1197 1071 }; 1198 1072 1199 1073 &xhci0 {

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