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x86/cpufeatures: Add AMD CPPC Performance Priority feature.

Some future AMD processors have feature named "CPPC Performance
Priority" which lets userspace specify different floor performance
levels for different CPUs. The platform firmware takes these different
floor performance levels into consideration while throttling the CPUs
under power/thermal constraints. The presence of this feature is
indicated by bit 16 of the EDX register for CPUID leaf
0x80000007. More details can be found in AMD Publication titled "AMD64
Collaborative Processor Performance Control (CPPC) Performance
Priority" Revision 1.10.

Define a new feature bit named X86_FEATURE_CPPC_PERF_PRIO to map to
CPUID 0x80000007.EDX[16].

Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>

authored by

Gautham R. Shenoy and committed by
Mario Limonciello (AMD) 17210008 e67a5b65

+3 -2
+1 -1
arch/x86/include/asm/cpufeatures.h
··· 415 415 */ 416 416 #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA overflow recovery support */ 417 417 #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error containment and recovery */ 418 - 418 + #define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ 419 419 #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ 420 420 421 421 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
+1
arch/x86/kernel/cpu/scattered.c
··· 52 52 { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, 53 53 { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, 54 54 { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, 55 + { X86_FEATURE_CPPC_PERF_PRIO, CPUID_EDX, 16, 0x80000007, 0 }, 55 56 { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, 56 57 { X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 }, 57 58 { X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 },
+1 -1
tools/arch/x86/include/asm/cpufeatures.h
··· 415 415 */ 416 416 #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA overflow recovery support */ 417 417 #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error containment and recovery */ 418 - 418 + #define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ 419 419 #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ 420 420 421 421 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */