Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"A bunch of radeon fixes for oops on module unload, and problems with
resetting the dma engine, one nouveau fix for black boxes in rendering
on my mbp retina, one sti fix, and a couple of intel fixes"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau: ltc/gf100-: fix cbc issues on certain boards
drm/bochs: add missing drm_connector_register call
drm/cirrus: add missing drm_connector_register call
drm/radeon: Fix typo 'addr' -> 'entry' in rs400_gart_set_page
drm/nouveau/runpm: fix module unload
drm/radeon/px: fix module unload
vgaswitcheroo: add vga_switcheroo_fini_domain_pm_ops
drm/radeon: don't reset dma on r6xx-evergreen init
drm/radeon: don't reset sdma on CIK init
drm/radeon: don't reset dma on NI/SI init
drm/radeon/dpm: fix resume on mullins
drm/radeon: Disable HDP flush before every CS again for < r600
drm/radeon: delete unused PTE_* defines
drm/i915: Add limited color range readout for HDMI/DP ports on g4x/vlv/chv
drm: sti: do not iterate over the info frame array
drm/i915: Fix SRC_COPY width on 830/845g
+85
-63
+1
drivers/gpu/drm/bochs/bochs_kms.c
+1
drivers/gpu/drm/bochs/bochs_kms.c
+1
drivers/gpu/drm/cirrus/cirrus_mode.c
+1
drivers/gpu/drm/cirrus/cirrus_mode.c
+4
drivers/gpu/drm/i915/intel_dp.c
+4
drivers/gpu/drm/i915/intel_dp.c
···
1631
1631
1632
1632
pipe_config->adjusted_mode.flags |= flags;
1633
1633
1634
+
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1635
+
tmp & DP_COLOR_RANGE_16_235)
1636
+
pipe_config->limited_color_range = true;
1637
+
1634
1638
pipe_config->has_dp_encoder = true;
1635
1639
1636
1640
intel_dp_get_m_n(crtc, pipe_config);
+6
-1
drivers/gpu/drm/i915/intel_hdmi.c
+6
-1
drivers/gpu/drm/i915/intel_hdmi.c
···
712
712
struct intel_crtc_config *pipe_config)
713
713
{
714
714
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
715
-
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
715
+
struct drm_device *dev = encoder->base.dev;
716
+
struct drm_i915_private *dev_priv = dev->dev_private;
716
717
u32 tmp, flags = 0;
717
718
int dotclock;
718
719
···
734
733
735
734
if (tmp & HDMI_MODE_SELECT_HDMI)
736
735
pipe_config->has_audio = true;
736
+
737
+
if (!HAS_PCH_SPLIT(dev) &&
738
+
tmp & HDMI_COLOR_RANGE_16_235)
739
+
pipe_config->limited_color_range = true;
737
740
738
741
pipe_config->adjusted_mode.flags |= flags;
739
742
+1
-1
drivers/gpu/drm/i915/intel_ringbuffer.c
+1
-1
drivers/gpu/drm/i915/intel_ringbuffer.c
···
1400
1400
*/
1401
1401
intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1402
1402
intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1403
-
intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024);
1403
+
intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1404
1404
intel_ring_emit(ring, cs_offset);
1405
1405
intel_ring_emit(ring, 4096);
1406
1406
intel_ring_emit(ring, offset);
-1
drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
-1
drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
+1
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
+1
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
+2
drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
+2
drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
···
98
98
gf100_ltc_init(struct nouveau_object *object)
99
99
{
100
100
struct nvkm_ltc_priv *priv = (void *)object;
101
+
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
101
102
int ret;
102
103
103
104
ret = nvkm_ltc_init(priv);
···
108
107
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
109
108
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
110
109
nv_wr32(priv, 0x17e8d4, priv->tag_base);
110
+
nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
111
111
return 0;
112
112
}
113
113
+2
drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
+2
drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
···
28
28
gk104_ltc_init(struct nouveau_object *object)
29
29
{
30
30
struct nvkm_ltc_priv *priv = (void *)object;
31
+
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
31
32
int ret;
32
33
33
34
ret = nvkm_ltc_init(priv);
···
38
37
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
39
38
nv_wr32(priv, 0x17e000, priv->ltc_nr);
40
39
nv_wr32(priv, 0x17e8d4, priv->tag_base);
40
+
nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
41
41
return 0;
42
42
}
43
43
+2
drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
+2
drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
···
98
98
gm107_ltc_init(struct nouveau_object *object)
99
99
{
100
100
struct nvkm_ltc_priv *priv = (void *)object;
101
+
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
101
102
int ret;
102
103
103
104
ret = nvkm_ltc_init(priv);
···
107
106
108
107
nv_wr32(priv, 0x17e27c, priv->ltc_nr);
109
108
nv_wr32(priv, 0x17e278, priv->tag_base);
109
+
nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
110
110
return 0;
111
111
}
112
112
+9
drivers/gpu/drm/nouveau/nouveau_vga.c
+9
drivers/gpu/drm/nouveau/nouveau_vga.c
···
108
108
nouveau_vga_fini(struct nouveau_drm *drm)
109
109
{
110
110
struct drm_device *dev = drm->dev;
111
+
bool runtime = false;
112
+
113
+
if (nouveau_runtime_pm == 1)
114
+
runtime = true;
115
+
if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm()))
116
+
runtime = true;
117
+
111
118
vga_switcheroo_unregister_client(dev->pdev);
119
+
if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
120
+
vga_switcheroo_fini_domain_pm_ops(drm->dev->dev);
112
121
vga_client_register(dev->pdev, NULL, NULL, NULL);
113
122
}
114
123
-7
drivers/gpu/drm/radeon/cik_sdma.c
-7
drivers/gpu/drm/radeon/cik_sdma.c
···
489
489
{
490
490
int r;
491
491
492
-
/* Reset dma */
493
-
WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
494
-
RREG32(SRBM_SOFT_RESET);
495
-
udelay(50);
496
-
WREG32(SRBM_SOFT_RESET, 0);
497
-
RREG32(SRBM_SOFT_RESET);
498
-
499
492
r = cik_sdma_load_microcode(rdev);
500
493
if (r)
501
494
return r;
+21
-7
drivers/gpu/drm/radeon/kv_dpm.c
+21
-7
drivers/gpu/drm/radeon/kv_dpm.c
···
33
33
#define KV_MINIMUM_ENGINE_CLOCK 800
34
34
#define SMC_RAM_END 0x40000
35
35
36
+
static int kv_enable_nb_dpm(struct radeon_device *rdev,
37
+
bool enable);
36
38
static void kv_init_graphics_levels(struct radeon_device *rdev);
37
39
static int kv_calculate_ds_divider(struct radeon_device *rdev);
38
40
static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
···
1297
1295
{
1298
1296
kv_smc_bapm_enable(rdev, false);
1299
1297
1298
+
if (rdev->family == CHIP_MULLINS)
1299
+
kv_enable_nb_dpm(rdev, false);
1300
+
1300
1301
/* powerup blocks */
1301
1302
kv_dpm_powergate_acp(rdev, false);
1302
1303
kv_dpm_powergate_samu(rdev, false);
···
1774
1769
return ret;
1775
1770
}
1776
1771
1777
-
static int kv_enable_nb_dpm(struct radeon_device *rdev)
1772
+
static int kv_enable_nb_dpm(struct radeon_device *rdev,
1773
+
bool enable)
1778
1774
{
1779
1775
struct kv_power_info *pi = kv_get_pi(rdev);
1780
1776
int ret = 0;
1781
1777
1782
-
if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1783
-
ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1784
-
if (ret == 0)
1785
-
pi->nb_dpm_enabled = true;
1778
+
if (enable) {
1779
+
if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1780
+
ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1781
+
if (ret == 0)
1782
+
pi->nb_dpm_enabled = true;
1783
+
}
1784
+
} else {
1785
+
if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1786
+
ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
1787
+
if (ret == 0)
1788
+
pi->nb_dpm_enabled = false;
1789
+
}
1786
1790
}
1787
1791
1788
1792
return ret;
···
1878
1864
}
1879
1865
kv_update_sclk_t(rdev);
1880
1866
if (rdev->family == CHIP_MULLINS)
1881
-
kv_enable_nb_dpm(rdev);
1867
+
kv_enable_nb_dpm(rdev, true);
1882
1868
}
1883
1869
} else {
1884
1870
if (pi->enable_dpm) {
···
1903
1889
}
1904
1890
kv_update_acp_boot_level(rdev);
1905
1891
kv_update_sclk_t(rdev);
1906
-
kv_enable_nb_dpm(rdev);
1892
+
kv_enable_nb_dpm(rdev, true);
1907
1893
}
1908
1894
}
1909
1895
-6
drivers/gpu/drm/radeon/ni_dma.c
-6
drivers/gpu/drm/radeon/ni_dma.c
···
191
191
u32 reg_offset, wb_offset;
192
192
int i, r;
193
193
194
-
/* Reset dma */
195
-
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
196
-
RREG32(SRBM_SOFT_RESET);
197
-
udelay(50);
198
-
WREG32(SRBM_SOFT_RESET, 0);
199
-
200
194
for (i = 0; i < 2; i++) {
201
195
if (i == 0) {
202
196
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
+14
-14
drivers/gpu/drm/radeon/r100.c
+14
-14
drivers/gpu/drm/radeon/r100.c
···
821
821
return RREG32(RADEON_CRTC2_CRNT_FRAME);
822
822
}
823
823
824
+
/**
825
+
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
826
+
* rdev: radeon device structure
827
+
* ring: ring buffer struct for emitting packets
828
+
*/
829
+
static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
830
+
{
831
+
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
832
+
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
833
+
RADEON_HDP_READ_BUFFER_INVALIDATE);
834
+
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
835
+
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
836
+
}
837
+
824
838
/* Who ever call radeon_fence_emit should call ring_lock and ask
825
839
* for enough space (today caller are ib schedule and buffer move) */
826
840
void r100_fence_ring_emit(struct radeon_device *rdev,
···
1068
1054
{
1069
1055
WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1070
1056
(void)RREG32(RADEON_CP_RB_WPTR);
1071
-
}
1072
-
1073
-
/**
1074
-
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
1075
-
* rdev: radeon device structure
1076
-
* ring: ring buffer struct for emitting packets
1077
-
*/
1078
-
void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
1079
-
{
1080
-
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
1081
-
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
1082
-
RADEON_HDP_READ_BUFFER_INVALIDATE);
1083
-
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
1084
-
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
1085
1057
}
1086
1058
1087
1059
static void r100_cp_load_microcode(struct radeon_device *rdev)
-9
drivers/gpu/drm/radeon/r600_dma.c
-9
drivers/gpu/drm/radeon/r600_dma.c
···
124
124
u32 rb_bufsz;
125
125
int r;
126
126
127
-
/* Reset dma */
128
-
if (rdev->family >= CHIP_RV770)
129
-
WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
130
-
else
131
-
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
132
-
RREG32(SRBM_SOFT_RESET);
133
-
udelay(50);
134
-
WREG32(SRBM_SOFT_RESET, 0);
135
-
136
127
WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
137
128
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
138
129
-7
drivers/gpu/drm/radeon/r600d.h
-7
drivers/gpu/drm/radeon/r600d.h
···
44
44
#define R6XX_MAX_PIPES 8
45
45
#define R6XX_MAX_PIPES_MASK 0xff
46
46
47
-
/* PTE flags */
48
-
#define PTE_VALID (1 << 0)
49
-
#define PTE_SYSTEM (1 << 1)
50
-
#define PTE_SNOOPED (1 << 2)
51
-
#define PTE_READABLE (1 << 5)
52
-
#define PTE_WRITEABLE (1 << 6)
53
-
54
47
/* tiling bits */
55
48
#define ARRAY_LINEAR_GENERAL 0x00000000
56
49
#define ARRAY_LINEAR_ALIGNED 0x00000001
-2
drivers/gpu/drm/radeon/radeon_asic.c
-2
drivers/gpu/drm/radeon/radeon_asic.c
···
185
185
.get_rptr = &r100_gfx_get_rptr,
186
186
.get_wptr = &r100_gfx_get_wptr,
187
187
.set_wptr = &r100_gfx_set_wptr,
188
-
.hdp_flush = &r100_ring_hdp_flush,
189
188
};
190
189
191
190
static struct radeon_asic r100_asic = {
···
331
332
.get_rptr = &r100_gfx_get_rptr,
332
333
.get_wptr = &r100_gfx_get_wptr,
333
334
.set_wptr = &r100_gfx_set_wptr,
334
-
.hdp_flush = &r100_ring_hdp_flush,
335
335
};
336
336
337
337
static struct radeon_asic r300_asic = {
+1
-2
drivers/gpu/drm/radeon/radeon_asic.h
+1
-2
drivers/gpu/drm/radeon/radeon_asic.h
+9
-2
drivers/gpu/drm/radeon/radeon_device.c
+9
-2
drivers/gpu/drm/radeon/radeon_device.c
···
1393
1393
1394
1394
r = radeon_init(rdev);
1395
1395
if (r)
1396
-
return r;
1396
+
goto failed;
1397
1397
1398
1398
r = radeon_ib_ring_tests(rdev);
1399
1399
if (r)
···
1413
1413
radeon_agp_disable(rdev);
1414
1414
r = radeon_init(rdev);
1415
1415
if (r)
1416
-
return r;
1416
+
goto failed;
1417
1417
}
1418
1418
1419
1419
if ((radeon_testing & 1)) {
···
1435
1435
DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1436
1436
}
1437
1437
return 0;
1438
+
1439
+
failed:
1440
+
if (runtime)
1441
+
vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1442
+
return r;
1438
1443
}
1439
1444
1440
1445
static void radeon_debugfs_remove_files(struct radeon_device *rdev);
···
1460
1455
radeon_bo_evict_vram(rdev);
1461
1456
radeon_fini(rdev);
1462
1457
vga_switcheroo_unregister_client(rdev->pdev);
1458
+
if (rdev->flags & RADEON_IS_PX)
1459
+
vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1463
1460
vga_client_register(rdev->pdev, NULL, NULL, NULL);
1464
1461
if (rdev->rio_mem)
1465
1462
pci_iounmap(rdev->pdev, rdev->rio_mem);
+1
-1
drivers/gpu/drm/radeon/radeon_drv.c
+1
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
83
83
* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
84
84
* 2.39.0 - Add INFO query for number of active CUs
85
85
* 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
86
-
* CS to GPU
86
+
* CS to GPU on >= r600
87
87
*/
88
88
#define KMS_DRIVER_MAJOR 2
89
89
#define KMS_DRIVER_MINOR 40
+2
-2
drivers/gpu/drm/radeon/rs400.c
+2
-2
drivers/gpu/drm/radeon/rs400.c
···
221
221
entry = (lower_32_bits(addr) & PAGE_MASK) |
222
222
((upper_32_bits(addr) & 0xff) << 4);
223
223
if (flags & RADEON_GART_PAGE_READ)
224
-
addr |= RS400_PTE_READABLE;
224
+
entry |= RS400_PTE_READABLE;
225
225
if (flags & RADEON_GART_PAGE_WRITE)
226
-
addr |= RS400_PTE_WRITEABLE;
226
+
entry |= RS400_PTE_WRITEABLE;
227
227
if (!(flags & RADEON_GART_PAGE_SNOOP))
228
228
entry |= RS400_PTE_UNSNOOPED;
229
229
entry = cpu_to_le32(entry);
-1
drivers/gpu/drm/sti/sti_hdmi.c
-1
drivers/gpu/drm/sti/sti_hdmi.c
+6
drivers/gpu/vga/vga_switcheroo.c
+6
drivers/gpu/vga/vga_switcheroo.c
···
660
660
}
661
661
EXPORT_SYMBOL(vga_switcheroo_init_domain_pm_ops);
662
662
663
+
void vga_switcheroo_fini_domain_pm_ops(struct device *dev)
664
+
{
665
+
dev->pm_domain = NULL;
666
+
}
667
+
EXPORT_SYMBOL(vga_switcheroo_fini_domain_pm_ops);
668
+
663
669
static int vga_switcheroo_runtime_resume_hdmi_audio(struct device *dev)
664
670
{
665
671
struct pci_dev *pdev = to_pci_dev(dev);
+2
include/linux/vga_switcheroo.h
+2
include/linux/vga_switcheroo.h
···
64
64
void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic);
65
65
66
66
int vga_switcheroo_init_domain_pm_ops(struct device *dev, struct dev_pm_domain *domain);
67
+
void vga_switcheroo_fini_domain_pm_ops(struct device *dev);
67
68
int vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, struct dev_pm_domain *domain);
68
69
#else
69
70
···
83
82
static inline void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic) {}
84
83
85
84
static inline int vga_switcheroo_init_domain_pm_ops(struct device *dev, struct dev_pm_domain *domain) { return -EINVAL; }
85
+
static inline void vga_switcheroo_fini_domain_pm_ops(struct device *dev) {}
86
86
static inline int vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, struct dev_pm_domain *domain) { return -EINVAL; }
87
87
88
88
#endif