Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Make pci_stop_dev() and pci_destroy_dev() safe so concurrent
callers can't stop a device multiple times, even as we migrate from
the global pci_rescan_remove_lock to finer-grained locking (Keith
Busch)
- Improve pci_walk_bus() implementation by making it recursive and
moving locking up to avoid need for a 'locked' parameter (Keith
Busch)
- Unexport pci_walk_bus_locked(), which is only used internally by
the PCI core (Keith Busch)
- Detect some Thunderbolt chips that are built-in and hence
'trustworthy' by a heuristic since the 'ExternalFacingPort' and
'usb4-host-interface' ACPI properties are not quite enough (Esther
Shimanovich)
Resource management:
- Use PCI bus addresses (not CPU addresses) in 'ranges' properties
when building dynamic DT nodes so systems where PCI and CPU
addresses differ work correctly (Andrea della Porta)
- Tidy resource sizing and assignment with helpers to reduce
redundancy (Ilpo Järvinen)
- Improve pdev_sort_resources() 'bogus alignment' warning to be more
specific (Ilpo Järvinen)
Driver binding:
- Convert driver .remove_new() callbacks to .remove() again to finish
the conversion from returning 'int' to being 'void' (Sergio
Paracuellos)
- Export pcim_request_all_regions(), a managed interface to request
all BARs (Philipp Stanner)
- Replace pcim_iomap_regions_request_all() with
pcim_request_all_regions(), and pcim_iomap_table()[n] with
pcim_iomap(n), in the following drivers: ahci, crypto qat, crypto
octeontx2, intel_th, iwlwifi, ntb idt, serial rp2, ALSA korg1212
(Philipp Stanner)
- Remove the now unused pcim_iomap_regions_request_all() (Philipp
Stanner)
- Export pcim_iounmap_region(), a managed interface to unmap and
release a PCI BAR (Philipp Stanner)
- Replace pcim_iomap_regions(mask) with pcim_iomap_region(n), and
pcim_iounmap_regions(mask) with pcim_iounmap_region(n), in the
following drivers: fpga dfl-pci, block mtip32xx, gpio-merrifield,
cavium (Philipp Stanner)
Error handling:
- Add sysfs 'reset_subordinate' to reset the entire hierarchy below a
bridge; previously Secondary Bus Reset could only be used when
there was a single device below a bridge (Keith Busch)
- Warn if we reset a running device where the driver didn't register
pci_error_handlers notification callbacks (Keith Busch)
ASPM:
- Disable ASPM L1 before touching L1 PM Substates to follow the spec
closer and avoid a CPU load timeout on some platforms (Ajay
Agarwal)
- Set devices below Intel VMD to D0 before enabling ASPM L1 Substates
as required per spec for all L1 Substates changes (Jian-Hong Pan)
Power management:
- Enable starfive controller runtime PM before probing host bridge
(Mayank Rana)
- Enable runtime power management for host bridges (Krishna chaitanya
chundru)
Power control:
- Use of_platform_device_create() instead of of_platform_populate()
to create pwrctl platform devices so we can control it based on the
child nodes (Manivannan Sadhasivam)
- Create pwrctrl platform devices only if there's a relevant power
supply property (Manivannan Sadhasivam)
- Add device link from the pwrctl supplier to the PCI dev to ensure
pwrctl drivers are probed before the PCI dev driver; this avoids a
race where pwrctl could change device power state while the PCI
driver was active (Manivannan Sadhasivam)
- Find pwrctl device for removal with of_find_device_by_node()
instead of searching all children of the parent (Manivannan
Sadhasivam)
- Rename 'pwrctl' to 'pwrctrl' to match new bandwidth controller
('bwctrl') and hotplug files (Bjorn Helgaas)
Bandwidth control:
- Add read/modify/write locking for Link Control 2, which is used to
manage Link speed (Ilpo Järvinen)
- Extract Link Bandwidth Management Status check into
pcie_lbms_seen(), where it can be shared between the bandwidth
controller and quirks that use it to help retrain failed links
(Ilpo Järvinen)
- Re-add Link Bandwidth notification support with updates to address
the reasons it was previously reverted (Alexandru Gagniuc, Ilpo
Järvinen)
- Add pcie_set_target_speed() and related functionality so drivers
can manage PCIe Link speed based on thermal or other constraints
(Ilpo Järvinen)
- Add a thermal cooling driver to throttle PCIe Links via the
existing thermal management framework (Ilpo Järvinen)
- Add a userspace selftest for the PCIe bandwidth controller (Ilpo
Järvinen)
PCI device hotplug:
- Add hotplug controller driver for Marvell OCTEON multi-function
device where function 0 has a management console interface to
enable/disable and provision various personalities for the other
functions (Shijith Thotton)
- Retain a reference to the pci_bus for the lifetime of a pci_slot to
avoid a use-after-free when the thunderbolt driver resets USB4 host
routers on boot, causing hotplug remove/add of downstream docks or
other devices (Lukas Wunner)
- Remove unused cpcihp struct cpci_hp_controller_ops.hardware_test
(Guilherme Giacomo Simoes)
- Remove unused cpqphp struct ctrl_dbg.ctrl (Christophe JAILLET)
- Use pci_bus_read_dev_vendor_id() instead of hand-coded presence
detection in cpqphp (Ilpo Järvinen)
- Simplify cpqphp enumeration, which is already simple-minded and
doesn't handle devices below hot-added bridges (Ilpo Järvinen)
Virtualization:
- Add ACS quirk for Wangxun FF5xxx NICs, which don't advertise an ACS
capability but do isolate functions as though PCI_ACS_RR and
PCI_ACS_CR were set, so the functions can be in independent IOMMU
groups (Mengyuan Lou)
TLP Processing Hints (TPH):
- Add and document TLP Processing Hints (TPH) support so drivers can
enable and disable TPH and the kernel can save/restore TPH
configuration (Wei Huang)
- Add TPH Steering Tag support so drivers can retrieve Steering Tag
values associated with specific CPUs via an ACPI _DSM to improve
performance by directing DMA writes closer to their consumers (Wei
Huang)
Data Object Exchange (DOE):
- Wait up to 1 second for DOE Busy bit to clear before writing a
request to the mailbox to avoid failures if the mailbox is still
busy from a previous transfer (Gregory Price)
Endpoint framework:
- Skip attempts to allocate from endpoint controller memory window if
the requested size is larger than the window (Damien Le Moal)
- Add and document pci_epc_mem_map() and pci_epc_mem_unmap() to
handle controller-specific size and alignment constraints, and add
test cases to the endpoint test driver (Damien Le Moal)
- Implement dwc pci_epc_ops.align_addr() so pci_epc_mem_map() can
observe DWC-specific alignment requirements (Damien Le Moal)
- Synchronously cancel command handler work in endpoint test before
cleaning up DMA and BARs (Damien Le Moal)
- Respect endpoint page size in dw_pcie_ep_align_addr() (Niklas
Cassel)
- Use dw_pcie_ep_align_addr() in dw_pcie_ep_raise_msi_irq() and
dw_pcie_ep_raise_msix_irq() instead of open coding the equivalent
(Niklas Cassel)
- Avoid NULL dereference if Modem Host Interface Endpoint lacks
'mmio' DT property (Zhongqiu Han)
- Release PCI domain ID of Endpoint controller parent (not controller
itself) and before unregistering the controller, to avoid
use-after-free (Zijun Hu)
- Clear secondary (not primary) EPC in pci_epc_remove_epf() when
removing the secondary controller associated with an NTB (Zijun Hu)
Cadence PCIe controller driver:
- Lower severity of 'phy-names' message (Bartosz Wawrzyniak)
Freescale i.MX6 PCIe controller driver:
- Fix suspend/resume support on i.MX6QDL, which has a hardware
erratum that prevents use of L2 (Stefan Eichenberger)
Intel VMD host bridge driver:
- Add 0xb60b and 0xb06f Device IDs for client SKUs (Nirmal Patel)
MediaTek PCIe Gen3 controller driver:
- Update mediatek-gen3 DT binding to require the exact number of
clocks for each SoC (Fei Shao)
- Add support for DT 'max-link-speed' and 'num-lanes' properties to
restrict the link speed and width (AngeloGioacchino Del Regno)
Microchip PolarFlare PCIe controller driver:
- Add DT and driver support for using either of the two PolarFire
Root Ports (Conor Dooley)
NVIDIA Tegra194 PCIe controller driver:
- Move endpoint controller cleanups that depend on refclk from the
host to the notifier that tells us the host has deasserted PERST#,
when refclk should be valid (Manivannan Sadhasivam)
Qualcomm PCIe controller driver:
- Add qcom SAR2130P DT binding with an additional clock (Dmitry
Baryshkov)
- Enable MSI interrupts if 'global' IRQ is supported, since a
previous commit unintentionally masked them (Manivannan Sadhasivam)
- Move endpoint controller cleanups that depend on refclk from the
host to the notifier that tells us the host has deasserted PERST#,
when refclk should be valid (Manivannan Sadhasivam)
- Add DT binding and driver support for IPQ9574, with Synopsys IP
v5.80a and Qcom IP 1.27.0 (devi priya)
- Move the OPP "operating-points-v2" table from the
qcom,pcie-sm8450.yaml DT binding to qcom,pcie-common.yaml, where it
can be used by other Qcom platforms (Qiang Yu)
- Add 'global' SPI interrupt for events like link-up, link-down to
qcom,pcie-x1e80100 DT binding so we can start enumeration when the
link comes up (Qiang Yu)
- Disable ASPM L0s for qcom,pcie-x1e80100 since the PHY is not tuned
to support this (Qiang Yu)
- Add ops_1_21_0 for SC8280X family SoC, which doesn't use the
'iommu-map' DT property and doesn't need BDF-to-SID translation
(Qiang Yu)
Rockchip PCIe controller driver:
- Define ROCKCHIP_PCIE_AT_SIZE_ALIGN to replace magic 256 endpoint
.align value (Damien Le Moal)
- When unmapping an endpoint window, compute the region index instead
of searching for it, and verify that the address was mapped (Damien
Le Moal)
- When mapping an endpoint window, verify that the address hasn't
been mapped already (Damien Le Moal)
- Implement pci_epc_ops.align_addr() for rockchip-ep (Damien Le Moal)
- Fix MSI IRQ data mapping to observe the alignment constraint, which
fixes intermittent page faults in memcpy_toio() and memcpy_fromio()
(Damien Le Moal)
- Rename rockchip_pcie_parse_ep_dt() to
rockchip_pcie_ep_get_resources() for consistency with similar DT
interfaces (Damien Le Moal)
- Skip the unnecessary link train in rockchip_pcie_ep_probe() and do
it only in the endpoint start operation (Damien Le Moal)
- Implement pci_epc_ops.stop_link() to disable link training and
controller configuration (Damien Le Moal)
- Attempt link training at 5 GT/s when both partners support it
(Damien Le Moal)
- Add a handler for PERST# signal so we can detect host-initiated
resets and start link training after PERST# is deasserted (Damien
Le Moal)
Synopsys DesignWare PCIe controller driver:
- Clear outbound address on unmap so dw_pcie_find_index() won't match
an ATU index that was already unmapped (Damien Le Moal)
- Use of_property_present() instead of of_property_read_bool() when
testing for presence of non-boolean DT properties (Rob Herring)
- Advertise 1MB size if endpoint supports Resizable BARs, which was
inadvertently lost in v6.11 (Niklas Cassel)
TI J721E PCIe driver:
- Add PCIe support for J722S SoC (Siddharth Vadapalli)
- Delay PCIE_T_PVPERL_MS (100 ms), not just PCIE_T_PERST_CLK_US (100
us), before deasserting PERST# to ensure power and refclk are
stable (Siddharth Vadapalli)
TI Keystone PCIe controller driver:
- Set the 'ti,keystone-pcie' mode so v3.65a devices work in Root
Complex mode (Kishon Vijay Abraham I)
- Try to avoid unrecoverable SError for attempts to issue config
transactions when the link is down; this is racy but the best we
can do (Kishon Vijay Abraham I)
Miscellaneous:
- Reorganize kerneldoc parameter names to match order in function
signature (Julia Lawall)
- Fix sysfs reset_method_store() memory leak (Todd Kjos)
- Simplify pci_create_slot() (Ilpo Järvinen)
- Fix incorrect printf format specifiers in pcitest (Luo Yifan)"
* tag 'pci-v6.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (127 commits)
PCI: rockchip-ep: Handle PERST# signal in EP mode
PCI: rockchip-ep: Improve link training
PCI: rockship-ep: Implement the pci_epc_ops::stop_link() operation
PCI: rockchip-ep: Refactor endpoint link training enable
PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding
PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() memory allocations
PCI: rockchip-ep: Rename rockchip_pcie_parse_ep_dt()
PCI: rockchip-ep: Fix MSI IRQ data mapping
PCI: rockchip-ep: Implement the pci_epc_ops::align_addr() operation
PCI: rockchip-ep: Improve rockchip_pcie_ep_map_addr()
PCI: rockchip-ep: Improve rockchip_pcie_ep_unmap_addr()
PCI: rockchip-ep: Use a macro to define EP controller .align feature
PCI: rockchip-ep: Fix address translation unit programming
PCI/pwrctrl: Rename pwrctrl functions and structures
PCI/pwrctrl: Rename pwrctl files to pwrctrl
PCI/pwrctl: Remove pwrctl device without iterating over all children of pwrctl parent
PCI/pwrctl: Ensure that pwrctl drivers are probed before PCI client drivers
PCI/pwrctl: Create pwrctl device only if at least one power supply is present
PCI/pwrctl: Use of_platform_device_create() to create pwrctl devices
tools: PCI: Fix incorrect printf format specifiers
...
+4181
-1172
+11
Documentation/ABI/testing/sysfs-bus-pci
+11
Documentation/ABI/testing/sysfs-bus-pci
···
163
163
will be present in sysfs. Writing 1 to this file
164
164
will perform reset.
165
165
166
+
What: /sys/bus/pci/devices/.../reset_subordinate
167
+
Date: October 2024
168
+
Contact: linux-pci@vger.kernel.org
169
+
Description:
170
+
This is visible only for bridge devices. If you want to reset
171
+
all devices attached through the subordinate bus of a specific
172
+
bridge device, writing 1 to this will try to do it. This will
173
+
affect all devices attached to the system through this bridge
174
+
similiar to writing 1 to their individual "reset" file, so use
175
+
with caution.
176
+
166
177
What: /sys/bus/pci/devices/.../vpd
167
178
Date: February 2008
168
179
Contact: Ben Hutchings <bwh@kernel.org>
+29
Documentation/PCI/endpoint/pci-endpoint.rst
+29
Documentation/PCI/endpoint/pci-endpoint.rst
···
117
117
The PCI endpoint function driver should use pci_epc_mem_free_addr() to
118
118
free the memory space allocated using pci_epc_mem_alloc_addr().
119
119
120
+
* pci_epc_map_addr()
121
+
122
+
A PCI endpoint function driver should use pci_epc_map_addr() to map to a RC
123
+
PCI address the CPU address of local memory obtained with
124
+
pci_epc_mem_alloc_addr().
125
+
126
+
* pci_epc_unmap_addr()
127
+
128
+
A PCI endpoint function driver should use pci_epc_unmap_addr() to unmap the
129
+
CPU address of local memory mapped to a RC address with pci_epc_map_addr().
130
+
131
+
* pci_epc_mem_map()
132
+
133
+
A PCI endpoint controller may impose constraints on the RC PCI addresses that
134
+
can be mapped. The function pci_epc_mem_map() allows endpoint function
135
+
drivers to allocate and map controller memory while handling such
136
+
constraints. This function will determine the size of the memory that must be
137
+
allocated with pci_epc_mem_alloc_addr() for successfully mapping a RC PCI
138
+
address range. This function will also indicate the size of the PCI address
139
+
range that was actually mapped, which can be less than the requested size, as
140
+
well as the offset into the allocated memory to use for accessing the mapped
141
+
RC PCI address range.
142
+
143
+
* pci_epc_mem_unmap()
144
+
145
+
A PCI endpoint function driver can use pci_epc_mem_unmap() to unmap and free
146
+
controller memory that was allocated and mapped using pci_epc_mem_map().
147
+
148
+
120
149
Other EPC APIs
121
150
~~~~~~~~~~~~~~
122
151
+1
Documentation/PCI/index.rst
+1
Documentation/PCI/index.rst
+9
-5
Documentation/PCI/pciebus-howto.rst
+9
-5
Documentation/PCI/pciebus-howto.rst
···
217
217
that is shared between many drivers including the service drivers.
218
218
RMW Capability accessors (pcie_capability_clear_and_set_word(),
219
219
pcie_capability_set_word(), and pcie_capability_clear_word()) protect
220
-
a selected set of PCI Express Capability Registers (Link Control
221
-
Register and Root Control Register). Any change to those registers
222
-
should be performed using RMW accessors to avoid problems due to
223
-
concurrent updates. For the up-to-date list of protected registers,
224
-
see pcie_capability_clear_and_set_word().
220
+
a selected set of PCI Express Capability Registers:
221
+
222
+
* Link Control Register
223
+
* Root Control Register
224
+
* Link Control 2 Register
225
+
226
+
Any change to those registers should be performed using RMW accessors to
227
+
avoid problems due to concurrent updates. For the up-to-date list of
228
+
protected registers, see pcie_capability_clear_and_set_word().
+132
Documentation/PCI/tph.rst
+132
Documentation/PCI/tph.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
4
+
===========
5
+
TPH Support
6
+
===========
7
+
8
+
:Copyright: 2024 Advanced Micro Devices, Inc.
9
+
:Authors: - Eric van Tassell <eric.vantassell@amd.com>
10
+
- Wei Huang <wei.huang2@amd.com>
11
+
12
+
13
+
Overview
14
+
========
15
+
16
+
TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices
17
+
to provide optimization hints for requests that target memory space.
18
+
These hints, in a format called Steering Tags (STs), are embedded in the
19
+
requester's TLP headers, enabling the system hardware, such as the Root
20
+
Complex, to better manage platform resources for these requests.
21
+
22
+
For example, on platforms with TPH-based direct data cache injection
23
+
support, an endpoint device can include appropriate STs in its DMA
24
+
traffic to specify which cache the data should be written to. This allows
25
+
the CPU core to have a higher probability of getting data from cache,
26
+
potentially improving performance and reducing latency in data
27
+
processing.
28
+
29
+
30
+
How to Use TPH
31
+
==============
32
+
33
+
TPH is presented as an optional extended capability in PCIe. The Linux
34
+
kernel handles TPH discovery during boot, but it is up to the device
35
+
driver to request TPH enablement if it is to be utilized. Once enabled,
36
+
the driver uses the provided API to obtain the Steering Tag for the
37
+
target memory and to program the ST into the device's ST table.
38
+
39
+
Enable TPH support in Linux
40
+
---------------------------
41
+
42
+
To support TPH, the kernel must be built with the CONFIG_PCIE_TPH option
43
+
enabled.
44
+
45
+
Manage TPH
46
+
----------
47
+
48
+
To enable TPH for a device, use the following function::
49
+
50
+
int pcie_enable_tph(struct pci_dev *pdev, int mode);
51
+
52
+
This function enables TPH support for device with a specific ST mode.
53
+
Current supported modes include:
54
+
55
+
* PCI_TPH_ST_NS_MODE - NO ST Mode
56
+
* PCI_TPH_ST_IV_MODE - Interrupt Vector Mode
57
+
* PCI_TPH_ST_DS_MODE - Device Specific Mode
58
+
59
+
`pcie_enable_tph()` checks whether the requested mode is actually
60
+
supported by the device before enabling. The device driver can figure out
61
+
which TPH mode is supported and can be properly enabled based on the
62
+
return value of `pcie_enable_tph()`.
63
+
64
+
To disable TPH, use the following function::
65
+
66
+
void pcie_disable_tph(struct pci_dev *pdev);
67
+
68
+
Manage ST
69
+
---------
70
+
71
+
Steering Tags are platform specific. PCIe spec does not specify where STs
72
+
are from. Instead PCI Firmware Specification defines an ACPI _DSM method
73
+
(see the `Revised _DSM for Cache Locality TPH Features ECN
74
+
<https://members.pcisig.com/wg/PCI-SIG/document/15470>`_) for retrieving
75
+
STs for a target memory of various properties. This method is what is
76
+
supported in this implementation.
77
+
78
+
To retrieve a Steering Tag for a target memory associated with a specific
79
+
CPU, use the following function::
80
+
81
+
int pcie_tph_get_cpu_st(struct pci_dev *pdev, enum tph_mem_type type,
82
+
unsigned int cpu_uid, u16 *tag);
83
+
84
+
The `type` argument is used to specify the memory type, either volatile
85
+
or persistent, of the target memory. The `cpu_uid` argument specifies the
86
+
CPU where the memory is associated to.
87
+
88
+
After the ST value is retrieved, the device driver can use the following
89
+
function to write the ST into the device::
90
+
91
+
int pcie_tph_set_st_entry(struct pci_dev *pdev, unsigned int index,
92
+
u16 tag);
93
+
94
+
The `index` argument is the ST table entry index the ST tag will be
95
+
written into. `pcie_tph_set_st_entry()` will figure out the proper
96
+
location of ST table, either in the MSI-X table or in the TPH Extended
97
+
Capability space, and write the Steering Tag into the ST entry pointed by
98
+
the `index` argument.
99
+
100
+
It is completely up to the driver to decide how to use these TPH
101
+
functions. For example a network device driver can use the TPH APIs above
102
+
to update the Steering Tag when interrupt affinity of a RX/TX queue has
103
+
been changed. Here is a sample code for IRQ affinity notifier:
104
+
105
+
.. code-block:: c
106
+
107
+
static void irq_affinity_notified(struct irq_affinity_notify *notify,
108
+
const cpumask_t *mask)
109
+
{
110
+
struct drv_irq *irq;
111
+
unsigned int cpu_id;
112
+
u16 tag;
113
+
114
+
irq = container_of(notify, struct drv_irq, affinity_notify);
115
+
cpumask_copy(irq->cpu_mask, mask);
116
+
117
+
/* Pick a right CPU as the target - here is just an example */
118
+
cpu_id = cpumask_first(irq->cpu_mask);
119
+
120
+
if (pcie_tph_get_cpu_st(irq->pdev, TPH_MEM_TYPE_VM, cpu_id,
121
+
&tag))
122
+
return;
123
+
124
+
if (pcie_tph_set_st_entry(irq->pdev, irq->msix_nr, tag))
125
+
return;
126
+
}
127
+
128
+
Disable TPH system-wide
129
+
-----------------------
130
+
131
+
There is a kernel command line option available to control TPH feature:
132
+
* "notph": TPH will be disabled for all endpoint devices.
+4
Documentation/admin-guide/kernel-parameters.txt
+4
Documentation/admin-guide/kernel-parameters.txt
···
4686
4686
nomio [S390] Do not use MIO instructions.
4687
4687
norid [S390] ignore the RID field and force use of
4688
4688
one PCI domain per PCI function
4689
+
notph [PCIE] If the PCIE_TPH kernel config parameter
4690
+
is enabled, this kernel boot option can be used
4691
+
to disable PCIe TLP Processing Hints support
4692
+
system-wide.
4689
4693
4690
4694
pcie_aspm= [PCIE] Forcibly enable or ignore PCIe Active State Power
4691
4695
Management.
+3
-2
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+3
-2
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
···
149
149
then:
150
150
properties:
151
151
clocks:
152
-
minItems: 4
152
+
minItems: 6
153
153
154
154
clock-names:
155
155
items:
···
178
178
then:
179
179
properties:
180
180
clocks:
181
-
minItems: 4
181
+
minItems: 6
182
182
183
183
clock-names:
184
184
items:
···
207
207
properties:
208
208
clocks:
209
209
minItems: 4
210
+
maxItems: 4
210
211
211
212
clock-names:
212
213
items:
+9
-2
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+9
-2
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
···
17
17
compatible:
18
18
const: microchip,pcie-host-1.0 # PolarFire
19
19
20
+
reg:
21
+
minItems: 3
22
+
23
+
reg-names:
24
+
minItems: 3
25
+
20
26
clocks:
21
27
description:
22
28
Fabric Interface Controllers, FICs, are the interface between the FPGA
···
68
62
pcie0: pcie@2030000000 {
69
63
compatible = "microchip,pcie-host-1.0";
70
64
reg = <0x0 0x70000000 0x0 0x08000000>,
71
-
<0x0 0x43000000 0x0 0x00010000>;
72
-
reg-names = "cfg", "apb";
65
+
<0x0 0x43008000 0x0 0x00002000>,
66
+
<0x0 0x4300a000 0x0 0x00002000>;
67
+
reg-names = "cfg", "bridge", "ctrl";
73
68
device_type = "pci";
74
69
#address-cells = <3>;
75
70
#size-cells = <2>;
+10
-4
Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml
+10
-4
Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml
···
18
18
19
19
properties:
20
20
reg:
21
-
maxItems: 2
21
+
maxItems: 3
22
+
minItems: 2
22
23
23
24
reg-names:
24
-
items:
25
-
- const: cfg
26
-
- const: apb
25
+
oneOf:
26
+
- items:
27
+
- const: cfg
28
+
- const: apb
29
+
- items:
30
+
- const: cfg
31
+
- const: bridge
32
+
- const: ctrl
27
33
28
34
interrupts:
29
35
minItems: 1
+4
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
+4
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
-4
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
-4
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
+3
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
+3
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
···
20
20
- const: qcom,pcie-sm8550
21
21
- items:
22
22
- enum:
23
+
- qcom,sar2130p-pcie
23
24
- qcom,pcie-sm8650
24
25
- const: qcom,pcie-sm8550
25
26
···
40
39
41
40
clocks:
42
41
minItems: 7
43
-
maxItems: 8
42
+
maxItems: 9
44
43
45
44
clock-names:
46
45
minItems: 7
···
53
52
- const: ddrss_sf_tbu # PCIe SF TBU clock
54
53
- const: noc_aggr # Aggre NoC PCIe AXI clock
55
54
- const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
55
+
- const: qmip_pcie_ahb # QMIP PCIe AHB clock
56
56
57
57
interrupts:
58
58
minItems: 8
+6
-3
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
+6
-3
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
···
47
47
48
48
interrupts:
49
49
minItems: 8
50
-
maxItems: 8
50
+
maxItems: 9
51
51
52
52
interrupt-names:
53
+
minItems: 8
53
54
items:
54
55
- const: msi0
55
56
- const: msi1
···
60
59
- const: msi5
61
60
- const: msi6
62
61
- const: msi7
62
+
- const: global
63
63
64
64
resets:
65
65
minItems: 1
···
132
130
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
133
131
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
134
132
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
135
-
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
133
+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
134
+
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
136
135
interrupt-names = "msi0", "msi1", "msi2", "msi3",
137
-
"msi4", "msi5", "msi6", "msi7";
136
+
"msi4", "msi5", "msi6", "msi7", "global";
138
137
#interrupt-cells = <1>;
139
138
interrupt-map-mask = <0 0 0 0x7>;
140
139
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+50
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+50
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
···
26
26
- qcom,pcie-ipq8064-v2
27
27
- qcom,pcie-ipq8074
28
28
- qcom,pcie-ipq8074-gen3
29
+
- qcom,pcie-ipq9574
29
30
- qcom,pcie-msm8996
30
31
- qcom,pcie-qcs404
31
32
- qcom,pcie-sdm845
···
165
164
enum:
166
165
- qcom,pcie-ipq6018
167
166
- qcom,pcie-ipq8074-gen3
167
+
- qcom,pcie-ipq9574
168
168
then:
169
169
properties:
170
170
reg:
···
407
405
compatible:
408
406
contains:
409
407
enum:
408
+
- qcom,pcie-ipq9574
409
+
then:
410
+
properties:
411
+
clocks:
412
+
minItems: 6
413
+
maxItems: 6
414
+
clock-names:
415
+
items:
416
+
- const: axi_m # AXI Master clock
417
+
- const: axi_s # AXI Slave clock
418
+
- const: axi_bridge
419
+
- const: rchng
420
+
- const: ahb
421
+
- const: aux
422
+
423
+
resets:
424
+
minItems: 8
425
+
maxItems: 8
426
+
reset-names:
427
+
items:
428
+
- const: pipe # PIPE reset
429
+
- const: sticky # Core Sticky reset
430
+
- const: axi_s_sticky # AXI Slave Sticky reset
431
+
- const: axi_s # AXI Slave reset
432
+
- const: axi_m_sticky # AXI Master Sticky reset
433
+
- const: axi_m # AXI Master reset
434
+
- const: aux # AUX Reset
435
+
- const: ahb # AHB Reset
436
+
437
+
interrupts:
438
+
minItems: 8
439
+
interrupt-names:
440
+
items:
441
+
- const: msi0
442
+
- const: msi1
443
+
- const: msi2
444
+
- const: msi3
445
+
- const: msi4
446
+
- const: msi5
447
+
- const: msi6
448
+
- const: msi7
449
+
450
+
- if:
451
+
properties:
452
+
compatible:
453
+
contains:
454
+
enum:
410
455
- qcom,pcie-qcs404
411
456
then:
412
457
properties:
···
559
510
- qcom,pcie-ipq8064v2
560
511
- qcom,pcie-ipq8074
561
512
- qcom,pcie-ipq8074-gen3
513
+
- qcom,pcie-ipq9574
562
514
- qcom,pcie-qcs404
563
515
then:
564
516
required:
-1
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
-1
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+7
Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
+7
Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
-1
Documentation/driver-api/driver-model/devres.rst
-1
Documentation/driver-api/driver-model/devres.rst
···
394
394
pcim_enable_device() : after success, some PCI ops become managed
395
395
pcim_iomap() : do iomap() on a single BAR
396
396
pcim_iomap_regions() : do request_region() and iomap() on multiple BARs
397
-
pcim_iomap_regions_request_all() : do request_region() on all and iomap() on multiple BARs
398
397
pcim_iomap_table() : array of mapped addresses indexed by BAR
399
398
pcim_iounmap() : do iounmap() on a single BAR
400
399
pcim_iounmap_regions() : do iounmap() and release_region() on multiple BARs
+3
Documentation/driver-api/pci/pci.rst
+3
Documentation/driver-api/pci/pci.rst
+17
-2
MAINTAINERS
+17
-2
MAINTAINERS
···
13927
13927
R: vattunuru@marvell.com
13928
13928
F: drivers/vdpa/octeon_ep/
13929
13929
13930
+
MARVELL OCTEON HOTPLUG DRIVER
13931
+
R: Shijith Thotton <sthotton@marvell.com>
13932
+
R: Vamsi Attunuru <vattunuru@marvell.com>
13933
+
S: Supported
13934
+
F: drivers/pci/hotplug/octep_hp.c
13935
+
13930
13936
MATROX FRAMEBUFFER DRIVER
13931
13937
L: linux-fbdev@vger.kernel.org
13932
13938
S: Orphan
···
18000
17994
L: linux-pci@vger.kernel.org
18001
17995
S: Maintained
18002
17996
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
18003
-
F: drivers/pci/pwrctl/*
18004
-
F: include/linux/pci-pwrctl.h
17997
+
F: drivers/pci/pwrctrl/*
17998
+
F: include/linux/pci-pwrctrl.h
18005
17999
18006
18000
PCI SUBSYSTEM
18007
18001
M: Bjorn Helgaas <bhelgaas@google.com>
···
18022
18016
F: include/linux/of_pci.h
18023
18017
F: include/linux/pci*
18024
18018
F: include/uapi/linux/pci*
18019
+
18020
+
PCIE BANDWIDTH CONTROLLER
18021
+
M: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
18022
+
L: linux-pci@vger.kernel.org
18023
+
S: Supported
18024
+
F: drivers/pci/pcie/bwctrl.c
18025
+
F: drivers/thermal/pcie_cooling.c
18026
+
F: include/linux/pci-bwctrl.h
18027
+
F: tools/testing/selftests/pcie_bwctrl/
18025
18028
18026
18029
PCIE DRIVER FOR AMAZON ANNAPURNA LABS
18027
18030
M: Jonathan Chocron <jonnyc@amazon.com>
+1
-1
arch/s390/pci/pci_bus.c
+1
-1
arch/s390/pci/pci_bus.c
+119
arch/x86/pci/acpi.c
+119
arch/x86/pci/acpi.c
···
250
250
pr_info("Please notify linux-pci@vger.kernel.org so future kernels can do this automatically\n");
251
251
}
252
252
253
+
/*
254
+
* Check if pdev is part of a PCIe switch that is directly below the
255
+
* specified bridge.
256
+
*/
257
+
static bool pcie_switch_directly_under(struct pci_dev *bridge,
258
+
struct pci_dev *pdev)
259
+
{
260
+
struct pci_dev *parent = pci_upstream_bridge(pdev);
261
+
262
+
/* If the device doesn't have a parent, it's not under anything */
263
+
if (!parent)
264
+
return false;
265
+
266
+
/*
267
+
* If the device has a PCIe type, check if it is below the
268
+
* corresponding PCIe switch components (if applicable). Then check
269
+
* if its upstream port is directly beneath the specified bridge.
270
+
*/
271
+
switch (pci_pcie_type(pdev)) {
272
+
case PCI_EXP_TYPE_UPSTREAM:
273
+
return parent == bridge;
274
+
275
+
case PCI_EXP_TYPE_DOWNSTREAM:
276
+
if (pci_pcie_type(parent) != PCI_EXP_TYPE_UPSTREAM)
277
+
return false;
278
+
parent = pci_upstream_bridge(parent);
279
+
return parent == bridge;
280
+
281
+
case PCI_EXP_TYPE_ENDPOINT:
282
+
if (pci_pcie_type(parent) != PCI_EXP_TYPE_DOWNSTREAM)
283
+
return false;
284
+
parent = pci_upstream_bridge(parent);
285
+
if (!parent || pci_pcie_type(parent) != PCI_EXP_TYPE_UPSTREAM)
286
+
return false;
287
+
parent = pci_upstream_bridge(parent);
288
+
return parent == bridge;
289
+
}
290
+
291
+
return false;
292
+
}
293
+
294
+
static bool pcie_has_usb4_host_interface(struct pci_dev *pdev)
295
+
{
296
+
struct fwnode_handle *fwnode;
297
+
298
+
/*
299
+
* For USB4, the tunneled PCIe Root or Downstream Ports are marked
300
+
* with the "usb4-host-interface" ACPI property, so we look for
301
+
* that first. This should cover most cases.
302
+
*/
303
+
fwnode = fwnode_find_reference(dev_fwnode(&pdev->dev),
304
+
"usb4-host-interface", 0);
305
+
if (!IS_ERR(fwnode)) {
306
+
fwnode_handle_put(fwnode);
307
+
return true;
308
+
}
309
+
310
+
/*
311
+
* Any integrated Thunderbolt 3/4 PCIe Root Ports from Intel
312
+
* before Alder Lake do not have the "usb4-host-interface"
313
+
* property so we use their PCI IDs instead. All these are
314
+
* tunneled. This list is not expected to grow.
315
+
*/
316
+
if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
317
+
switch (pdev->device) {
318
+
/* Ice Lake Thunderbolt 3 PCIe Root Ports */
319
+
case 0x8a1d:
320
+
case 0x8a1f:
321
+
case 0x8a21:
322
+
case 0x8a23:
323
+
/* Tiger Lake-LP Thunderbolt 4 PCIe Root Ports */
324
+
case 0x9a23:
325
+
case 0x9a25:
326
+
case 0x9a27:
327
+
case 0x9a29:
328
+
/* Tiger Lake-H Thunderbolt 4 PCIe Root Ports */
329
+
case 0x9a2b:
330
+
case 0x9a2d:
331
+
case 0x9a2f:
332
+
case 0x9a31:
333
+
return true;
334
+
}
335
+
}
336
+
337
+
return false;
338
+
}
339
+
340
+
bool arch_pci_dev_is_removable(struct pci_dev *pdev)
341
+
{
342
+
struct pci_dev *parent, *root;
343
+
344
+
/* pdev without a parent or Root Port is never tunneled */
345
+
parent = pci_upstream_bridge(pdev);
346
+
if (!parent)
347
+
return false;
348
+
root = pcie_find_root_port(pdev);
349
+
if (!root)
350
+
return false;
351
+
352
+
/* Internal PCIe devices are not tunneled */
353
+
if (!root->external_facing)
354
+
return false;
355
+
356
+
/* Anything directly behind a "usb4-host-interface" is tunneled */
357
+
if (pcie_has_usb4_host_interface(parent))
358
+
return true;
359
+
360
+
/*
361
+
* Check if this is a discrete Thunderbolt/USB4 controller that is
362
+
* directly behind the non-USB4 PCIe Root Port marked as
363
+
* "ExternalFacingPort". Those are not behind a PCIe tunnel.
364
+
*/
365
+
if (pcie_switch_directly_under(root, pdev))
366
+
return false;
367
+
368
+
/* PCIe devices after the discrete chip are tunneled */
369
+
return true;
370
+
}
371
+
253
372
#ifdef CONFIG_PCI_MMCONFIG
254
373
static int check_segment(u16 seg, struct device *dev, char *estr)
255
374
{
+1
-1
arch/x86/pci/fixup.c
+1
-1
arch/x86/pci/fixup.c
···
757
757
dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
758
758
res);
759
759
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
760
-
pci_bus_add_resource(dev->bus, res, 0);
760
+
pci_bus_add_resource(dev->bus, res);
761
761
}
762
762
763
763
base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
+4
-2
drivers/ata/acard-ahci.c
+4
-2
drivers/ata/acard-ahci.c
···
370
370
/* AHCI controllers often implement SFF compatible interface.
371
371
* Grab all PCI BARs just in case.
372
372
*/
373
-
rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
373
+
rc = pcim_request_all_regions(pdev, DRV_NAME);
374
374
if (rc == -EBUSY)
375
375
pcim_pin_device(pdev);
376
376
if (rc)
···
386
386
if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
387
387
pci_enable_msi(pdev);
388
388
389
-
hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
389
+
hpriv->mmio = pcim_iomap(pdev, AHCI_PCI_BAR, 0);
390
+
if (!hpriv->mmio)
391
+
return -ENOMEM;
390
392
391
393
/* save initial config */
392
394
ahci_save_initial_config(&pdev->dev, hpriv);
+4
-2
drivers/ata/ahci.c
+4
-2
drivers/ata/ahci.c
···
1869
1869
/* AHCI controllers often implement SFF compatible interface.
1870
1870
* Grab all PCI BARs just in case.
1871
1871
*/
1872
-
rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1872
+
rc = pcim_request_all_regions(pdev, DRV_NAME);
1873
1873
if (rc == -EBUSY)
1874
1874
pcim_pin_device(pdev);
1875
1875
if (rc)
···
1893
1893
if (ahci_sb600_enable_64bit(pdev))
1894
1894
hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1895
1895
1896
-
hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1896
+
hpriv->mmio = pcim_iomap(pdev, ahci_pci_bar, 0);
1897
+
if (!hpriv->mmio)
1898
+
return -ENOMEM;
1897
1899
1898
1900
/* detect remapped nvme devices */
1899
1901
ahci_remap_check(pdev, ahci_pci_bar, hpriv);
+8
-3
drivers/crypto/intel/qat/qat_420xx/adf_drv.c
+8
-3
drivers/crypto/intel/qat/qat_420xx/adf_drv.c
···
129
129
/* Find and map all the device's BARS */
130
130
bar_mask = pci_select_bars(pdev, IORESOURCE_MEM) & ADF_GEN4_BAR_MASK;
131
131
132
-
ret = pcim_iomap_regions_request_all(pdev, bar_mask, pci_name(pdev));
132
+
ret = pcim_request_all_regions(pdev, pci_name(pdev));
133
133
if (ret) {
134
-
dev_err(&pdev->dev, "Failed to map pci regions.\n");
134
+
dev_err(&pdev->dev, "Failed to request PCI regions.\n");
135
135
goto out_err;
136
136
}
137
137
138
138
i = 0;
139
139
for_each_set_bit(bar_nr, &bar_mask, PCI_STD_NUM_BARS) {
140
140
bar = &accel_pci_dev->pci_bars[i++];
141
-
bar->virt_addr = pcim_iomap_table(pdev)[bar_nr];
141
+
bar->virt_addr = pcim_iomap(pdev, bar_nr, 0);
142
+
if (!bar->virt_addr) {
143
+
dev_err(&pdev->dev, "Failed to ioremap PCI region.\n");
144
+
ret = -ENOMEM;
145
+
goto out_err;
146
+
}
142
147
}
143
148
144
149
pci_set_master(pdev);
+8
-3
drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
+8
-3
drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
···
131
131
/* Find and map all the device's BARS */
132
132
bar_mask = pci_select_bars(pdev, IORESOURCE_MEM) & ADF_GEN4_BAR_MASK;
133
133
134
-
ret = pcim_iomap_regions_request_all(pdev, bar_mask, pci_name(pdev));
134
+
ret = pcim_request_all_regions(pdev, pci_name(pdev));
135
135
if (ret) {
136
-
dev_err(&pdev->dev, "Failed to map pci regions.\n");
136
+
dev_err(&pdev->dev, "Failed to request PCI regions.\n");
137
137
goto out_err;
138
138
}
139
139
140
140
i = 0;
141
141
for_each_set_bit(bar_nr, &bar_mask, PCI_STD_NUM_BARS) {
142
142
bar = &accel_pci_dev->pci_bars[i++];
143
-
bar->virt_addr = pcim_iomap_table(pdev)[bar_nr];
143
+
bar->virt_addr = pcim_iomap(pdev, bar_nr, 0);
144
+
if (!bar->virt_addr) {
145
+
dev_err(&pdev->dev, "Failed to ioremap PCI region.\n");
146
+
ret = -ENOMEM;
147
+
goto out_err;
148
+
}
144
149
}
145
150
146
151
pci_set_master(pdev);
+9
-5
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+9
-5
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
···
739
739
dev_err(dev, "Unable to get usable DMA configuration\n");
740
740
goto clear_drvdata;
741
741
}
742
-
/* Map PF's configuration registers */
743
-
err = pcim_iomap_regions_request_all(pdev, 1 << PCI_PF_REG_BAR_NUM,
744
-
OTX2_CPT_DRV_NAME);
742
+
err = pcim_request_all_regions(pdev, OTX2_CPT_DRV_NAME);
745
743
if (err) {
746
-
dev_err(dev, "Couldn't get PCI resources 0x%x\n", err);
744
+
dev_err(dev, "Couldn't request PCI resources 0x%x\n", err);
747
745
goto clear_drvdata;
748
746
}
749
747
pci_set_master(pdev);
750
748
pci_set_drvdata(pdev, cptpf);
751
749
cptpf->pdev = pdev;
752
750
753
-
cptpf->reg_base = pcim_iomap_table(pdev)[PCI_PF_REG_BAR_NUM];
751
+
/* Map PF's configuration registers */
752
+
cptpf->reg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
753
+
if (!cptpf->reg_base) {
754
+
err = -ENOMEM;
755
+
dev_err(dev, "Couldn't ioremap PCI resource 0x%x\n", err);
756
+
goto clear_drvdata;
757
+
}
754
758
755
759
/* Check if AF driver is up, otherwise defer probe */
756
760
err = cpt_is_pf_usable(cptpf);
+9
-4
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+9
-4
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
···
358
358
dev_err(dev, "Unable to get usable DMA configuration\n");
359
359
goto clear_drvdata;
360
360
}
361
-
/* Map VF's configuration registers */
362
-
ret = pcim_iomap_regions_request_all(pdev, 1 << PCI_PF_REG_BAR_NUM,
363
-
OTX2_CPTVF_DRV_NAME);
361
+
362
+
ret = pcim_request_all_regions(pdev, OTX2_CPTVF_DRV_NAME);
364
363
if (ret) {
365
364
dev_err(dev, "Couldn't get PCI resources 0x%x\n", ret);
366
365
goto clear_drvdata;
···
368
369
pci_set_drvdata(pdev, cptvf);
369
370
cptvf->pdev = pdev;
370
371
371
-
cptvf->reg_base = pcim_iomap_table(pdev)[PCI_PF_REG_BAR_NUM];
372
+
/* Map VF's configuration registers */
373
+
cptvf->reg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
374
+
if (!cptvf->reg_base) {
375
+
ret = -ENOMEM;
376
+
dev_err(dev, "Couldn't ioremap PCI resource 0x%x\n", ret);
377
+
goto clear_drvdata;
378
+
}
372
379
373
380
otx2_cpt_set_hw_caps(pdev, &cptvf->cap_flag);
374
381
+4
-12
drivers/fpga/dfl-pci.c
+4
-12
drivers/fpga/dfl-pci.c
···
39
39
struct dfl_fpga_cdev *cdev; /* container device */
40
40
};
41
41
42
-
static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev)
43
-
{
44
-
if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME))
45
-
return NULL;
46
-
47
-
return pcim_iomap_table(pcidev)[0];
48
-
}
49
-
50
42
static int cci_pci_alloc_irq(struct pci_dev *pcidev)
51
43
{
52
44
int ret, nvec = pci_msix_vec_count(pcidev);
···
227
235
u64 v;
228
236
229
237
/* start to find Device Feature List from Bar 0 */
230
-
base = cci_pci_ioremap_bar0(pcidev);
231
-
if (!base)
232
-
return -ENOMEM;
238
+
base = pcim_iomap_region(pcidev, 0, DRV_NAME);
239
+
if (IS_ERR(base))
240
+
return PTR_ERR(base);
233
241
234
242
/*
235
243
* PF device has FME and Ports/AFUs, and VF device only has one
···
288
296
}
289
297
290
298
/* release I/O mappings for next step enumeration */
291
-
pcim_iounmap_regions(pcidev, BIT(0));
299
+
pcim_iounmap_region(pcidev, 0);
292
300
293
301
return ret;
294
302
}
+8
-7
drivers/gpio/gpio-merrifield.c
+8
-7
drivers/gpio/gpio-merrifield.c
···
78
78
if (retval)
79
79
return retval;
80
80
81
-
retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
82
-
if (retval)
83
-
return dev_err_probe(dev, retval, "I/O memory mapping error\n");
84
-
85
-
base = pcim_iomap_table(pdev)[1];
81
+
base = pcim_iomap_region(pdev, 1, pci_name(pdev));
82
+
if (IS_ERR(base))
83
+
return dev_err_probe(dev, PTR_ERR(base), "I/O memory mapping error\n");
86
84
87
85
irq_base = readl(base + 0 * sizeof(u32));
88
86
gpio_base = readl(base + 1 * sizeof(u32));
89
87
90
88
/* Release the IO mapping, since we already get the info from BAR1 */
91
-
pcim_iounmap_regions(pdev, BIT(1));
89
+
pcim_iounmap_region(pdev, 1);
92
90
93
91
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
94
92
if (!priv)
95
93
return -ENOMEM;
96
94
97
95
priv->dev = dev;
98
-
priv->reg_base = pcim_iomap_table(pdev)[0];
96
+
priv->reg_base = pcim_iomap_region(pdev, 0, pci_name(pdev));
97
+
if (IS_ERR(priv->reg_base))
98
+
return dev_err_probe(dev, PTR_ERR(priv->reg_base),
99
+
"I/O memory mapping error\n");
99
100
100
101
priv->pin_info.pin_ranges = mrfld_gpio_ranges;
101
102
priv->pin_info.nranges = ARRAY_SIZE(mrfld_gpio_ranges);
+7
-2
drivers/hwtracing/intel_th/pci.c
+7
-2
drivers/hwtracing/intel_th/pci.c
···
23
23
TH_PCI_RTIT_BAR = 4,
24
24
};
25
25
26
-
#define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) | BIT(TH_PCI_STH_SW_BAR))
27
26
28
27
#define PCI_REG_NPKDSC 0x80
29
28
#define NPKDSC_TSACT BIT(5)
···
82
83
if (err)
83
84
return err;
84
85
85
-
err = pcim_iomap_regions_request_all(pdev, BAR_MASK, DRIVER_NAME);
86
+
err = pcim_request_all_regions(pdev, DRIVER_NAME);
86
87
if (err)
87
88
return err;
89
+
90
+
if (!pcim_iomap(pdev, TH_PCI_CONFIG_BAR, 0))
91
+
return -ENOMEM;
92
+
93
+
if (!pcim_iomap(pdev, TH_PCI_STH_SW_BAR, 0))
94
+
return -ENOMEM;
88
95
89
96
if (pdev->resource[TH_PCI_RTIT_BAR].start) {
90
97
resource[TH_MMIO_RTIT] = pdev->resource[TH_PCI_RTIT_BAR];
+3
-4
drivers/net/ethernet/cavium/common/cavium_ptp.c
+3
-4
drivers/net/ethernet/cavium/common/cavium_ptp.c
···
239
239
if (err)
240
240
goto error_free;
241
241
242
-
err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev));
242
+
clock->reg_base = pcim_iomap_region(pdev, PCI_PTP_BAR_NO, pci_name(pdev));
243
+
err = PTR_ERR_OR_ZERO(clock->reg_base);
243
244
if (err)
244
245
goto error_free;
245
-
246
-
clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
247
246
248
247
spin_lock_init(&clock->spin_lock);
249
248
···
291
292
clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
292
293
clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
293
294
writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
294
-
pcim_iounmap_regions(pdev, 1 << PCI_PTP_BAR_NO);
295
+
pcim_iounmap_region(pdev, PCI_PTP_BAR_NO);
295
296
296
297
error_free:
297
298
devm_kfree(dev, clock);
+4
-12
drivers/net/wireless/intel/iwlwifi/pcie/trans.c
+4
-12
drivers/net/wireless/intel/iwlwifi/pcie/trans.c
···
3535
3535
struct iwl_trans_pcie *trans_pcie, **priv;
3536
3536
struct iwl_trans *trans;
3537
3537
int ret, addr_size;
3538
-
void __iomem * const *table;
3539
3538
u32 bar0;
3540
3539
3541
3540
/* reassign our BAR 0 if invalid due to possible runtime PM races */
···
3660
3661
}
3661
3662
}
3662
3663
3663
-
ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3664
+
ret = pcim_request_all_regions(pdev, DRV_NAME);
3664
3665
if (ret) {
3665
-
dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3666
+
dev_err(&pdev->dev, "Requesting all PCI BARs failed.\n");
3666
3667
goto out_no_pci;
3667
3668
}
3668
3669
3669
-
table = pcim_iomap_table(pdev);
3670
-
if (!table) {
3671
-
dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3672
-
ret = -ENOMEM;
3673
-
goto out_no_pci;
3674
-
}
3675
-
3676
-
trans_pcie->hw_base = table[0];
3670
+
trans_pcie->hw_base = pcim_iomap(pdev, 0, 0);
3677
3671
if (!trans_pcie->hw_base) {
3678
-
dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
3672
+
dev_err(&pdev->dev, "Could not ioremap PCI BAR 0.\n");
3679
3673
ret = -ENODEV;
3680
3674
goto out_no_pci;
3681
3675
}
+9
-4
drivers/ntb/hw/idt/ntb_hw_idt.c
+9
-4
drivers/ntb/hw/idt/ntb_hw_idt.c
···
2671
2671
*/
2672
2672
pci_set_master(pdev);
2673
2673
2674
-
/* Request all BARs resources and map BAR0 only */
2675
-
ret = pcim_iomap_regions_request_all(pdev, 1, NTB_NAME);
2674
+
/* Request all BARs resources */
2675
+
ret = pcim_request_all_regions(pdev, NTB_NAME);
2676
2676
if (ret != 0) {
2677
2677
dev_err(&pdev->dev, "Failed to request resources\n");
2678
2678
goto err_clear_master;
2679
2679
}
2680
2680
2681
-
/* Retrieve virtual address of BAR0 - PCI configuration space */
2682
-
ndev->cfgspc = pcim_iomap_table(pdev)[0];
2681
+
/* ioremap BAR0 - PCI configuration space */
2682
+
ndev->cfgspc = pcim_iomap(pdev, 0, 0);
2683
+
if (!ndev->cfgspc) {
2684
+
dev_err(&pdev->dev, "Failed to ioremap BAR 0\n");
2685
+
ret = -ENOMEM;
2686
+
goto err_clear_master;
2687
+
}
2683
2688
2684
2689
/* Put the IDT driver data pointer to the PCI-device private pointer */
2685
2690
pci_set_drvdata(pdev, ndev);
+10
-1
drivers/pci/Kconfig
+10
-1
drivers/pci/Kconfig
···
173
173
174
174
If unsure, say N.
175
175
176
+
config PCIE_TPH
177
+
bool "TLP Processing Hints"
178
+
help
179
+
This option adds support for PCIe TLP Processing Hints (TPH).
180
+
TPH allows endpoint devices to provide optimization hints, such as
181
+
desired caching behavior, for requests that target memory space.
182
+
These hints, called Steering Tags, can empower the system hardware
183
+
to optimize the utilization of platform resources.
184
+
176
185
config PCI_P2PDMA
177
186
bool "PCI peer-to-peer transfer support"
178
187
depends on ZONE_DEVICE
···
314
305
source "drivers/pci/controller/Kconfig"
315
306
source "drivers/pci/endpoint/Kconfig"
316
307
source "drivers/pci/switch/Kconfig"
317
-
source "drivers/pci/pwrctl/Kconfig"
308
+
source "drivers/pci/pwrctrl/Kconfig"
318
309
319
310
endif
+2
-1
drivers/pci/Makefile
+2
-1
drivers/pci/Makefile
···
9
9
10
10
obj-$(CONFIG_PCI) += msi/
11
11
obj-$(CONFIG_PCI) += pcie/
12
-
obj-$(CONFIG_PCI) += pwrctl/
12
+
obj-$(CONFIG_PCI) += pwrctrl/
13
13
14
14
ifdef CONFIG_PCI
15
15
obj-$(CONFIG_PROC_FS) += proc.o
···
36
36
obj-$(CONFIG_PCI_DOE) += doe.o
37
37
obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) += of_property.o
38
38
obj-$(CONFIG_PCI_NPEM) += npem.o
39
+
obj-$(CONFIG_PCIE_TPH) += tph.o
39
40
40
41
# Endpoint library must be initialized before its users
41
42
obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
+89
-45
drivers/pci/bus.c
+89
-45
drivers/pci/bus.c
···
13
13
#include <linux/ioport.h>
14
14
#include <linux/of.h>
15
15
#include <linux/of_platform.h>
16
+
#include <linux/platform_device.h>
16
17
#include <linux/proc_fs.h>
17
18
#include <linux/slab.h>
18
19
19
20
#include "pci.h"
21
+
22
+
/*
23
+
* The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
24
+
* to P2P or CardBus bridge windows) go in a table. Additional ones (for
25
+
* buses below host bridges or subtractive decode bridges) go in the list.
26
+
* Use pci_bus_for_each_resource() to iterate through all the resources.
27
+
*/
28
+
29
+
struct pci_bus_resource {
30
+
struct list_head list;
31
+
struct resource *res;
32
+
};
20
33
21
34
void pci_add_resource_offset(struct list_head *resources, struct resource *res,
22
35
resource_size_t offset)
···
59
46
}
60
47
EXPORT_SYMBOL(pci_free_resource_list);
61
48
62
-
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
63
-
unsigned int flags)
49
+
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res)
64
50
{
65
51
struct pci_bus_resource *bus_res;
66
52
···
70
58
}
71
59
72
60
bus_res->res = res;
73
-
bus_res->flags = flags;
74
61
list_add_tail(&bus_res->list, &bus->resources);
75
62
}
76
63
···
331
320
332
321
void __weak pcibios_bus_add_device(struct pci_dev *pdev) { }
333
322
323
+
/*
324
+
* Create pwrctrl devices (if required) for the PCI devices to handle the power
325
+
* state.
326
+
*/
327
+
static void pci_pwrctrl_create_devices(struct pci_dev *dev)
328
+
{
329
+
struct device_node *np = dev_of_node(&dev->dev);
330
+
struct device *parent = &dev->dev;
331
+
struct platform_device *pdev;
332
+
333
+
/*
334
+
* First ensure that we are starting from a PCI bridge and it has a
335
+
* corresponding devicetree node.
336
+
*/
337
+
if (np && pci_is_bridge(dev)) {
338
+
/*
339
+
* Now look for the child PCI device nodes and create pwrctrl
340
+
* devices for them. The pwrctrl device drivers will manage the
341
+
* power state of the devices.
342
+
*/
343
+
for_each_available_child_of_node_scoped(np, child) {
344
+
/*
345
+
* First check whether the pwrctrl device really
346
+
* needs to be created or not. This is decided
347
+
* based on at least one of the power supplies
348
+
* being defined in the devicetree node of the
349
+
* device.
350
+
*/
351
+
if (!of_pci_supply_present(child)) {
352
+
pci_dbg(dev, "skipping OF node: %s\n", child->name);
353
+
return;
354
+
}
355
+
356
+
/* Now create the pwrctrl device */
357
+
pdev = of_platform_device_create(child, NULL, parent);
358
+
if (!pdev)
359
+
pci_err(dev, "failed to create OF node: %s\n", child->name);
360
+
}
361
+
}
362
+
}
363
+
334
364
/**
335
365
* pci_bus_add_device - start driver for a single device
336
366
* @dev: device to add
···
381
329
void pci_bus_add_device(struct pci_dev *dev)
382
330
{
383
331
struct device_node *dn = dev->dev.of_node;
332
+
struct platform_device *pdev;
384
333
int retval;
385
334
386
335
/*
···
396
343
pci_proc_attach_device(dev);
397
344
pci_bridge_d3_update(dev);
398
345
346
+
pci_pwrctrl_create_devices(dev);
347
+
348
+
/*
349
+
* If the PCI device is associated with a pwrctrl device with a
350
+
* power supply, create a device link between the PCI device and
351
+
* pwrctrl device. This ensures that pwrctrl drivers are probed
352
+
* before PCI client drivers.
353
+
*/
354
+
pdev = of_find_device_by_node(dn);
355
+
if (pdev && of_pci_supply_present(dn)) {
356
+
if (!device_link_add(&dev->dev, &pdev->dev,
357
+
DL_FLAG_AUTOREMOVE_CONSUMER))
358
+
pci_err(dev, "failed to add device link to power control device %s\n",
359
+
pdev->name);
360
+
}
361
+
399
362
dev->match_driver = !dn || of_device_is_available(dn);
400
363
retval = device_attach(&dev->dev);
401
364
if (retval < 0 && retval != -EPROBE_DEFER)
402
365
pci_warn(dev, "device attach failed (%d)\n", retval);
403
366
404
-
pci_dev_assign_added(dev, true);
405
-
406
-
if (dev_of_node(&dev->dev) && pci_is_bridge(dev)) {
407
-
retval = of_platform_populate(dev_of_node(&dev->dev), NULL, NULL,
408
-
&dev->dev);
409
-
if (retval)
410
-
pci_err(dev, "failed to populate child OF nodes (%d)\n",
411
-
retval);
412
-
}
367
+
pci_dev_assign_added(dev);
413
368
}
414
369
EXPORT_SYMBOL_GPL(pci_bus_add_device);
415
370
···
450
389
}
451
390
EXPORT_SYMBOL(pci_bus_add_devices);
452
391
453
-
static void __pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
454
-
void *userdata, bool locked)
392
+
static int __pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
393
+
void *userdata)
455
394
{
456
395
struct pci_dev *dev;
457
-
struct pci_bus *bus;
458
-
struct list_head *next;
459
-
int retval;
396
+
int ret = 0;
460
397
461
-
bus = top;
462
-
if (!locked)
463
-
down_read(&pci_bus_sem);
464
-
next = top->devices.next;
465
-
for (;;) {
466
-
if (next == &bus->devices) {
467
-
/* end of this bus, go up or finish */
468
-
if (bus == top)
469
-
break;
470
-
next = bus->self->bus_list.next;
471
-
bus = bus->self->bus;
472
-
continue;
473
-
}
474
-
dev = list_entry(next, struct pci_dev, bus_list);
475
-
if (dev->subordinate) {
476
-
/* this is a pci-pci bridge, do its devices next */
477
-
next = dev->subordinate->devices.next;
478
-
bus = dev->subordinate;
479
-
} else
480
-
next = dev->bus_list.next;
481
-
482
-
retval = cb(dev, userdata);
483
-
if (retval)
398
+
list_for_each_entry(dev, &top->devices, bus_list) {
399
+
ret = cb(dev, userdata);
400
+
if (ret)
484
401
break;
402
+
if (dev->subordinate) {
403
+
ret = __pci_walk_bus(dev->subordinate, cb, userdata);
404
+
if (ret)
405
+
break;
406
+
}
485
407
}
486
-
if (!locked)
487
-
up_read(&pci_bus_sem);
408
+
return ret;
488
409
}
489
410
490
411
/**
···
484
441
*/
485
442
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), void *userdata)
486
443
{
487
-
__pci_walk_bus(top, cb, userdata, false);
444
+
down_read(&pci_bus_sem);
445
+
__pci_walk_bus(top, cb, userdata);
446
+
up_read(&pci_bus_sem);
488
447
}
489
448
EXPORT_SYMBOL_GPL(pci_walk_bus);
490
449
···
494
449
{
495
450
lockdep_assert_held(&pci_bus_sem);
496
451
497
-
__pci_walk_bus(top, cb, userdata, true);
452
+
__pci_walk_bus(top, cb, userdata);
498
453
}
499
-
EXPORT_SYMBOL_GPL(pci_walk_bus_locked);
500
454
501
455
struct pci_bus *pci_bus_get(struct pci_bus *bus)
502
456
{
+24
-15
drivers/pci/controller/cadence/pci-j721e.c
+24
-15
drivers/pci/controller/cadence/pci-j721e.c
···
386
386
.max_lanes = 4,
387
387
};
388
388
389
+
static const struct j721e_pcie_data j722s_pcie_rc_data = {
390
+
.mode = PCI_MODE_RC,
391
+
.linkdown_irq_regfield = J7200_LINK_DOWN,
392
+
.byte_access_allowed = true,
393
+
.max_lanes = 1,
394
+
};
395
+
389
396
static const struct of_device_id of_j721e_pcie_match[] = {
390
397
{
391
398
.compatible = "ti,j721e-pcie-host",
···
425
418
{
426
419
.compatible = "ti,j784s4-pcie-ep",
427
420
.data = &j784s4_pcie_ep_data,
421
+
},
422
+
{
423
+
.compatible = "ti,j722s-pcie-host",
424
+
.data = &j722s_pcie_rc_data,
428
425
},
429
426
{},
430
427
};
···
583
572
pcie->refclk = clk;
584
573
585
574
/*
586
-
* The "Power Sequencing and Reset Signal Timings" table of the
587
-
* PCI Express Card Electromechanical Specification, Revision
588
-
* 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
589
-
* should be deasserted after minimum of 100us once REFCLK is
590
-
* stable. The REFCLK to the connector in RC mode is selected
591
-
* while enabling the PHY. So deassert PERST# after 100 us.
575
+
* Section 2.2 of the PCI Express Card Electromechanical
576
+
* Specification (Revision 5.1) mandates that the deassertion
577
+
* of the PERST# signal should be delayed by 100 ms (TPVPERL).
578
+
* This shall ensure that the power and the reference clock
579
+
* are stable.
592
580
*/
593
581
if (gpiod) {
594
-
fsleep(PCIE_T_PERST_CLK_US);
582
+
msleep(PCIE_T_PVPERL_MS);
595
583
gpiod_set_value_cansleep(gpiod, 1);
596
584
}
597
585
···
681
671
return ret;
682
672
683
673
/*
684
-
* The "Power Sequencing and Reset Signal Timings" table of the
685
-
* PCI Express Card Electromechanical Specification, Revision
686
-
* 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
687
-
* should be deasserted after minimum of 100us once REFCLK is
688
-
* stable. The REFCLK to the connector in RC mode is selected
689
-
* while enabling the PHY. So deassert PERST# after 100 us.
674
+
* Section 2.2 of the PCI Express Card Electromechanical
675
+
* Specification (Revision 5.1) mandates that the deassertion
676
+
* of the PERST# signal should be delayed by 100 ms (TPVPERL).
677
+
* This shall ensure that the power and the reference clock
678
+
* are stable.
690
679
*/
691
680
if (pcie->reset_gpio) {
692
-
fsleep(PCIE_T_PERST_CLK_US);
681
+
msleep(PCIE_T_PVPERL_MS);
693
682
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
694
683
}
695
684
···
721
712
722
713
static struct platform_driver j721e_pcie_driver = {
723
714
.probe = j721e_pcie_probe,
724
-
.remove_new = j721e_pcie_remove,
715
+
.remove = j721e_pcie_remove,
725
716
.driver = {
726
717
.name = "j721e-pcie",
727
718
.of_match_table = of_j721e_pcie_match,
+2
-2
drivers/pci/controller/cadence/pcie-cadence.c
+2
-2
drivers/pci/controller/cadence/pcie-cadence.c
···
197
197
198
198
phy_count = of_property_count_strings(np, "phy-names");
199
199
if (phy_count < 1) {
200
-
dev_err(dev, "no phy-names. PHY will not be initialized\n");
200
+
dev_info(dev, "no \"phy-names\" property found; PHY will not be initialized\n");
201
201
pcie->phy_count = 0;
202
202
return 0;
203
203
}
···
260
260
261
261
ret = cdns_pcie_enable_phy(pcie);
262
262
if (ret) {
263
-
dev_err(dev, "failed to enable phy\n");
263
+
dev_err(dev, "failed to enable PHY\n");
264
264
return ret;
265
265
}
266
266
+1
-1
drivers/pci/controller/dwc/pci-exynos.c
+1
-1
drivers/pci/controller/dwc/pci-exynos.c
+46
-11
drivers/pci/controller/dwc/pci-imx6.c
+46
-11
drivers/pci/controller/dwc/pci-imx6.c
···
82
82
#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
83
83
#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
84
84
#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8)
85
+
/*
86
+
* Because of ERR005723 (PCIe does not support L2 power down) we need to
87
+
* workaround suspend resume on some devices which are affected by this errata.
88
+
*/
89
+
#define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9)
85
90
86
91
#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
87
92
···
1242
1237
return 0;
1243
1238
1244
1239
imx_pcie_msi_save_restore(imx_pcie, true);
1245
-
imx_pcie_pm_turnoff(imx_pcie);
1246
-
imx_pcie_stop_link(imx_pcie->pci);
1247
-
imx_pcie_host_exit(pp);
1240
+
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) {
1241
+
/*
1242
+
* The minimum for a workaround would be to set PERST# and to
1243
+
* set the PCIE_TEST_PD flag. However, we can also disable the
1244
+
* clock which saves some power.
1245
+
*/
1246
+
imx_pcie_assert_core_reset(imx_pcie);
1247
+
imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
1248
+
} else {
1249
+
imx_pcie_pm_turnoff(imx_pcie);
1250
+
imx_pcie_stop_link(imx_pcie->pci);
1251
+
imx_pcie_host_exit(pp);
1252
+
}
1248
1253
1249
1254
return 0;
1250
1255
}
···
1268
1253
if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
1269
1254
return 0;
1270
1255
1271
-
ret = imx_pcie_host_init(pp);
1272
-
if (ret)
1273
-
return ret;
1274
-
imx_pcie_msi_save_restore(imx_pcie, false);
1275
-
dw_pcie_setup_rc(pp);
1256
+
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) {
1257
+
ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true);
1258
+
if (ret)
1259
+
return ret;
1260
+
ret = imx_pcie_deassert_core_reset(imx_pcie);
1261
+
if (ret)
1262
+
return ret;
1263
+
/*
1264
+
* Using PCIE_TEST_PD seems to disable MSI and powers down the
1265
+
* root complex. This is why we have to setup the rc again and
1266
+
* why we have to restore the MSI register.
1267
+
*/
1268
+
ret = dw_pcie_setup_rc(&imx_pcie->pci->pp);
1269
+
if (ret)
1270
+
return ret;
1271
+
imx_pcie_msi_save_restore(imx_pcie, false);
1272
+
} else {
1273
+
ret = imx_pcie_host_init(pp);
1274
+
if (ret)
1275
+
return ret;
1276
+
imx_pcie_msi_save_restore(imx_pcie, false);
1277
+
dw_pcie_setup_rc(pp);
1276
1278
1277
-
if (imx_pcie->link_is_up)
1278
-
imx_pcie_start_link(imx_pcie->pci);
1279
+
if (imx_pcie->link_is_up)
1280
+
imx_pcie_start_link(imx_pcie->pci);
1281
+
}
1279
1282
1280
1283
return 0;
1281
1284
}
···
1518
1485
[IMX6Q] = {
1519
1486
.variant = IMX6Q,
1520
1487
.flags = IMX_PCIE_FLAG_IMX_PHY |
1521
-
IMX_PCIE_FLAG_IMX_SPEED_CHANGE,
1488
+
IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
1489
+
IMX_PCIE_FLAG_BROKEN_SUSPEND |
1490
+
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1522
1491
.dbi_length = 0x200,
1523
1492
.gpr = "fsl,imx6q-iomuxc-gpr",
1524
1493
.clk_names = imx6q_clks,
+13
-1
drivers/pci/controller/dwc/pci-keystone.c
+13
-1
drivers/pci/controller/dwc/pci-keystone.c
···
455
455
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
456
456
u32 reg;
457
457
458
+
/*
459
+
* Checking whether the link is up here is a last line of defense
460
+
* against platforms that forward errors on the system bus as
461
+
* SError upon PCI configuration transactions issued when the link
462
+
* is down. This check is racy by definition and does not stop
463
+
* the system from triggering an SError if the link goes down
464
+
* after this check is performed.
465
+
*/
466
+
if (!dw_pcie_link_up(pci))
467
+
return NULL;
468
+
458
469
reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
459
470
CFG_FUNC(PCI_FUNC(devfn));
460
471
if (!pci_is_root_bus(bus->parent))
···
1104
1093
1105
1094
static const struct ks_pcie_of_data ks_pcie_rc_of_data = {
1106
1095
.host_ops = &ks_pcie_host_ops,
1096
+
.mode = DW_PCIE_RC_TYPE,
1107
1097
.version = DW_PCIE_VER_365A,
1108
1098
};
1109
1099
···
1375
1363
1376
1364
static struct platform_driver ks_pcie_driver = {
1377
1365
.probe = ks_pcie_probe,
1378
-
.remove_new = ks_pcie_remove,
1366
+
.remove = ks_pcie_remove,
1379
1367
.driver = {
1380
1368
.name = "keystone-pcie",
1381
1369
.of_match_table = ks_pcie_of_match,
+1
-1
drivers/pci/controller/dwc/pcie-bt1.c
+1
-1
drivers/pci/controller/dwc/pcie-bt1.c
+27
-11
drivers/pci/controller/dwc/pcie-designware-ep.c
+27
-11
drivers/pci/controller/dwc/pcie-designware-ep.c
···
268
268
return -EINVAL;
269
269
}
270
270
271
+
static u64 dw_pcie_ep_align_addr(struct pci_epc *epc, u64 pci_addr,
272
+
size_t *pci_size, size_t *offset)
273
+
{
274
+
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
275
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
276
+
u64 mask = pci->region_align - 1;
277
+
size_t ofst = pci_addr & mask;
278
+
279
+
*pci_size = ALIGN(ofst + *pci_size, epc->mem->window.page_size);
280
+
*offset = ofst;
281
+
282
+
return pci_addr & ~mask;
283
+
}
284
+
271
285
static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
272
286
phys_addr_t addr)
273
287
{
···
294
280
if (ret < 0)
295
281
return;
296
282
283
+
ep->outbound_addr[atu_index] = 0;
297
284
dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, atu_index);
298
285
clear_bit(atu_index, ep->ob_window_map);
299
286
}
···
459
444
.write_header = dw_pcie_ep_write_header,
460
445
.set_bar = dw_pcie_ep_set_bar,
461
446
.clear_bar = dw_pcie_ep_clear_bar,
447
+
.align_addr = dw_pcie_ep_align_addr,
462
448
.map_addr = dw_pcie_ep_map_addr,
463
449
.unmap_addr = dw_pcie_ep_unmap_addr,
464
450
.set_msi = dw_pcie_ep_set_msi,
···
504
488
u32 msg_addr_lower, msg_addr_upper, reg;
505
489
struct dw_pcie_ep_func *ep_func;
506
490
struct pci_epc *epc = ep->epc;
507
-
unsigned int aligned_offset;
491
+
size_t map_size = sizeof(u32);
492
+
size_t offset;
508
493
u16 msg_ctrl, msg_data;
509
494
bool has_upper;
510
495
u64 msg_addr;
···
533
516
}
534
517
msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
535
518
536
-
aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
537
-
msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
519
+
msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset);
538
520
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
539
-
epc->mem->window.page_size);
521
+
map_size);
540
522
if (ret)
541
523
return ret;
542
524
543
-
writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
525
+
writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);
544
526
545
527
dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
546
528
···
590
574
struct pci_epf_msix_tbl *msix_tbl;
591
575
struct dw_pcie_ep_func *ep_func;
592
576
struct pci_epc *epc = ep->epc;
577
+
size_t map_size = sizeof(u32);
578
+
size_t offset;
593
579
u32 reg, msg_data, vec_ctrl;
594
-
unsigned int aligned_offset;
595
580
u32 tbl_offset;
596
581
u64 msg_addr;
597
582
int ret;
···
617
600
return -EPERM;
618
601
}
619
602
620
-
aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
621
-
msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
603
+
msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset);
622
604
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
623
-
epc->mem->window.page_size);
605
+
map_size);
624
606
if (ret)
625
607
return ret;
626
608
627
-
writel(msg_data, ep->msi_mem + aligned_offset);
609
+
writel(msg_data, ep->msi_mem + offset);
628
610
629
611
dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
630
612
···
705
689
* for 1 MB BAR size only.
706
690
*/
707
691
for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
708
-
dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
692
+
dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4));
709
693
}
710
694
711
695
dw_pcie_setup(pci);
+2
-2
drivers/pci/controller/dwc/pcie-designware-host.c
+2
-2
drivers/pci/controller/dwc/pcie-designware-host.c
···
474
474
475
475
if (pci_msi_enabled()) {
476
476
pp->has_msi_ctrl = !(pp->ops->msi_init ||
477
-
of_property_read_bool(np, "msi-parent") ||
478
-
of_property_read_bool(np, "msi-map"));
477
+
of_property_present(np, "msi-parent") ||
478
+
of_property_present(np, "msi-map"));
479
479
480
480
/*
481
481
* For the has_msi_ctrl case the default assignment is handled
+1
-1
drivers/pci/controller/dwc/pcie-histb.c
+1
-1
drivers/pci/controller/dwc/pcie-histb.c
+1
-1
drivers/pci/controller/dwc/pcie-intel-gw.c
+1
-1
drivers/pci/controller/dwc/pcie-intel-gw.c
+1
-1
drivers/pci/controller/dwc/pcie-kirin.c
+1
-1
drivers/pci/controller/dwc/pcie-kirin.c
+5
-3
drivers/pci/controller/dwc/pcie-qcom-ep.c
+5
-3
drivers/pci/controller/dwc/pcie-qcom-ep.c
···
396
396
return ret;
397
397
}
398
398
399
+
/* Perform cleanup that requires refclk */
400
+
pci_epc_deinit_notify(pci->ep.epc);
401
+
dw_pcie_ep_cleanup(&pci->ep);
402
+
399
403
/* Assert WAKE# to RC to indicate device is ready */
400
404
gpiod_set_value_cansleep(pcie_ep->wake, 1);
401
405
usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
···
544
540
{
545
541
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
546
542
547
-
pci_epc_deinit_notify(pci->ep.epc);
548
-
dw_pcie_ep_cleanup(&pci->ep);
549
543
qcom_pcie_disable_resources(pcie_ep);
550
544
pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
551
545
}
···
939
937
940
938
static struct platform_driver qcom_pcie_ep_driver = {
941
939
.probe = qcom_pcie_ep_probe,
942
-
.remove_new = qcom_pcie_ep_remove,
940
+
.remove = qcom_pcie_ep_remove,
943
941
.driver = {
944
942
.name = "qcom-pcie-ep",
945
943
.of_match_table = qcom_pcie_ep_match,
+16
-3
drivers/pci/controller/dwc/pcie-qcom.c
+16
-3
drivers/pci/controller/dwc/pcie-qcom.c
···
133
133
134
134
/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
135
135
#define PARF_INT_ALL_LINK_UP BIT(13)
136
+
#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
136
137
137
138
/* PARF_NO_SNOOP_OVERIDE register fields */
138
139
#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
···
1365
1364
.config_sid = qcom_pcie_config_sid_1_9_0,
1366
1365
};
1367
1366
1367
+
/* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */
1368
+
static const struct qcom_pcie_ops ops_1_21_0 = {
1369
+
.get_resources = qcom_pcie_get_resources_2_7_0,
1370
+
.init = qcom_pcie_init_2_7_0,
1371
+
.post_init = qcom_pcie_post_init_2_7_0,
1372
+
.host_post_init = qcom_pcie_host_post_init_2_7_0,
1373
+
.deinit = qcom_pcie_deinit_2_7_0,
1374
+
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1375
+
};
1376
+
1368
1377
/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
1369
1378
static const struct qcom_pcie_ops ops_2_9_0 = {
1370
1379
.get_resources = qcom_pcie_get_resources_2_9_0,
···
1422
1411
};
1423
1412
1424
1413
static const struct qcom_pcie_cfg cfg_sc8280xp = {
1425
-
.ops = &ops_1_9_0,
1414
+
.ops = &ops_1_21_0,
1426
1415
.no_l0s = true,
1427
1416
};
1428
1417
···
1727
1716
goto err_host_deinit;
1728
1717
}
1729
1718
1730
-
writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK);
1719
+
writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7,
1720
+
pcie->parf + PARF_INT_ALL_MASK);
1731
1721
}
1732
1722
1733
1723
qcom_pcie_icc_opp_update(pcie);
···
1840
1828
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1841
1829
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1842
1830
{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1831
+
{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
1843
1832
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1844
1833
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1845
1834
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
···
1856
1843
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1857
1844
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1858
1845
{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1859
-
{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
1846
+
{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
1860
1847
{ }
1861
1848
};
1862
1849
+1
-1
drivers/pci/controller/dwc/pcie-rcar-gen4.c
+1
-1
drivers/pci/controller/dwc/pcie-rcar-gen4.c
+5
-4
drivers/pci/controller/dwc/pcie-tegra194.c
+5
-4
drivers/pci/controller/dwc/pcie-tegra194.c
···
1704
1704
if (ret)
1705
1705
dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1706
1706
1707
-
pci_epc_deinit_notify(pcie->pci.ep.epc);
1708
-
dw_pcie_ep_cleanup(&pcie->pci.ep);
1709
-
1710
1707
reset_control_assert(pcie->core_rst);
1711
1708
1712
1709
tegra_pcie_disable_phy(pcie);
···
1781
1784
dev_err(dev, "Failed to enable PHY: %d\n", ret);
1782
1785
goto fail_phy;
1783
1786
}
1787
+
1788
+
/* Perform cleanup that requires refclk */
1789
+
pci_epc_deinit_notify(pcie->pci.ep.epc);
1790
+
dw_pcie_ep_cleanup(&pcie->pci.ep);
1784
1791
1785
1792
/* Clear any stale interrupt statuses */
1786
1793
appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
···
2494
2493
2495
2494
static struct platform_driver tegra_pcie_dw_driver = {
2496
2495
.probe = tegra_pcie_dw_probe,
2497
-
.remove_new = tegra_pcie_dw_remove,
2496
+
.remove = tegra_pcie_dw_remove,
2498
2497
.shutdown = tegra_pcie_dw_shutdown,
2499
2498
.driver = {
2500
2499
.name = "tegra194-pcie",
+1
-1
drivers/pci/controller/pci-aardvark.c
+1
-1
drivers/pci/controller/pci-aardvark.c
+1
-1
drivers/pci/controller/pci-host-generic.c
+1
-1
drivers/pci/controller/pci-host-generic.c
+1
-1
drivers/pci/controller/pci-mvebu.c
+1
-1
drivers/pci/controller/pci-mvebu.c
+2
-2
drivers/pci/controller/pci-tegra.c
+2
-2
drivers/pci/controller/pci-tegra.c
···
1460
1460
pcie->cs = *res;
1461
1461
1462
1462
/* constrain configuration space to 4 KiB */
1463
-
pcie->cs.end = pcie->cs.start + SZ_4K - 1;
1463
+
resource_set_size(&pcie->cs, SZ_4K);
1464
1464
1465
1465
pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
1466
1466
if (IS_ERR(pcie->cfg)) {
···
2800
2800
.pm = &tegra_pcie_pm_ops,
2801
2801
},
2802
2802
.probe = tegra_pcie_probe,
2803
-
.remove_new = tegra_pcie_remove,
2803
+
.remove = tegra_pcie_remove,
2804
2804
};
2805
2805
module_platform_driver(tegra_pcie_driver);
+2
-2
drivers/pci/controller/pci-thunder-pem.c
+2
-2
drivers/pci/controller/pci-thunder-pem.c
···
400
400
* Reserve 64K size PEM specific resources. The full 16M range
401
401
* size is required for thunder_pem_init() call.
402
402
*/
403
-
res_pem->end = res_pem->start + SZ_64K - 1;
403
+
resource_set_size(res_pem, SZ_64K);
404
404
thunder_pem_reserve_range(dev, root->segment, res_pem);
405
-
res_pem->end = res_pem->start + SZ_16M - 1;
405
+
resource_set_size(res_pem, SZ_16M);
406
406
407
407
/* Reserve PCI configuration space as well. */
408
408
thunder_pem_reserve_range(dev, root->segment, &cfg->res);
+1
-1
drivers/pci/controller/pci-xgene-msi.c
+1
-1
drivers/pci/controller/pci-xgene-msi.c
+1
-1
drivers/pci/controller/pcie-altera-msi.c
+1
-1
drivers/pci/controller/pcie-altera-msi.c
+3
-3
drivers/pci/controller/pcie-altera.c
+3
-3
drivers/pci/controller/pcie-altera.c
···
815
815
}
816
816
817
817
static struct platform_driver altera_pcie_driver = {
818
-
.probe = altera_pcie_probe,
819
-
.remove_new = altera_pcie_remove,
818
+
.probe = altera_pcie_probe,
819
+
.remove = altera_pcie_remove,
820
820
.driver = {
821
-
.name = "altera-pcie",
821
+
.name = "altera-pcie",
822
822
.of_match_table = altera_pcie_of_match,
823
823
},
824
824
};
+1
-1
drivers/pci/controller/pcie-brcmstb.c
+1
-1
drivers/pci/controller/pcie-brcmstb.c
+1
-1
drivers/pci/controller/pcie-hisi-error.c
+1
-1
drivers/pci/controller/pcie-hisi-error.c
+1
-1
drivers/pci/controller/pcie-iproc-platform.c
+1
-1
drivers/pci/controller/pcie-iproc-platform.c
···
134
134
.of_match_table = of_match_ptr(iproc_pcie_of_match_table),
135
135
},
136
136
.probe = iproc_pltfm_pcie_probe,
137
-
.remove_new = iproc_pltfm_pcie_remove,
137
+
.remove = iproc_pltfm_pcie_remove,
138
138
.shutdown = iproc_pltfm_pcie_shutdown,
139
139
};
140
140
module_platform_driver(iproc_pltfm_pcie_driver);
+74
-3
drivers/pci/controller/pcie-mediatek-gen3.c
+74
-3
drivers/pci/controller/pcie-mediatek-gen3.c
···
28
28
29
29
#include "../pci.h"
30
30
31
+
#define PCIE_BASE_CFG_REG 0x14
32
+
#define PCIE_BASE_CFG_SPEED GENMASK(15, 8)
33
+
31
34
#define PCIE_SETTING_REG 0x80
35
+
#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)
36
+
#define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)
32
37
#define PCIE_PCI_IDS_1 0x9c
33
38
#define PCI_CLASS(class) (class << 8)
34
39
#define PCIE_RC_MODE BIT(0)
···
130
125
131
126
struct mtk_gen3_pcie;
132
127
128
+
#define PCIE_CONF_LINK2_CTL_STS (PCIE_CFG_OFFSET_ADDR + 0xb0)
129
+
#define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0)
130
+
133
131
/**
134
132
* struct mtk_gen3_pcie_pdata - differentiate between host generations
135
133
* @power_up: pcie power_up callback
···
168
160
* @phy: PHY controller block
169
161
* @clks: PCIe clocks
170
162
* @num_clks: PCIe clocks count for this port
163
+
* @max_link_speed: Maximum link speed (PCIe Gen) for this port
164
+
* @num_lanes: Number of PCIe lanes for this port
171
165
* @irq: PCIe controller interrupt number
172
166
* @saved_irq_state: IRQ enable state saved at suspend time
173
167
* @irq_lock: lock protecting IRQ register access
···
190
180
struct phy *phy;
191
181
struct clk_bulk_data *clks;
192
182
int num_clks;
183
+
u8 max_link_speed;
184
+
u8 num_lanes;
193
185
194
186
int irq;
195
187
u32 saved_irq_state;
···
393
381
int err;
394
382
u32 val;
395
383
396
-
/* Set as RC mode */
384
+
/* Set as RC mode and set controller PCIe Gen speed restriction, if any */
397
385
val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
398
386
val |= PCIE_RC_MODE;
387
+
if (pcie->max_link_speed) {
388
+
val &= ~PCIE_SETTING_GEN_SUPPORT;
389
+
390
+
/* Can enable link speed support only from Gen2 onwards */
391
+
if (pcie->max_link_speed >= 2)
392
+
val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
393
+
GENMASK(pcie->max_link_speed - 2, 0));
394
+
}
395
+
if (pcie->num_lanes) {
396
+
val &= ~PCIE_SETTING_LINK_WIDTH;
397
+
398
+
/* Zero means one lane, each bit activates x2/x4/x8/x16 */
399
+
if (pcie->num_lanes > 1)
400
+
val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
401
+
GENMASK(fls(pcie->num_lanes >> 2), 0));
402
+
}
399
403
writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
404
+
405
+
/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
406
+
if (pcie->max_link_speed) {
407
+
val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
408
+
val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;
409
+
val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
410
+
writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
411
+
}
400
412
401
413
/* Set class code */
402
414
val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
···
849
813
struct device *dev = pcie->dev;
850
814
struct platform_device *pdev = to_platform_device(dev);
851
815
struct resource *regs;
816
+
u32 num_lanes;
852
817
853
818
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
854
819
if (!regs)
···
894
857
dev_err(dev, "failed to get clocks\n");
895
858
return pcie->num_clks;
896
859
}
860
+
861
+
ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
862
+
if (ret == 0) {
863
+
if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
864
+
dev_warn(dev, "invalid num-lanes, using controller defaults\n");
865
+
else
866
+
pcie->num_lanes = num_lanes;
867
+
}
897
868
898
869
return 0;
899
870
}
···
1049
1004
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1050
1005
}
1051
1006
1007
+
static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
1008
+
{
1009
+
u32 val;
1010
+
int ret;
1011
+
1012
+
val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);
1013
+
val = FIELD_GET(PCIE_BASE_CFG_SPEED, val);
1014
+
ret = fls(val);
1015
+
1016
+
return ret > 0 ? ret : -EINVAL;
1017
+
}
1018
+
1052
1019
static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
1053
1020
{
1054
-
int err;
1021
+
int err, max_speed;
1055
1022
1056
1023
err = mtk_pcie_parse_port(pcie);
1057
1024
if (err)
···
1087
1030
err = pcie->soc->power_up(pcie);
1088
1031
if (err)
1089
1032
return err;
1033
+
1034
+
err = of_pci_get_max_link_speed(pcie->dev->of_node);
1035
+
if (err) {
1036
+
/* Get the maximum speed supported by the controller */
1037
+
max_speed = mtk_pcie_get_controller_max_link_speed(pcie);
1038
+
1039
+
/* Set max_link_speed only if the controller supports it */
1040
+
if (max_speed >= 0 && max_speed <= err) {
1041
+
pcie->max_link_speed = err;
1042
+
dev_info(pcie->dev,
1043
+
"maximum controller link speed Gen%d, overriding to Gen%u",
1044
+
max_speed, pcie->max_link_speed);
1045
+
}
1046
+
}
1090
1047
1091
1048
/* Try link up */
1092
1049
err = mtk_pcie_startup_port(pcie);
···
1296
1225
1297
1226
static struct platform_driver mtk_pcie_driver = {
1298
1227
.probe = mtk_pcie_probe,
1299
-
.remove_new = mtk_pcie_remove,
1228
+
.remove = mtk_pcie_remove,
1300
1229
.driver = {
1301
1230
.name = "mtk-pcie-gen3",
1302
1231
.of_match_table = mtk_pcie_of_match,
+1
-1
drivers/pci/controller/pcie-mediatek.c
+1
-1
drivers/pci/controller/pcie-mediatek.c
+1
-1
drivers/pci/controller/pcie-mt7621.c
+1
-1
drivers/pci/controller/pcie-mt7621.c
+2
-2
drivers/pci/controller/pcie-rcar-host.c
+2
-2
drivers/pci/controller/pcie-rcar-host.c
···
796
796
rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
797
797
798
798
/*
799
-
* Setup MSI data target using RC base address address, which
800
-
* is guaranteed to be in the low 32bit range on any R-Car HW.
799
+
* Setup MSI data target using RC base address, which is guaranteed
800
+
* to be in the low 32bit range on any R-Car HW.
801
801
*/
802
802
rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
803
803
rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
+357
-83
drivers/pci/controller/pcie-rockchip-ep.c
+357
-83
drivers/pci/controller/pcie-rockchip-ep.c
···
10
10
11
11
#include <linux/configfs.h>
12
12
#include <linux/delay.h>
13
+
#include <linux/gpio/consumer.h>
14
+
#include <linux/iopoll.h>
13
15
#include <linux/kernel.h>
16
+
#include <linux/irq.h>
14
17
#include <linux/of.h>
15
18
#include <linux/pci-epc.h>
16
19
#include <linux/platform_device.h>
17
20
#include <linux/pci-epf.h>
18
21
#include <linux/sizes.h>
22
+
#include <linux/workqueue.h>
19
23
20
24
#include "pcie-rockchip.h"
21
25
···
52
48
u64 irq_pci_addr;
53
49
u8 irq_pci_fn;
54
50
u8 irq_pending;
51
+
int perst_irq;
52
+
bool perst_asserted;
53
+
bool link_up;
54
+
struct delayed_work link_training;
55
55
};
56
56
57
57
static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
···
71
63
ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
72
64
}
73
65
66
+
static int rockchip_pcie_ep_ob_atu_num_bits(struct rockchip_pcie *rockchip,
67
+
u64 pci_addr, size_t size)
68
+
{
69
+
int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1));
70
+
71
+
return clamp(num_pass_bits,
72
+
ROCKCHIP_PCIE_AT_MIN_NUM_BITS,
73
+
ROCKCHIP_PCIE_AT_MAX_NUM_BITS);
74
+
}
75
+
74
76
static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
75
77
u32 r, u64 cpu_addr, u64 pci_addr,
76
78
size_t size)
77
79
{
78
-
int num_pass_bits = fls64(size - 1);
80
+
int num_pass_bits;
79
81
u32 addr0, addr1, desc0;
80
82
81
-
if (num_pass_bits < 8)
82
-
num_pass_bits = 8;
83
+
num_pass_bits = rockchip_pcie_ep_ob_atu_num_bits(rockchip,
84
+
pci_addr, size);
83
85
84
86
addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
85
87
(lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
···
246
228
return (addr >> ilog2(SZ_1M)) & 0x1f;
247
229
}
248
230
231
+
static u64 rockchip_pcie_ep_align_addr(struct pci_epc *epc, u64 pci_addr,
232
+
size_t *pci_size, size_t *addr_offset)
233
+
{
234
+
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
235
+
size_t size = *pci_size;
236
+
u64 offset, mask;
237
+
int num_bits;
238
+
239
+
num_bits = rockchip_pcie_ep_ob_atu_num_bits(&ep->rockchip,
240
+
pci_addr, size);
241
+
mask = (1ULL << num_bits) - 1;
242
+
243
+
offset = pci_addr & mask;
244
+
if (size + offset > SZ_1M)
245
+
size = SZ_1M - offset;
246
+
247
+
*pci_size = ALIGN(offset + size, ROCKCHIP_PCIE_AT_SIZE_ALIGN);
248
+
*addr_offset = offset;
249
+
250
+
return pci_addr & ~mask;
251
+
}
252
+
249
253
static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
250
254
phys_addr_t addr, u64 pci_addr,
251
255
size_t size)
···
275
235
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
276
236
struct rockchip_pcie *pcie = &ep->rockchip;
277
237
u32 r = rockchip_ob_region(addr);
238
+
239
+
if (test_bit(r, &ep->ob_region_map))
240
+
return -EBUSY;
278
241
279
242
rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, addr, pci_addr, size);
280
243
···
292
249
{
293
250
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
294
251
struct rockchip_pcie *rockchip = &ep->rockchip;
295
-
u32 r;
252
+
u32 r = rockchip_ob_region(addr);
296
253
297
-
for (r = 0; r < ep->max_regions; r++)
298
-
if (ep->ob_addr[r] == addr)
299
-
break;
300
-
301
-
if (r == ep->max_regions)
254
+
if (addr != ep->ob_addr[r] || !test_bit(r, &ep->ob_region_map))
302
255
return;
303
256
304
257
rockchip_pcie_clear_ep_ob_atu(rockchip, r);
···
390
351
{
391
352
struct rockchip_pcie *rockchip = &ep->rockchip;
392
353
u32 flags, mme, data, data_mask;
354
+
size_t irq_pci_size, offset;
355
+
u64 irq_pci_addr;
393
356
u8 msi_count;
394
357
u64 pci_addr;
395
-
u32 r;
396
358
397
359
/* Check MSI enable bit */
398
360
flags = rockchip_pcie_read(&ep->rockchip,
···
429
389
PCI_MSI_ADDRESS_LO);
430
390
431
391
/* Set the outbound region if needed. */
432
-
if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) ||
392
+
irq_pci_size = ~PCIE_ADDR_MASK + 1;
393
+
irq_pci_addr = rockchip_pcie_ep_align_addr(ep->epc,
394
+
pci_addr & PCIE_ADDR_MASK,
395
+
&irq_pci_size, &offset);
396
+
if (unlikely(ep->irq_pci_addr != irq_pci_addr ||
433
397
ep->irq_pci_fn != fn)) {
434
-
r = rockchip_ob_region(ep->irq_phys_addr);
435
-
rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
436
-
ep->irq_phys_addr,
437
-
pci_addr & PCIE_ADDR_MASK,
438
-
~PCIE_ADDR_MASK + 1);
439
-
ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK);
398
+
rockchip_pcie_prog_ep_ob_atu(rockchip, fn,
399
+
rockchip_ob_region(ep->irq_phys_addr),
400
+
ep->irq_phys_addr,
401
+
irq_pci_addr, irq_pci_size);
402
+
ep->irq_pci_addr = irq_pci_addr;
440
403
ep->irq_pci_fn = fn;
441
404
}
442
405
443
-
writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK));
406
+
writew(data, ep->irq_cpu_addr + offset + (pci_addr & ~PCIE_ADDR_MASK));
444
407
return 0;
445
408
}
446
409
···
475
432
476
433
rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
477
434
435
+
if (rockchip->perst_gpio)
436
+
enable_irq(ep->perst_irq);
437
+
438
+
/* Enable configuration and start link training */
439
+
rockchip_pcie_write(rockchip,
440
+
PCIE_CLIENT_LINK_TRAIN_ENABLE |
441
+
PCIE_CLIENT_CONF_ENABLE,
442
+
PCIE_CLIENT_CONFIG);
443
+
444
+
if (!rockchip->perst_gpio)
445
+
schedule_delayed_work(&ep->link_training, 0);
446
+
447
+
return 0;
448
+
}
449
+
450
+
static void rockchip_pcie_ep_stop(struct pci_epc *epc)
451
+
{
452
+
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
453
+
struct rockchip_pcie *rockchip = &ep->rockchip;
454
+
455
+
if (rockchip->perst_gpio) {
456
+
ep->perst_asserted = true;
457
+
disable_irq(ep->perst_irq);
458
+
}
459
+
460
+
cancel_delayed_work_sync(&ep->link_training);
461
+
462
+
/* Stop link training and disable configuration */
463
+
rockchip_pcie_write(rockchip,
464
+
PCIE_CLIENT_CONF_DISABLE |
465
+
PCIE_CLIENT_LINK_TRAIN_DISABLE,
466
+
PCIE_CLIENT_CONFIG);
467
+
}
468
+
469
+
static void rockchip_pcie_ep_retrain_link(struct rockchip_pcie *rockchip)
470
+
{
471
+
u32 status;
472
+
473
+
status = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS);
474
+
status |= PCI_EXP_LNKCTL_RL;
475
+
rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS);
476
+
}
477
+
478
+
static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip)
479
+
{
480
+
u32 val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
481
+
482
+
return PCIE_LINK_UP(val);
483
+
}
484
+
485
+
static void rockchip_pcie_ep_link_training(struct work_struct *work)
486
+
{
487
+
struct rockchip_pcie_ep *ep =
488
+
container_of(work, struct rockchip_pcie_ep, link_training.work);
489
+
struct rockchip_pcie *rockchip = &ep->rockchip;
490
+
struct device *dev = rockchip->dev;
491
+
u32 val;
492
+
int ret;
493
+
494
+
/* Enable Gen1 training and wait for its completion */
495
+
ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
496
+
val, PCIE_LINK_TRAINING_DONE(val), 50,
497
+
LINK_TRAIN_TIMEOUT);
498
+
if (ret)
499
+
goto again;
500
+
501
+
/* Make sure that the link is up */
502
+
ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
503
+
val, PCIE_LINK_UP(val), 50,
504
+
LINK_TRAIN_TIMEOUT);
505
+
if (ret)
506
+
goto again;
507
+
508
+
/*
509
+
* Check the current speed: if gen2 speed was requested and we are not
510
+
* at gen2 speed yet, retrain again for gen2.
511
+
*/
512
+
val = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
513
+
if (!PCIE_LINK_IS_GEN2(val) && rockchip->link_gen == 2) {
514
+
/* Enable retrain for gen2 */
515
+
rockchip_pcie_ep_retrain_link(rockchip);
516
+
readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
517
+
val, PCIE_LINK_IS_GEN2(val), 50,
518
+
LINK_TRAIN_TIMEOUT);
519
+
}
520
+
521
+
/* Check again that the link is up */
522
+
if (!rockchip_pcie_ep_link_up(rockchip))
523
+
goto again;
524
+
525
+
/*
526
+
* If PERST# was asserted while polling the link, do not notify
527
+
* the function.
528
+
*/
529
+
if (ep->perst_asserted)
530
+
return;
531
+
532
+
val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS0);
533
+
dev_info(dev,
534
+
"link up (negotiated speed: %sGT/s, width: x%lu)\n",
535
+
(val & PCIE_CLIENT_NEG_LINK_SPEED) ? "5" : "2.5",
536
+
((val & PCIE_CLIENT_NEG_LINK_WIDTH_MASK) >>
537
+
PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT) << 1);
538
+
539
+
/* Notify the function */
540
+
pci_epc_linkup(ep->epc);
541
+
ep->link_up = true;
542
+
543
+
return;
544
+
545
+
again:
546
+
schedule_delayed_work(&ep->link_training, msecs_to_jiffies(5));
547
+
}
548
+
549
+
static void rockchip_pcie_ep_perst_assert(struct rockchip_pcie_ep *ep)
550
+
{
551
+
struct rockchip_pcie *rockchip = &ep->rockchip;
552
+
553
+
dev_dbg(rockchip->dev, "PERST# asserted, link down\n");
554
+
555
+
if (ep->perst_asserted)
556
+
return;
557
+
558
+
ep->perst_asserted = true;
559
+
560
+
cancel_delayed_work_sync(&ep->link_training);
561
+
562
+
if (ep->link_up) {
563
+
pci_epc_linkdown(ep->epc);
564
+
ep->link_up = false;
565
+
}
566
+
}
567
+
568
+
static void rockchip_pcie_ep_perst_deassert(struct rockchip_pcie_ep *ep)
569
+
{
570
+
struct rockchip_pcie *rockchip = &ep->rockchip;
571
+
572
+
dev_dbg(rockchip->dev, "PERST# de-asserted, starting link training\n");
573
+
574
+
if (!ep->perst_asserted)
575
+
return;
576
+
577
+
ep->perst_asserted = false;
578
+
579
+
/* Enable link re-training */
580
+
rockchip_pcie_ep_retrain_link(rockchip);
581
+
582
+
/* Start link training */
583
+
schedule_delayed_work(&ep->link_training, 0);
584
+
}
585
+
586
+
static irqreturn_t rockchip_pcie_ep_perst_irq_thread(int irq, void *data)
587
+
{
588
+
struct pci_epc *epc = data;
589
+
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
590
+
struct rockchip_pcie *rockchip = &ep->rockchip;
591
+
u32 perst = gpiod_get_value(rockchip->perst_gpio);
592
+
593
+
if (perst)
594
+
rockchip_pcie_ep_perst_assert(ep);
595
+
else
596
+
rockchip_pcie_ep_perst_deassert(ep);
597
+
598
+
irq_set_irq_type(ep->perst_irq,
599
+
(perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
600
+
601
+
return IRQ_HANDLED;
602
+
}
603
+
604
+
static int rockchip_pcie_ep_setup_irq(struct pci_epc *epc)
605
+
{
606
+
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
607
+
struct rockchip_pcie *rockchip = &ep->rockchip;
608
+
struct device *dev = rockchip->dev;
609
+
int ret;
610
+
611
+
if (!rockchip->perst_gpio)
612
+
return 0;
613
+
614
+
/* PCIe reset interrupt */
615
+
ep->perst_irq = gpiod_to_irq(rockchip->perst_gpio);
616
+
if (ep->perst_irq < 0) {
617
+
dev_err(dev,
618
+
"failed to get IRQ for PERST# GPIO: %d\n",
619
+
ep->perst_irq);
620
+
621
+
return ep->perst_irq;
622
+
}
623
+
624
+
/*
625
+
* The perst_gpio is active low, so when it is inactive on start, it
626
+
* is high and will trigger the perst_irq handler. So treat this initial
627
+
* IRQ as a dummy one by faking the host asserting PERST#.
628
+
*/
629
+
ep->perst_asserted = true;
630
+
irq_set_status_flags(ep->perst_irq, IRQ_NOAUTOEN);
631
+
ret = devm_request_threaded_irq(dev, ep->perst_irq, NULL,
632
+
rockchip_pcie_ep_perst_irq_thread,
633
+
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
634
+
"pcie-ep-perst", epc);
635
+
if (ret) {
636
+
dev_err(dev,
637
+
"failed to request IRQ for PERST# GPIO: %d\n",
638
+
ret);
639
+
640
+
return ret;
641
+
}
642
+
478
643
return 0;
479
644
}
480
645
481
646
static const struct pci_epc_features rockchip_pcie_epc_features = {
482
-
.linkup_notifier = false,
647
+
.linkup_notifier = true,
483
648
.msi_capable = true,
484
649
.msix_capable = false,
485
-
.align = 256,
650
+
.align = ROCKCHIP_PCIE_AT_SIZE_ALIGN,
486
651
};
487
652
488
653
static const struct pci_epc_features*
···
703
452
.write_header = rockchip_pcie_ep_write_header,
704
453
.set_bar = rockchip_pcie_ep_set_bar,
705
454
.clear_bar = rockchip_pcie_ep_clear_bar,
455
+
.align_addr = rockchip_pcie_ep_align_addr,
706
456
.map_addr = rockchip_pcie_ep_map_addr,
707
457
.unmap_addr = rockchip_pcie_ep_unmap_addr,
708
458
.set_msi = rockchip_pcie_ep_set_msi,
709
459
.get_msi = rockchip_pcie_ep_get_msi,
710
460
.raise_irq = rockchip_pcie_ep_raise_irq,
711
461
.start = rockchip_pcie_ep_start,
462
+
.stop = rockchip_pcie_ep_stop,
712
463
.get_features = rockchip_pcie_ep_get_features,
713
464
};
714
465
715
-
static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
716
-
struct rockchip_pcie_ep *ep)
466
+
static int rockchip_pcie_ep_get_resources(struct rockchip_pcie *rockchip,
467
+
struct rockchip_pcie_ep *ep)
717
468
{
718
469
struct device *dev = rockchip->dev;
719
470
int err;
···
749
496
{},
750
497
};
751
498
752
-
static int rockchip_pcie_ep_probe(struct platform_device *pdev)
499
+
static int rockchip_pcie_ep_init_ob_mem(struct rockchip_pcie_ep *ep)
753
500
{
754
-
struct device *dev = &pdev->dev;
755
-
struct rockchip_pcie_ep *ep;
756
-
struct rockchip_pcie *rockchip;
757
-
struct pci_epc *epc;
758
-
size_t max_regions;
501
+
struct rockchip_pcie *rockchip = &ep->rockchip;
502
+
struct device *dev = rockchip->dev;
759
503
struct pci_epc_mem_window *windows = NULL;
760
504
int err, i;
761
-
u32 cfg_msi, cfg_msix_cp;
762
505
763
-
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
764
-
if (!ep)
765
-
return -ENOMEM;
766
-
767
-
rockchip = &ep->rockchip;
768
-
rockchip->is_rc = false;
769
-
rockchip->dev = dev;
770
-
771
-
epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
772
-
if (IS_ERR(epc)) {
773
-
dev_err(dev, "failed to create epc device\n");
774
-
return PTR_ERR(epc);
775
-
}
776
-
777
-
ep->epc = epc;
778
-
epc_set_drvdata(epc, ep);
779
-
780
-
err = rockchip_pcie_parse_ep_dt(rockchip, ep);
781
-
if (err)
782
-
return err;
783
-
784
-
err = rockchip_pcie_enable_clocks(rockchip);
785
-
if (err)
786
-
return err;
787
-
788
-
err = rockchip_pcie_init_port(rockchip);
789
-
if (err)
790
-
goto err_disable_clocks;
791
-
792
-
/* Establish the link automatically */
793
-
rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
794
-
PCIE_CLIENT_CONFIG);
795
-
796
-
max_regions = ep->max_regions;
797
-
ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),
506
+
ep->ob_addr = devm_kcalloc(dev, ep->max_regions, sizeof(*ep->ob_addr),
798
507
GFP_KERNEL);
799
508
800
-
if (!ep->ob_addr) {
801
-
err = -ENOMEM;
802
-
goto err_uninit_port;
803
-
}
804
-
805
-
/* Only enable function 0 by default */
806
-
rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
509
+
if (!ep->ob_addr)
510
+
return -ENOMEM;
807
511
808
512
windows = devm_kcalloc(dev, ep->max_regions,
809
513
sizeof(struct pci_epc_mem_window), GFP_KERNEL);
810
-
if (!windows) {
811
-
err = -ENOMEM;
812
-
goto err_uninit_port;
813
-
}
514
+
if (!windows)
515
+
return -ENOMEM;
516
+
814
517
for (i = 0; i < ep->max_regions; i++) {
815
518
windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i);
816
519
windows[i].size = SZ_1M;
817
520
windows[i].page_size = SZ_1M;
818
521
}
819
-
err = pci_epc_multi_mem_init(epc, windows, ep->max_regions);
522
+
err = pci_epc_multi_mem_init(ep->epc, windows, ep->max_regions);
820
523
devm_kfree(dev, windows);
821
524
822
525
if (err < 0) {
823
526
dev_err(dev, "failed to initialize the memory space\n");
824
-
goto err_uninit_port;
527
+
return err;
825
528
}
826
529
827
-
ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
530
+
ep->irq_cpu_addr = pci_epc_mem_alloc_addr(ep->epc, &ep->irq_phys_addr,
828
531
SZ_1M);
829
532
if (!ep->irq_cpu_addr) {
830
533
dev_err(dev, "failed to reserve memory space for MSI\n");
831
-
err = -ENOMEM;
832
534
goto err_epc_mem_exit;
833
535
}
834
536
835
537
ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
538
+
539
+
return 0;
540
+
541
+
err_epc_mem_exit:
542
+
pci_epc_mem_exit(ep->epc);
543
+
544
+
return err;
545
+
}
546
+
547
+
static void rockchip_pcie_ep_exit_ob_mem(struct rockchip_pcie_ep *ep)
548
+
{
549
+
pci_epc_mem_exit(ep->epc);
550
+
}
551
+
552
+
static void rockchip_pcie_ep_hide_broken_msix_cap(struct rockchip_pcie *rockchip)
553
+
{
554
+
u32 cfg_msi, cfg_msix_cp;
836
555
837
556
/*
838
557
* MSI-X is not supported but the controller still advertises the MSI-X
···
828
603
829
604
rockchip_pcie_write(rockchip, cfg_msi,
830
605
PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
606
+
}
831
607
832
-
rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
833
-
PCIE_CLIENT_CONFIG);
608
+
static int rockchip_pcie_ep_probe(struct platform_device *pdev)
609
+
{
610
+
struct device *dev = &pdev->dev;
611
+
struct rockchip_pcie_ep *ep;
612
+
struct rockchip_pcie *rockchip;
613
+
struct pci_epc *epc;
614
+
int err;
615
+
616
+
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
617
+
if (!ep)
618
+
return -ENOMEM;
619
+
620
+
rockchip = &ep->rockchip;
621
+
rockchip->is_rc = false;
622
+
rockchip->dev = dev;
623
+
INIT_DELAYED_WORK(&ep->link_training, rockchip_pcie_ep_link_training);
624
+
625
+
epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
626
+
if (IS_ERR(epc)) {
627
+
dev_err(dev, "failed to create EPC device\n");
628
+
return PTR_ERR(epc);
629
+
}
630
+
631
+
ep->epc = epc;
632
+
epc_set_drvdata(epc, ep);
633
+
634
+
err = rockchip_pcie_ep_get_resources(rockchip, ep);
635
+
if (err)
636
+
return err;
637
+
638
+
err = rockchip_pcie_ep_init_ob_mem(ep);
639
+
if (err)
640
+
return err;
641
+
642
+
err = rockchip_pcie_enable_clocks(rockchip);
643
+
if (err)
644
+
goto err_exit_ob_mem;
645
+
646
+
err = rockchip_pcie_init_port(rockchip);
647
+
if (err)
648
+
goto err_disable_clocks;
649
+
650
+
rockchip_pcie_ep_hide_broken_msix_cap(rockchip);
651
+
652
+
/* Only enable function 0 by default */
653
+
rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
834
654
835
655
pci_epc_init_notify(epc);
836
656
657
+
err = rockchip_pcie_ep_setup_irq(epc);
658
+
if (err < 0)
659
+
goto err_uninit_port;
660
+
837
661
return 0;
838
-
err_epc_mem_exit:
839
-
pci_epc_mem_exit(epc);
840
662
err_uninit_port:
841
663
rockchip_pcie_deinit_phys(rockchip);
842
664
err_disable_clocks:
843
665
rockchip_pcie_disable_clocks(rockchip);
666
+
err_exit_ob_mem:
667
+
rockchip_pcie_ep_exit_ob_mem(ep);
844
668
return err;
845
669
}
846
670
+3
-3
drivers/pci/controller/pcie-rockchip-host.c
+3
-3
drivers/pci/controller/pcie-rockchip-host.c
···
294
294
int err, i = MAX_LANE_NUM;
295
295
u32 status;
296
296
297
-
gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
297
+
gpiod_set_value_cansleep(rockchip->perst_gpio, 0);
298
298
299
299
err = rockchip_pcie_init_port(rockchip);
300
300
if (err)
···
323
323
PCIE_CLIENT_CONFIG);
324
324
325
325
msleep(PCIE_T_PVPERL_MS);
326
-
gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
326
+
gpiod_set_value_cansleep(rockchip->perst_gpio, 1);
327
327
328
328
msleep(PCIE_T_RRS_READY_MS);
329
329
···
1050
1050
.pm = &rockchip_pcie_pm_ops,
1051
1051
},
1052
1052
.probe = rockchip_pcie_probe,
1053
-
.remove_new = rockchip_pcie_remove,
1053
+
.remove = rockchip_pcie_remove,
1054
1054
};
1055
1055
module_platform_driver(rockchip_pcie_driver);
1056
1056
+12
-9
drivers/pci/controller/pcie-rockchip.c
+12
-9
drivers/pci/controller/pcie-rockchip.c
···
119
119
return PTR_ERR(rockchip->aclk_rst);
120
120
}
121
121
122
-
if (rockchip->is_rc) {
123
-
rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
124
-
GPIOD_OUT_LOW);
125
-
if (IS_ERR(rockchip->ep_gpio))
126
-
return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
127
-
"failed to get ep GPIO\n");
128
-
}
122
+
if (rockchip->is_rc)
123
+
rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep",
124
+
GPIOD_OUT_LOW);
125
+
else
126
+
rockchip->perst_gpio = devm_gpiod_get_optional(dev, "reset",
127
+
GPIOD_IN);
128
+
if (IS_ERR(rockchip->perst_gpio))
129
+
return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio),
130
+
"failed to get PERST# GPIO\n");
129
131
130
132
rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
131
133
if (IS_ERR(rockchip->aclk_pcie)) {
···
246
244
rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
247
245
PCIE_CLIENT_CONFIG);
248
246
249
-
regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE |
247
+
regs = PCIE_CLIENT_ARI_ENABLE |
250
248
PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
251
249
252
250
if (rockchip->is_rc)
253
-
regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
251
+
regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE |
252
+
PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
254
253
else
255
254
regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;
256
255
+23
-1
drivers/pci/controller/pcie-rockchip.h
+23
-1
drivers/pci/controller/pcie-rockchip.h
···
26
26
#define MAX_LANE_NUM 4
27
27
#define MAX_REGION_LIMIT 32
28
28
#define MIN_EP_APERTURE 28
29
+
#define LINK_TRAIN_TIMEOUT (500 * USEC_PER_MSEC)
29
30
30
31
#define PCIE_CLIENT_BASE 0x0
31
32
#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
32
33
#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
33
34
#define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
34
35
#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
36
+
#define PCIE_CLIENT_LINK_TRAIN_DISABLE HIWORD_UPDATE(0x0002, 0)
35
37
#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
36
38
#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
37
39
#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
···
51
49
#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
52
50
#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18
53
51
#define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19
52
+
#define PCIE_CLIENT_BASIC_STATUS0 (PCIE_CLIENT_BASE + 0x44)
53
+
#define PCIE_CLIENT_NEG_LINK_WIDTH_MASK GENMASK(7, 6)
54
+
#define PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT 6
55
+
#define PCIE_CLIENT_NEG_LINK_SPEED BIT(5)
54
56
#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
55
57
#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
56
58
#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
···
92
86
93
87
#define PCIE_CORE_CTRL_MGMT_BASE 0x900000
94
88
#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
89
+
#define PCIE_CORE_PL_CONF_LS_MASK 0x00000001
90
+
#define PCIE_CORE_PL_CONF_LS_READY 0x00000001
95
91
#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
96
92
#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
97
93
#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
···
151
143
#define PCIE_RC_CONFIG_BASE 0xa00000
152
144
#define PCIE_EP_CONFIG_BASE 0xa00000
153
145
#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00)
146
+
#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0)
154
147
#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
155
148
#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
156
149
#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
···
163
154
#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
164
155
#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
165
156
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
157
+
#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0)
166
158
#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
167
159
#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
168
160
#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
···
201
191
#define ROCKCHIP_VENDOR_ID 0x1d87
202
192
#define PCIE_LINK_IS_L2(x) \
203
193
(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
194
+
#define PCIE_LINK_TRAINING_DONE(x) \
195
+
(((x) & PCIE_CORE_PL_CONF_LS_MASK) == PCIE_CORE_PL_CONF_LS_READY)
204
196
#define PCIE_LINK_UP(x) \
205
197
(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
206
198
#define PCIE_LINK_IS_GEN2(x) \
···
253
241
#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK GENMASK(15, 8)
254
242
#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1
255
243
#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3
244
+
245
+
#define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8
246
+
#define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20
247
+
#define ROCKCHIP_PCIE_AT_SIZE_ALIGN (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS)
248
+
256
249
#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \
257
250
(PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12)))
258
251
#define ROCKCHIP_PCIE_EP_VIRT_FUNC_BASE(fn) \
259
252
(PCIE_EP_PF_CONFIG_REGS_BASE + 0x10000 + (((fn) << 12) & GENMASK(19, 12)))
253
+
254
+
#define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8
255
+
#define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20
256
+
#define ROCKCHIP_PCIE_AT_SIZE_ALIGN (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS)
257
+
260
258
#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
261
259
(PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008)
262
260
#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
···
329
307
struct regulator *vpcie3v3; /* 3.3V power supply */
330
308
struct regulator *vpcie1v8; /* 1.8V power supply */
331
309
struct regulator *vpcie0v9; /* 0.9V power supply */
332
-
struct gpio_desc *ep_gpio;
310
+
struct gpio_desc *perst_gpio;
333
311
u32 lanes;
334
312
u8 lanes_map;
335
313
int link_gen;
+1
-1
drivers/pci/controller/pcie-xilinx-nwl.c
+1
-1
drivers/pci/controller/pcie-xilinx-nwl.c
+67
-59
drivers/pci/controller/plda/pcie-microchip-host.c
+67
-59
drivers/pci/controller/plda/pcie-microchip-host.c
···
25
25
#define MC_PCIE1_BRIDGE_ADDR 0x00008000u
26
26
#define MC_PCIE1_CTRL_ADDR 0x0000a000u
27
27
28
-
#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
29
-
#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
30
-
31
28
/* PCIe Controller Phy Regs */
32
29
#define SEC_ERROR_EVENT_CNT 0x20
33
30
#define DED_ERROR_EVENT_CNT 0x24
···
125
128
[EVENT_LOCAL_ ## x] = { __stringify(x), s }
126
129
127
130
#define PCIE_EVENT(x) \
128
-
.base = MC_PCIE_CTRL_ADDR, \
129
131
.offset = PCIE_EVENT_INT, \
130
132
.mask_offset = PCIE_EVENT_INT, \
131
133
.mask_high = 1, \
···
132
136
.enb_mask = PCIE_EVENT_INT_ENB_MASK
133
137
134
138
#define SEC_EVENT(x) \
135
-
.base = MC_PCIE_CTRL_ADDR, \
136
139
.offset = SEC_ERROR_INT, \
137
140
.mask_offset = SEC_ERROR_INT_MASK, \
138
141
.mask = SEC_ERROR_INT_ ## x ## _INT, \
···
139
144
.enb_mask = 0
140
145
141
146
#define DED_EVENT(x) \
142
-
.base = MC_PCIE_CTRL_ADDR, \
143
147
.offset = DED_ERROR_INT, \
144
148
.mask_offset = DED_ERROR_INT_MASK, \
145
149
.mask_high = 1, \
···
146
152
.enb_mask = 0
147
153
148
154
#define LOCAL_EVENT(x) \
149
-
.base = MC_PCIE_BRIDGE_ADDR, \
150
155
.offset = ISTATUS_LOCAL, \
151
156
.mask_offset = IMASK_LOCAL, \
152
157
.mask_high = 0, \
···
172
179
173
180
struct mc_pcie {
174
181
struct plda_pcie_rp plda;
175
-
void __iomem *axi_base_addr;
182
+
void __iomem *bridge_base_addr;
183
+
void __iomem *ctrl_base_addr;
176
184
};
177
185
178
186
struct cause {
···
247
253
};
248
254
249
255
static struct {
250
-
u32 base;
251
256
u32 offset;
252
257
u32 mask;
253
258
u32 shift;
···
318
325
319
326
static u32 pcie_events(struct mc_pcie *port)
320
327
{
321
-
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
322
-
u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT);
328
+
u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT);
323
329
u32 val = 0;
324
330
int i;
325
331
···
330
338
331
339
static u32 sec_errors(struct mc_pcie *port)
332
340
{
333
-
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
334
-
u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT);
341
+
u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT);
335
342
u32 val = 0;
336
343
int i;
337
344
···
342
351
343
352
static u32 ded_errors(struct mc_pcie *port)
344
353
{
345
-
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
346
-
u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT);
354
+
u32 reg = readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT);
347
355
u32 val = 0;
348
356
int i;
349
357
···
354
364
355
365
static u32 local_events(struct mc_pcie *port)
356
366
{
357
-
void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
358
-
u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
367
+
u32 reg = readl_relaxed(port->bridge_base_addr + ISTATUS_LOCAL);
359
368
u32 val = 0;
360
369
int i;
361
370
···
401
412
void __iomem *addr;
402
413
u32 mask;
403
414
404
-
addr = mc_port->axi_base_addr + event_descs[event].base +
405
-
event_descs[event].offset;
415
+
if (event_descs[event].offset == ISTATUS_LOCAL)
416
+
addr = mc_port->bridge_base_addr;
417
+
else
418
+
addr = mc_port->ctrl_base_addr;
419
+
420
+
addr += event_descs[event].offset;
406
421
mask = event_descs[event].mask;
407
422
mask |= event_descs[event].enb_mask;
408
423
···
422
429
u32 mask;
423
430
u32 val;
424
431
425
-
addr = mc_port->axi_base_addr + event_descs[event].base +
426
-
event_descs[event].mask_offset;
432
+
if (event_descs[event].offset == ISTATUS_LOCAL)
433
+
addr = mc_port->bridge_base_addr;
434
+
else
435
+
addr = mc_port->ctrl_base_addr;
436
+
437
+
addr += event_descs[event].mask_offset;
427
438
mask = event_descs[event].mask;
428
439
if (event_descs[event].enb_mask) {
429
440
mask <<= PCIE_EVENT_INT_ENB_SHIFT;
···
457
460
u32 mask;
458
461
u32 val;
459
462
460
-
addr = mc_port->axi_base_addr + event_descs[event].base +
461
-
event_descs[event].mask_offset;
463
+
if (event_descs[event].offset == ISTATUS_LOCAL)
464
+
addr = mc_port->bridge_base_addr;
465
+
else
466
+
addr = mc_port->ctrl_base_addr;
467
+
468
+
addr += event_descs[event].mask_offset;
462
469
mask = event_descs[event].mask;
463
470
464
471
if (event_descs[event].enb_mask)
···
555
554
556
555
static inline void mc_clear_secs(struct mc_pcie *port)
557
556
{
558
-
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
559
-
560
-
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
561
-
SEC_ERROR_INT);
562
-
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);
557
+
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT,
558
+
port->ctrl_base_addr + SEC_ERROR_INT);
559
+
writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT);
563
560
}
564
561
565
562
static inline void mc_clear_deds(struct mc_pcie *port)
566
563
{
567
-
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
568
-
569
-
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
570
-
DED_ERROR_INT);
571
-
writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);
564
+
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT,
565
+
port->ctrl_base_addr + DED_ERROR_INT);
566
+
writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT);
572
567
}
573
568
574
569
static void mc_disable_interrupts(struct mc_pcie *port)
575
570
{
576
-
void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
577
-
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
578
571
u32 val;
579
572
580
573
/* Ensure ECC bypass is enabled */
···
576
581
ECC_CONTROL_RX_RAM_ECC_BYPASS |
577
582
ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS |
578
583
ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS;
579
-
writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
584
+
writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL);
580
585
581
586
/* Disable SEC errors and clear any outstanding */
582
-
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
583
-
SEC_ERROR_INT_MASK);
587
+
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT,
588
+
port->ctrl_base_addr + SEC_ERROR_INT_MASK);
584
589
mc_clear_secs(port);
585
590
586
591
/* Disable DED errors and clear any outstanding */
587
-
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
588
-
DED_ERROR_INT_MASK);
592
+
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT,
593
+
port->ctrl_base_addr + DED_ERROR_INT_MASK);
589
594
mc_clear_deds(port);
590
595
591
596
/* Disable local interrupts and clear any outstanding */
592
-
writel_relaxed(0, bridge_base_addr + IMASK_LOCAL);
593
-
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL);
594
-
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI);
597
+
writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL);
598
+
writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL);
599
+
writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI);
595
600
596
601
/* Disable PCIe events and clear any outstanding */
597
602
val = PCIE_EVENT_INT_L2_EXIT_INT |
···
600
605
PCIE_EVENT_INT_L2_EXIT_INT_MASK |
601
606
PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK |
602
607
PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;
603
-
writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
608
+
writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT);
604
609
605
610
/* Disable host interrupts and clear any outstanding */
606
-
writel_relaxed(0, bridge_base_addr + IMASK_HOST);
607
-
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
611
+
writel_relaxed(0, port->bridge_base_addr + IMASK_HOST);
612
+
writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST);
608
613
}
609
614
610
615
static int mc_platform_init(struct pci_config_window *cfg)
···
612
617
struct device *dev = cfg->parent;
613
618
struct platform_device *pdev = to_platform_device(dev);
614
619
struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
615
-
void __iomem *bridge_base_addr =
616
-
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
617
620
int ret;
618
621
619
622
/* Configure address translation table 0 for PCIe config space */
620
-
plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,
623
+
plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start,
621
624
cfg->res.start,
622
625
resource_size(&cfg->res));
623
626
···
642
649
static int mc_host_probe(struct platform_device *pdev)
643
650
{
644
651
struct device *dev = &pdev->dev;
645
-
void __iomem *bridge_base_addr;
652
+
void __iomem *apb_base_addr;
646
653
struct plda_pcie_rp *plda;
647
654
int ret;
648
655
u32 val;
···
654
661
plda = &port->plda;
655
662
plda->dev = dev;
656
663
657
-
port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
658
-
if (IS_ERR(port->axi_base_addr))
659
-
return PTR_ERR(port->axi_base_addr);
664
+
port->bridge_base_addr = devm_platform_ioremap_resource_byname(pdev,
665
+
"bridge");
666
+
port->ctrl_base_addr = devm_platform_ioremap_resource_byname(pdev,
667
+
"ctrl");
668
+
if (!IS_ERR(port->bridge_base_addr) && !IS_ERR(port->ctrl_base_addr))
669
+
goto addrs_set;
660
670
671
+
/*
672
+
* The original, incorrect, binding that lumped the control and
673
+
* bridge addresses together still needs to be handled by the driver.
674
+
*/
675
+
apb_base_addr = devm_platform_ioremap_resource_byname(pdev, "apb");
676
+
if (IS_ERR(apb_base_addr))
677
+
return dev_err_probe(dev, PTR_ERR(apb_base_addr),
678
+
"both legacy apb register and ctrl/bridge regions missing");
679
+
680
+
port->bridge_base_addr = apb_base_addr + MC_PCIE1_BRIDGE_ADDR;
681
+
port->ctrl_base_addr = apb_base_addr + MC_PCIE1_CTRL_ADDR;
682
+
683
+
addrs_set:
661
684
mc_disable_interrupts(port);
662
685
663
-
bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
664
-
plda->bridge_addr = bridge_base_addr;
686
+
plda->bridge_addr = port->bridge_base_addr;
665
687
plda->num_events = NUM_EVENTS;
666
688
667
689
/* Allow enabling MSI by disabling MSI-X */
668
-
val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
690
+
val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
669
691
val &= ~MSIX_CAP_MASK;
670
-
writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);
692
+
writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
671
693
672
694
/* Pick num vectors from bitfile programmed onto FPGA fabric */
673
-
val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
695
+
val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
674
696
val &= NUM_MSI_MSGS_MASK;
675
697
val >>= NUM_MSI_MSGS_SHIFT;
676
698
677
699
plda->msi.num_vectors = 1 << val;
678
700
679
701
/* Pick vector address from design */
680
-
plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);
702
+
plda->msi.vector_phy = readl_relaxed(port->bridge_base_addr + IMSI_ADDR);
681
703
682
704
ret = mc_pcie_init_clks(dev);
683
705
if (ret) {
+8
-4
drivers/pci/controller/plda/pcie-starfive.c
+8
-4
drivers/pci/controller/plda/pcie-starfive.c
···
404
404
if (ret)
405
405
return ret;
406
406
407
+
pm_runtime_enable(&pdev->dev);
408
+
pm_runtime_get_sync(&pdev->dev);
409
+
407
410
plda->host_ops = &sf_host_ops;
408
411
plda->num_events = PLDA_MAX_EVENT_NUM;
409
412
/* mask doorbell event */
···
416
413
plda->events_bitmap <<= PLDA_NUM_DMA_EVENTS;
417
414
ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops,
418
415
&stf_pcie_event);
419
-
if (ret)
416
+
if (ret) {
417
+
pm_runtime_put_sync(&pdev->dev);
418
+
pm_runtime_disable(&pdev->dev);
420
419
return ret;
420
+
}
421
421
422
-
pm_runtime_enable(&pdev->dev);
423
-
pm_runtime_get_sync(&pdev->dev);
424
422
platform_set_drvdata(pdev, pcie);
425
423
426
424
return 0;
···
484
480
.pm = pm_sleep_ptr(&starfive_pcie_pm_ops),
485
481
},
486
482
.probe = starfive_pcie_probe,
487
-
.remove_new = starfive_pcie_remove,
483
+
.remove = starfive_pcie_remove,
488
484
};
489
485
module_platform_driver(starfive_pcie_driver);
490
486
+13
-4
drivers/pci/controller/vmd.c
+13
-4
drivers/pci/controller/vmd.c
···
740
740
if (!(features & VMD_FEAT_BIOS_PM_QUIRK))
741
741
return 0;
742
742
743
-
pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
744
-
745
743
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR);
746
744
if (!pos)
747
-
return 0;
745
+
goto out_state_change;
748
746
749
747
/*
750
748
* Skip if the max snoop LTR is non-zero, indicating BIOS has set it
···
750
752
*/
751
753
pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg);
752
754
if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK)))
753
-
return 0;
755
+
goto out_state_change;
754
756
755
757
/*
756
758
* Set the default values to the maximum required by the platform to
···
762
764
pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg);
763
765
pci_info(pdev, "VMD: Default LTR value set by driver\n");
764
766
767
+
out_state_change:
768
+
/*
769
+
* Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
770
+
* PCIe r6.0, sec 5.5.4.
771
+
*/
772
+
pci_set_power_state_locked(pdev, PCI_D0);
773
+
pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
765
774
return 0;
766
775
}
767
776
···
1105
1100
.driver_data = VMD_FEATS_CLIENT,},
1106
1101
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
1107
1102
.driver_data = VMD_FEATS_CLIENT,},
1103
+
{PCI_VDEVICE(INTEL, 0xb60b),
1104
+
.driver_data = VMD_FEATS_CLIENT,},
1105
+
{PCI_VDEVICE(INTEL, 0xb06f),
1106
+
.driver_data = VMD_FEATS_CLIENT,},
1108
1107
{0,}
1109
1108
};
1110
1109
MODULE_DEVICE_TABLE(pci, vmd_ids);
+8
-59
drivers/pci/devres.c
+8
-59
drivers/pci/devres.c
···
773
773
* Unmap a BAR and release its region manually. Only pass BARs that were
774
774
* previously mapped by pcim_iomap_region().
775
775
*/
776
-
static void pcim_iounmap_region(struct pci_dev *pdev, int bar)
776
+
void pcim_iounmap_region(struct pci_dev *pdev, int bar)
777
777
{
778
778
struct pcim_addr_devres res_searched;
779
779
···
784
784
devres_release(&pdev->dev, pcim_addr_resource_release,
785
785
pcim_addr_resources_match, &res_searched);
786
786
}
787
+
EXPORT_SYMBOL(pcim_iounmap_region);
787
788
788
789
/**
789
790
* pcim_iomap_regions - Request and iomap PCI BARs (DEPRECATED)
···
940
939
* desired, release individual regions with pcim_release_region() or all of
941
940
* them at once with pcim_release_all_regions().
942
941
*/
943
-
static int pcim_request_all_regions(struct pci_dev *pdev, const char *name)
942
+
int pcim_request_all_regions(struct pci_dev *pdev, const char *name)
944
943
{
945
944
int ret;
946
945
int bar;
···
958
957
959
958
return ret;
960
959
}
960
+
EXPORT_SYMBOL(pcim_request_all_regions);
961
961
962
962
/**
963
-
* pcim_iomap_regions_request_all - Request all BARs and iomap specified ones
964
-
* (DEPRECATED)
965
-
* @pdev: PCI device to map IO resources for
966
-
* @mask: Mask of BARs to iomap
967
-
* @name: Name associated with the requests
968
-
*
969
-
* Returns: 0 on success, negative error code on failure.
970
-
*
971
-
* Request all PCI BARs and iomap regions specified by @mask.
972
-
*
973
-
* To release these resources manually, call pcim_release_region() for the
974
-
* regions and pcim_iounmap() for the mappings.
975
-
*
976
-
* This function is DEPRECATED. Don't use it in new code. Instead, use one
977
-
* of the pcim_* region request functions in combination with a pcim_*
978
-
* mapping function.
979
-
*/
980
-
int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
981
-
const char *name)
982
-
{
983
-
int bar;
984
-
int ret;
985
-
void __iomem **legacy_iomap_table;
986
-
987
-
ret = pcim_request_all_regions(pdev, name);
988
-
if (ret != 0)
989
-
return ret;
990
-
991
-
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
992
-
if (!mask_contains_bar(mask, bar))
993
-
continue;
994
-
if (!pcim_iomap(pdev, bar, 0))
995
-
goto err;
996
-
}
997
-
998
-
return 0;
999
-
1000
-
err:
1001
-
/*
1002
-
* If bar is larger than 0, then pcim_iomap() above has most likely
1003
-
* failed because of -EINVAL. If it is equal 0, most likely the table
1004
-
* couldn't be created, indicating -ENOMEM.
1005
-
*/
1006
-
ret = bar > 0 ? -EINVAL : -ENOMEM;
1007
-
legacy_iomap_table = (void __iomem **)pcim_iomap_table(pdev);
1008
-
1009
-
while (--bar >= 0)
1010
-
pcim_iounmap(pdev, legacy_iomap_table[bar]);
1011
-
1012
-
pcim_release_all_regions(pdev);
1013
-
1014
-
return ret;
1015
-
}
1016
-
EXPORT_SYMBOL(pcim_iomap_regions_request_all);
1017
-
1018
-
/**
1019
-
* pcim_iounmap_regions - Unmap and release PCI BARs
963
+
* pcim_iounmap_regions - Unmap and release PCI BARs (DEPRECATED)
1020
964
* @pdev: PCI device to map IO resources for
1021
965
* @mask: Mask of BARs to unmap and release
1022
966
*
1023
967
* Unmap and release regions specified by @mask.
968
+
*
969
+
* This function is DEPRECATED. Do not use it in new code.
970
+
* Use pcim_iounmap_region() instead.
1024
971
*/
1025
972
void pcim_iounmap_regions(struct pci_dev *pdev, int mask)
1026
973
{
+13
-1
drivers/pci/doe.c
+13
-1
drivers/pci/doe.c
···
146
146
{
147
147
struct pci_dev *pdev = doe_mb->pdev;
148
148
int offset = doe_mb->cap_offset;
149
+
unsigned long timeout_jiffies;
149
150
size_t length, remainder;
150
151
u32 val;
151
152
int i;
···
156
155
* someone other than Linux (e.g. firmware) is using the mailbox. Note
157
156
* it is expected that firmware and OS will negotiate access rights via
158
157
* an, as yet to be defined, method.
158
+
*
159
+
* Wait up to one PCI_DOE_TIMEOUT period to allow the prior command to
160
+
* finish. Otherwise, simply error out as unable to field the request.
161
+
*
162
+
* PCIe r6.2 sec 6.30.3 states no interrupt is raised when the DOE Busy
163
+
* bit is cleared, so polling here is our best option for the moment.
159
164
*/
160
-
pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
165
+
timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
166
+
do {
167
+
pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
168
+
} while (FIELD_GET(PCI_DOE_STATUS_BUSY, val) &&
169
+
!time_after(jiffies, timeout_jiffies));
170
+
161
171
if (FIELD_GET(PCI_DOE_STATUS_BUSY, val))
162
172
return -EBUSY;
163
173
+1
-1
drivers/pci/ecam.c
+1
-1
drivers/pci/ecam.c
···
55
55
bus_range_max = resource_size(cfgres) >> bus_shift;
56
56
if (bus_range > bus_range_max) {
57
57
bus_range = bus_range_max;
58
-
cfg->busr.end = busr->start + bus_range - 1;
58
+
resource_set_size(&cfg->busr, bus_range);
59
59
dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
60
60
cfgres, &cfg->busr, busr);
61
61
}
+6
drivers/pci/endpoint/functions/pci-epf-mhi.c
+6
drivers/pci/endpoint/functions/pci-epf-mhi.c
···
867
867
{
868
868
struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
869
869
struct pci_epc *epc = epf->epc;
870
+
struct device *dev = &epf->dev;
870
871
struct platform_device *pdev = to_platform_device(epc->dev.parent);
871
872
struct resource *res;
872
873
int ret;
873
874
874
875
/* Get MMIO base address from Endpoint controller */
875
876
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio");
877
+
if (!res) {
878
+
dev_err(dev, "Failed to get \"mmio\" resource\n");
879
+
return -ENODEV;
880
+
}
881
+
876
882
epf_mhi->mmio_phys = res->start;
877
883
epf_mhi->mmio_size = resource_size(res);
878
884
+196
-184
drivers/pci/endpoint/functions/pci-epf-test.c
+196
-184
drivers/pci/endpoint/functions/pci-epf-test.c
···
291
291
292
292
dma_release_channel(epf_test->dma_chan_rx);
293
293
epf_test->dma_chan_rx = NULL;
294
-
295
-
return;
296
294
}
297
295
298
296
static void pci_epf_test_print_rate(struct pci_epf_test *epf_test,
···
315
317
static void pci_epf_test_copy(struct pci_epf_test *epf_test,
316
318
struct pci_epf_test_reg *reg)
317
319
{
318
-
int ret;
319
-
void __iomem *src_addr;
320
-
void __iomem *dst_addr;
321
-
phys_addr_t src_phys_addr;
322
-
phys_addr_t dst_phys_addr;
320
+
int ret = 0;
323
321
struct timespec64 start, end;
324
322
struct pci_epf *epf = epf_test->epf;
325
-
struct device *dev = &epf->dev;
326
323
struct pci_epc *epc = epf->epc;
324
+
struct device *dev = &epf->dev;
325
+
struct pci_epc_map src_map, dst_map;
326
+
u64 src_addr = reg->src_addr;
327
+
u64 dst_addr = reg->dst_addr;
328
+
size_t copy_size = reg->size;
329
+
ssize_t map_size = 0;
330
+
void *copy_buf = NULL, *buf;
327
331
328
-
src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
329
-
if (!src_addr) {
330
-
dev_err(dev, "Failed to allocate source address\n");
331
-
reg->status = STATUS_SRC_ADDR_INVALID;
332
-
ret = -ENOMEM;
333
-
goto err;
334
-
}
335
-
336
-
ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, src_phys_addr,
337
-
reg->src_addr, reg->size);
338
-
if (ret) {
339
-
dev_err(dev, "Failed to map source address\n");
340
-
reg->status = STATUS_SRC_ADDR_INVALID;
341
-
goto err_src_addr;
342
-
}
343
-
344
-
dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
345
-
if (!dst_addr) {
346
-
dev_err(dev, "Failed to allocate destination address\n");
347
-
reg->status = STATUS_DST_ADDR_INVALID;
348
-
ret = -ENOMEM;
349
-
goto err_src_map_addr;
350
-
}
351
-
352
-
ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr,
353
-
reg->dst_addr, reg->size);
354
-
if (ret) {
355
-
dev_err(dev, "Failed to map destination address\n");
356
-
reg->status = STATUS_DST_ADDR_INVALID;
357
-
goto err_dst_addr;
358
-
}
359
-
360
-
ktime_get_ts64(&start);
361
332
if (reg->flags & FLAG_USE_DMA) {
362
333
if (epf_test->dma_private) {
363
334
dev_err(dev, "Cannot transfer data using DMA\n");
364
335
ret = -EINVAL;
365
-
goto err_map_addr;
336
+
goto set_status;
366
337
}
367
-
368
-
ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr,
369
-
src_phys_addr, reg->size, 0,
370
-
DMA_MEM_TO_MEM);
371
-
if (ret)
372
-
dev_err(dev, "Data transfer failed\n");
373
338
} else {
374
-
void *buf;
375
-
376
-
buf = kzalloc(reg->size, GFP_KERNEL);
377
-
if (!buf) {
339
+
copy_buf = kzalloc(copy_size, GFP_KERNEL);
340
+
if (!copy_buf) {
378
341
ret = -ENOMEM;
379
-
goto err_map_addr;
342
+
goto set_status;
343
+
}
344
+
buf = copy_buf;
345
+
}
346
+
347
+
while (copy_size) {
348
+
ret = pci_epc_mem_map(epc, epf->func_no, epf->vfunc_no,
349
+
src_addr, copy_size, &src_map);
350
+
if (ret) {
351
+
dev_err(dev, "Failed to map source address\n");
352
+
reg->status = STATUS_SRC_ADDR_INVALID;
353
+
goto free_buf;
380
354
}
381
355
382
-
memcpy_fromio(buf, src_addr, reg->size);
383
-
memcpy_toio(dst_addr, buf, reg->size);
384
-
kfree(buf);
356
+
ret = pci_epc_mem_map(epf->epc, epf->func_no, epf->vfunc_no,
357
+
dst_addr, copy_size, &dst_map);
358
+
if (ret) {
359
+
dev_err(dev, "Failed to map destination address\n");
360
+
reg->status = STATUS_DST_ADDR_INVALID;
361
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no,
362
+
&src_map);
363
+
goto free_buf;
364
+
}
365
+
366
+
map_size = min_t(size_t, dst_map.pci_size, src_map.pci_size);
367
+
368
+
ktime_get_ts64(&start);
369
+
if (reg->flags & FLAG_USE_DMA) {
370
+
ret = pci_epf_test_data_transfer(epf_test,
371
+
dst_map.phys_addr, src_map.phys_addr,
372
+
map_size, 0, DMA_MEM_TO_MEM);
373
+
if (ret) {
374
+
dev_err(dev, "Data transfer failed\n");
375
+
goto unmap;
376
+
}
377
+
} else {
378
+
memcpy_fromio(buf, src_map.virt_addr, map_size);
379
+
memcpy_toio(dst_map.virt_addr, buf, map_size);
380
+
buf += map_size;
381
+
}
382
+
ktime_get_ts64(&end);
383
+
384
+
copy_size -= map_size;
385
+
src_addr += map_size;
386
+
dst_addr += map_size;
387
+
388
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &dst_map);
389
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &src_map);
390
+
map_size = 0;
385
391
}
386
-
ktime_get_ts64(&end);
387
-
pci_epf_test_print_rate(epf_test, "COPY", reg->size, &start, &end,
388
-
reg->flags & FLAG_USE_DMA);
389
392
390
-
err_map_addr:
391
-
pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr);
393
+
pci_epf_test_print_rate(epf_test, "COPY", reg->size, &start,
394
+
&end, reg->flags & FLAG_USE_DMA);
392
395
393
-
err_dst_addr:
394
-
pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
396
+
unmap:
397
+
if (map_size) {
398
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &dst_map);
399
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &src_map);
400
+
}
395
401
396
-
err_src_map_addr:
397
-
pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, src_phys_addr);
402
+
free_buf:
403
+
kfree(copy_buf);
398
404
399
-
err_src_addr:
400
-
pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
401
-
402
-
err:
405
+
set_status:
403
406
if (!ret)
404
407
reg->status |= STATUS_COPY_SUCCESS;
405
408
else
···
410
411
static void pci_epf_test_read(struct pci_epf_test *epf_test,
411
412
struct pci_epf_test_reg *reg)
412
413
{
413
-
int ret;
414
-
void __iomem *src_addr;
415
-
void *buf;
414
+
int ret = 0;
415
+
void *src_buf, *buf;
416
416
u32 crc32;
417
-
phys_addr_t phys_addr;
417
+
struct pci_epc_map map;
418
418
phys_addr_t dst_phys_addr;
419
419
struct timespec64 start, end;
420
420
struct pci_epf *epf = epf_test->epf;
421
-
struct device *dev = &epf->dev;
422
421
struct pci_epc *epc = epf->epc;
422
+
struct device *dev = &epf->dev;
423
423
struct device *dma_dev = epf->epc->dev.parent;
424
+
u64 src_addr = reg->src_addr;
425
+
size_t src_size = reg->size;
426
+
ssize_t map_size = 0;
424
427
425
-
src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
426
-
if (!src_addr) {
427
-
dev_err(dev, "Failed to allocate address\n");
428
-
reg->status = STATUS_SRC_ADDR_INVALID;
428
+
src_buf = kzalloc(src_size, GFP_KERNEL);
429
+
if (!src_buf) {
429
430
ret = -ENOMEM;
430
-
goto err;
431
+
goto set_status;
431
432
}
433
+
buf = src_buf;
432
434
433
-
ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr,
434
-
reg->src_addr, reg->size);
435
-
if (ret) {
436
-
dev_err(dev, "Failed to map address\n");
437
-
reg->status = STATUS_SRC_ADDR_INVALID;
438
-
goto err_addr;
439
-
}
440
-
441
-
buf = kzalloc(reg->size, GFP_KERNEL);
442
-
if (!buf) {
443
-
ret = -ENOMEM;
444
-
goto err_map_addr;
445
-
}
446
-
447
-
if (reg->flags & FLAG_USE_DMA) {
448
-
dst_phys_addr = dma_map_single(dma_dev, buf, reg->size,
449
-
DMA_FROM_DEVICE);
450
-
if (dma_mapping_error(dma_dev, dst_phys_addr)) {
451
-
dev_err(dev, "Failed to map destination buffer addr\n");
452
-
ret = -ENOMEM;
453
-
goto err_dma_map;
435
+
while (src_size) {
436
+
ret = pci_epc_mem_map(epc, epf->func_no, epf->vfunc_no,
437
+
src_addr, src_size, &map);
438
+
if (ret) {
439
+
dev_err(dev, "Failed to map address\n");
440
+
reg->status = STATUS_SRC_ADDR_INVALID;
441
+
goto free_buf;
454
442
}
455
443
456
-
ktime_get_ts64(&start);
457
-
ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr,
458
-
phys_addr, reg->size,
459
-
reg->src_addr, DMA_DEV_TO_MEM);
460
-
if (ret)
461
-
dev_err(dev, "Data transfer failed\n");
462
-
ktime_get_ts64(&end);
444
+
map_size = map.pci_size;
445
+
if (reg->flags & FLAG_USE_DMA) {
446
+
dst_phys_addr = dma_map_single(dma_dev, buf, map_size,
447
+
DMA_FROM_DEVICE);
448
+
if (dma_mapping_error(dma_dev, dst_phys_addr)) {
449
+
dev_err(dev,
450
+
"Failed to map destination buffer addr\n");
451
+
ret = -ENOMEM;
452
+
goto unmap;
453
+
}
463
454
464
-
dma_unmap_single(dma_dev, dst_phys_addr, reg->size,
465
-
DMA_FROM_DEVICE);
466
-
} else {
467
-
ktime_get_ts64(&start);
468
-
memcpy_fromio(buf, src_addr, reg->size);
469
-
ktime_get_ts64(&end);
455
+
ktime_get_ts64(&start);
456
+
ret = pci_epf_test_data_transfer(epf_test,
457
+
dst_phys_addr, map.phys_addr,
458
+
map_size, src_addr, DMA_DEV_TO_MEM);
459
+
if (ret)
460
+
dev_err(dev, "Data transfer failed\n");
461
+
ktime_get_ts64(&end);
462
+
463
+
dma_unmap_single(dma_dev, dst_phys_addr, map_size,
464
+
DMA_FROM_DEVICE);
465
+
466
+
if (ret)
467
+
goto unmap;
468
+
} else {
469
+
ktime_get_ts64(&start);
470
+
memcpy_fromio(buf, map.virt_addr, map_size);
471
+
ktime_get_ts64(&end);
472
+
}
473
+
474
+
src_size -= map_size;
475
+
src_addr += map_size;
476
+
buf += map_size;
477
+
478
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map);
479
+
map_size = 0;
470
480
}
471
481
472
-
pci_epf_test_print_rate(epf_test, "READ", reg->size, &start, &end,
473
-
reg->flags & FLAG_USE_DMA);
482
+
pci_epf_test_print_rate(epf_test, "READ", reg->size, &start,
483
+
&end, reg->flags & FLAG_USE_DMA);
474
484
475
-
crc32 = crc32_le(~0, buf, reg->size);
485
+
crc32 = crc32_le(~0, src_buf, reg->size);
476
486
if (crc32 != reg->checksum)
477
487
ret = -EIO;
478
488
479
-
err_dma_map:
480
-
kfree(buf);
489
+
unmap:
490
+
if (map_size)
491
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map);
481
492
482
-
err_map_addr:
483
-
pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr);
493
+
free_buf:
494
+
kfree(src_buf);
484
495
485
-
err_addr:
486
-
pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
487
-
488
-
err:
496
+
set_status:
489
497
if (!ret)
490
498
reg->status |= STATUS_READ_SUCCESS;
491
499
else
···
502
496
static void pci_epf_test_write(struct pci_epf_test *epf_test,
503
497
struct pci_epf_test_reg *reg)
504
498
{
505
-
int ret;
506
-
void __iomem *dst_addr;
507
-
void *buf;
508
-
phys_addr_t phys_addr;
499
+
int ret = 0;
500
+
void *dst_buf, *buf;
501
+
struct pci_epc_map map;
509
502
phys_addr_t src_phys_addr;
510
503
struct timespec64 start, end;
511
504
struct pci_epf *epf = epf_test->epf;
512
-
struct device *dev = &epf->dev;
513
505
struct pci_epc *epc = epf->epc;
506
+
struct device *dev = &epf->dev;
514
507
struct device *dma_dev = epf->epc->dev.parent;
508
+
u64 dst_addr = reg->dst_addr;
509
+
size_t dst_size = reg->size;
510
+
ssize_t map_size = 0;
515
511
516
-
dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
517
-
if (!dst_addr) {
518
-
dev_err(dev, "Failed to allocate address\n");
519
-
reg->status = STATUS_DST_ADDR_INVALID;
512
+
dst_buf = kzalloc(dst_size, GFP_KERNEL);
513
+
if (!dst_buf) {
520
514
ret = -ENOMEM;
521
-
goto err;
515
+
goto set_status;
522
516
}
517
+
get_random_bytes(dst_buf, dst_size);
518
+
reg->checksum = crc32_le(~0, dst_buf, dst_size);
519
+
buf = dst_buf;
523
520
524
-
ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr,
525
-
reg->dst_addr, reg->size);
526
-
if (ret) {
527
-
dev_err(dev, "Failed to map address\n");
528
-
reg->status = STATUS_DST_ADDR_INVALID;
529
-
goto err_addr;
530
-
}
531
-
532
-
buf = kzalloc(reg->size, GFP_KERNEL);
533
-
if (!buf) {
534
-
ret = -ENOMEM;
535
-
goto err_map_addr;
536
-
}
537
-
538
-
get_random_bytes(buf, reg->size);
539
-
reg->checksum = crc32_le(~0, buf, reg->size);
540
-
541
-
if (reg->flags & FLAG_USE_DMA) {
542
-
src_phys_addr = dma_map_single(dma_dev, buf, reg->size,
543
-
DMA_TO_DEVICE);
544
-
if (dma_mapping_error(dma_dev, src_phys_addr)) {
545
-
dev_err(dev, "Failed to map source buffer addr\n");
546
-
ret = -ENOMEM;
547
-
goto err_dma_map;
521
+
while (dst_size) {
522
+
ret = pci_epc_mem_map(epc, epf->func_no, epf->vfunc_no,
523
+
dst_addr, dst_size, &map);
524
+
if (ret) {
525
+
dev_err(dev, "Failed to map address\n");
526
+
reg->status = STATUS_DST_ADDR_INVALID;
527
+
goto free_buf;
548
528
}
549
529
550
-
ktime_get_ts64(&start);
530
+
map_size = map.pci_size;
531
+
if (reg->flags & FLAG_USE_DMA) {
532
+
src_phys_addr = dma_map_single(dma_dev, buf, map_size,
533
+
DMA_TO_DEVICE);
534
+
if (dma_mapping_error(dma_dev, src_phys_addr)) {
535
+
dev_err(dev,
536
+
"Failed to map source buffer addr\n");
537
+
ret = -ENOMEM;
538
+
goto unmap;
539
+
}
551
540
552
-
ret = pci_epf_test_data_transfer(epf_test, phys_addr,
553
-
src_phys_addr, reg->size,
554
-
reg->dst_addr,
555
-
DMA_MEM_TO_DEV);
556
-
if (ret)
557
-
dev_err(dev, "Data transfer failed\n");
558
-
ktime_get_ts64(&end);
541
+
ktime_get_ts64(&start);
559
542
560
-
dma_unmap_single(dma_dev, src_phys_addr, reg->size,
561
-
DMA_TO_DEVICE);
562
-
} else {
563
-
ktime_get_ts64(&start);
564
-
memcpy_toio(dst_addr, buf, reg->size);
565
-
ktime_get_ts64(&end);
543
+
ret = pci_epf_test_data_transfer(epf_test,
544
+
map.phys_addr, src_phys_addr,
545
+
map_size, dst_addr,
546
+
DMA_MEM_TO_DEV);
547
+
if (ret)
548
+
dev_err(dev, "Data transfer failed\n");
549
+
ktime_get_ts64(&end);
550
+
551
+
dma_unmap_single(dma_dev, src_phys_addr, map_size,
552
+
DMA_TO_DEVICE);
553
+
554
+
if (ret)
555
+
goto unmap;
556
+
} else {
557
+
ktime_get_ts64(&start);
558
+
memcpy_toio(map.virt_addr, buf, map_size);
559
+
ktime_get_ts64(&end);
560
+
}
561
+
562
+
dst_size -= map_size;
563
+
dst_addr += map_size;
564
+
buf += map_size;
565
+
566
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map);
567
+
map_size = 0;
566
568
}
567
569
568
-
pci_epf_test_print_rate(epf_test, "WRITE", reg->size, &start, &end,
569
-
reg->flags & FLAG_USE_DMA);
570
+
pci_epf_test_print_rate(epf_test, "WRITE", reg->size, &start,
571
+
&end, reg->flags & FLAG_USE_DMA);
570
572
571
573
/*
572
574
* wait 1ms inorder for the write to complete. Without this delay L3
···
582
568
*/
583
569
usleep_range(1000, 2000);
584
570
585
-
err_dma_map:
586
-
kfree(buf);
571
+
unmap:
572
+
if (map_size)
573
+
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map);
587
574
588
-
err_map_addr:
589
-
pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr);
575
+
free_buf:
576
+
kfree(dst_buf);
590
577
591
-
err_addr:
592
-
pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
593
-
594
-
err:
578
+
set_status:
595
579
if (!ret)
596
580
reg->status |= STATUS_WRITE_SUCCESS;
597
581
else
···
798
786
{
799
787
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
800
788
801
-
cancel_delayed_work(&epf_test->cmd_handler);
789
+
cancel_delayed_work_sync(&epf_test->cmd_handler);
802
790
pci_epf_test_clean_dma_chan(epf_test);
803
791
pci_epf_test_clear_bar(epf);
804
792
}
···
929
917
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
930
918
struct pci_epc *epc = epf->epc;
931
919
932
-
cancel_delayed_work(&epf_test->cmd_handler);
920
+
cancel_delayed_work_sync(&epf_test->cmd_handler);
933
921
if (epc->init_complete) {
934
922
pci_epf_test_clean_dma_chan(epf_test);
935
923
pci_epf_test_clear_bar(epf);
+139
-54
drivers/pci/endpoint/pci-epc-core.c
+139
-54
drivers/pci/endpoint/pci-epc-core.c
···
128
128
}
129
129
EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar);
130
130
131
+
static bool pci_epc_function_is_valid(struct pci_epc *epc,
132
+
u8 func_no, u8 vfunc_no)
133
+
{
134
+
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
135
+
return false;
136
+
137
+
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
138
+
return false;
139
+
140
+
return true;
141
+
}
142
+
131
143
/**
132
144
* pci_epc_get_features() - get the features supported by EPC
133
145
* @epc: the features supported by *this* EPC device will be returned
···
157
145
{
158
146
const struct pci_epc_features *epc_features;
159
147
160
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
161
-
return NULL;
162
-
163
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
148
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
164
149
return NULL;
165
150
166
151
if (!epc->ops->get_features)
···
227
218
{
228
219
int ret;
229
220
230
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
231
-
return -EINVAL;
232
-
233
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
221
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
234
222
return -EINVAL;
235
223
236
224
if (!epc->ops->raise_irq)
···
268
262
{
269
263
int ret;
270
264
271
-
if (IS_ERR_OR_NULL(epc))
272
-
return -EINVAL;
273
-
274
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
265
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
275
266
return -EINVAL;
276
267
277
268
if (!epc->ops->map_msi_irq)
···
296
293
{
297
294
int interrupt;
298
295
299
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
300
-
return 0;
301
-
302
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
296
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
303
297
return 0;
304
298
305
299
if (!epc->ops->get_msi)
···
329
329
int ret;
330
330
u8 encode_int;
331
331
332
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
333
-
interrupts < 1 || interrupts > 32)
332
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
334
333
return -EINVAL;
335
334
336
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
335
+
if (interrupts < 1 || interrupts > 32)
337
336
return -EINVAL;
338
337
339
338
if (!epc->ops->set_msi)
···
360
361
{
361
362
int interrupt;
362
363
363
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
364
-
return 0;
365
-
366
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
364
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
367
365
return 0;
368
366
369
367
if (!epc->ops->get_msix)
···
393
397
{
394
398
int ret;
395
399
396
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
397
-
interrupts < 1 || interrupts > 2048)
400
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
398
401
return -EINVAL;
399
402
400
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
403
+
if (interrupts < 1 || interrupts > 2048)
401
404
return -EINVAL;
402
405
403
406
if (!epc->ops->set_msix)
···
423
428
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
424
429
phys_addr_t phys_addr)
425
430
{
426
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
427
-
return;
428
-
429
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
431
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
430
432
return;
431
433
432
434
if (!epc->ops->unmap_addr)
···
451
459
{
452
460
int ret;
453
461
454
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
455
-
return -EINVAL;
456
-
457
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
462
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
458
463
return -EINVAL;
459
464
460
465
if (!epc->ops->map_addr)
···
467
478
EXPORT_SYMBOL_GPL(pci_epc_map_addr);
468
479
469
480
/**
481
+
* pci_epc_mem_map() - allocate and map a PCI address to a CPU address
482
+
* @epc: the EPC device on which the CPU address is to be allocated and mapped
483
+
* @func_no: the physical endpoint function number in the EPC device
484
+
* @vfunc_no: the virtual endpoint function number in the physical function
485
+
* @pci_addr: PCI address to which the CPU address should be mapped
486
+
* @pci_size: the number of bytes to map starting from @pci_addr
487
+
* @map: where to return the mapping information
488
+
*
489
+
* Allocate a controller memory address region and map it to a RC PCI address
490
+
* region, taking into account the controller physical address mapping
491
+
* constraints using the controller operation align_addr(). If this operation is
492
+
* not defined, we assume that there are no alignment constraints for the
493
+
* mapping.
494
+
*
495
+
* The effective size of the PCI address range mapped from @pci_addr is
496
+
* indicated by @map->pci_size. This size may be less than the requested
497
+
* @pci_size. The local virtual CPU address for the mapping is indicated by
498
+
* @map->virt_addr (@map->phys_addr indicates the physical address).
499
+
* The size and CPU address of the controller memory allocated and mapped are
500
+
* respectively indicated by @map->map_size and @map->virt_base (and
501
+
* @map->phys_base for the physical address of @map->virt_base).
502
+
*
503
+
* Returns 0 on success and a negative error code in case of error.
504
+
*/
505
+
int pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
506
+
u64 pci_addr, size_t pci_size, struct pci_epc_map *map)
507
+
{
508
+
size_t map_size = pci_size;
509
+
size_t map_offset = 0;
510
+
int ret;
511
+
512
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
513
+
return -EINVAL;
514
+
515
+
if (!pci_size || !map)
516
+
return -EINVAL;
517
+
518
+
/*
519
+
* Align the PCI address to map. If the controller defines the
520
+
* .align_addr() operation, use it to determine the PCI address to map
521
+
* and the size of the mapping. Otherwise, assume that the controller
522
+
* has no alignment constraint.
523
+
*/
524
+
memset(map, 0, sizeof(*map));
525
+
map->pci_addr = pci_addr;
526
+
if (epc->ops->align_addr)
527
+
map->map_pci_addr =
528
+
epc->ops->align_addr(epc, pci_addr,
529
+
&map_size, &map_offset);
530
+
else
531
+
map->map_pci_addr = pci_addr;
532
+
map->map_size = map_size;
533
+
if (map->map_pci_addr + map->map_size < pci_addr + pci_size)
534
+
map->pci_size = map->map_pci_addr + map->map_size - pci_addr;
535
+
else
536
+
map->pci_size = pci_size;
537
+
538
+
map->virt_base = pci_epc_mem_alloc_addr(epc, &map->phys_base,
539
+
map->map_size);
540
+
if (!map->virt_base)
541
+
return -ENOMEM;
542
+
543
+
map->phys_addr = map->phys_base + map_offset;
544
+
map->virt_addr = map->virt_base + map_offset;
545
+
546
+
ret = pci_epc_map_addr(epc, func_no, vfunc_no, map->phys_base,
547
+
map->map_pci_addr, map->map_size);
548
+
if (ret) {
549
+
pci_epc_mem_free_addr(epc, map->phys_base, map->virt_base,
550
+
map->map_size);
551
+
return ret;
552
+
}
553
+
554
+
return 0;
555
+
}
556
+
EXPORT_SYMBOL_GPL(pci_epc_mem_map);
557
+
558
+
/**
559
+
* pci_epc_mem_unmap() - unmap and free a CPU address region
560
+
* @epc: the EPC device on which the CPU address is allocated and mapped
561
+
* @func_no: the physical endpoint function number in the EPC device
562
+
* @vfunc_no: the virtual endpoint function number in the physical function
563
+
* @map: the mapping information
564
+
*
565
+
* Unmap and free a CPU address region that was allocated and mapped with
566
+
* pci_epc_mem_map().
567
+
*/
568
+
void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
569
+
struct pci_epc_map *map)
570
+
{
571
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
572
+
return;
573
+
574
+
if (!map || !map->virt_base)
575
+
return;
576
+
577
+
pci_epc_unmap_addr(epc, func_no, vfunc_no, map->phys_base);
578
+
pci_epc_mem_free_addr(epc, map->phys_base, map->virt_base,
579
+
map->map_size);
580
+
}
581
+
EXPORT_SYMBOL_GPL(pci_epc_mem_unmap);
582
+
583
+
/**
470
584
* pci_epc_clear_bar() - reset the BAR
471
585
* @epc: the EPC device for which the BAR has to be cleared
472
586
* @func_no: the physical endpoint function number in the EPC device
···
581
489
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
582
490
struct pci_epf_bar *epf_bar)
583
491
{
584
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
585
-
(epf_bar->barno == BAR_5 &&
586
-
epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
492
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
587
493
return;
588
494
589
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
495
+
if (epf_bar->barno == BAR_5 &&
496
+
epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
590
497
return;
591
498
592
499
if (!epc->ops->clear_bar)
···
612
521
int ret;
613
522
int flags = epf_bar->flags;
614
523
615
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
616
-
(epf_bar->barno == BAR_5 &&
617
-
flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
524
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
525
+
return -EINVAL;
526
+
527
+
if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
618
528
(flags & PCI_BASE_ADDRESS_SPACE_IO &&
619
529
flags & PCI_BASE_ADDRESS_IO_MASK) ||
620
530
(upper_32_bits(epf_bar->size) &&
621
531
!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
622
-
return -EINVAL;
623
-
624
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
625
532
return -EINVAL;
626
533
627
534
if (!epc->ops->set_bar)
···
650
561
{
651
562
int ret;
652
563
653
-
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
654
-
return -EINVAL;
655
-
656
-
if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no]))
564
+
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
657
565
return -EINVAL;
658
566
659
567
/* Only Virtual Function #1 has deviceID */
···
746
660
if (IS_ERR_OR_NULL(epc) || !epf)
747
661
return;
748
662
663
+
mutex_lock(&epc->list_lock);
749
664
if (type == PRIMARY_INTERFACE) {
750
665
func_no = epf->func_no;
751
666
list = &epf->list;
667
+
epf->epc = NULL;
752
668
} else {
753
669
func_no = epf->sec_epc_func_no;
754
670
list = &epf->sec_epc_list;
671
+
epf->sec_epc = NULL;
755
672
}
756
-
757
-
mutex_lock(&epc->list_lock);
758
673
clear_bit(func_no, &epc->function_num_map);
759
674
list_del(list);
760
-
epf->epc = NULL;
761
675
mutex_unlock(&epc->list_lock);
762
676
}
763
677
EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
···
923
837
void pci_epc_destroy(struct pci_epc *epc)
924
838
{
925
839
pci_ep_cfs_remove_epc_group(epc->group);
926
-
device_unregister(&epc->dev);
927
-
928
840
#ifdef CONFIG_PCI_DOMAINS_GENERIC
929
-
pci_bus_release_domain_nr(&epc->dev, epc->domain_nr);
841
+
pci_bus_release_domain_nr(epc->dev.parent, epc->domain_nr);
930
842
#endif
843
+
device_unregister(&epc->dev);
931
844
}
932
845
EXPORT_SYMBOL_GPL(pci_epc_destroy);
933
846
+6
-3
drivers/pci/endpoint/pci-epc-mem.c
+6
-3
drivers/pci/endpoint/pci-epc-mem.c
···
178
178
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
179
179
phys_addr_t *phys_addr, size_t size)
180
180
{
181
-
void __iomem *virt_addr = NULL;
181
+
void __iomem *virt_addr;
182
182
struct pci_epc_mem *mem;
183
183
unsigned int page_shift;
184
184
size_t align_size;
···
188
188
189
189
for (i = 0; i < epc->num_windows; i++) {
190
190
mem = epc->windows[i];
191
-
mutex_lock(&mem->lock);
191
+
if (size > mem->window.size)
192
+
continue;
193
+
192
194
align_size = ALIGN(size, mem->window.page_size);
193
195
order = pci_epc_mem_get_order(mem, align_size);
194
196
197
+
mutex_lock(&mem->lock);
195
198
pageno = bitmap_find_free_region(mem->bitmap, mem->pages,
196
199
order);
197
200
if (pageno >= 0) {
···
214
211
mutex_unlock(&mem->lock);
215
212
}
216
213
217
-
return virt_addr;
214
+
return NULL;
218
215
}
219
216
EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
220
217
+10
drivers/pci/hotplug/Kconfig
+10
drivers/pci/hotplug/Kconfig
···
118
118
119
119
When in doubt, say N.
120
120
121
+
config HOTPLUG_PCI_OCTEONEP
122
+
bool "Marvell OCTEON PCI Hotplug driver"
123
+
depends on HOTPLUG_PCI
124
+
help
125
+
Say Y here if you have an OCTEON PCIe device with a hotplug
126
+
controller. This driver enables the non-controller functions of the
127
+
device to be registered as hotplug slots.
128
+
129
+
When in doubt, say N.
130
+
121
131
config HOTPLUG_PCI_SHPC
122
132
bool "SHPC PCI Hotplug driver"
123
133
help
+1
drivers/pci/hotplug/Makefile
+1
drivers/pci/hotplug/Makefile
···
20
20
obj-$(CONFIG_HOTPLUG_PCI_RPA_DLPAR) += rpadlpar_io.o
21
21
obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o
22
22
obj-$(CONFIG_HOTPLUG_PCI_S390) += s390_pci_hpc.o
23
+
obj-$(CONFIG_HOTPLUG_PCI_OCTEONEP) += octep_hp.o
23
24
24
25
# acpiphp_ibm extends acpiphp, so should be linked afterwards.
25
26
+1
-1
drivers/pci/hotplug/acpiphp_ampere_altra.c
+1
-1
drivers/pci/hotplug/acpiphp_ampere_altra.c
-1
drivers/pci/hotplug/cpci_hotplug.h
-1
drivers/pci/hotplug/cpci_hotplug.h
+19
-28
drivers/pci/hotplug/cpqphp_pci.c
+19
-28
drivers/pci/hotplug/cpqphp_pci.c
···
12
12
*
13
13
*/
14
14
15
+
#define pr_fmt(fmt) "cpqphp: " fmt
16
+
15
17
#include <linux/module.h>
16
18
#include <linux/kernel.h>
19
+
#include <linux/printk.h>
17
20
#include <linux/types.h>
18
21
#include <linux/slab.h>
19
22
#include <linux/workqueue.h>
···
135
132
return 0;
136
133
}
137
134
138
-
static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
139
-
{
140
-
u32 vendID = 0;
141
-
142
-
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
143
-
return -1;
144
-
if (PCI_POSSIBLE_ERROR(vendID))
145
-
return -1;
146
-
return pci_bus_read_config_dword(bus, devfn, offset, value);
147
-
}
148
-
149
-
150
135
/*
151
136
* cpqhp_set_irq
152
137
*
···
193
202
{
194
203
u16 tdevice;
195
204
u32 work;
196
-
u8 tbus;
205
+
int ret = -1;
197
206
198
207
ctrl->pci_bus->number = bus_num;
199
208
200
209
for (tdevice = 0; tdevice < 0xFF; tdevice++) {
201
210
/* Scan for access first */
202
-
if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
211
+
if (!pci_bus_read_dev_vendor_id(ctrl->pci_bus, tdevice, &work, 0))
212
+
continue;
213
+
ret = pci_bus_read_config_dword(ctrl->pci_bus, tdevice, PCI_CLASS_REVISION, &work);
214
+
if (ret)
203
215
continue;
204
216
dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
205
217
/* Yep we got one. Not a bridge ? */
···
210
216
*dev_num = tdevice;
211
217
dbg("found it !\n");
212
218
return 0;
213
-
}
214
-
}
215
-
for (tdevice = 0; tdevice < 0xFF; tdevice++) {
216
-
/* Scan for access first */
217
-
if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
218
-
continue;
219
-
dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
220
-
/* Yep we got one. bridge ? */
221
-
if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
222
-
pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
223
-
/* XXX: no recursion, wtf? */
224
-
dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
225
-
return 0;
219
+
} else {
220
+
/*
221
+
* XXX: Code whose debug printout indicated
222
+
* recursion to buses underneath bridges might be
223
+
* necessary was removed because it never did
224
+
* any recursion.
225
+
*/
226
+
ret = 0;
227
+
pr_warn("missing feature: bridge scan recursion not implemented\n");
226
228
}
227
229
}
228
230
229
-
return -1;
231
+
232
+
return ret;
230
233
}
231
234
232
235
-1
drivers/pci/hotplug/cpqphp_sysfs.c
-1
drivers/pci/hotplug/cpqphp_sysfs.c
+427
drivers/pci/hotplug/octep_hp.c
+427
drivers/pci/hotplug/octep_hp.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright (C) 2024 Marvell. */
3
+
4
+
#include <linux/cleanup.h>
5
+
#include <linux/container_of.h>
6
+
#include <linux/delay.h>
7
+
#include <linux/dev_printk.h>
8
+
#include <linux/init.h>
9
+
#include <linux/interrupt.h>
10
+
#include <linux/io-64-nonatomic-lo-hi.h>
11
+
#include <linux/kernel.h>
12
+
#include <linux/list.h>
13
+
#include <linux/module.h>
14
+
#include <linux/mutex.h>
15
+
#include <linux/pci.h>
16
+
#include <linux/pci_hotplug.h>
17
+
#include <linux/slab.h>
18
+
#include <linux/spinlock.h>
19
+
#include <linux/workqueue.h>
20
+
21
+
#define OCTEP_HP_INTR_OFFSET(x) (0x20400 + ((x) << 4))
22
+
#define OCTEP_HP_INTR_VECTOR(x) (16 + (x))
23
+
#define OCTEP_HP_DRV_NAME "octep_hp"
24
+
25
+
/*
26
+
* Type of MSI-X interrupts. OCTEP_HP_INTR_VECTOR() and
27
+
* OCTEP_HP_INTR_OFFSET() generate the vector and offset for an interrupt
28
+
* type.
29
+
*/
30
+
enum octep_hp_intr_type {
31
+
OCTEP_HP_INTR_INVALID = -1,
32
+
OCTEP_HP_INTR_ENA = 0,
33
+
OCTEP_HP_INTR_DIS = 1,
34
+
OCTEP_HP_INTR_MAX = 2,
35
+
};
36
+
37
+
struct octep_hp_cmd {
38
+
struct list_head list;
39
+
enum octep_hp_intr_type intr_type;
40
+
u64 intr_val;
41
+
};
42
+
43
+
struct octep_hp_slot {
44
+
struct list_head list;
45
+
struct hotplug_slot slot;
46
+
u16 slot_number;
47
+
struct pci_dev *hp_pdev;
48
+
unsigned int hp_devfn;
49
+
struct octep_hp_controller *ctrl;
50
+
};
51
+
52
+
struct octep_hp_intr_info {
53
+
enum octep_hp_intr_type type;
54
+
int number;
55
+
char name[16];
56
+
};
57
+
58
+
struct octep_hp_controller {
59
+
void __iomem *base;
60
+
struct pci_dev *pdev;
61
+
struct octep_hp_intr_info intr[OCTEP_HP_INTR_MAX];
62
+
struct work_struct work;
63
+
struct list_head slot_list;
64
+
struct mutex slot_lock; /* Protects slot_list */
65
+
struct list_head hp_cmd_list;
66
+
spinlock_t hp_cmd_lock; /* Protects hp_cmd_list */
67
+
};
68
+
69
+
static void octep_hp_enable_pdev(struct octep_hp_controller *hp_ctrl,
70
+
struct octep_hp_slot *hp_slot)
71
+
{
72
+
guard(mutex)(&hp_ctrl->slot_lock);
73
+
if (hp_slot->hp_pdev) {
74
+
pci_dbg(hp_slot->hp_pdev, "Slot %s is already enabled\n",
75
+
hotplug_slot_name(&hp_slot->slot));
76
+
return;
77
+
}
78
+
79
+
/* Scan the device and add it to the bus */
80
+
hp_slot->hp_pdev = pci_scan_single_device(hp_ctrl->pdev->bus,
81
+
hp_slot->hp_devfn);
82
+
pci_bus_assign_resources(hp_ctrl->pdev->bus);
83
+
pci_bus_add_device(hp_slot->hp_pdev);
84
+
85
+
dev_dbg(&hp_slot->hp_pdev->dev, "Enabled slot %s\n",
86
+
hotplug_slot_name(&hp_slot->slot));
87
+
}
88
+
89
+
static void octep_hp_disable_pdev(struct octep_hp_controller *hp_ctrl,
90
+
struct octep_hp_slot *hp_slot)
91
+
{
92
+
guard(mutex)(&hp_ctrl->slot_lock);
93
+
if (!hp_slot->hp_pdev) {
94
+
pci_dbg(hp_ctrl->pdev, "Slot %s is already disabled\n",
95
+
hotplug_slot_name(&hp_slot->slot));
96
+
return;
97
+
}
98
+
99
+
pci_dbg(hp_slot->hp_pdev, "Disabling slot %s\n",
100
+
hotplug_slot_name(&hp_slot->slot));
101
+
102
+
/* Remove the device from the bus */
103
+
pci_stop_and_remove_bus_device_locked(hp_slot->hp_pdev);
104
+
hp_slot->hp_pdev = NULL;
105
+
}
106
+
107
+
static int octep_hp_enable_slot(struct hotplug_slot *slot)
108
+
{
109
+
struct octep_hp_slot *hp_slot =
110
+
container_of(slot, struct octep_hp_slot, slot);
111
+
112
+
octep_hp_enable_pdev(hp_slot->ctrl, hp_slot);
113
+
return 0;
114
+
}
115
+
116
+
static int octep_hp_disable_slot(struct hotplug_slot *slot)
117
+
{
118
+
struct octep_hp_slot *hp_slot =
119
+
container_of(slot, struct octep_hp_slot, slot);
120
+
121
+
octep_hp_disable_pdev(hp_slot->ctrl, hp_slot);
122
+
return 0;
123
+
}
124
+
125
+
static struct hotplug_slot_ops octep_hp_slot_ops = {
126
+
.enable_slot = octep_hp_enable_slot,
127
+
.disable_slot = octep_hp_disable_slot,
128
+
};
129
+
130
+
#define SLOT_NAME_SIZE 16
131
+
static struct octep_hp_slot *
132
+
octep_hp_register_slot(struct octep_hp_controller *hp_ctrl,
133
+
struct pci_dev *pdev, u16 slot_number)
134
+
{
135
+
char slot_name[SLOT_NAME_SIZE];
136
+
struct octep_hp_slot *hp_slot;
137
+
int ret;
138
+
139
+
hp_slot = kzalloc(sizeof(*hp_slot), GFP_KERNEL);
140
+
if (!hp_slot)
141
+
return ERR_PTR(-ENOMEM);
142
+
143
+
hp_slot->ctrl = hp_ctrl;
144
+
hp_slot->hp_pdev = pdev;
145
+
hp_slot->hp_devfn = pdev->devfn;
146
+
hp_slot->slot_number = slot_number;
147
+
hp_slot->slot.ops = &octep_hp_slot_ops;
148
+
149
+
snprintf(slot_name, sizeof(slot_name), "octep_hp_%u", slot_number);
150
+
ret = pci_hp_register(&hp_slot->slot, hp_ctrl->pdev->bus,
151
+
PCI_SLOT(pdev->devfn), slot_name);
152
+
if (ret) {
153
+
kfree(hp_slot);
154
+
return ERR_PTR(ret);
155
+
}
156
+
157
+
pci_info(pdev, "Registered slot %s for device %s\n",
158
+
slot_name, pci_name(pdev));
159
+
160
+
list_add_tail(&hp_slot->list, &hp_ctrl->slot_list);
161
+
octep_hp_disable_pdev(hp_ctrl, hp_slot);
162
+
163
+
return hp_slot;
164
+
}
165
+
166
+
static void octep_hp_deregister_slot(void *data)
167
+
{
168
+
struct octep_hp_slot *hp_slot = data;
169
+
struct octep_hp_controller *hp_ctrl = hp_slot->ctrl;
170
+
171
+
pci_hp_deregister(&hp_slot->slot);
172
+
octep_hp_enable_pdev(hp_ctrl, hp_slot);
173
+
list_del(&hp_slot->list);
174
+
kfree(hp_slot);
175
+
}
176
+
177
+
static const char *octep_hp_cmd_name(enum octep_hp_intr_type type)
178
+
{
179
+
switch (type) {
180
+
case OCTEP_HP_INTR_ENA:
181
+
return "hotplug enable";
182
+
case OCTEP_HP_INTR_DIS:
183
+
return "hotplug disable";
184
+
default:
185
+
return "invalid";
186
+
}
187
+
}
188
+
189
+
static void octep_hp_cmd_handler(struct octep_hp_controller *hp_ctrl,
190
+
struct octep_hp_cmd *hp_cmd)
191
+
{
192
+
struct octep_hp_slot *hp_slot;
193
+
194
+
/*
195
+
* Enable or disable the slots based on the slot mask.
196
+
* intr_val is a bit mask where each bit represents a slot.
197
+
*/
198
+
list_for_each_entry(hp_slot, &hp_ctrl->slot_list, list) {
199
+
if (!(hp_cmd->intr_val & BIT(hp_slot->slot_number)))
200
+
continue;
201
+
202
+
pci_info(hp_ctrl->pdev, "Received %s command for slot %s\n",
203
+
octep_hp_cmd_name(hp_cmd->intr_type),
204
+
hotplug_slot_name(&hp_slot->slot));
205
+
206
+
switch (hp_cmd->intr_type) {
207
+
case OCTEP_HP_INTR_ENA:
208
+
octep_hp_enable_pdev(hp_ctrl, hp_slot);
209
+
break;
210
+
case OCTEP_HP_INTR_DIS:
211
+
octep_hp_disable_pdev(hp_ctrl, hp_slot);
212
+
break;
213
+
default:
214
+
break;
215
+
}
216
+
}
217
+
}
218
+
219
+
static void octep_hp_work_handler(struct work_struct *work)
220
+
{
221
+
struct octep_hp_controller *hp_ctrl;
222
+
struct octep_hp_cmd *hp_cmd;
223
+
unsigned long flags;
224
+
225
+
hp_ctrl = container_of(work, struct octep_hp_controller, work);
226
+
227
+
/* Process all the hotplug commands */
228
+
spin_lock_irqsave(&hp_ctrl->hp_cmd_lock, flags);
229
+
while (!list_empty(&hp_ctrl->hp_cmd_list)) {
230
+
hp_cmd = list_first_entry(&hp_ctrl->hp_cmd_list,
231
+
struct octep_hp_cmd, list);
232
+
list_del(&hp_cmd->list);
233
+
spin_unlock_irqrestore(&hp_ctrl->hp_cmd_lock, flags);
234
+
235
+
octep_hp_cmd_handler(hp_ctrl, hp_cmd);
236
+
kfree(hp_cmd);
237
+
238
+
spin_lock_irqsave(&hp_ctrl->hp_cmd_lock, flags);
239
+
}
240
+
spin_unlock_irqrestore(&hp_ctrl->hp_cmd_lock, flags);
241
+
}
242
+
243
+
static enum octep_hp_intr_type octep_hp_intr_type(struct octep_hp_intr_info *intr,
244
+
int irq)
245
+
{
246
+
enum octep_hp_intr_type type;
247
+
248
+
for (type = OCTEP_HP_INTR_ENA; type < OCTEP_HP_INTR_MAX; type++) {
249
+
if (intr[type].number == irq)
250
+
return type;
251
+
}
252
+
253
+
return OCTEP_HP_INTR_INVALID;
254
+
}
255
+
256
+
static irqreturn_t octep_hp_intr_handler(int irq, void *data)
257
+
{
258
+
struct octep_hp_controller *hp_ctrl = data;
259
+
struct pci_dev *pdev = hp_ctrl->pdev;
260
+
enum octep_hp_intr_type type;
261
+
struct octep_hp_cmd *hp_cmd;
262
+
u64 intr_val;
263
+
264
+
type = octep_hp_intr_type(hp_ctrl->intr, irq);
265
+
if (type == OCTEP_HP_INTR_INVALID) {
266
+
pci_err(pdev, "Invalid interrupt %d\n", irq);
267
+
return IRQ_HANDLED;
268
+
}
269
+
270
+
/* Read and clear the interrupt */
271
+
intr_val = readq(hp_ctrl->base + OCTEP_HP_INTR_OFFSET(type));
272
+
writeq(intr_val, hp_ctrl->base + OCTEP_HP_INTR_OFFSET(type));
273
+
274
+
hp_cmd = kzalloc(sizeof(*hp_cmd), GFP_ATOMIC);
275
+
if (!hp_cmd)
276
+
return IRQ_HANDLED;
277
+
278
+
hp_cmd->intr_val = intr_val;
279
+
hp_cmd->intr_type = type;
280
+
281
+
/* Add the command to the list and schedule the work */
282
+
spin_lock(&hp_ctrl->hp_cmd_lock);
283
+
list_add_tail(&hp_cmd->list, &hp_ctrl->hp_cmd_list);
284
+
spin_unlock(&hp_ctrl->hp_cmd_lock);
285
+
schedule_work(&hp_ctrl->work);
286
+
287
+
return IRQ_HANDLED;
288
+
}
289
+
290
+
static void octep_hp_irq_cleanup(void *data)
291
+
{
292
+
struct octep_hp_controller *hp_ctrl = data;
293
+
294
+
pci_free_irq_vectors(hp_ctrl->pdev);
295
+
flush_work(&hp_ctrl->work);
296
+
}
297
+
298
+
static int octep_hp_request_irq(struct octep_hp_controller *hp_ctrl,
299
+
enum octep_hp_intr_type type)
300
+
{
301
+
struct pci_dev *pdev = hp_ctrl->pdev;
302
+
struct octep_hp_intr_info *intr;
303
+
int irq;
304
+
305
+
irq = pci_irq_vector(pdev, OCTEP_HP_INTR_VECTOR(type));
306
+
if (irq < 0)
307
+
return irq;
308
+
309
+
intr = &hp_ctrl->intr[type];
310
+
intr->number = irq;
311
+
intr->type = type;
312
+
snprintf(intr->name, sizeof(intr->name), "octep_hp_%d", type);
313
+
314
+
return devm_request_irq(&pdev->dev, irq, octep_hp_intr_handler,
315
+
IRQF_SHARED, intr->name, hp_ctrl);
316
+
}
317
+
318
+
static int octep_hp_controller_setup(struct pci_dev *pdev,
319
+
struct octep_hp_controller *hp_ctrl)
320
+
{
321
+
struct device *dev = &pdev->dev;
322
+
enum octep_hp_intr_type type;
323
+
int ret;
324
+
325
+
ret = pcim_enable_device(pdev);
326
+
if (ret)
327
+
return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
328
+
329
+
hp_ctrl->base = pcim_iomap_region(pdev, 0, OCTEP_HP_DRV_NAME);
330
+
if (IS_ERR(hp_ctrl->base))
331
+
return dev_err_probe(dev, PTR_ERR(hp_ctrl->base),
332
+
"Failed to map PCI device region\n");
333
+
334
+
pci_set_master(pdev);
335
+
pci_set_drvdata(pdev, hp_ctrl);
336
+
337
+
INIT_LIST_HEAD(&hp_ctrl->slot_list);
338
+
INIT_LIST_HEAD(&hp_ctrl->hp_cmd_list);
339
+
mutex_init(&hp_ctrl->slot_lock);
340
+
spin_lock_init(&hp_ctrl->hp_cmd_lock);
341
+
INIT_WORK(&hp_ctrl->work, octep_hp_work_handler);
342
+
hp_ctrl->pdev = pdev;
343
+
344
+
ret = pci_alloc_irq_vectors(pdev, 1,
345
+
OCTEP_HP_INTR_VECTOR(OCTEP_HP_INTR_MAX),
346
+
PCI_IRQ_MSIX);
347
+
if (ret < 0)
348
+
return dev_err_probe(dev, ret, "Failed to alloc MSI-X vectors\n");
349
+
350
+
ret = devm_add_action(&pdev->dev, octep_hp_irq_cleanup, hp_ctrl);
351
+
if (ret)
352
+
return dev_err_probe(&pdev->dev, ret, "Failed to add IRQ cleanup action\n");
353
+
354
+
for (type = OCTEP_HP_INTR_ENA; type < OCTEP_HP_INTR_MAX; type++) {
355
+
ret = octep_hp_request_irq(hp_ctrl, type);
356
+
if (ret)
357
+
return dev_err_probe(dev, ret,
358
+
"Failed to request IRQ for vector %d\n",
359
+
OCTEP_HP_INTR_VECTOR(type));
360
+
}
361
+
362
+
return 0;
363
+
}
364
+
365
+
static int octep_hp_pci_probe(struct pci_dev *pdev,
366
+
const struct pci_device_id *id)
367
+
{
368
+
struct octep_hp_controller *hp_ctrl;
369
+
struct pci_dev *tmp_pdev, *next;
370
+
struct octep_hp_slot *hp_slot;
371
+
u16 slot_number = 0;
372
+
int ret;
373
+
374
+
hp_ctrl = devm_kzalloc(&pdev->dev, sizeof(*hp_ctrl), GFP_KERNEL);
375
+
if (!hp_ctrl)
376
+
return -ENOMEM;
377
+
378
+
ret = octep_hp_controller_setup(pdev, hp_ctrl);
379
+
if (ret)
380
+
return ret;
381
+
382
+
/*
383
+
* Register all hotplug slots. Hotplug controller is the first function
384
+
* of the PCI device. The hotplug slots are the remaining functions of
385
+
* the PCI device. The hotplug slot functions are logically removed from
386
+
* the bus during probing and are re-enabled by the driver when a
387
+
* hotplug event is received.
388
+
*/
389
+
list_for_each_entry_safe(tmp_pdev, next, &pdev->bus->devices, bus_list) {
390
+
if (tmp_pdev == pdev)
391
+
continue;
392
+
393
+
hp_slot = octep_hp_register_slot(hp_ctrl, tmp_pdev, slot_number);
394
+
if (IS_ERR(hp_slot))
395
+
return dev_err_probe(&pdev->dev, PTR_ERR(hp_slot),
396
+
"Failed to register hotplug slot %u\n",
397
+
slot_number);
398
+
399
+
ret = devm_add_action(&pdev->dev, octep_hp_deregister_slot,
400
+
hp_slot);
401
+
if (ret)
402
+
return dev_err_probe(&pdev->dev, ret,
403
+
"Failed to add action for deregistering slot %u\n",
404
+
slot_number);
405
+
slot_number++;
406
+
}
407
+
408
+
return 0;
409
+
}
410
+
411
+
#define PCI_DEVICE_ID_CAVIUM_OCTEP_HP_CTLR 0xa0e3
412
+
static struct pci_device_id octep_hp_pci_map[] = {
413
+
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_OCTEP_HP_CTLR) },
414
+
{ },
415
+
};
416
+
417
+
static struct pci_driver octep_hp = {
418
+
.name = OCTEP_HP_DRV_NAME,
419
+
.id_table = octep_hp_pci_map,
420
+
.probe = octep_hp_pci_probe,
421
+
};
422
+
423
+
module_pci_driver(octep_hp);
424
+
425
+
MODULE_LICENSE("GPL");
426
+
MODULE_AUTHOR("Marvell");
427
+
MODULE_DESCRIPTION("Marvell OCTEON PCI Hotplug driver");
+1
-7
drivers/pci/hotplug/pci_hotplug_core.c
+1
-7
drivers/pci/hotplug/pci_hotplug_core.c
···
388
388
389
389
/**
390
390
* __pci_hp_register - register a hotplug_slot with the PCI hotplug subsystem
391
-
* @bus: bus this slot is on
392
391
* @slot: pointer to the &struct hotplug_slot to register
392
+
* @bus: bus this slot is on
393
393
* @devnr: device number
394
394
* @name: name registered with kobject core
395
395
* @owner: caller module owner
···
498
498
*
499
499
* The @slot must have been registered with the pci hotplug subsystem
500
500
* previously with a call to pci_hp_register().
501
-
*
502
-
* Returns 0 if successful, anything else for an error.
503
501
*/
504
502
void pci_hp_deregister(struct hotplug_slot *slot)
505
503
{
···
511
513
* @slot: pointer to the &struct hotplug_slot to unpublish
512
514
*
513
515
* Remove a hotplug slot's sysfs interface.
514
-
*
515
-
* Returns 0 on success or a negative int on error.
516
516
*/
517
517
void pci_hp_del(struct hotplug_slot *slot)
518
518
{
···
541
545
* the driver may no longer invoke hotplug_slot_name() to get the slot's
542
546
* unique name. The driver no longer needs to handle a ->reset_slot callback
543
547
* from this point on.
544
-
*
545
-
* Returns 0 on success or a negative int on error.
546
548
*/
547
549
void pci_hp_destroy(struct hotplug_slot *slot)
548
550
{
+5
drivers/pci/hotplug/pciehp_ctrl.c
+5
drivers/pci/hotplug/pciehp_ctrl.c
···
19
19
#include <linux/types.h>
20
20
#include <linux/pm_runtime.h>
21
21
#include <linux/pci.h>
22
+
23
+
#include "../pci.h"
22
24
#include "pciehp.h"
23
25
24
26
/* The following routines constitute the bulk of the
···
129
127
130
128
pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
131
129
INDICATOR_NOOP);
130
+
131
+
/* Don't carry LBMS indications across */
132
+
pcie_reset_lbms_count(ctrl->pcie->port);
132
133
}
133
134
134
135
static int pciehp_enable_slot(struct controller *ctrl);
+1
-1
drivers/pci/hotplug/pciehp_hpc.c
+1
-1
drivers/pci/hotplug/pciehp_hpc.c
+3
-3
drivers/pci/iov.c
+3
-3
drivers/pci/iov.c
···
327
327
virtfn->resource[i].name = pci_name(virtfn);
328
328
virtfn->resource[i].flags = res->flags;
329
329
size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
330
-
virtfn->resource[i].start = res->start + size * id;
331
-
virtfn->resource[i].end = virtfn->resource[i].start + size - 1;
330
+
resource_set_range(&virtfn->resource[i],
331
+
res->start + size * id, size);
332
332
rc = request_resource(res, &virtfn->resource[i]);
333
333
BUG_ON(rc);
334
334
}
···
804
804
goto failed;
805
805
}
806
806
iov->barsz[i] = resource_size(res);
807
-
res->end = res->start + resource_size(res) * total - 1;
807
+
resource_set_size(res, resource_size(res) * total);
808
808
pci_info(dev, "%s %pR: contains BAR %d for %d VFs\n",
809
809
res_name, res, i, total);
810
810
i += bar64;
+27
drivers/pci/of.c
+27
drivers/pci/of.c
···
728
728
}
729
729
#endif
730
730
731
+
/**
732
+
* of_pci_supply_present() - Check if the power supply is present for the PCI
733
+
* device
734
+
* @np: Device tree node
735
+
*
736
+
* Check if the power supply for the PCI device is present in the device tree
737
+
* node or not.
738
+
*
739
+
* Return: true if at least one power supply exists; false otherwise.
740
+
*/
741
+
bool of_pci_supply_present(struct device_node *np)
742
+
{
743
+
struct property *prop;
744
+
char *supply;
745
+
746
+
if (!np)
747
+
return false;
748
+
749
+
for_each_property_of_node(np, prop) {
750
+
supply = strrchr(prop->name, '-');
751
+
if (supply && !strcmp(supply, "-supply"))
752
+
return true;
753
+
}
754
+
755
+
return false;
756
+
}
757
+
731
758
#endif /* CONFIG_PCI */
732
759
733
760
/**
+1
-1
drivers/pci/of_property.c
+1
-1
drivers/pci/of_property.c
+26
drivers/pci/pci-sysfs.c
+26
drivers/pci/pci-sysfs.c
···
521
521
static struct device_attribute dev_attr_bus_rescan = __ATTR(rescan, 0200, NULL,
522
522
bus_rescan_store);
523
523
524
+
static ssize_t reset_subordinate_store(struct device *dev,
525
+
struct device_attribute *attr,
526
+
const char *buf, size_t count)
527
+
{
528
+
struct pci_dev *pdev = to_pci_dev(dev);
529
+
struct pci_bus *bus = pdev->subordinate;
530
+
unsigned long val;
531
+
532
+
if (!capable(CAP_SYS_ADMIN))
533
+
return -EPERM;
534
+
535
+
if (kstrtoul(buf, 0, &val) < 0)
536
+
return -EINVAL;
537
+
538
+
if (val) {
539
+
int ret = __pci_reset_bus(bus);
540
+
541
+
if (ret)
542
+
return ret;
543
+
}
544
+
545
+
return count;
546
+
}
547
+
static DEVICE_ATTR_WO(reset_subordinate);
548
+
524
549
#if defined(CONFIG_PM) && defined(CONFIG_ACPI)
525
550
static ssize_t d3cold_allowed_store(struct device *dev,
526
551
struct device_attribute *attr,
···
650
625
static struct attribute *pci_bridge_attrs[] = {
651
626
&dev_attr_subordinate_bus_number.attr,
652
627
&dev_attr_secondary_bus_number.attr,
628
+
&dev_attr_reset_subordinate.attr,
653
629
NULL,
654
630
};
655
631
+66
-32
drivers/pci/pci.c
+66
-32
drivers/pci/pci.c
···
1832
1832
pci_save_dpc_state(dev);
1833
1833
pci_save_aer_state(dev);
1834
1834
pci_save_ptm_state(dev);
1835
+
pci_save_tph_state(dev);
1835
1836
return pci_save_vc_state(dev);
1836
1837
}
1837
1838
EXPORT_SYMBOL(pci_save_state);
···
1938
1937
pci_restore_rebar_state(dev);
1939
1938
pci_restore_dpc_state(dev);
1940
1939
pci_restore_ptm_state(dev);
1940
+
pci_restore_tph_state(dev);
1941
1941
1942
1942
pci_aer_clear_status(dev);
1943
1943
pci_restore_aer_state(dev);
···
4746
4744
* to track link speed or width changes made by hardware itself
4747
4745
* in attempt to correct unreliable link operation.
4748
4746
*/
4749
-
pcie_capability_write_word(pdev, PCI_EXP_LNKSTA, PCI_EXP_LNKSTA_LBMS);
4747
+
pcie_reset_lbms_count(pdev);
4750
4748
return rc;
4751
4749
}
4752
4750
···
5164
5162
*/
5165
5163
if (err_handler && err_handler->reset_prepare)
5166
5164
err_handler->reset_prepare(dev);
5165
+
else if (dev->driver)
5166
+
pci_warn(dev, "resetting");
5167
5167
5168
5168
/*
5169
5169
* Wake-up device prior to save. PM registers default to D0 after
···
5199
5195
*/
5200
5196
if (err_handler && err_handler->reset_done)
5201
5197
err_handler->reset_done(dev);
5198
+
else if (dev->driver)
5199
+
pci_warn(dev, "reset done");
5202
5200
}
5203
5201
5204
5202
/* dev->reset_methods[] is a 0-terminated list of indices into this array */
···
5254
5248
const char *buf, size_t count)
5255
5249
{
5256
5250
struct pci_dev *pdev = to_pci_dev(dev);
5257
-
char *options, *name;
5251
+
char *options, *tmp_options, *name;
5258
5252
int m, n;
5259
5253
u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5260
5254
···
5274
5268
return -ENOMEM;
5275
5269
5276
5270
n = 0;
5277
-
while ((name = strsep(&options, " ")) != NULL) {
5271
+
tmp_options = options;
5272
+
while ((name = strsep(&tmp_options, " ")) != NULL) {
5278
5273
if (sysfs_streq(name, ""))
5279
5274
continue;
5280
5275
···
5891
5884
*
5892
5885
* Same as above except return -EAGAIN if the bus cannot be locked
5893
5886
*/
5894
-
static int __pci_reset_bus(struct pci_bus *bus)
5887
+
int __pci_reset_bus(struct pci_bus *bus)
5895
5888
{
5896
5889
int rc;
5897
5890
···
6200
6193
EXPORT_SYMBOL(pcie_bandwidth_available);
6201
6194
6202
6195
/**
6196
+
* pcie_get_supported_speeds - query Supported Link Speed Vector
6197
+
* @dev: PCI device to query
6198
+
*
6199
+
* Query @dev supported link speeds.
6200
+
*
6201
+
* Implementation Note in PCIe r6.0 sec 7.5.3.18 recommends determining
6202
+
* supported link speeds using the Supported Link Speeds Vector in the Link
6203
+
* Capabilities 2 Register (when available).
6204
+
*
6205
+
* Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18.
6206
+
*
6207
+
* Without Link Capabilities 2, i.e., prior to PCIe r3.0, Supported Link
6208
+
* Speeds field in Link Capabilities is used and only 2.5 GT/s and 5.0 GT/s
6209
+
* speeds were defined.
6210
+
*
6211
+
* For @dev without Supported Link Speed Vector, the field is synthesized
6212
+
* from the Max Link Speed field in the Link Capabilities Register.
6213
+
*
6214
+
* Return: Supported Link Speeds Vector (+ reserved 0 at LSB).
6215
+
*/
6216
+
u8 pcie_get_supported_speeds(struct pci_dev *dev)
6217
+
{
6218
+
u32 lnkcap2, lnkcap;
6219
+
u8 speeds;
6220
+
6221
+
/*
6222
+
* Speeds retain the reserved 0 at LSB before PCIe Supported Link
6223
+
* Speeds Vector to allow using SLS Vector bit defines directly.
6224
+
*/
6225
+
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6226
+
speeds = lnkcap2 & PCI_EXP_LNKCAP2_SLS;
6227
+
6228
+
/* PCIe r3.0-compliant */
6229
+
if (speeds)
6230
+
return speeds;
6231
+
6232
+
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6233
+
6234
+
/* Synthesize from the Max Link Speed field */
6235
+
if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6236
+
speeds = PCI_EXP_LNKCAP2_SLS_5_0GB | PCI_EXP_LNKCAP2_SLS_2_5GB;
6237
+
else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6238
+
speeds = PCI_EXP_LNKCAP2_SLS_2_5GB;
6239
+
6240
+
return speeds;
6241
+
}
6242
+
6243
+
/**
6203
6244
* pcie_get_speed_cap - query for the PCI device's link speed capability
6204
6245
* @dev: PCI device to query
6205
6246
*
6206
-
* Query the PCI device speed capability. Return the maximum link speed
6207
-
* supported by the device.
6247
+
* Query the PCI device speed capability.
6248
+
*
6249
+
* Return: the maximum link speed supported by the device.
6208
6250
*/
6209
6251
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6210
6252
{
6211
-
u32 lnkcap2, lnkcap;
6212
-
6213
-
/*
6214
-
* Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6215
-
* implementation note there recommends using the Supported Link
6216
-
* Speeds Vector in Link Capabilities 2 when supported.
6217
-
*
6218
-
* Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6219
-
* should use the Supported Link Speeds field in Link Capabilities,
6220
-
* where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6221
-
*/
6222
-
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6223
-
6224
-
/* PCIe r3.0-compliant */
6225
-
if (lnkcap2)
6226
-
return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6227
-
6228
-
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6229
-
if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6230
-
return PCIE_SPEED_5_0GT;
6231
-
else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6232
-
return PCIE_SPEED_2_5GT;
6233
-
6234
-
return PCI_SPEED_UNKNOWN;
6253
+
return PCIE_LNKCAP2_SLS2SPEED(dev->supported_speeds);
6235
6254
}
6236
6255
EXPORT_SYMBOL(pcie_get_speed_cap);
6237
6256
···
6686
6653
} else {
6687
6654
r->flags &= ~IORESOURCE_SIZEALIGN;
6688
6655
r->flags |= IORESOURCE_STARTALIGN;
6689
-
r->start = align;
6690
-
r->end = r->start + size - 1;
6656
+
resource_set_range(r, align, size);
6691
6657
}
6692
6658
r->flags |= IORESOURCE_UNSET;
6693
6659
}
···
6932
6900
pci_no_domains();
6933
6901
} else if (!strncmp(str, "noari", 5)) {
6934
6902
pcie_ari_disabled = true;
6903
+
} else if (!strncmp(str, "notph", 5)) {
6904
+
pci_no_tph();
6935
6905
} else if (!strncmp(str, "cbiosize=", 9)) {
6936
6906
pci_cardbus_io_size = memparse(str + 9, &str);
6937
6907
} else if (!strncmp(str, "cbmemsize=", 10)) {
+74
-5
drivers/pci/pci.h
+74
-5
drivers/pci/pci.h
···
104
104
void pci_init_reset_methods(struct pci_dev *dev);
105
105
int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
106
106
int pci_bus_error_reset(struct pci_dev *dev);
107
+
int __pci_reset_bus(struct pci_bus *bus);
107
108
108
109
struct pci_cap_saved_data {
109
110
u16 cap_nr;
···
324
323
struct list_head *realloc_head,
325
324
struct list_head *fail_head);
326
325
bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
326
+
void pci_walk_bus_locked(struct pci_bus *top,
327
+
int (*cb)(struct pci_dev *, void *),
328
+
void *userdata);
327
329
328
330
const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
329
331
···
334
330
void pci_disable_bridge_window(struct pci_dev *dev);
335
331
struct pci_bus *pci_bus_get(struct pci_bus *bus);
336
332
void pci_bus_put(struct pci_bus *bus);
333
+
334
+
#define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
335
+
({ \
336
+
((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
337
+
(lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
338
+
(lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
339
+
(lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
340
+
(lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
341
+
(lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
342
+
PCI_SPEED_UNKNOWN); \
343
+
})
337
344
338
345
/* PCIe link information from Link Capabilities 2 */
339
346
#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
···
354
339
(lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
355
340
(lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
356
341
(lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
342
+
PCI_SPEED_UNKNOWN)
343
+
344
+
#define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
345
+
((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
346
+
(lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
347
+
(lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
348
+
(lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
349
+
(lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
350
+
(lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
357
351
PCI_SPEED_UNKNOWN)
358
352
359
353
/* PCIe speed to Mb/s reduced by encoding overhead */
···
397
373
return -EINVAL;
398
374
}
399
375
376
+
u8 pcie_get_supported_speeds(struct pci_dev *dev);
400
377
const char *pci_speed_string(enum pci_bus_speed speed);
401
-
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
402
-
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
403
378
void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
404
379
void pcie_report_downtraining(struct pci_dev *dev);
405
-
void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
380
+
381
+
static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
382
+
{
383
+
bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
384
+
}
385
+
void pcie_update_link_speed(struct pci_bus *bus);
406
386
407
387
/* Single Root I/O Virtualization */
408
388
struct pci_sriov {
···
497
469
#define PCI_DEV_ADDED 0
498
470
#define PCI_DPC_RECOVERED 1
499
471
#define PCI_DPC_RECOVERING 2
472
+
#define PCI_DEV_REMOVED 3
500
473
501
-
static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
474
+
static inline void pci_dev_assign_added(struct pci_dev *dev)
502
475
{
503
-
assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
476
+
smp_mb__before_atomic();
477
+
set_bit(PCI_DEV_ADDED, &dev->priv_flags);
478
+
smp_mb__after_atomic();
479
+
}
480
+
481
+
static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev)
482
+
{
483
+
return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags);
504
484
}
505
485
506
486
static inline bool pci_dev_is_added(const struct pci_dev *dev)
507
487
{
508
488
return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
489
+
}
490
+
491
+
static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev)
492
+
{
493
+
return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags);
509
494
}
510
495
511
496
#ifdef CONFIG_PCIEAER
···
638
597
639
598
#endif /* CONFIG_PCI_IOV */
640
599
600
+
#ifdef CONFIG_PCIE_TPH
601
+
void pci_restore_tph_state(struct pci_dev *dev);
602
+
void pci_save_tph_state(struct pci_dev *dev);
603
+
void pci_no_tph(void);
604
+
void pci_tph_init(struct pci_dev *dev);
605
+
#else
606
+
static inline void pci_restore_tph_state(struct pci_dev *dev) { }
607
+
static inline void pci_save_tph_state(struct pci_dev *dev) { }
608
+
static inline void pci_no_tph(void) { }
609
+
static inline void pci_tph_init(struct pci_dev *dev) { }
610
+
#endif
611
+
641
612
#ifdef CONFIG_PCIE_PTM
642
613
void pci_ptm_init(struct pci_dev *dev);
643
614
void pci_save_ptm_state(struct pci_dev *dev);
···
745
692
static inline void pcie_ecrc_get_policy(char *str) { }
746
693
#endif
747
694
695
+
#ifdef CONFIG_PCIEPORTBUS
696
+
void pcie_reset_lbms_count(struct pci_dev *port);
697
+
int pcie_lbms_count(struct pci_dev *port, unsigned long *val);
698
+
#else
699
+
static inline void pcie_reset_lbms_count(struct pci_dev *port) {}
700
+
static inline int pcie_lbms_count(struct pci_dev *port, unsigned long *val)
701
+
{
702
+
return -EOPNOTSUPP;
703
+
}
704
+
#endif
705
+
748
706
struct pci_dev_reset_methods {
749
707
u16 vendor;
750
708
u16 device;
···
810
746
void pci_release_bus_of_node(struct pci_bus *bus);
811
747
812
748
int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
749
+
bool of_pci_supply_present(struct device_node *np);
813
750
814
751
#else
815
752
static inline int
···
858
793
return 0;
859
794
}
860
795
796
+
static inline bool of_pci_supply_present(struct device_node *np)
797
+
{
798
+
return false;
799
+
}
861
800
#endif /* CONFIG_OF */
862
801
863
802
struct of_changeset;
+1
-1
drivers/pci/pcie/Makefile
+1
-1
drivers/pci/pcie/Makefile
+9
-6
drivers/pci/pcie/aer.c
+9
-6
drivers/pci/pcie/aer.c
···
180
180
}
181
181
182
182
/**
183
-
* pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
183
+
* pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based
184
+
* on global policy
184
185
* @dev: the PCI device
185
186
*/
186
187
void pcie_set_ecrc_checking(struct pci_dev *dev)
···
1149
1148
continue;
1150
1149
}
1151
1150
pci_print_aer(pdev, entry.severity, entry.regs);
1151
+
1152
1152
/*
1153
-
* Memory for aer_capability_regs(entry.regs) is being allocated from the
1154
-
* ghes_estatus_pool to protect it from overwriting when multiple sections
1155
-
* are present in the error status. Thus free the same after processing
1156
-
* the data.
1153
+
* Memory for aer_capability_regs(entry.regs) is being
1154
+
* allocated from the ghes_estatus_pool to protect it from
1155
+
* overwriting when multiple sections are present in the
1156
+
* error status. Thus free the same after processing the
1157
+
* data.
1157
1158
*/
1158
1159
ghes_estatus_pool_region_free((unsigned long)entry.regs,
1159
-
sizeof(struct aer_capability_regs));
1160
+
sizeof(struct aer_capability_regs));
1160
1161
1161
1162
if (entry.severity == AER_NONFATAL)
1162
1163
pcie_do_recovery(pdev, pci_channel_io_normal,
+57
-43
drivers/pci/pcie/aspm.c
+57
-43
drivers/pci/pcie/aspm.c
···
805
805
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
806
806
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
807
807
808
+
/* Disable L0s/L1 before updating L1SS config */
809
+
if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
810
+
FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
811
+
pcie_capability_write_word(child, PCI_EXP_LNKCTL,
812
+
child_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
813
+
pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
814
+
parent_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
815
+
}
816
+
808
817
/*
809
818
* Setup L0s state
810
819
*
···
838
829
839
830
aspm_l1ss_init(link);
840
831
832
+
/* Restore L0s/L1 if they were enabled */
833
+
if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
834
+
FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
835
+
pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_lnkctl);
836
+
pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_lnkctl);
837
+
}
838
+
841
839
/* Save default state */
842
840
link->aspm_default = link->aspm_enabled;
843
841
···
861
845
}
862
846
}
863
847
864
-
/* Configure the ASPM L1 substates */
848
+
/* Configure the ASPM L1 substates. Caller must disable L1 first. */
865
849
static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
866
850
{
867
-
u32 val, enable_req;
851
+
u32 val;
868
852
struct pci_dev *child = link->downstream, *parent = link->pdev;
869
-
870
-
enable_req = (link->aspm_enabled ^ state) & state;
871
-
872
-
/*
873
-
* Here are the rules specified in the PCIe spec for enabling L1SS:
874
-
* - When enabling L1.x, enable bit at parent first, then at child
875
-
* - When disabling L1.x, disable bit at child first, then at parent
876
-
* - When enabling ASPM L1.x, need to disable L1
877
-
* (at child followed by parent).
878
-
* - The ASPM/PCIPM L1.2 must be disabled while programming timing
879
-
* parameters
880
-
*
881
-
* To keep it simple, disable all L1SS bits first, and later enable
882
-
* what is needed.
883
-
*/
884
-
885
-
/* Disable all L1 substates */
886
-
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
887
-
PCI_L1SS_CTL1_L1SS_MASK, 0);
888
-
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
889
-
PCI_L1SS_CTL1_L1SS_MASK, 0);
890
-
/*
891
-
* If needed, disable L1, and it gets enabled later
892
-
* in pcie_config_aspm_link().
893
-
*/
894
-
if (enable_req & (PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2)) {
895
-
pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
896
-
PCI_EXP_LNKCTL_ASPM_L1);
897
-
pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
898
-
PCI_EXP_LNKCTL_ASPM_L1);
899
-
}
900
853
901
854
val = 0;
902
855
if (state & PCIE_LINK_STATE_L1_1)
···
876
891
val |= PCI_L1SS_CTL1_PCIPM_L1_1;
877
892
if (state & PCIE_LINK_STATE_L1_2_PCIPM)
878
893
val |= PCI_L1SS_CTL1_PCIPM_L1_2;
894
+
895
+
/*
896
+
* PCIe r6.2, sec 5.5.4, rules for enabling L1 PM Substates:
897
+
* - Clear L1.x enable bits at child first, then at parent
898
+
* - Set L1.x enable bits at parent first, then at child
899
+
* - ASPM/PCIPM L1.2 must be disabled while programming timing
900
+
* parameters
901
+
*/
902
+
903
+
/* Disable all L1 substates */
904
+
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
905
+
PCI_L1SS_CTL1_L1SS_MASK, 0);
906
+
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
907
+
PCI_L1SS_CTL1_L1SS_MASK, 0);
879
908
880
909
/* Enable what we need to enable */
881
910
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
···
936
937
dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
937
938
}
938
939
940
+
/*
941
+
* Per PCIe r6.2, sec 5.5.4, setting either or both of the enable
942
+
* bits for ASPM L1 PM Substates must be done while ASPM L1 is
943
+
* disabled. Disable L1 here and apply new configuration after L1SS
944
+
* configuration has been completed.
945
+
*
946
+
* Per sec 7.5.3.7, when disabling ASPM L1, software must disable
947
+
* it in the Downstream component prior to disabling it in the
948
+
* Upstream component, and ASPM L1 must be enabled in the Upstream
949
+
* component prior to enabling it in the Downstream component.
950
+
*
951
+
* Sec 7.5.3.7 also recommends programming the same ASPM Control
952
+
* value for all functions of a multi-function device.
953
+
*/
954
+
list_for_each_entry(child, &linkbus->devices, bus_list)
955
+
pcie_config_aspm_dev(child, 0);
956
+
pcie_config_aspm_dev(parent, 0);
957
+
939
958
if (link->aspm_capable & PCIE_LINK_STATE_L1SS)
940
959
pcie_config_aspm_l1ss(link, state);
941
960
942
-
/*
943
-
* Spec 2.0 suggests all functions should be configured the
944
-
* same setting for ASPM. Enabling ASPM L1 should be done in
945
-
* upstream component first and then downstream, and vice
946
-
* versa for disabling ASPM L1. Spec doesn't mention L0S.
947
-
*/
948
-
if (state & PCIE_LINK_STATE_L1)
949
-
pcie_config_aspm_dev(parent, upstream);
961
+
pcie_config_aspm_dev(parent, upstream);
950
962
list_for_each_entry(child, &linkbus->devices, bus_list)
951
963
pcie_config_aspm_dev(child, dwstream);
952
-
if (!(state & PCIE_LINK_STATE_L1))
953
-
pcie_config_aspm_dev(parent, upstream);
954
964
955
965
link->aspm_enabled = state;
956
966
···
1450
1442
* touch the LNKCTL register. Also note that this does not enable states
1451
1443
* disabled by pci_disable_link_state(). Return 0 or a negative errno.
1452
1444
*
1445
+
* Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1446
+
* PCIe r6.0, sec 5.5.4.
1447
+
*
1453
1448
* @pdev: PCI device
1454
1449
* @state: Mask of ASPM link states to enable
1455
1450
*/
···
1468
1457
* the BIOS didn't grant ASPM control to the OS, this does nothing because we
1469
1458
* can't touch the LNKCTL register. Also note that this does not enable states
1470
1459
* disabled by pci_disable_link_state(). Return 0 or a negative errno.
1460
+
*
1461
+
* Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1462
+
* PCIe r6.0, sec 5.5.4.
1471
1463
*
1472
1464
* @pdev: PCI device
1473
1465
* @state: Mask of ASPM link states to enable
+366
drivers/pci/pcie/bwctrl.c
+366
drivers/pci/pcie/bwctrl.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* PCIe bandwidth controller
4
+
*
5
+
* Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
6
+
*
7
+
* Copyright (C) 2019 Dell Inc
8
+
* Copyright (C) 2023-2024 Intel Corporation
9
+
*
10
+
* The PCIe bandwidth controller provides a way to alter PCIe Link Speeds
11
+
* and notify the operating system when the Link Width or Speed changes. The
12
+
* notification capability is required for all Root Ports and Downstream
13
+
* Ports supporting Link Width wider than x1 and/or multiple Link Speeds.
14
+
*
15
+
* This service port driver hooks into the Bandwidth Notification interrupt
16
+
* watching for changes or links becoming degraded in operation. It updates
17
+
* the cached Current Link Speed that is exposed to user space through sysfs.
18
+
*/
19
+
20
+
#define dev_fmt(fmt) "bwctrl: " fmt
21
+
22
+
#include <linux/atomic.h>
23
+
#include <linux/bitops.h>
24
+
#include <linux/bits.h>
25
+
#include <linux/cleanup.h>
26
+
#include <linux/errno.h>
27
+
#include <linux/interrupt.h>
28
+
#include <linux/mutex.h>
29
+
#include <linux/pci.h>
30
+
#include <linux/pci-bwctrl.h>
31
+
#include <linux/rwsem.h>
32
+
#include <linux/slab.h>
33
+
#include <linux/types.h>
34
+
35
+
#include "../pci.h"
36
+
#include "portdrv.h"
37
+
38
+
/**
39
+
* struct pcie_bwctrl_data - PCIe bandwidth controller
40
+
* @set_speed_mutex: Serializes link speed changes
41
+
* @lbms_count: Count for LBMS (since last reset)
42
+
* @cdev: Thermal cooling device associated with the port
43
+
*/
44
+
struct pcie_bwctrl_data {
45
+
struct mutex set_speed_mutex;
46
+
atomic_t lbms_count;
47
+
struct thermal_cooling_device *cdev;
48
+
};
49
+
50
+
/*
51
+
* Prevent port removal during LBMS count accessors and Link Speed changes.
52
+
*
53
+
* These have to be differentiated because pcie_bwctrl_change_speed() calls
54
+
* pcie_retrain_link() which uses LBMS count reset accessor on success
55
+
* (using just one rwsem triggers "possible recursive locking detected"
56
+
* warning).
57
+
*/
58
+
static DECLARE_RWSEM(pcie_bwctrl_lbms_rwsem);
59
+
static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
60
+
61
+
static bool pcie_valid_speed(enum pci_bus_speed speed)
62
+
{
63
+
return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
64
+
}
65
+
66
+
static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
67
+
{
68
+
static const u8 speed_conv[] = {
69
+
[PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
70
+
[PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
71
+
[PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
72
+
[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
73
+
[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
74
+
[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
75
+
};
76
+
77
+
if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
78
+
return 0;
79
+
80
+
return speed_conv[speed];
81
+
}
82
+
83
+
static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
84
+
{
85
+
return __fls(supported_speeds);
86
+
}
87
+
88
+
/**
89
+
* pcie_bwctrl_select_speed - Select Target Link Speed
90
+
* @port: PCIe Port
91
+
* @speed_req: Requested PCIe Link Speed
92
+
*
93
+
* Select Target Link Speed by take into account Supported Link Speeds of
94
+
* both the Root Port and the Endpoint.
95
+
*
96
+
* Return: Target Link Speed (1=2.5GT/s, 2=5GT/s, 3=8GT/s, etc.)
97
+
*/
98
+
static u16 pcie_bwctrl_select_speed(struct pci_dev *port, enum pci_bus_speed speed_req)
99
+
{
100
+
struct pci_bus *bus = port->subordinate;
101
+
u8 desired_speeds, supported_speeds;
102
+
struct pci_dev *dev;
103
+
104
+
desired_speeds = GENMASK(pci_bus_speed2lnkctl2(speed_req),
105
+
__fls(PCI_EXP_LNKCAP2_SLS_2_5GB));
106
+
107
+
supported_speeds = port->supported_speeds;
108
+
if (bus) {
109
+
down_read(&pci_bus_sem);
110
+
dev = list_first_entry_or_null(&bus->devices, struct pci_dev, bus_list);
111
+
if (dev)
112
+
supported_speeds &= dev->supported_speeds;
113
+
up_read(&pci_bus_sem);
114
+
}
115
+
if (!supported_speeds)
116
+
return PCI_EXP_LNKCAP2_SLS_2_5GB;
117
+
118
+
return pcie_supported_speeds2target_speed(supported_speeds & desired_speeds);
119
+
}
120
+
121
+
static int pcie_bwctrl_change_speed(struct pci_dev *port, u16 target_speed, bool use_lt)
122
+
{
123
+
int ret;
124
+
125
+
ret = pcie_capability_clear_and_set_word(port, PCI_EXP_LNKCTL2,
126
+
PCI_EXP_LNKCTL2_TLS, target_speed);
127
+
if (ret != PCIBIOS_SUCCESSFUL)
128
+
return pcibios_err_to_errno(ret);
129
+
130
+
ret = pcie_retrain_link(port, use_lt);
131
+
if (ret < 0)
132
+
return ret;
133
+
134
+
/*
135
+
* Ensure link speed updates also with platforms that have problems
136
+
* with notifications.
137
+
*/
138
+
if (port->subordinate)
139
+
pcie_update_link_speed(port->subordinate);
140
+
141
+
return 0;
142
+
}
143
+
144
+
/**
145
+
* pcie_set_target_speed - Set downstream Link Speed for PCIe Port
146
+
* @port: PCIe Port
147
+
* @speed_req: Requested PCIe Link Speed
148
+
* @use_lt: Wait for the LT or DLLLA bit to detect the end of link training
149
+
*
150
+
* Attempt to set PCIe Port Link Speed to @speed_req. @speed_req may be
151
+
* adjusted downwards to the best speed supported by both the Port and PCIe
152
+
* Device underneath it.
153
+
*
154
+
* Return:
155
+
* * 0 - on success
156
+
* * -EINVAL - @speed_req is not a PCIe Link Speed
157
+
* * -ENODEV - @port is not controllable
158
+
* * -ETIMEDOUT - changing Link Speed took too long
159
+
* * -EAGAIN - Link Speed was changed but @speed_req was not achieved
160
+
*/
161
+
int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req,
162
+
bool use_lt)
163
+
{
164
+
struct pci_bus *bus = port->subordinate;
165
+
u16 target_speed;
166
+
int ret;
167
+
168
+
if (WARN_ON_ONCE(!pcie_valid_speed(speed_req)))
169
+
return -EINVAL;
170
+
171
+
if (bus && bus->cur_bus_speed == speed_req)
172
+
return 0;
173
+
174
+
target_speed = pcie_bwctrl_select_speed(port, speed_req);
175
+
176
+
scoped_guard(rwsem_read, &pcie_bwctrl_setspeed_rwsem) {
177
+
struct pcie_bwctrl_data *data = port->link_bwctrl;
178
+
179
+
/*
180
+
* port->link_bwctrl is NULL during initial scan when called
181
+
* e.g. from the Target Speed quirk.
182
+
*/
183
+
if (data)
184
+
mutex_lock(&data->set_speed_mutex);
185
+
186
+
ret = pcie_bwctrl_change_speed(port, target_speed, use_lt);
187
+
188
+
if (data)
189
+
mutex_unlock(&data->set_speed_mutex);
190
+
}
191
+
192
+
/*
193
+
* Despite setting higher speed into the Target Link Speed, empty
194
+
* bus won't train to 5GT+ speeds.
195
+
*/
196
+
if (!ret && bus && bus->cur_bus_speed != speed_req &&
197
+
!list_empty(&bus->devices))
198
+
ret = -EAGAIN;
199
+
200
+
return ret;
201
+
}
202
+
203
+
static void pcie_bwnotif_enable(struct pcie_device *srv)
204
+
{
205
+
struct pcie_bwctrl_data *data = srv->port->link_bwctrl;
206
+
struct pci_dev *port = srv->port;
207
+
u16 link_status;
208
+
int ret;
209
+
210
+
/* Count LBMS seen so far as one */
211
+
ret = pcie_capability_read_word(port, PCI_EXP_LNKSTA, &link_status);
212
+
if (ret == PCIBIOS_SUCCESSFUL && link_status & PCI_EXP_LNKSTA_LBMS)
213
+
atomic_inc(&data->lbms_count);
214
+
215
+
pcie_capability_set_word(port, PCI_EXP_LNKCTL,
216
+
PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
217
+
pcie_capability_write_word(port, PCI_EXP_LNKSTA,
218
+
PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS);
219
+
220
+
/*
221
+
* Update after enabling notifications & clearing status bits ensures
222
+
* link speed is up to date.
223
+
*/
224
+
pcie_update_link_speed(port->subordinate);
225
+
}
226
+
227
+
static void pcie_bwnotif_disable(struct pci_dev *port)
228
+
{
229
+
pcie_capability_clear_word(port, PCI_EXP_LNKCTL,
230
+
PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
231
+
}
232
+
233
+
static irqreturn_t pcie_bwnotif_irq(int irq, void *context)
234
+
{
235
+
struct pcie_device *srv = context;
236
+
struct pcie_bwctrl_data *data = srv->port->link_bwctrl;
237
+
struct pci_dev *port = srv->port;
238
+
u16 link_status, events;
239
+
int ret;
240
+
241
+
ret = pcie_capability_read_word(port, PCI_EXP_LNKSTA, &link_status);
242
+
if (ret != PCIBIOS_SUCCESSFUL)
243
+
return IRQ_NONE;
244
+
245
+
events = link_status & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS);
246
+
if (!events)
247
+
return IRQ_NONE;
248
+
249
+
if (events & PCI_EXP_LNKSTA_LBMS)
250
+
atomic_inc(&data->lbms_count);
251
+
252
+
pcie_capability_write_word(port, PCI_EXP_LNKSTA, events);
253
+
254
+
/*
255
+
* Interrupts will not be triggered from any further Link Speed
256
+
* change until LBMS is cleared by the write. Therefore, re-read the
257
+
* speed (inside pcie_update_link_speed()) after LBMS has been
258
+
* cleared to avoid missing link speed changes.
259
+
*/
260
+
pcie_update_link_speed(port->subordinate);
261
+
262
+
return IRQ_HANDLED;
263
+
}
264
+
265
+
void pcie_reset_lbms_count(struct pci_dev *port)
266
+
{
267
+
struct pcie_bwctrl_data *data;
268
+
269
+
guard(rwsem_read)(&pcie_bwctrl_lbms_rwsem);
270
+
data = port->link_bwctrl;
271
+
if (data)
272
+
atomic_set(&data->lbms_count, 0);
273
+
else
274
+
pcie_capability_write_word(port, PCI_EXP_LNKSTA,
275
+
PCI_EXP_LNKSTA_LBMS);
276
+
}
277
+
278
+
int pcie_lbms_count(struct pci_dev *port, unsigned long *val)
279
+
{
280
+
struct pcie_bwctrl_data *data;
281
+
282
+
guard(rwsem_read)(&pcie_bwctrl_lbms_rwsem);
283
+
data = port->link_bwctrl;
284
+
if (!data)
285
+
return -ENOTTY;
286
+
287
+
*val = atomic_read(&data->lbms_count);
288
+
289
+
return 0;
290
+
}
291
+
292
+
static int pcie_bwnotif_probe(struct pcie_device *srv)
293
+
{
294
+
struct pci_dev *port = srv->port;
295
+
int ret;
296
+
297
+
struct pcie_bwctrl_data *data = devm_kzalloc(&srv->device,
298
+
sizeof(*data), GFP_KERNEL);
299
+
if (!data)
300
+
return -ENOMEM;
301
+
302
+
ret = devm_mutex_init(&srv->device, &data->set_speed_mutex);
303
+
if (ret)
304
+
return ret;
305
+
306
+
ret = devm_request_irq(&srv->device, srv->irq, pcie_bwnotif_irq,
307
+
IRQF_SHARED, "PCIe bwctrl", srv);
308
+
if (ret)
309
+
return ret;
310
+
311
+
scoped_guard(rwsem_write, &pcie_bwctrl_setspeed_rwsem) {
312
+
scoped_guard(rwsem_write, &pcie_bwctrl_lbms_rwsem) {
313
+
port->link_bwctrl = no_free_ptr(data);
314
+
pcie_bwnotif_enable(srv);
315
+
}
316
+
}
317
+
318
+
pci_dbg(port, "enabled with IRQ %d\n", srv->irq);
319
+
320
+
/* Don't fail on errors. Don't leave IS_ERR() "pointer" into ->cdev */
321
+
port->link_bwctrl->cdev = pcie_cooling_device_register(port);
322
+
if (IS_ERR(port->link_bwctrl->cdev))
323
+
port->link_bwctrl->cdev = NULL;
324
+
325
+
return 0;
326
+
}
327
+
328
+
static void pcie_bwnotif_remove(struct pcie_device *srv)
329
+
{
330
+
struct pcie_bwctrl_data *data = srv->port->link_bwctrl;
331
+
332
+
pcie_cooling_device_unregister(data->cdev);
333
+
334
+
pcie_bwnotif_disable(srv->port);
335
+
336
+
scoped_guard(rwsem_write, &pcie_bwctrl_setspeed_rwsem)
337
+
scoped_guard(rwsem_write, &pcie_bwctrl_lbms_rwsem)
338
+
srv->port->link_bwctrl = NULL;
339
+
}
340
+
341
+
static int pcie_bwnotif_suspend(struct pcie_device *srv)
342
+
{
343
+
pcie_bwnotif_disable(srv->port);
344
+
return 0;
345
+
}
346
+
347
+
static int pcie_bwnotif_resume(struct pcie_device *srv)
348
+
{
349
+
pcie_bwnotif_enable(srv);
350
+
return 0;
351
+
}
352
+
353
+
static struct pcie_port_service_driver pcie_bwctrl_driver = {
354
+
.name = "pcie_bwctrl",
355
+
.port_type = PCIE_ANY_PORT,
356
+
.service = PCIE_PORT_SERVICE_BWCTRL,
357
+
.probe = pcie_bwnotif_probe,
358
+
.suspend = pcie_bwnotif_suspend,
359
+
.resume = pcie_bwnotif_resume,
360
+
.remove = pcie_bwnotif_remove,
361
+
};
362
+
363
+
int __init pcie_bwctrl_init(void)
364
+
{
365
+
return pcie_port_service_register(&pcie_bwctrl_driver);
366
+
}
+5
-4
drivers/pci/pcie/portdrv.c
+5
-4
drivers/pci/pcie/portdrv.c
···
68
68
*/
69
69
70
70
if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP |
71
-
PCIE_PORT_SERVICE_BWNOTIF)) {
71
+
PCIE_PORT_SERVICE_BWCTRL)) {
72
72
pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16);
73
73
*pme = FIELD_GET(PCI_EXP_FLAGS_IRQ, reg16);
74
74
nvec = *pme + 1;
···
150
150
151
151
/* PME, hotplug and bandwidth notification share an MSI/MSI-X vector */
152
152
if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP |
153
-
PCIE_PORT_SERVICE_BWNOTIF)) {
153
+
PCIE_PORT_SERVICE_BWCTRL)) {
154
154
pcie_irq = pci_irq_vector(dev, pme);
155
155
irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pcie_irq;
156
156
irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pcie_irq;
157
-
irqs[PCIE_PORT_SERVICE_BWNOTIF_SHIFT] = pcie_irq;
157
+
irqs[PCIE_PORT_SERVICE_BWCTRL_SHIFT] = pcie_irq;
158
158
}
159
159
160
160
if (mask & PCIE_PORT_SERVICE_AER)
···
271
271
272
272
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap);
273
273
if (linkcap & PCI_EXP_LNKCAP_LBNC)
274
-
services |= PCIE_PORT_SERVICE_BWNOTIF;
274
+
services |= PCIE_PORT_SERVICE_BWCTRL;
275
275
}
276
276
277
277
return services;
···
828
828
pcie_aer_init();
829
829
pcie_pme_init();
830
830
pcie_dpc_init();
831
+
pcie_bwctrl_init();
831
832
pcie_hp_init();
832
833
}
833
834
+4
-2
drivers/pci/pcie/portdrv.h
+4
-2
drivers/pci/pcie/portdrv.h
···
20
20
#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
21
21
#define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
22
22
#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
23
-
#define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4 /* Bandwidth notification */
24
-
#define PCIE_PORT_SERVICE_BWNOTIF (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT)
23
+
#define PCIE_PORT_SERVICE_BWCTRL_SHIFT 4 /* Bandwidth Controller (notifications) */
24
+
#define PCIE_PORT_SERVICE_BWCTRL (1 << PCIE_PORT_SERVICE_BWCTRL_SHIFT)
25
25
26
26
#define PCIE_PORT_DEVICE_MAXSERVICES 5
27
27
···
50
50
#else
51
51
static inline int pcie_dpc_init(void) { return 0; }
52
52
#endif
53
+
54
+
int pcie_bwctrl_init(void);
53
55
54
56
/* Port Type */
55
57
#define PCIE_ANY_PORT (~0)
+55
-22
drivers/pci/probe.c
+55
-22
drivers/pci/probe.c
···
543
543
pci_read_bridge_mmio(child->self, child->resource[1], false);
544
544
pci_read_bridge_mmio_pref(child->self, child->resource[2], false);
545
545
546
-
if (dev->transparent) {
547
-
pci_bus_for_each_resource(child->parent, res) {
548
-
if (res && res->flags) {
549
-
pci_bus_add_resource(child, res,
550
-
PCI_SUBTRACTIVE_DECODE);
551
-
pci_info(dev, " bridge window %pR (subtractive decode)\n",
552
-
res);
553
-
}
554
-
}
546
+
if (!dev->transparent)
547
+
return;
548
+
549
+
pci_bus_for_each_resource(child->parent, res) {
550
+
if (!res || !res->flags)
551
+
continue;
552
+
553
+
pci_bus_add_resource(child, res);
554
+
pci_info(dev, " bridge window %pR (subtractive decode)\n", res);
555
555
}
556
556
}
557
557
···
742
742
}
743
743
EXPORT_SYMBOL_GPL(pci_speed_string);
744
744
745
-
void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
745
+
void pcie_update_link_speed(struct pci_bus *bus)
746
746
{
747
-
bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
747
+
struct pci_dev *bridge = bus->self;
748
+
u16 linksta;
749
+
750
+
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
751
+
__pcie_update_link_speed(bus, linksta);
748
752
}
749
753
EXPORT_SYMBOL_GPL(pcie_update_link_speed);
750
754
···
831
827
832
828
if (pci_is_pcie(bridge)) {
833
829
u32 linkcap;
834
-
u16 linksta;
835
830
836
831
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
837
832
bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
838
833
839
-
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
840
-
pcie_update_link_speed(bus, linksta);
834
+
pcie_update_link_speed(bus);
841
835
}
842
836
}
843
837
···
1034
1032
if (res->flags & IORESOURCE_BUS)
1035
1033
pci_bus_insert_busn_res(bus, bus->number, res->end);
1036
1034
else
1037
-
pci_bus_add_resource(bus, res, 0);
1035
+
pci_bus_add_resource(bus, res);
1038
1036
1039
1037
if (offset) {
1040
1038
if (resource_type(res) == IORESOURCE_IO)
···
1635
1633
1636
1634
static void set_pcie_untrusted(struct pci_dev *dev)
1637
1635
{
1638
-
struct pci_dev *parent;
1636
+
struct pci_dev *parent = pci_upstream_bridge(dev);
1639
1637
1638
+
if (!parent)
1639
+
return;
1640
1640
/*
1641
-
* If the upstream bridge is untrusted we treat this device
1641
+
* If the upstream bridge is untrusted we treat this device as
1642
1642
* untrusted as well.
1643
1643
*/
1644
-
parent = pci_upstream_bridge(dev);
1645
-
if (parent && (parent->untrusted || parent->external_facing))
1644
+
if (parent->untrusted) {
1646
1645
dev->untrusted = true;
1646
+
return;
1647
+
}
1648
+
1649
+
if (arch_pci_dev_is_removable(dev)) {
1650
+
pci_dbg(dev, "marking as untrusted\n");
1651
+
dev->untrusted = true;
1652
+
}
1647
1653
}
1648
1654
1649
1655
static void pci_set_removable(struct pci_dev *dev)
1650
1656
{
1651
1657
struct pci_dev *parent = pci_upstream_bridge(dev);
1652
1658
1659
+
if (!parent)
1660
+
return;
1653
1661
/*
1654
-
* We (only) consider everything downstream from an external_facing
1662
+
* We (only) consider everything tunneled below an external_facing
1655
1663
* device to be removable by the user. We're mainly concerned with
1656
1664
* consumer platforms with user accessible thunderbolt ports that are
1657
1665
* vulnerable to DMA attacks, and we expect those ports to be marked by
···
1671
1659
* accessible to user / may not be removed by end user, and thus not
1672
1660
* exposed as "removable" to userspace.
1673
1661
*/
1674
-
if (parent &&
1675
-
(parent->external_facing || dev_is_removable(&parent->dev)))
1662
+
if (dev_is_removable(&parent->dev)) {
1676
1663
dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1664
+
return;
1665
+
}
1666
+
1667
+
if (arch_pci_dev_is_removable(dev)) {
1668
+
pci_dbg(dev, "marking as removable\n");
1669
+
dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1670
+
}
1677
1671
}
1678
1672
1679
1673
/**
···
1964
1946
set_pcie_thunderbolt(dev);
1965
1947
1966
1948
set_pcie_untrusted(dev);
1949
+
1950
+
if (pci_is_pcie(dev))
1951
+
dev->supported_speeds = pcie_get_supported_speeds(dev);
1967
1952
1968
1953
/* "Unknown power state" */
1969
1954
dev->current_state = PCI_UNKNOWN;
···
2516
2495
pci_dpc_init(dev); /* Downstream Port Containment */
2517
2496
pci_rcec_init(dev); /* Root Complex Event Collector */
2518
2497
pci_doe_init(dev); /* Data Object Exchange */
2498
+
pci_tph_init(dev); /* TLP Processing Hints */
2519
2499
2520
2500
pcie_report_downtraining(dev);
2521
2501
pci_init_reset_methods(dev);
···
3130
3108
pci_lock_rescan_remove();
3131
3109
pci_bus_add_devices(bus);
3132
3110
pci_unlock_rescan_remove();
3111
+
3112
+
/*
3113
+
* Ensure pm_runtime_enable() is called for the controller drivers
3114
+
* before calling pci_host_probe(). The PM framework expects that
3115
+
* if the parent device supports runtime PM, it will be enabled
3116
+
* before child runtime PM is enabled.
3117
+
*/
3118
+
pm_runtime_set_active(&bridge->dev);
3119
+
pm_runtime_no_callbacks(&bridge->dev);
3120
+
devm_pm_runtime_enable(&bridge->dev);
3121
+
3133
3122
return 0;
3134
3123
}
3135
3124
EXPORT_SYMBOL_GPL(pci_host_probe);
drivers/pci/pwrctl/Kconfig
drivers/pci/pwrctrl/Kconfig
drivers/pci/pwrctl/Kconfig
drivers/pci/pwrctrl/Kconfig
-6
drivers/pci/pwrctl/Makefile
-6
drivers/pci/pwrctl/Makefile
-157
drivers/pci/pwrctl/core.c
-157
drivers/pci/pwrctl/core.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* Copyright (C) 2024 Linaro Ltd.
4
-
*/
5
-
6
-
#include <linux/device.h>
7
-
#include <linux/export.h>
8
-
#include <linux/kernel.h>
9
-
#include <linux/pci.h>
10
-
#include <linux/pci-pwrctl.h>
11
-
#include <linux/property.h>
12
-
#include <linux/slab.h>
13
-
14
-
static int pci_pwrctl_notify(struct notifier_block *nb, unsigned long action,
15
-
void *data)
16
-
{
17
-
struct pci_pwrctl *pwrctl = container_of(nb, struct pci_pwrctl, nb);
18
-
struct device *dev = data;
19
-
20
-
if (dev_fwnode(dev) != dev_fwnode(pwrctl->dev))
21
-
return NOTIFY_DONE;
22
-
23
-
switch (action) {
24
-
case BUS_NOTIFY_ADD_DEVICE:
25
-
/*
26
-
* We will have two struct device objects bound to two different
27
-
* drivers on different buses but consuming the same DT node. We
28
-
* must not bind the pins twice in this case but only once for
29
-
* the first device to be added.
30
-
*
31
-
* If we got here then the PCI device is the second after the
32
-
* power control platform device. Mark its OF node as reused.
33
-
*/
34
-
dev->of_node_reused = true;
35
-
break;
36
-
case BUS_NOTIFY_BOUND_DRIVER:
37
-
pwrctl->link = device_link_add(dev, pwrctl->dev,
38
-
DL_FLAG_AUTOREMOVE_CONSUMER);
39
-
if (!pwrctl->link)
40
-
dev_err(pwrctl->dev, "Failed to add device link\n");
41
-
break;
42
-
case BUS_NOTIFY_UNBOUND_DRIVER:
43
-
if (pwrctl->link)
44
-
device_link_remove(dev, pwrctl->dev);
45
-
break;
46
-
}
47
-
48
-
return NOTIFY_DONE;
49
-
}
50
-
51
-
static void rescan_work_func(struct work_struct *work)
52
-
{
53
-
struct pci_pwrctl *pwrctl = container_of(work, struct pci_pwrctl, work);
54
-
55
-
pci_lock_rescan_remove();
56
-
pci_rescan_bus(to_pci_dev(pwrctl->dev->parent)->bus);
57
-
pci_unlock_rescan_remove();
58
-
}
59
-
60
-
/**
61
-
* pci_pwrctl_init() - Initialize the PCI power control context struct
62
-
*
63
-
* @pwrctl: PCI power control data
64
-
* @dev: Parent device
65
-
*/
66
-
void pci_pwrctl_init(struct pci_pwrctl *pwrctl, struct device *dev)
67
-
{
68
-
pwrctl->dev = dev;
69
-
INIT_WORK(&pwrctl->work, rescan_work_func);
70
-
}
71
-
EXPORT_SYMBOL_GPL(pci_pwrctl_init);
72
-
73
-
/**
74
-
* pci_pwrctl_device_set_ready() - Notify the pwrctl subsystem that the PCI
75
-
* device is powered-up and ready to be detected.
76
-
*
77
-
* @pwrctl: PCI power control data.
78
-
*
79
-
* Returns:
80
-
* 0 on success, negative error number on error.
81
-
*
82
-
* Note:
83
-
* This function returning 0 doesn't mean the device was detected. It means,
84
-
* that the bus rescan was successfully started. The device will get bound to
85
-
* its PCI driver asynchronously.
86
-
*/
87
-
int pci_pwrctl_device_set_ready(struct pci_pwrctl *pwrctl)
88
-
{
89
-
int ret;
90
-
91
-
if (!pwrctl->dev)
92
-
return -ENODEV;
93
-
94
-
pwrctl->nb.notifier_call = pci_pwrctl_notify;
95
-
ret = bus_register_notifier(&pci_bus_type, &pwrctl->nb);
96
-
if (ret)
97
-
return ret;
98
-
99
-
schedule_work(&pwrctl->work);
100
-
101
-
return 0;
102
-
}
103
-
EXPORT_SYMBOL_GPL(pci_pwrctl_device_set_ready);
104
-
105
-
/**
106
-
* pci_pwrctl_device_unset_ready() - Notify the pwrctl subsystem that the PCI
107
-
* device is about to be powered-down.
108
-
*
109
-
* @pwrctl: PCI power control data.
110
-
*/
111
-
void pci_pwrctl_device_unset_ready(struct pci_pwrctl *pwrctl)
112
-
{
113
-
/*
114
-
* We don't have to delete the link here. Typically, this function
115
-
* is only called when the power control device is being detached. If
116
-
* it is being detached then the child PCI device must have already
117
-
* been unbound too or the device core wouldn't let us unbind.
118
-
*/
119
-
bus_unregister_notifier(&pci_bus_type, &pwrctl->nb);
120
-
}
121
-
EXPORT_SYMBOL_GPL(pci_pwrctl_device_unset_ready);
122
-
123
-
static void devm_pci_pwrctl_device_unset_ready(void *data)
124
-
{
125
-
struct pci_pwrctl *pwrctl = data;
126
-
127
-
pci_pwrctl_device_unset_ready(pwrctl);
128
-
}
129
-
130
-
/**
131
-
* devm_pci_pwrctl_device_set_ready - Managed variant of
132
-
* pci_pwrctl_device_set_ready().
133
-
*
134
-
* @dev: Device managing this pwrctl provider.
135
-
* @pwrctl: PCI power control data.
136
-
*
137
-
* Returns:
138
-
* 0 on success, negative error number on error.
139
-
*/
140
-
int devm_pci_pwrctl_device_set_ready(struct device *dev,
141
-
struct pci_pwrctl *pwrctl)
142
-
{
143
-
int ret;
144
-
145
-
ret = pci_pwrctl_device_set_ready(pwrctl);
146
-
if (ret)
147
-
return ret;
148
-
149
-
return devm_add_action_or_reset(dev,
150
-
devm_pci_pwrctl_device_unset_ready,
151
-
pwrctl);
152
-
}
153
-
EXPORT_SYMBOL_GPL(devm_pci_pwrctl_device_set_ready);
154
-
155
-
MODULE_AUTHOR("Bartosz Golaszewski <bartosz.golaszewski@linaro.org>");
156
-
MODULE_DESCRIPTION("PCI Device Power Control core driver");
157
-
MODULE_LICENSE("GPL");
+25
-25
drivers/pci/pwrctl/pci-pwrctl-pwrseq.c
drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c
+25
-25
drivers/pci/pwrctl/pci-pwrctl-pwrseq.c
drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c
···
6
6
#include <linux/device.h>
7
7
#include <linux/mod_devicetable.h>
8
8
#include <linux/module.h>
9
-
#include <linux/pci-pwrctl.h>
9
+
#include <linux/pci-pwrctrl.h>
10
10
#include <linux/platform_device.h>
11
11
#include <linux/property.h>
12
12
#include <linux/pwrseq/consumer.h>
13
13
#include <linux/slab.h>
14
14
#include <linux/types.h>
15
15
16
-
struct pci_pwrctl_pwrseq_data {
17
-
struct pci_pwrctl ctx;
16
+
struct pci_pwrctrl_pwrseq_data {
17
+
struct pci_pwrctrl ctx;
18
18
struct pwrseq_desc *pwrseq;
19
19
};
20
20
21
-
struct pci_pwrctl_pwrseq_pdata {
21
+
struct pci_pwrctrl_pwrseq_pdata {
22
22
const char *target;
23
23
/*
24
24
* Called before doing anything else to perform device-specific
···
27
27
int (*validate_device)(struct device *dev);
28
28
};
29
29
30
-
static int pci_pwrctl_pwrseq_qcm_wcn_validate_device(struct device *dev)
30
+
static int pci_pwrctrl_pwrseq_qcm_wcn_validate_device(struct device *dev)
31
31
{
32
32
/*
33
33
* Old device trees for some platforms already define wifi nodes for
···
47
47
return 0;
48
48
}
49
49
50
-
static const struct pci_pwrctl_pwrseq_pdata pci_pwrctl_pwrseq_qcom_wcn_pdata = {
50
+
static const struct pci_pwrctrl_pwrseq_pdata pci_pwrctrl_pwrseq_qcom_wcn_pdata = {
51
51
.target = "wlan",
52
-
.validate_device = pci_pwrctl_pwrseq_qcm_wcn_validate_device,
52
+
.validate_device = pci_pwrctrl_pwrseq_qcm_wcn_validate_device,
53
53
};
54
54
55
-
static void devm_pci_pwrctl_pwrseq_power_off(void *data)
55
+
static void devm_pci_pwrctrl_pwrseq_power_off(void *data)
56
56
{
57
57
struct pwrseq_desc *pwrseq = data;
58
58
59
59
pwrseq_power_off(pwrseq);
60
60
}
61
61
62
-
static int pci_pwrctl_pwrseq_probe(struct platform_device *pdev)
62
+
static int pci_pwrctrl_pwrseq_probe(struct platform_device *pdev)
63
63
{
64
-
const struct pci_pwrctl_pwrseq_pdata *pdata;
65
-
struct pci_pwrctl_pwrseq_data *data;
64
+
const struct pci_pwrctrl_pwrseq_pdata *pdata;
65
+
struct pci_pwrctrl_pwrseq_data *data;
66
66
struct device *dev = &pdev->dev;
67
67
int ret;
68
68
···
90
90
return dev_err_probe(dev, ret,
91
91
"Failed to power-on the device\n");
92
92
93
-
ret = devm_add_action_or_reset(dev, devm_pci_pwrctl_pwrseq_power_off,
93
+
ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_pwrseq_power_off,
94
94
data->pwrseq);
95
95
if (ret)
96
96
return ret;
97
97
98
-
pci_pwrctl_init(&data->ctx, dev);
98
+
pci_pwrctrl_init(&data->ctx, dev);
99
99
100
-
ret = devm_pci_pwrctl_device_set_ready(dev, &data->ctx);
100
+
ret = devm_pci_pwrctrl_device_set_ready(dev, &data->ctx);
101
101
if (ret)
102
102
return dev_err_probe(dev, ret,
103
-
"Failed to register the pwrctl wrapper\n");
103
+
"Failed to register the pwrctrl wrapper\n");
104
104
105
105
return 0;
106
106
}
107
107
108
-
static const struct of_device_id pci_pwrctl_pwrseq_of_match[] = {
108
+
static const struct of_device_id pci_pwrctrl_pwrseq_of_match[] = {
109
109
{
110
110
/* ATH11K in QCA6390 package. */
111
111
.compatible = "pci17cb,1101",
112
-
.data = &pci_pwrctl_pwrseq_qcom_wcn_pdata,
112
+
.data = &pci_pwrctrl_pwrseq_qcom_wcn_pdata,
113
113
},
114
114
{
115
115
/* ATH11K in WCN6855 package. */
116
116
.compatible = "pci17cb,1103",
117
-
.data = &pci_pwrctl_pwrseq_qcom_wcn_pdata,
117
+
.data = &pci_pwrctrl_pwrseq_qcom_wcn_pdata,
118
118
},
119
119
{
120
120
/* ATH12K in WCN7850 package. */
121
121
.compatible = "pci17cb,1107",
122
-
.data = &pci_pwrctl_pwrseq_qcom_wcn_pdata,
122
+
.data = &pci_pwrctrl_pwrseq_qcom_wcn_pdata,
123
123
},
124
124
{ }
125
125
};
126
-
MODULE_DEVICE_TABLE(of, pci_pwrctl_pwrseq_of_match);
126
+
MODULE_DEVICE_TABLE(of, pci_pwrctrl_pwrseq_of_match);
127
127
128
-
static struct platform_driver pci_pwrctl_pwrseq_driver = {
128
+
static struct platform_driver pci_pwrctrl_pwrseq_driver = {
129
129
.driver = {
130
-
.name = "pci-pwrctl-pwrseq",
131
-
.of_match_table = pci_pwrctl_pwrseq_of_match,
130
+
.name = "pci-pwrctrl-pwrseq",
131
+
.of_match_table = pci_pwrctrl_pwrseq_of_match,
132
132
},
133
-
.probe = pci_pwrctl_pwrseq_probe,
133
+
.probe = pci_pwrctrl_pwrseq_probe,
134
134
};
135
-
module_platform_driver(pci_pwrctl_pwrseq_driver);
135
+
module_platform_driver(pci_pwrctrl_pwrseq_driver);
136
136
137
137
MODULE_AUTHOR("Bartosz Golaszewski <bartosz.golaszewski@linaro.org>");
138
138
MODULE_DESCRIPTION("Generic PCI Power Control module for power sequenced devices");
+6
drivers/pci/pwrctrl/Makefile
+6
drivers/pci/pwrctrl/Makefile
+148
drivers/pci/pwrctrl/core.c
+148
drivers/pci/pwrctrl/core.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2024 Linaro Ltd.
4
+
*/
5
+
6
+
#include <linux/device.h>
7
+
#include <linux/export.h>
8
+
#include <linux/kernel.h>
9
+
#include <linux/pci.h>
10
+
#include <linux/pci-pwrctrl.h>
11
+
#include <linux/property.h>
12
+
#include <linux/slab.h>
13
+
14
+
static int pci_pwrctrl_notify(struct notifier_block *nb, unsigned long action,
15
+
void *data)
16
+
{
17
+
struct pci_pwrctrl *pwrctrl = container_of(nb, struct pci_pwrctrl, nb);
18
+
struct device *dev = data;
19
+
20
+
if (dev_fwnode(dev) != dev_fwnode(pwrctrl->dev))
21
+
return NOTIFY_DONE;
22
+
23
+
switch (action) {
24
+
case BUS_NOTIFY_ADD_DEVICE:
25
+
/*
26
+
* We will have two struct device objects bound to two different
27
+
* drivers on different buses but consuming the same DT node. We
28
+
* must not bind the pins twice in this case but only once for
29
+
* the first device to be added.
30
+
*
31
+
* If we got here then the PCI device is the second after the
32
+
* power control platform device. Mark its OF node as reused.
33
+
*/
34
+
dev->of_node_reused = true;
35
+
break;
36
+
}
37
+
38
+
return NOTIFY_DONE;
39
+
}
40
+
41
+
static void rescan_work_func(struct work_struct *work)
42
+
{
43
+
struct pci_pwrctrl *pwrctrl = container_of(work,
44
+
struct pci_pwrctrl, work);
45
+
46
+
pci_lock_rescan_remove();
47
+
pci_rescan_bus(to_pci_dev(pwrctrl->dev->parent)->bus);
48
+
pci_unlock_rescan_remove();
49
+
}
50
+
51
+
/**
52
+
* pci_pwrctrl_init() - Initialize the PCI power control context struct
53
+
*
54
+
* @pwrctrl: PCI power control data
55
+
* @dev: Parent device
56
+
*/
57
+
void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct device *dev)
58
+
{
59
+
pwrctrl->dev = dev;
60
+
INIT_WORK(&pwrctrl->work, rescan_work_func);
61
+
}
62
+
EXPORT_SYMBOL_GPL(pci_pwrctrl_init);
63
+
64
+
/**
65
+
* pci_pwrctrl_device_set_ready() - Notify the pwrctrl subsystem that the PCI
66
+
* device is powered-up and ready to be detected.
67
+
*
68
+
* @pwrctrl: PCI power control data.
69
+
*
70
+
* Returns:
71
+
* 0 on success, negative error number on error.
72
+
*
73
+
* Note:
74
+
* This function returning 0 doesn't mean the device was detected. It means,
75
+
* that the bus rescan was successfully started. The device will get bound to
76
+
* its PCI driver asynchronously.
77
+
*/
78
+
int pci_pwrctrl_device_set_ready(struct pci_pwrctrl *pwrctrl)
79
+
{
80
+
int ret;
81
+
82
+
if (!pwrctrl->dev)
83
+
return -ENODEV;
84
+
85
+
pwrctrl->nb.notifier_call = pci_pwrctrl_notify;
86
+
ret = bus_register_notifier(&pci_bus_type, &pwrctrl->nb);
87
+
if (ret)
88
+
return ret;
89
+
90
+
schedule_work(&pwrctrl->work);
91
+
92
+
return 0;
93
+
}
94
+
EXPORT_SYMBOL_GPL(pci_pwrctrl_device_set_ready);
95
+
96
+
/**
97
+
* pci_pwrctrl_device_unset_ready() - Notify the pwrctrl subsystem that the PCI
98
+
* device is about to be powered-down.
99
+
*
100
+
* @pwrctrl: PCI power control data.
101
+
*/
102
+
void pci_pwrctrl_device_unset_ready(struct pci_pwrctrl *pwrctrl)
103
+
{
104
+
/*
105
+
* We don't have to delete the link here. Typically, this function
106
+
* is only called when the power control device is being detached. If
107
+
* it is being detached then the child PCI device must have already
108
+
* been unbound too or the device core wouldn't let us unbind.
109
+
*/
110
+
bus_unregister_notifier(&pci_bus_type, &pwrctrl->nb);
111
+
}
112
+
EXPORT_SYMBOL_GPL(pci_pwrctrl_device_unset_ready);
113
+
114
+
static void devm_pci_pwrctrl_device_unset_ready(void *data)
115
+
{
116
+
struct pci_pwrctrl *pwrctrl = data;
117
+
118
+
pci_pwrctrl_device_unset_ready(pwrctrl);
119
+
}
120
+
121
+
/**
122
+
* devm_pci_pwrctrl_device_set_ready - Managed variant of
123
+
* pci_pwrctrl_device_set_ready().
124
+
*
125
+
* @dev: Device managing this pwrctrl provider.
126
+
* @pwrctrl: PCI power control data.
127
+
*
128
+
* Returns:
129
+
* 0 on success, negative error number on error.
130
+
*/
131
+
int devm_pci_pwrctrl_device_set_ready(struct device *dev,
132
+
struct pci_pwrctrl *pwrctrl)
133
+
{
134
+
int ret;
135
+
136
+
ret = pci_pwrctrl_device_set_ready(pwrctrl);
137
+
if (ret)
138
+
return ret;
139
+
140
+
return devm_add_action_or_reset(dev,
141
+
devm_pci_pwrctrl_device_unset_ready,
142
+
pwrctrl);
143
+
}
144
+
EXPORT_SYMBOL_GPL(devm_pci_pwrctrl_device_set_ready);
145
+
146
+
MODULE_AUTHOR("Bartosz Golaszewski <bartosz.golaszewski@linaro.org>");
147
+
MODULE_DESCRIPTION("PCI Device Power Control core driver");
148
+
MODULE_LICENSE("GPL");
+36
-34
drivers/pci/quirks.c
+36
-34
drivers/pci/quirks.c
···
12
12
* file, where their drivers can use them.
13
13
*/
14
14
15
+
#include <linux/align.h>
15
16
#include <linux/bitfield.h>
16
17
#include <linux/types.h>
17
18
#include <linux/kernel.h>
···
30
29
#include <linux/nvme.h>
31
30
#include <linux/platform_data/x86/apple.h>
32
31
#include <linux/pm_runtime.h>
32
+
#include <linux/sizes.h>
33
33
#include <linux/suspend.h>
34
34
#include <linux/switchtec.h>
35
35
#include "pci.h"
36
+
37
+
static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta)
38
+
{
39
+
unsigned long count;
40
+
int ret;
41
+
42
+
ret = pcie_lbms_count(dev, &count);
43
+
if (ret < 0)
44
+
return lnksta & PCI_EXP_LNKSTA_LBMS;
45
+
46
+
return count > 0;
47
+
}
36
48
37
49
/*
38
50
* Retrain the link of a downstream PCIe port by hand if necessary.
···
110
96
111
97
pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);
112
98
pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
113
-
if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) ==
114
-
PCI_EXP_LNKSTA_LBMS) {
99
+
if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) {
115
100
u16 oldlnkctl2 = lnkctl2;
116
101
117
102
pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
118
103
119
-
lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
120
-
lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT;
121
-
pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2);
122
-
123
-
ret = pcie_retrain_link(dev, false);
104
+
ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false);
124
105
if (ret) {
125
106
pci_info(dev, "retraining failed\n");
126
-
pcie_capability_write_word(dev, PCI_EXP_LNKCTL2,
127
-
oldlnkctl2);
128
-
pcie_retrain_link(dev, true);
107
+
pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2),
108
+
true);
129
109
return ret;
130
110
}
131
111
···
133
125
134
126
pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n");
135
127
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
136
-
lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
137
-
lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS;
138
-
pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2);
139
-
140
-
ret = pcie_retrain_link(dev, false);
128
+
ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false);
141
129
if (ret) {
142
130
pci_info(dev, "retraining failed\n");
143
131
return ret;
···
590
586
const char *r_name = pci_resource_name(dev, i);
591
587
592
588
if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
593
-
r->end = PAGE_SIZE - 1;
594
-
r->start = 0;
589
+
resource_set_range(r, 0, PAGE_SIZE);
595
590
r->flags |= IORESOURCE_UNSET;
596
591
pci_info(dev, "%s %pR: expanded to page size\n",
597
592
r_name, r);
···
607
604
{
608
605
struct resource *r = &dev->resource[0];
609
606
610
-
if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
607
+
if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) {
611
608
r->flags |= IORESOURCE_UNSET;
612
-
r->start = 0;
613
-
r->end = 0x3ffffff;
609
+
resource_set_range(r, 0, SZ_64M);
614
610
}
615
611
}
616
612
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
···
1344
1342
struct resource *r = &dev->resource[1];
1345
1343
1346
1344
r->flags |= IORESOURCE_UNSET;
1347
-
r->start = 0;
1348
-
r->end = 0xffffff;
1345
+
resource_set_range(r, 0, SZ_16M);
1349
1346
}
1350
1347
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1351
1348
···
2341
2340
2342
2341
if (r->start & 0x8) {
2343
2342
r->flags |= IORESOURCE_UNSET;
2344
-
r->start = 0;
2345
-
r->end = 0xf;
2343
+
resource_set_range(r, 0, SZ_16);
2346
2344
}
2347
2345
}
2348
2346
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
···
2369
2369
pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2370
2370
bar);
2371
2371
r->flags |= IORESOURCE_UNSET;
2372
-
r->start = 0;
2373
-
r->end = 0xff;
2372
+
resource_set_range(r, 0, SZ_256);
2374
2373
}
2375
2374
}
2376
2375
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
···
3521
3522
if (rc)
3522
3523
return;
3523
3524
3524
-
dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3525
+
resource_set_size(&dev->resource[2], (resource_size_t)1 << val);
3525
3526
3526
3527
rc = pci_read_config_byte(dev, 0x00D1, &val);
3527
3528
if (rc)
3528
3529
return;
3529
3530
3530
-
dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3531
+
resource_set_size(&dev->resource[4], (resource_size_t)1 << val);
3531
3532
}
3532
3533
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3533
3534
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
···
4995
4996
}
4996
4997
4997
4998
/*
4998
-
* Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4999
-
* devices, peer-to-peer transactions are not be used between the functions.
5000
-
* So add an ACS quirk for below devices to isolate functions.
4999
+
* Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on
5000
+
* multi-function devices, the hardware isolates the functions by
5001
+
* directing all peer-to-peer traffic upstream as though PCI_ACS_RR and
5002
+
* PCI_ACS_CR were set.
5001
5003
* SFxxx 1G NICs(em).
5002
5004
* RP1000/RP2000 10G NICs(sp).
5005
+
* FF5xxx 40G/25G/10G NICs(aml).
5003
5006
*/
5004
5007
static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
5005
5008
{
5006
5009
switch (dev->device) {
5007
-
case 0x0100 ... 0x010F:
5008
-
case 0x1001:
5009
-
case 0x2001:
5010
+
case 0x0100 ... 0x010F: /* EM */
5011
+
case 0x1001: case 0x2001: /* SP */
5012
+
case 0x5010: case 0x5025: case 0x5040: /* AML */
5013
+
case 0x5110: case 0x5125: case 0x5140: /* AML */
5010
5014
return pci_acs_ctrl_enabled(acs_flags,
5011
5015
PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
5012
5016
}
+15
-17
drivers/pci/remove.c
+15
-17
drivers/pci/remove.c
···
17
17
}
18
18
}
19
19
20
-
static int pci_pwrctl_unregister(struct device *dev, void *data)
20
+
static void pci_pwrctrl_unregister(struct device *dev)
21
21
{
22
-
struct device_node *pci_node = data, *plat_node = dev_of_node(dev);
22
+
struct platform_device *pdev;
23
23
24
-
if (dev_is_platform(dev) && plat_node && plat_node == pci_node) {
25
-
of_device_unregister(to_platform_device(dev));
26
-
of_node_clear_flag(plat_node, OF_POPULATED);
27
-
}
24
+
pdev = of_find_device_by_node(dev_of_node(dev));
25
+
if (!pdev)
26
+
return;
28
27
29
-
return 0;
28
+
of_device_unregister(pdev);
29
+
of_node_clear_flag(dev_of_node(dev), OF_POPULATED);
30
30
}
31
31
32
32
static void pci_stop_dev(struct pci_dev *dev)
33
33
{
34
34
pci_pme_active(dev, false);
35
35
36
-
if (pci_dev_is_added(dev)) {
37
-
device_for_each_child(dev->dev.parent, dev_of_node(&dev->dev),
38
-
pci_pwrctl_unregister);
39
-
device_release_driver(&dev->dev);
40
-
pci_proc_detach_device(dev);
41
-
pci_remove_sysfs_dev_files(dev);
42
-
of_pci_remove_node(dev);
36
+
if (!pci_dev_test_and_clear_added(dev))
37
+
return;
43
38
44
-
pci_dev_assign_added(dev, false);
45
-
}
39
+
pci_pwrctrl_unregister(&dev->dev);
40
+
device_release_driver(&dev->dev);
41
+
pci_proc_detach_device(dev);
42
+
pci_remove_sysfs_dev_files(dev);
43
+
of_pci_remove_node(dev);
46
44
}
47
45
48
46
static void pci_destroy_dev(struct pci_dev *dev)
49
47
{
50
-
if (!dev->dev.kobj.parent)
48
+
if (pci_dev_test_and_set_removed(dev))
51
49
return;
52
50
53
51
pci_npem_remove(dev);
+19
-22
drivers/pci/setup-bus.c
+19
-22
drivers/pci/setup-bus.c
···
134
134
int i;
135
135
136
136
pci_dev_for_each_resource(dev, r, i) {
137
+
const char *r_name = pci_resource_name(dev, i);
137
138
struct pci_dev_resource *dev_res, *tmp;
138
139
resource_size_t r_align;
139
140
struct list_head *n;
···
147
146
148
147
r_align = pci_resource_alignment(dev, r);
149
148
if (!r_align) {
150
-
pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
151
-
i, r);
149
+
pci_warn(dev, "%s %pR: alignment must not be zero\n",
150
+
r_name, r);
152
151
continue;
153
152
}
154
153
···
247
246
add_size = add_res->add_size;
248
247
align = add_res->min_align;
249
248
if (!resource_size(res)) {
250
-
res->start = align;
251
-
res->end = res->start + add_size - 1;
249
+
resource_set_range(res, align, add_size);
252
250
if (pci_assign_resource(add_res->dev, idx))
253
251
reset_resource(res);
254
252
} else {
···
938
938
return;
939
939
}
940
940
941
-
b_res->start = min_align;
942
-
b_res->end = b_res->start + size0 - 1;
941
+
resource_set_range(b_res, min_align, size0);
943
942
b_res->flags |= IORESOURCE_STARTALIGN;
944
943
if (bus->self && size1 > size0 && realloc_head) {
945
944
add_to_list(realloc_head, bus->self, b_res, size1-size0,
···
1201
1202
* Reserve some resources for CardBus. We reserve a fixed amount
1202
1203
* of bus space for CardBus bridges.
1203
1204
*/
1204
-
b_res->start = pci_cardbus_io_size;
1205
-
b_res->end = b_res->start + pci_cardbus_io_size - 1;
1205
+
resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size);
1206
1206
b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1207
1207
if (realloc_head) {
1208
1208
b_res->end -= pci_cardbus_io_size;
···
1213
1215
b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
1214
1216
if (b_res->parent)
1215
1217
goto handle_b_res_2;
1216
-
b_res->start = pci_cardbus_io_size;
1217
-
b_res->end = b_res->start + pci_cardbus_io_size - 1;
1218
+
resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size);
1218
1219
b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1219
1220
if (realloc_head) {
1220
1221
b_res->end -= pci_cardbus_io_size;
···
1246
1249
* Otherwise, allocate one region of twice the size.
1247
1250
*/
1248
1251
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1249
-
b_res->start = pci_cardbus_mem_size;
1250
-
b_res->end = b_res->start + pci_cardbus_mem_size - 1;
1252
+
resource_set_range(b_res, pci_cardbus_mem_size,
1253
+
pci_cardbus_mem_size);
1251
1254
b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1252
1255
IORESOURCE_STARTALIGN;
1253
1256
if (realloc_head) {
···
1264
1267
b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
1265
1268
if (b_res->parent)
1266
1269
goto handle_done;
1267
-
b_res->start = pci_cardbus_mem_size;
1268
-
b_res->end = b_res->start + b_res_3_size - 1;
1270
+
resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size);
1269
1271
b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1270
1272
if (realloc_head) {
1271
1273
b_res->end -= b_res_3_size;
···
1843
1847
return;
1844
1848
}
1845
1849
1846
-
res->end = res->start + new_size - 1;
1850
+
resource_set_size(res, new_size);
1847
1851
1848
1852
/* If the resource is part of the add_list, remove it now */
1849
1853
if (add_list)
···
1894
1898
}
1895
1899
}
1896
1900
}
1901
+
1902
+
#define ALIGN_DOWN_IF_NONZERO(addr, align) \
1903
+
((align) ? ALIGN_DOWN((addr), (align)) : (addr))
1897
1904
1898
1905
/*
1899
1906
* io, mmio and mmio_pref contain the total amount of bridge window space
···
2009
2010
* what is available).
2010
2011
*/
2011
2012
align = pci_resource_alignment(dev, res);
2012
-
io.end = align ? io.start + ALIGN_DOWN(io_per_b, align) - 1
2013
-
: io.start + io_per_b - 1;
2013
+
resource_set_size(&io, ALIGN_DOWN_IF_NONZERO(io_per_b, align));
2014
2014
2015
2015
/*
2016
2016
* The x_per_b holds the extra resource space that can be
···
2021
2023
2022
2024
res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
2023
2025
align = pci_resource_alignment(dev, res);
2024
-
mmio.end = align ? mmio.start + ALIGN_DOWN(mmio_per_b, align) - 1
2025
-
: mmio.start + mmio_per_b - 1;
2026
+
resource_set_size(&mmio,
2027
+
ALIGN_DOWN_IF_NONZERO(mmio_per_b,align));
2026
2028
mmio.start -= resource_size(res);
2027
2029
2028
2030
res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2029
2031
align = pci_resource_alignment(dev, res);
2030
-
mmio_pref.end = align ? mmio_pref.start +
2031
-
ALIGN_DOWN(mmio_pref_per_b, align) - 1
2032
-
: mmio_pref.start + mmio_pref_per_b - 1;
2032
+
resource_set_size(&mmio_pref,
2033
+
ALIGN_DOWN_IF_NONZERO(mmio_pref_per_b, align));
2033
2034
mmio_pref.start -= resource_size(res);
2034
2035
2035
2036
pci_bus_distribute_available_resources(b, add_list, io, mmio,
+3
-4
drivers/pci/setup-res.c
+3
-4
drivers/pci/setup-res.c
···
211
211
212
212
start = res->start;
213
213
end = res->end;
214
-
res->start = fw_addr;
215
-
res->end = res->start + size - 1;
214
+
resource_set_range(res, fw_addr, size);
216
215
res->flags &= ~IORESOURCE_UNSET;
217
216
218
217
root = pci_find_parent_resource(dev, res);
···
462
463
if (ret)
463
464
return ret;
464
465
465
-
res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
466
+
resource_set_size(res, pci_rebar_size_to_bytes(size));
466
467
467
468
/* Check if the new config works by trying to assign everything. */
468
469
if (dev->bus->self) {
···
474
475
475
476
error_resize:
476
477
pci_rebar_set_size(dev, resno, old);
477
-
res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
478
+
resource_set_size(res, pci_rebar_size_to_bytes(old));
478
479
return ret;
479
480
}
480
481
EXPORT_SYMBOL(pci_resize_resource);
+14
-10
drivers/pci/slot.c
+14
-10
drivers/pci/slot.c
···
79
79
up_read(&pci_bus_sem);
80
80
81
81
list_del(&slot->list);
82
+
pci_bus_put(slot->bus);
82
83
83
84
kfree(slot);
84
85
}
···
245
244
slot = get_slot(parent, slot_nr);
246
245
if (slot) {
247
246
if (hotplug) {
248
-
if ((err = slot->hotplug ? -EBUSY : 0)
249
-
|| (err = rename_slot(slot, name))) {
250
-
kobject_put(&slot->kobj);
251
-
slot = NULL;
252
-
goto err;
247
+
if (slot->hotplug) {
248
+
err = -EBUSY;
249
+
goto put_slot;
253
250
}
251
+
err = rename_slot(slot, name);
252
+
if (err)
253
+
goto put_slot;
254
254
}
255
255
goto out;
256
256
}
···
263
261
goto err;
264
262
}
265
263
266
-
slot->bus = parent;
264
+
slot->bus = pci_bus_get(parent);
267
265
slot->number = slot_nr;
268
266
269
267
slot->kobj.kset = pci_slots_kset;
···
271
269
slot_name = make_slot_name(name);
272
270
if (!slot_name) {
273
271
err = -ENOMEM;
272
+
pci_bus_put(slot->bus);
274
273
kfree(slot);
275
274
goto err;
276
275
}
···
281
278
282
279
err = kobject_init_and_add(&slot->kobj, &pci_slot_ktype, NULL,
283
280
"%s", slot_name);
284
-
if (err) {
285
-
kobject_put(&slot->kobj);
286
-
goto err;
287
-
}
281
+
if (err)
282
+
goto put_slot;
288
283
289
284
down_read(&pci_bus_sem);
290
285
list_for_each_entry(dev, &parent->devices, bus_list)
···
297
296
kfree(slot_name);
298
297
mutex_unlock(&pci_slot_mutex);
299
298
return slot;
299
+
300
+
put_slot:
301
+
kobject_put(&slot->kobj);
300
302
err:
301
303
slot = ERR_PTR(err);
302
304
goto out;
+547
drivers/pci/tph.c
+547
drivers/pci/tph.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* TPH (TLP Processing Hints) support
4
+
*
5
+
* Copyright (C) 2024 Advanced Micro Devices, Inc.
6
+
* Eric Van Tassell <Eric.VanTassell@amd.com>
7
+
* Wei Huang <wei.huang2@amd.com>
8
+
*/
9
+
#include <linux/pci.h>
10
+
#include <linux/pci-acpi.h>
11
+
#include <linux/msi.h>
12
+
#include <linux/bitfield.h>
13
+
#include <linux/pci-tph.h>
14
+
15
+
#include "pci.h"
16
+
17
+
/* System-wide TPH disabled */
18
+
static bool pci_tph_disabled;
19
+
20
+
#ifdef CONFIG_ACPI
21
+
/*
22
+
* The st_info struct defines the Steering Tag (ST) info returned by the
23
+
* firmware PCI ACPI _DSM method (rev=0x7, func=0xF, "_DSM to Query Cache
24
+
* Locality TPH Features"), as specified in the approved ECN for PCI Firmware
25
+
* Spec and available at https://members.pcisig.com/wg/PCI-SIG/document/15470.
26
+
*
27
+
* @vm_st_valid: 8-bit ST for volatile memory is valid
28
+
* @vm_xst_valid: 16-bit extended ST for volatile memory is valid
29
+
* @vm_ph_ignore: 1 => PH was and will be ignored, 0 => PH should be supplied
30
+
* @vm_st: 8-bit ST for volatile mem
31
+
* @vm_xst: 16-bit extended ST for volatile mem
32
+
* @pm_st_valid: 8-bit ST for persistent memory is valid
33
+
* @pm_xst_valid: 16-bit extended ST for persistent memory is valid
34
+
* @pm_ph_ignore: 1 => PH was and will be ignored, 0 => PH should be supplied
35
+
* @pm_st: 8-bit ST for persistent mem
36
+
* @pm_xst: 16-bit extended ST for persistent mem
37
+
*/
38
+
union st_info {
39
+
struct {
40
+
u64 vm_st_valid : 1;
41
+
u64 vm_xst_valid : 1;
42
+
u64 vm_ph_ignore : 1;
43
+
u64 rsvd1 : 5;
44
+
u64 vm_st : 8;
45
+
u64 vm_xst : 16;
46
+
u64 pm_st_valid : 1;
47
+
u64 pm_xst_valid : 1;
48
+
u64 pm_ph_ignore : 1;
49
+
u64 rsvd2 : 5;
50
+
u64 pm_st : 8;
51
+
u64 pm_xst : 16;
52
+
};
53
+
u64 value;
54
+
};
55
+
56
+
static u16 tph_extract_tag(enum tph_mem_type mem_type, u8 req_type,
57
+
union st_info *info)
58
+
{
59
+
switch (req_type) {
60
+
case PCI_TPH_REQ_TPH_ONLY: /* 8-bit tag */
61
+
switch (mem_type) {
62
+
case TPH_MEM_TYPE_VM:
63
+
if (info->vm_st_valid)
64
+
return info->vm_st;
65
+
break;
66
+
case TPH_MEM_TYPE_PM:
67
+
if (info->pm_st_valid)
68
+
return info->pm_st;
69
+
break;
70
+
}
71
+
break;
72
+
case PCI_TPH_REQ_EXT_TPH: /* 16-bit tag */
73
+
switch (mem_type) {
74
+
case TPH_MEM_TYPE_VM:
75
+
if (info->vm_xst_valid)
76
+
return info->vm_xst;
77
+
break;
78
+
case TPH_MEM_TYPE_PM:
79
+
if (info->pm_xst_valid)
80
+
return info->pm_xst;
81
+
break;
82
+
}
83
+
break;
84
+
default:
85
+
return 0;
86
+
}
87
+
88
+
return 0;
89
+
}
90
+
91
+
#define TPH_ST_DSM_FUNC_INDEX 0xF
92
+
static acpi_status tph_invoke_dsm(acpi_handle handle, u32 cpu_uid,
93
+
union st_info *st_out)
94
+
{
95
+
union acpi_object arg3[3], in_obj, *out_obj;
96
+
97
+
if (!acpi_check_dsm(handle, &pci_acpi_dsm_guid, 7,
98
+
BIT(TPH_ST_DSM_FUNC_INDEX)))
99
+
return AE_ERROR;
100
+
101
+
/* DWORD: feature ID (0 for processor cache ST query) */
102
+
arg3[0].integer.type = ACPI_TYPE_INTEGER;
103
+
arg3[0].integer.value = 0;
104
+
105
+
/* DWORD: target UID */
106
+
arg3[1].integer.type = ACPI_TYPE_INTEGER;
107
+
arg3[1].integer.value = cpu_uid;
108
+
109
+
/* QWORD: properties, all 0's */
110
+
arg3[2].integer.type = ACPI_TYPE_INTEGER;
111
+
arg3[2].integer.value = 0;
112
+
113
+
in_obj.type = ACPI_TYPE_PACKAGE;
114
+
in_obj.package.count = ARRAY_SIZE(arg3);
115
+
in_obj.package.elements = arg3;
116
+
117
+
out_obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 7,
118
+
TPH_ST_DSM_FUNC_INDEX, &in_obj);
119
+
if (!out_obj)
120
+
return AE_ERROR;
121
+
122
+
if (out_obj->type != ACPI_TYPE_BUFFER) {
123
+
ACPI_FREE(out_obj);
124
+
return AE_ERROR;
125
+
}
126
+
127
+
st_out->value = *((u64 *)(out_obj->buffer.pointer));
128
+
129
+
ACPI_FREE(out_obj);
130
+
131
+
return AE_OK;
132
+
}
133
+
#endif
134
+
135
+
/* Update the TPH Requester Enable field of TPH Control Register */
136
+
static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type)
137
+
{
138
+
u32 reg;
139
+
140
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®);
141
+
142
+
reg &= ~PCI_TPH_CTRL_REQ_EN_MASK;
143
+
reg |= FIELD_PREP(PCI_TPH_CTRL_REQ_EN_MASK, req_type);
144
+
145
+
pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);
146
+
}
147
+
148
+
static u8 get_st_modes(struct pci_dev *pdev)
149
+
{
150
+
u32 reg;
151
+
152
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);
153
+
reg &= PCI_TPH_CAP_ST_NS | PCI_TPH_CAP_ST_IV | PCI_TPH_CAP_ST_DS;
154
+
155
+
return reg;
156
+
}
157
+
158
+
static u32 get_st_table_loc(struct pci_dev *pdev)
159
+
{
160
+
u32 reg;
161
+
162
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);
163
+
164
+
return FIELD_GET(PCI_TPH_CAP_LOC_MASK, reg);
165
+
}
166
+
167
+
/*
168
+
* Return the size of ST table. If ST table is not in TPH Requester Extended
169
+
* Capability space, return 0. Otherwise return the ST Table Size + 1.
170
+
*/
171
+
static u16 get_st_table_size(struct pci_dev *pdev)
172
+
{
173
+
u32 reg;
174
+
u32 loc;
175
+
176
+
/* Check ST table location first */
177
+
loc = get_st_table_loc(pdev);
178
+
179
+
/* Convert loc to match with PCI_TPH_LOC_* defined in pci_regs.h */
180
+
loc = FIELD_PREP(PCI_TPH_CAP_LOC_MASK, loc);
181
+
if (loc != PCI_TPH_LOC_CAP)
182
+
return 0;
183
+
184
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);
185
+
186
+
return FIELD_GET(PCI_TPH_CAP_ST_MASK, reg) + 1;
187
+
}
188
+
189
+
/* Return device's Root Port completer capability */
190
+
static u8 get_rp_completer_type(struct pci_dev *pdev)
191
+
{
192
+
struct pci_dev *rp;
193
+
u32 reg;
194
+
int ret;
195
+
196
+
rp = pcie_find_root_port(pdev);
197
+
if (!rp)
198
+
return 0;
199
+
200
+
ret = pcie_capability_read_dword(rp, PCI_EXP_DEVCAP2, ®);
201
+
if (ret)
202
+
return 0;
203
+
204
+
return FIELD_GET(PCI_EXP_DEVCAP2_TPH_COMP_MASK, reg);
205
+
}
206
+
207
+
/* Write ST to MSI-X vector control reg - Return 0 if OK, otherwise -errno */
208
+
static int write_tag_to_msix(struct pci_dev *pdev, int msix_idx, u16 tag)
209
+
{
210
+
#ifdef CONFIG_PCI_MSI
211
+
struct msi_desc *msi_desc = NULL;
212
+
void __iomem *vec_ctrl;
213
+
u32 val;
214
+
int err = 0;
215
+
216
+
msi_lock_descs(&pdev->dev);
217
+
218
+
/* Find the msi_desc entry with matching msix_idx */
219
+
msi_for_each_desc(msi_desc, &pdev->dev, MSI_DESC_ASSOCIATED) {
220
+
if (msi_desc->msi_index == msix_idx)
221
+
break;
222
+
}
223
+
224
+
if (!msi_desc) {
225
+
err = -ENXIO;
226
+
goto err_out;
227
+
}
228
+
229
+
/* Get the vector control register (offset 0xc) pointed by msix_idx */
230
+
vec_ctrl = pdev->msix_base + msix_idx * PCI_MSIX_ENTRY_SIZE;
231
+
vec_ctrl += PCI_MSIX_ENTRY_VECTOR_CTRL;
232
+
233
+
val = readl(vec_ctrl);
234
+
val &= ~PCI_MSIX_ENTRY_CTRL_ST;
235
+
val |= FIELD_PREP(PCI_MSIX_ENTRY_CTRL_ST, tag);
236
+
writel(val, vec_ctrl);
237
+
238
+
/* Read back to flush the update */
239
+
val = readl(vec_ctrl);
240
+
241
+
err_out:
242
+
msi_unlock_descs(&pdev->dev);
243
+
return err;
244
+
#else
245
+
return -ENODEV;
246
+
#endif
247
+
}
248
+
249
+
/* Write tag to ST table - Return 0 if OK, otherwise -errno */
250
+
static int write_tag_to_st_table(struct pci_dev *pdev, int index, u16 tag)
251
+
{
252
+
int st_table_size;
253
+
int offset;
254
+
255
+
/* Check if index is out of bound */
256
+
st_table_size = get_st_table_size(pdev);
257
+
if (index >= st_table_size)
258
+
return -ENXIO;
259
+
260
+
offset = pdev->tph_cap + PCI_TPH_BASE_SIZEOF + index * sizeof(u16);
261
+
262
+
return pci_write_config_word(pdev, offset, tag);
263
+
}
264
+
265
+
/**
266
+
* pcie_tph_get_cpu_st() - Retrieve Steering Tag for a target memory associated
267
+
* with a specific CPU
268
+
* @pdev: PCI device
269
+
* @mem_type: target memory type (volatile or persistent RAM)
270
+
* @cpu_uid: associated CPU id
271
+
* @tag: Steering Tag to be returned
272
+
*
273
+
* Return the Steering Tag for a target memory that is associated with a
274
+
* specific CPU as indicated by cpu_uid.
275
+
*
276
+
* Return: 0 if success, otherwise negative value (-errno)
277
+
*/
278
+
int pcie_tph_get_cpu_st(struct pci_dev *pdev, enum tph_mem_type mem_type,
279
+
unsigned int cpu_uid, u16 *tag)
280
+
{
281
+
#ifdef CONFIG_ACPI
282
+
struct pci_dev *rp;
283
+
acpi_handle rp_acpi_handle;
284
+
union st_info info;
285
+
286
+
rp = pcie_find_root_port(pdev);
287
+
if (!rp || !rp->bus || !rp->bus->bridge)
288
+
return -ENODEV;
289
+
290
+
rp_acpi_handle = ACPI_HANDLE(rp->bus->bridge);
291
+
292
+
if (tph_invoke_dsm(rp_acpi_handle, cpu_uid, &info) != AE_OK) {
293
+
*tag = 0;
294
+
return -EINVAL;
295
+
}
296
+
297
+
*tag = tph_extract_tag(mem_type, pdev->tph_req_type, &info);
298
+
299
+
pci_dbg(pdev, "get steering tag: mem_type=%s, cpu_uid=%d, tag=%#04x\n",
300
+
(mem_type == TPH_MEM_TYPE_VM) ? "volatile" : "persistent",
301
+
cpu_uid, *tag);
302
+
303
+
return 0;
304
+
#else
305
+
return -ENODEV;
306
+
#endif
307
+
}
308
+
EXPORT_SYMBOL(pcie_tph_get_cpu_st);
309
+
310
+
/**
311
+
* pcie_tph_set_st_entry() - Set Steering Tag in the ST table entry
312
+
* @pdev: PCI device
313
+
* @index: ST table entry index
314
+
* @tag: Steering Tag to be written
315
+
*
316
+
* Figure out the proper location of ST table, either in the MSI-X table or
317
+
* in the TPH Extended Capability space, and write the Steering Tag into
318
+
* the ST entry pointed by index.
319
+
*
320
+
* Return: 0 if success, otherwise negative value (-errno)
321
+
*/
322
+
int pcie_tph_set_st_entry(struct pci_dev *pdev, unsigned int index, u16 tag)
323
+
{
324
+
u32 loc;
325
+
int err = 0;
326
+
327
+
if (!pdev->tph_cap)
328
+
return -EINVAL;
329
+
330
+
if (!pdev->tph_enabled)
331
+
return -EINVAL;
332
+
333
+
/* No need to write tag if device is in "No ST Mode" */
334
+
if (pdev->tph_mode == PCI_TPH_ST_NS_MODE)
335
+
return 0;
336
+
337
+
/*
338
+
* Disable TPH before updating ST to avoid potential instability as
339
+
* cautioned in PCIe r6.2, sec 6.17.3, "ST Modes of Operation"
340
+
*/
341
+
set_ctrl_reg_req_en(pdev, PCI_TPH_REQ_DISABLE);
342
+
343
+
loc = get_st_table_loc(pdev);
344
+
/* Convert loc to match with PCI_TPH_LOC_* */
345
+
loc = FIELD_PREP(PCI_TPH_CAP_LOC_MASK, loc);
346
+
347
+
switch (loc) {
348
+
case PCI_TPH_LOC_MSIX:
349
+
err = write_tag_to_msix(pdev, index, tag);
350
+
break;
351
+
case PCI_TPH_LOC_CAP:
352
+
err = write_tag_to_st_table(pdev, index, tag);
353
+
break;
354
+
default:
355
+
err = -EINVAL;
356
+
}
357
+
358
+
if (err) {
359
+
pcie_disable_tph(pdev);
360
+
return err;
361
+
}
362
+
363
+
set_ctrl_reg_req_en(pdev, pdev->tph_mode);
364
+
365
+
pci_dbg(pdev, "set steering tag: %s table, index=%d, tag=%#04x\n",
366
+
(loc == PCI_TPH_LOC_MSIX) ? "MSI-X" : "ST", index, tag);
367
+
368
+
return 0;
369
+
}
370
+
EXPORT_SYMBOL(pcie_tph_set_st_entry);
371
+
372
+
/**
373
+
* pcie_disable_tph - Turn off TPH support for device
374
+
* @pdev: PCI device
375
+
*
376
+
* Return: none
377
+
*/
378
+
void pcie_disable_tph(struct pci_dev *pdev)
379
+
{
380
+
if (!pdev->tph_cap)
381
+
return;
382
+
383
+
if (!pdev->tph_enabled)
384
+
return;
385
+
386
+
pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, 0);
387
+
388
+
pdev->tph_mode = 0;
389
+
pdev->tph_req_type = 0;
390
+
pdev->tph_enabled = 0;
391
+
}
392
+
EXPORT_SYMBOL(pcie_disable_tph);
393
+
394
+
/**
395
+
* pcie_enable_tph - Enable TPH support for device using a specific ST mode
396
+
* @pdev: PCI device
397
+
* @mode: ST mode to enable. Current supported modes include:
398
+
*
399
+
* - PCI_TPH_ST_NS_MODE: NO ST Mode
400
+
* - PCI_TPH_ST_IV_MODE: Interrupt Vector Mode
401
+
* - PCI_TPH_ST_DS_MODE: Device Specific Mode
402
+
*
403
+
* Check whether the mode is actually supported by the device before enabling
404
+
* and return an error if not. Additionally determine what types of requests,
405
+
* TPH or extended TPH, can be issued by the device based on its TPH requester
406
+
* capability and the Root Port's completer capability.
407
+
*
408
+
* Return: 0 on success, otherwise negative value (-errno)
409
+
*/
410
+
int pcie_enable_tph(struct pci_dev *pdev, int mode)
411
+
{
412
+
u32 reg;
413
+
u8 dev_modes;
414
+
u8 rp_req_type;
415
+
416
+
/* Honor "notph" kernel parameter */
417
+
if (pci_tph_disabled)
418
+
return -EINVAL;
419
+
420
+
if (!pdev->tph_cap)
421
+
return -EINVAL;
422
+
423
+
if (pdev->tph_enabled)
424
+
return -EBUSY;
425
+
426
+
/* Sanitize and check ST mode compatibility */
427
+
mode &= PCI_TPH_CTRL_MODE_SEL_MASK;
428
+
dev_modes = get_st_modes(pdev);
429
+
if (!((1 << mode) & dev_modes))
430
+
return -EINVAL;
431
+
432
+
pdev->tph_mode = mode;
433
+
434
+
/* Get req_type supported by device and its Root Port */
435
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);
436
+
if (FIELD_GET(PCI_TPH_CAP_EXT_TPH, reg))
437
+
pdev->tph_req_type = PCI_TPH_REQ_EXT_TPH;
438
+
else
439
+
pdev->tph_req_type = PCI_TPH_REQ_TPH_ONLY;
440
+
441
+
rp_req_type = get_rp_completer_type(pdev);
442
+
443
+
/* Final req_type is the smallest value of two */
444
+
pdev->tph_req_type = min(pdev->tph_req_type, rp_req_type);
445
+
446
+
if (pdev->tph_req_type == PCI_TPH_REQ_DISABLE)
447
+
return -EINVAL;
448
+
449
+
/* Write them into TPH control register */
450
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®);
451
+
452
+
reg &= ~PCI_TPH_CTRL_MODE_SEL_MASK;
453
+
reg |= FIELD_PREP(PCI_TPH_CTRL_MODE_SEL_MASK, pdev->tph_mode);
454
+
455
+
reg &= ~PCI_TPH_CTRL_REQ_EN_MASK;
456
+
reg |= FIELD_PREP(PCI_TPH_CTRL_REQ_EN_MASK, pdev->tph_req_type);
457
+
458
+
pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);
459
+
460
+
pdev->tph_enabled = 1;
461
+
462
+
return 0;
463
+
}
464
+
EXPORT_SYMBOL(pcie_enable_tph);
465
+
466
+
void pci_restore_tph_state(struct pci_dev *pdev)
467
+
{
468
+
struct pci_cap_saved_state *save_state;
469
+
int num_entries, i, offset;
470
+
u16 *st_entry;
471
+
u32 *cap;
472
+
473
+
if (!pdev->tph_cap)
474
+
return;
475
+
476
+
if (!pdev->tph_enabled)
477
+
return;
478
+
479
+
save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_TPH);
480
+
if (!save_state)
481
+
return;
482
+
483
+
/* Restore control register and all ST entries */
484
+
cap = &save_state->cap.data[0];
485
+
pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, *cap++);
486
+
st_entry = (u16 *)cap;
487
+
offset = PCI_TPH_BASE_SIZEOF;
488
+
num_entries = get_st_table_size(pdev);
489
+
for (i = 0; i < num_entries; i++) {
490
+
pci_write_config_word(pdev, pdev->tph_cap + offset,
491
+
*st_entry++);
492
+
offset += sizeof(u16);
493
+
}
494
+
}
495
+
496
+
void pci_save_tph_state(struct pci_dev *pdev)
497
+
{
498
+
struct pci_cap_saved_state *save_state;
499
+
int num_entries, i, offset;
500
+
u16 *st_entry;
501
+
u32 *cap;
502
+
503
+
if (!pdev->tph_cap)
504
+
return;
505
+
506
+
if (!pdev->tph_enabled)
507
+
return;
508
+
509
+
save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_TPH);
510
+
if (!save_state)
511
+
return;
512
+
513
+
/* Save control register */
514
+
cap = &save_state->cap.data[0];
515
+
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, cap++);
516
+
517
+
/* Save all ST entries in extended capability structure */
518
+
st_entry = (u16 *)cap;
519
+
offset = PCI_TPH_BASE_SIZEOF;
520
+
num_entries = get_st_table_size(pdev);
521
+
for (i = 0; i < num_entries; i++) {
522
+
pci_read_config_word(pdev, pdev->tph_cap + offset,
523
+
st_entry++);
524
+
offset += sizeof(u16);
525
+
}
526
+
}
527
+
528
+
void pci_no_tph(void)
529
+
{
530
+
pci_tph_disabled = true;
531
+
532
+
pr_info("PCIe TPH is disabled\n");
533
+
}
534
+
535
+
void pci_tph_init(struct pci_dev *pdev)
536
+
{
537
+
int num_entries;
538
+
u32 save_size;
539
+
540
+
pdev->tph_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_TPH);
541
+
if (!pdev->tph_cap)
542
+
return;
543
+
544
+
num_entries = get_st_table_size(pdev);
545
+
save_size = sizeof(u32) + num_entries * sizeof(u16);
546
+
pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_TPH, save_size);
547
+
}
+9
drivers/thermal/Kconfig
+9
drivers/thermal/Kconfig
···
220
220
221
221
If you want this support, you should say Y here.
222
222
223
+
config PCIE_THERMAL
224
+
bool "PCIe cooling support"
225
+
depends on PCIEPORTBUS
226
+
help
227
+
This implements PCIe cooling mechanism through bandwidth reduction
228
+
for PCIe devices.
229
+
230
+
If you want this support, you should say Y here.
231
+
223
232
config THERMAL_EMULATION
224
233
bool "Thermal emulation mode support"
225
234
help
+2
drivers/thermal/Makefile
+2
drivers/thermal/Makefile
+80
drivers/thermal/pcie_cooling.c
+80
drivers/thermal/pcie_cooling.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* PCIe cooling device
4
+
*
5
+
* Copyright (C) 2023-2024 Intel Corporation
6
+
*/
7
+
8
+
#include <linux/build_bug.h>
9
+
#include <linux/cleanup.h>
10
+
#include <linux/err.h>
11
+
#include <linux/module.h>
12
+
#include <linux/pci.h>
13
+
#include <linux/pci-bwctrl.h>
14
+
#include <linux/slab.h>
15
+
#include <linux/sprintf.h>
16
+
#include <linux/thermal.h>
17
+
18
+
#define COOLING_DEV_TYPE_PREFIX "PCIe_Port_Link_Speed_"
19
+
20
+
static int pcie_cooling_get_max_level(struct thermal_cooling_device *cdev, unsigned long *state)
21
+
{
22
+
struct pci_dev *port = cdev->devdata;
23
+
24
+
/* cooling state 0 is same as the maximum PCIe speed */
25
+
*state = port->subordinate->max_bus_speed - PCIE_SPEED_2_5GT;
26
+
27
+
return 0;
28
+
}
29
+
30
+
static int pcie_cooling_get_cur_level(struct thermal_cooling_device *cdev, unsigned long *state)
31
+
{
32
+
struct pci_dev *port = cdev->devdata;
33
+
34
+
/* cooling state 0 is same as the maximum PCIe speed */
35
+
*state = cdev->max_state - (port->subordinate->cur_bus_speed - PCIE_SPEED_2_5GT);
36
+
37
+
return 0;
38
+
}
39
+
40
+
static int pcie_cooling_set_cur_level(struct thermal_cooling_device *cdev, unsigned long state)
41
+
{
42
+
struct pci_dev *port = cdev->devdata;
43
+
enum pci_bus_speed speed;
44
+
45
+
/* cooling state 0 is same as the maximum PCIe speed */
46
+
speed = (cdev->max_state - state) + PCIE_SPEED_2_5GT;
47
+
48
+
return pcie_set_target_speed(port, speed, true);
49
+
}
50
+
51
+
static struct thermal_cooling_device_ops pcie_cooling_ops = {
52
+
.get_max_state = pcie_cooling_get_max_level,
53
+
.get_cur_state = pcie_cooling_get_cur_level,
54
+
.set_cur_state = pcie_cooling_set_cur_level,
55
+
};
56
+
57
+
struct thermal_cooling_device *pcie_cooling_device_register(struct pci_dev *port)
58
+
{
59
+
char *name __free(kfree) =
60
+
kasprintf(GFP_KERNEL, COOLING_DEV_TYPE_PREFIX "%s", pci_name(port));
61
+
if (!name)
62
+
return ERR_PTR(-ENOMEM);
63
+
64
+
return thermal_cooling_device_register(name, port, &pcie_cooling_ops);
65
+
}
66
+
67
+
void pcie_cooling_device_unregister(struct thermal_cooling_device *cdev)
68
+
{
69
+
thermal_cooling_device_unregister(cdev);
70
+
}
71
+
72
+
/* For bus_speed <-> state arithmetic */
73
+
static_assert(PCIE_SPEED_2_5GT + 1 == PCIE_SPEED_5_0GT);
74
+
static_assert(PCIE_SPEED_5_0GT + 1 == PCIE_SPEED_8_0GT);
75
+
static_assert(PCIE_SPEED_8_0GT + 1 == PCIE_SPEED_16_0GT);
76
+
static_assert(PCIE_SPEED_16_0GT + 1 == PCIE_SPEED_32_0GT);
77
+
static_assert(PCIE_SPEED_32_0GT + 1 == PCIE_SPEED_64_0GT);
78
+
79
+
MODULE_AUTHOR("Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>");
80
+
MODULE_DESCRIPTION("PCIe cooling driver");
+7
-5
drivers/tty/serial/rp2.c
+7
-5
drivers/tty/serial/rp2.c
···
698
698
const struct firmware *fw;
699
699
struct rp2_card *card;
700
700
struct rp2_uart_port *ports;
701
-
void __iomem * const *bars;
702
701
int rc;
703
702
704
703
card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
···
710
711
if (rc)
711
712
return rc;
712
713
713
-
rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
714
+
rc = pcim_request_all_regions(pdev, DRV_NAME);
714
715
if (rc)
715
716
return rc;
716
717
717
-
bars = pcim_iomap_table(pdev);
718
-
card->bar0 = bars[0];
719
-
card->bar1 = bars[1];
718
+
card->bar0 = pcim_iomap(pdev, 0, 0);
719
+
if (!card->bar0)
720
+
return -ENOMEM;
721
+
card->bar1 = pcim_iomap(pdev, 1, 0);
722
+
if (!card->bar1)
723
+
return -ENOMEM;
720
724
card->pdev = pdev;
721
725
722
726
rp2_decode_cap(id, &card->n_ports, &card->smpte);
+32
include/linux/ioport.h
+32
include/linux/ioport.h
···
249
249
int adjust_resource(struct resource *res, resource_size_t start,
250
250
resource_size_t size);
251
251
resource_size_t resource_alignment(struct resource *res);
252
+
253
+
/**
254
+
* resource_set_size - Calculate resource end address from size and start
255
+
* @res: Resource descriptor
256
+
* @size: Size of the resource
257
+
*
258
+
* Calculate the end address for @res based on @size.
259
+
*
260
+
* Note: The start address of @res must be set when calling this function.
261
+
* Prefer resource_set_range() if setting both the start address and @size.
262
+
*/
263
+
static inline void resource_set_size(struct resource *res, resource_size_t size)
264
+
{
265
+
res->end = res->start + size - 1;
266
+
}
267
+
268
+
/**
269
+
* resource_set_range - Set resource start and end addresses
270
+
* @res: Resource descriptor
271
+
* @start: Start address for the resource
272
+
* @size: Size of the resource
273
+
*
274
+
* Set @res start address and calculate the end address based on @size.
275
+
*/
276
+
static inline void resource_set_range(struct resource *res,
277
+
resource_size_t start,
278
+
resource_size_t size)
279
+
{
280
+
res->start = start;
281
+
resource_set_size(res, size);
282
+
}
283
+
252
284
static inline resource_size_t resource_size(const struct resource *res)
253
285
{
254
286
return res->end - res->start + 1;
+28
include/linux/pci-bwctrl.h
+28
include/linux/pci-bwctrl.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* PCIe bandwidth controller
4
+
*
5
+
* Copyright (C) 2023-2024 Intel Corporation
6
+
*/
7
+
8
+
#ifndef LINUX_PCI_BWCTRL_H
9
+
#define LINUX_PCI_BWCTRL_H
10
+
11
+
#include <linux/pci.h>
12
+
13
+
struct thermal_cooling_device;
14
+
15
+
#ifdef CONFIG_PCIE_THERMAL
16
+
struct thermal_cooling_device *pcie_cooling_device_register(struct pci_dev *port);
17
+
void pcie_cooling_device_unregister(struct thermal_cooling_device *cdev);
18
+
#else
19
+
static inline struct thermal_cooling_device *pcie_cooling_device_register(struct pci_dev *port)
20
+
{
21
+
return NULL;
22
+
}
23
+
static inline void pcie_cooling_device_unregister(struct thermal_cooling_device *cdev)
24
+
{
25
+
}
26
+
#endif
27
+
28
+
#endif
+38
include/linux/pci-epc.h
+38
include/linux/pci-epc.h
···
33
33
}
34
34
35
35
/**
36
+
* struct pci_epc_map - information about EPC memory for mapping a RC PCI
37
+
* address range
38
+
* @pci_addr: start address of the RC PCI address range to map
39
+
* @pci_size: size of the RC PCI address range mapped from @pci_addr
40
+
* @map_pci_addr: RC PCI address used as the first address mapped (may be lower
41
+
* than @pci_addr)
42
+
* @map_size: size of the controller memory needed for mapping the RC PCI address
43
+
* range @map_pci_addr..@pci_addr+@pci_size
44
+
* @phys_base: base physical address of the allocated EPC memory for mapping the
45
+
* RC PCI address range
46
+
* @phys_addr: physical address at which @pci_addr is mapped
47
+
* @virt_base: base virtual address of the allocated EPC memory for mapping the
48
+
* RC PCI address range
49
+
* @virt_addr: virtual address at which @pci_addr is mapped
50
+
*/
51
+
struct pci_epc_map {
52
+
u64 pci_addr;
53
+
size_t pci_size;
54
+
55
+
u64 map_pci_addr;
56
+
size_t map_size;
57
+
58
+
phys_addr_t phys_base;
59
+
phys_addr_t phys_addr;
60
+
void __iomem *virt_base;
61
+
void __iomem *virt_addr;
62
+
};
63
+
64
+
/**
36
65
* struct pci_epc_ops - set of function pointers for performing EPC operations
37
66
* @write_header: ops to populate configuration space header
38
67
* @set_bar: ops to configure the BAR
39
68
* @clear_bar: ops to reset the BAR
69
+
* @align_addr: operation to get the mapping address, mapping size and offset
70
+
* into a controller memory window needed to map an RC PCI address
71
+
* region
40
72
* @map_addr: ops to map CPU address to PCI address
41
73
* @unmap_addr: ops to unmap CPU address and PCI address
42
74
* @set_msi: ops to set the requested number of MSI interrupts in the MSI
···
93
61
struct pci_epf_bar *epf_bar);
94
62
void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
95
63
struct pci_epf_bar *epf_bar);
64
+
u64 (*align_addr)(struct pci_epc *epc, u64 pci_addr, size_t *size,
65
+
size_t *offset);
96
66
int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
97
67
phys_addr_t addr, u64 pci_addr, size_t size);
98
68
void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
···
312
278
phys_addr_t *phys_addr, size_t size);
313
279
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
314
280
void __iomem *virt_addr, size_t size);
281
+
int pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
282
+
u64 pci_addr, size_t pci_size, struct pci_epc_map *map);
283
+
void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
284
+
struct pci_epc_map *map);
315
285
316
286
#else
317
287
static inline void pci_epc_init_notify(struct pci_epc *epc)
+11
-11
include/linux/pci-pwrctl.h
include/linux/pci-pwrctrl.h
+11
-11
include/linux/pci-pwrctl.h
include/linux/pci-pwrctrl.h
···
3
3
* Copyright (C) 2024 Linaro Ltd.
4
4
*/
5
5
6
-
#ifndef __PCI_PWRCTL_H__
7
-
#define __PCI_PWRCTL_H__
6
+
#ifndef __PCI_PWRCTRL_H__
7
+
#define __PCI_PWRCTRL_H__
8
8
9
9
#include <linux/notifier.h>
10
10
#include <linux/workqueue.h>
···
29
29
*/
30
30
31
31
/**
32
-
* struct pci_pwrctl - PCI device power control context.
32
+
* struct pci_pwrctrl - PCI device power control context.
33
33
* @dev: Address of the power controlling device.
34
34
*
35
35
* An object of this type must be allocated by the PCI power control device and
36
-
* passed to the pwrctl subsystem to trigger a bus rescan and setup a device
36
+
* passed to the pwrctrl subsystem to trigger a bus rescan and setup a device
37
37
* link with the device once it's up.
38
38
*/
39
-
struct pci_pwrctl {
39
+
struct pci_pwrctrl {
40
40
struct device *dev;
41
41
42
42
/* Private: don't use. */
···
45
45
struct work_struct work;
46
46
};
47
47
48
-
void pci_pwrctl_init(struct pci_pwrctl *pwrctl, struct device *dev);
49
-
int pci_pwrctl_device_set_ready(struct pci_pwrctl *pwrctl);
50
-
void pci_pwrctl_device_unset_ready(struct pci_pwrctl *pwrctl);
51
-
int devm_pci_pwrctl_device_set_ready(struct device *dev,
52
-
struct pci_pwrctl *pwrctl);
48
+
void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct device *dev);
49
+
int pci_pwrctrl_device_set_ready(struct pci_pwrctrl *pwrctrl);
50
+
void pci_pwrctrl_device_unset_ready(struct pci_pwrctrl *pwrctrl);
51
+
int devm_pci_pwrctrl_device_set_ready(struct device *dev,
52
+
struct pci_pwrctrl *pwrctrl);
53
53
54
-
#endif /* __PCI_PWRCTL_H__ */
54
+
#endif /* __PCI_PWRCTRL_H__ */
+44
include/linux/pci-tph.h
+44
include/linux/pci-tph.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* TPH (TLP Processing Hints)
4
+
*
5
+
* Copyright (C) 2024 Advanced Micro Devices, Inc.
6
+
* Eric Van Tassell <Eric.VanTassell@amd.com>
7
+
* Wei Huang <wei.huang2@amd.com>
8
+
*/
9
+
#ifndef LINUX_PCI_TPH_H
10
+
#define LINUX_PCI_TPH_H
11
+
12
+
/*
13
+
* According to the ECN for PCI Firmware Spec, Steering Tag can be different
14
+
* depending on the memory type: Volatile Memory or Persistent Memory. When a
15
+
* caller query about a target's Steering Tag, it must provide the target's
16
+
* tph_mem_type. ECN link: https://members.pcisig.com/wg/PCI-SIG/document/15470.
17
+
*/
18
+
enum tph_mem_type {
19
+
TPH_MEM_TYPE_VM, /* volatile memory */
20
+
TPH_MEM_TYPE_PM /* persistent memory */
21
+
};
22
+
23
+
#ifdef CONFIG_PCIE_TPH
24
+
int pcie_tph_set_st_entry(struct pci_dev *pdev,
25
+
unsigned int index, u16 tag);
26
+
int pcie_tph_get_cpu_st(struct pci_dev *dev,
27
+
enum tph_mem_type mem_type,
28
+
unsigned int cpu_uid, u16 *tag);
29
+
void pcie_disable_tph(struct pci_dev *pdev);
30
+
int pcie_enable_tph(struct pci_dev *pdev, int mode);
31
+
#else
32
+
static inline int pcie_tph_set_st_entry(struct pci_dev *pdev,
33
+
unsigned int index, u16 tag)
34
+
{ return -EINVAL; }
35
+
static inline int pcie_tph_get_cpu_st(struct pci_dev *dev,
36
+
enum tph_mem_type mem_type,
37
+
unsigned int cpu_uid, u16 *tag)
38
+
{ return -EINVAL; }
39
+
static inline void pcie_disable_tph(struct pci_dev *pdev) { }
40
+
static inline int pcie_enable_tph(struct pci_dev *pdev, int mode)
41
+
{ return -EINVAL; }
42
+
#endif
43
+
44
+
#endif /* LINUX_PCI_TPH_H */
+38
-28
include/linux/pci.h
+38
-28
include/linux/pci.h
···
313
313
};
314
314
315
315
struct irq_affinity;
316
+
struct pcie_bwctrl_data;
316
317
struct pcie_link_state;
317
318
struct pci_sriov;
318
319
struct pci_p2pdma;
319
320
struct rcec_ea;
320
321
321
-
/* The pci_dev structure describes PCI devices */
322
+
/* struct pci_dev - describes a PCI device
323
+
*
324
+
* @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at
325
+
* LSB). 0 when the supported speeds cannot be
326
+
* determined (e.g., for Root Complex Integrated
327
+
* Endpoints without the relevant Capability
328
+
* Registers).
329
+
*/
322
330
struct pci_dev {
323
331
struct list_head bus_list; /* Node in per-bus list */
324
332
struct pci_bus *bus; /* Bus this device is on */
···
442
434
unsigned int ats_enabled:1; /* Address Translation Svc */
443
435
unsigned int pasid_enabled:1; /* Process Address Space ID */
444
436
unsigned int pri_enabled:1; /* Page Request Interface */
437
+
unsigned int tph_enabled:1; /* TLP Processing Hints */
445
438
unsigned int is_managed:1; /* Managed via devres */
446
439
unsigned int is_msi_managed:1; /* MSI release via devres installed */
447
440
unsigned int needs_freset:1; /* Requires fundamental reset */
···
504
495
unsigned int dpc_rp_extensions:1;
505
496
u8 dpc_rp_log_size;
506
497
#endif
498
+
struct pcie_bwctrl_data *link_bwctrl;
507
499
#ifdef CONFIG_PCI_ATS
508
500
union {
509
501
struct pci_sriov *sriov; /* PF: SR-IOV info */
···
532
522
struct npem *npem; /* Native PCIe Enclosure Management */
533
523
#endif
534
524
u16 acs_cap; /* ACS Capability offset */
525
+
u8 supported_speeds; /* Supported Link Speeds Vector */
535
526
phys_addr_t rom; /* Physical address if not from BAR */
536
527
size_t romlen; /* Length if not from BAR */
537
528
/*
···
545
534
546
535
/* These methods index pci_reset_fn_methods[] */
547
536
u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
537
+
538
+
#ifdef CONFIG_PCIE_TPH
539
+
u16 tph_cap; /* TPH capability offset */
540
+
u8 tph_mode; /* TPH mode */
541
+
u8 tph_req_type; /* TPH requester type */
542
+
#endif
548
543
};
549
544
550
545
static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
···
642
625
void *release_data);
643
626
644
627
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
645
-
646
-
/*
647
-
* The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
648
-
* to P2P or CardBus bridge windows) go in a table. Additional ones (for
649
-
* buses below host bridges or subtractive decode bridges) go in the list.
650
-
* Use pci_bus_for_each_resource() to iterate through all the resources.
651
-
*/
652
-
653
-
/*
654
-
* PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
655
-
* and there's no way to program the bridge with the details of the window.
656
-
* This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
657
-
* decode bit set, because they are explicit and can be programmed with _SRS.
658
-
*/
659
-
#define PCI_SUBTRACTIVE_DECODE 0x1
660
-
661
-
struct pci_bus_resource {
662
-
struct list_head list;
663
-
struct resource *res;
664
-
unsigned int flags;
665
-
};
666
628
667
629
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
668
630
···
1270
1274
{
1271
1275
switch (pos) {
1272
1276
case PCI_EXP_LNKCTL:
1277
+
case PCI_EXP_LNKCTL2:
1273
1278
case PCI_EXP_RTCTL:
1274
1279
return pcie_capability_clear_and_set_word_locked(dev, pos,
1275
1280
clear, set);
···
1495
1498
void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1496
1499
resource_size_t offset);
1497
1500
void pci_free_resource_list(struct list_head *resources);
1498
-
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1499
-
unsigned int flags);
1501
+
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res);
1500
1502
struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1501
1503
void pci_bus_remove_resources(struct pci_bus *bus);
1502
1504
void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
···
1619
1623
1620
1624
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1621
1625
void *userdata);
1622
-
void pci_walk_bus_locked(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1623
-
void *userdata);
1624
1626
int pci_cfg_space_size(struct pci_dev *dev);
1625
1627
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1626
1628
void pci_setup_bridge(struct pci_bus *bus);
···
1780
1786
#ifdef CONFIG_PCIEPORTBUS
1781
1787
extern bool pcie_ports_disabled;
1782
1788
extern bool pcie_ports_native;
1789
+
1790
+
int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req,
1791
+
bool use_lt);
1783
1792
#else
1784
1793
#define pcie_ports_disabled true
1785
1794
#define pcie_ports_native false
1795
+
1796
+
static inline int pcie_set_target_speed(struct pci_dev *port,
1797
+
enum pci_bus_speed speed_req,
1798
+
bool use_lt)
1799
+
{
1800
+
return -EOPNOTSUPP;
1801
+
}
1786
1802
#endif
1787
1803
1788
1804
#define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */
···
2297
2293
struct pci_dev *dev) { }
2298
2294
#endif
2299
2295
2296
+
int pcim_request_all_regions(struct pci_dev *pdev, const char *name);
2300
2297
void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2301
2298
void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar,
2302
2299
const char *name);
2300
+
void pcim_iounmap_region(struct pci_dev *pdev, int bar);
2303
2301
void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2304
2302
void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2305
2303
int pcim_request_region(struct pci_dev *pdev, int bar, const char *name);
2306
2304
int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2307
-
int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2308
-
const char *name);
2309
2305
void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2310
2306
void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar,
2311
2307
unsigned long offset, unsigned long len);
···
2611
2607
static inline struct irq_domain *
2612
2608
pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2613
2609
static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2610
+
#endif
2611
+
2612
+
#if defined(CONFIG_X86) && defined(CONFIG_ACPI)
2613
+
bool arch_pci_dev_is_removable(struct pci_dev *pdev);
2614
+
#else
2615
+
static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; }
2614
2616
#endif
2615
2617
2616
2618
#ifdef CONFIG_EEH
+30
-8
include/uapi/linux/pci_regs.h
+30
-8
include/uapi/linux/pci_regs.h
···
340
340
#define PCI_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */
341
341
#define PCI_MSIX_ENTRY_DATA 0x8 /* Message Data */
342
342
#define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */
343
-
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
343
+
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* Mask Bit */
344
+
#define PCI_MSIX_ENTRY_CTRL_ST 0xffff0000 /* Steering Tag */
344
345
345
346
/* CompactPCI Hotswap Register */
346
347
···
660
659
#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */
661
660
#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */
662
661
#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
662
+
#define PCI_EXP_DEVCAP2_TPH_COMP_MASK 0x00003000 /* TPH completer support */
663
663
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
664
664
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
665
665
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
···
680
678
#define PCI_EXP_DEVSTA2 0x2a /* Device Status 2 */
681
679
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c /* end of v2 EPs w/o link */
682
680
#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities 2 */
681
+
#define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
683
682
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
684
683
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
685
684
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
···
1026
1023
#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1027
1024
#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */
1028
1025
1026
+
/* TPH Completer Support */
1027
+
#define PCI_EXP_DEVCAP2_TPH_COMP_NONE 0x0 /* None */
1028
+
#define PCI_EXP_DEVCAP2_TPH_COMP_TPH_ONLY 0x1 /* TPH only */
1029
+
#define PCI_EXP_DEVCAP2_TPH_COMP_EXT_TPH 0x3 /* TPH and Extended TPH */
1030
+
1029
1031
/* TPH Requester */
1030
1032
#define PCI_TPH_CAP 4 /* capability register */
1031
-
#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
1032
-
#define PCI_TPH_LOC_NONE 0x000 /* no location */
1033
-
#define PCI_TPH_LOC_CAP 0x200 /* in capability */
1034
-
#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
1035
-
#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST table mask */
1036
-
#define PCI_TPH_CAP_ST_SHIFT 16 /* ST table shift */
1037
-
#define PCI_TPH_BASE_SIZEOF 0xc /* size with no ST table */
1033
+
#define PCI_TPH_CAP_ST_NS 0x00000001 /* No ST Mode Supported */
1034
+
#define PCI_TPH_CAP_ST_IV 0x00000002 /* Interrupt Vector Mode Supported */
1035
+
#define PCI_TPH_CAP_ST_DS 0x00000004 /* Device Specific Mode Supported */
1036
+
#define PCI_TPH_CAP_EXT_TPH 0x00000100 /* Ext TPH Requester Supported */
1037
+
#define PCI_TPH_CAP_LOC_MASK 0x00000600 /* ST Table Location */
1038
+
#define PCI_TPH_LOC_NONE 0x00000000 /* Not present */
1039
+
#define PCI_TPH_LOC_CAP 0x00000200 /* In capability */
1040
+
#define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */
1041
+
#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST Table Size */
1042
+
#define PCI_TPH_CAP_ST_SHIFT 16 /* ST Table Size shift */
1043
+
#define PCI_TPH_BASE_SIZEOF 0xc /* Size with no ST table */
1044
+
1045
+
#define PCI_TPH_CTRL 8 /* control register */
1046
+
#define PCI_TPH_CTRL_MODE_SEL_MASK 0x00000007 /* ST Mode Select */
1047
+
#define PCI_TPH_ST_NS_MODE 0x0 /* No ST Mode */
1048
+
#define PCI_TPH_ST_IV_MODE 0x1 /* Interrupt Vector Mode */
1049
+
#define PCI_TPH_ST_DS_MODE 0x2 /* Device Specific Mode */
1050
+
#define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH Requester Enable */
1051
+
#define PCI_TPH_REQ_DISABLE 0x0 /* No TPH requests allowed */
1052
+
#define PCI_TPH_REQ_TPH_ONLY 0x1 /* TPH only requests allowed */
1053
+
#define PCI_TPH_REQ_EXT_TPH 0x3 /* Extended TPH requests allowed */
1038
1054
1039
1055
/* Downstream Port Containment */
1040
1056
#define PCI_EXP_DPC_CAP 0x04 /* DPC Capability */
+4
-2
sound/pci/korg1212/korg1212.c
+4
-2
sound/pci/korg1212/korg1212.c
···
2108
2108
for (i=0; i<kAudioChannels; i++)
2109
2109
korg1212->volumePhase[i] = 0;
2110
2110
2111
-
err = pcim_iomap_regions_request_all(pci, 1 << 0, "korg1212");
2111
+
err = pcim_request_all_regions(pci, "korg1212");
2112
2112
if (err < 0)
2113
2113
return err;
2114
2114
···
2130
2130
korg1212->iomem2, iomem2_size,
2131
2131
stateName[korg1212->cardState]);
2132
2132
2133
-
korg1212->iobase = pcim_iomap_table(pci)[0];
2133
+
korg1212->iobase = pcim_iomap(pci, 0, 0);
2134
+
if (!korg1212->iobase)
2135
+
return -ENOMEM;
2134
2136
2135
2137
err = devm_request_irq(&pci->dev, pci->irq, snd_korg1212_interrupt,
2136
2138
IRQF_SHARED,
+5
-5
tools/pci/pcitest.c
+5
-5
tools/pci/pcitest.c
···
95
95
96
96
if (test->msinum > 0 && test->msinum <= 32) {
97
97
ret = ioctl(fd, PCITEST_MSI, test->msinum);
98
-
fprintf(stdout, "MSI%d:\t\t", test->msinum);
98
+
fprintf(stdout, "MSI%u:\t\t", test->msinum);
99
99
if (ret < 0)
100
100
fprintf(stdout, "TEST FAILED\n");
101
101
else
···
104
104
105
105
if (test->msixnum > 0 && test->msixnum <= 2048) {
106
106
ret = ioctl(fd, PCITEST_MSIX, test->msixnum);
107
-
fprintf(stdout, "MSI-X%d:\t\t", test->msixnum);
107
+
fprintf(stdout, "MSI-X%u:\t\t", test->msixnum);
108
108
if (ret < 0)
109
109
fprintf(stdout, "TEST FAILED\n");
110
110
else
···
116
116
if (test->use_dma)
117
117
param.flags = PCITEST_FLAGS_USE_DMA;
118
118
ret = ioctl(fd, PCITEST_WRITE, ¶m);
119
-
fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
119
+
fprintf(stdout, "WRITE (%7lu bytes):\t\t", test->size);
120
120
if (ret < 0)
121
121
fprintf(stdout, "TEST FAILED\n");
122
122
else
···
128
128
if (test->use_dma)
129
129
param.flags = PCITEST_FLAGS_USE_DMA;
130
130
ret = ioctl(fd, PCITEST_READ, ¶m);
131
-
fprintf(stdout, "READ (%7ld bytes):\t\t", test->size);
131
+
fprintf(stdout, "READ (%7lu bytes):\t\t", test->size);
132
132
if (ret < 0)
133
133
fprintf(stdout, "TEST FAILED\n");
134
134
else
···
140
140
if (test->use_dma)
141
141
param.flags = PCITEST_FLAGS_USE_DMA;
142
142
ret = ioctl(fd, PCITEST_COPY, ¶m);
143
-
fprintf(stdout, "COPY (%7ld bytes):\t\t", test->size);
143
+
fprintf(stdout, "COPY (%7lu bytes):\t\t", test->size);
144
144
if (ret < 0)
145
145
fprintf(stdout, "TEST FAILED\n");
146
146
else
+1
tools/testing/selftests/Makefile
+1
tools/testing/selftests/Makefile
+2
tools/testing/selftests/pcie_bwctrl/Makefile
+2
tools/testing/selftests/pcie_bwctrl/Makefile
+122
tools/testing/selftests/pcie_bwctrl/set_pcie_cooling_state.sh
+122
tools/testing/selftests/pcie_bwctrl/set_pcie_cooling_state.sh
···
1
+
#!/bin/bash
2
+
# SPDX-License-Identifier: GPL-2.0-or-later
3
+
4
+
SYSFS=
5
+
# Kselftest framework requirement - SKIP code is 4.
6
+
ksft_skip=4
7
+
retval=0
8
+
skipmsg="skip all tests:"
9
+
10
+
PCIEPORTTYPE="PCIe_Port_Link_Speed"
11
+
12
+
prerequisite()
13
+
{
14
+
local ports
15
+
16
+
if [ $UID != 0 ]; then
17
+
echo $skipmsg must be run as root >&2
18
+
exit $ksft_skip
19
+
fi
20
+
21
+
SYSFS=`mount -t sysfs | head -1 | awk '{ print $3 }'`
22
+
23
+
if [ ! -d "$SYSFS" ]; then
24
+
echo $skipmsg sysfs is not mounted >&2
25
+
exit $ksft_skip
26
+
fi
27
+
28
+
if ! ls $SYSFS/class/thermal/cooling_device* > /dev/null 2>&1; then
29
+
echo $skipmsg thermal cooling devices missing >&2
30
+
exit $ksft_skip
31
+
fi
32
+
33
+
ports=`grep -e "^$PCIEPORTTYPE" $SYSFS/class/thermal/cooling_device*/type | wc -l`
34
+
if [ $ports -eq 0 ]; then
35
+
echo $skipmsg pcie cooling devices missing >&2
36
+
exit $ksft_skip
37
+
fi
38
+
}
39
+
40
+
testport=
41
+
find_pcie_port()
42
+
{
43
+
local patt="$1"
44
+
local pcieports
45
+
local max
46
+
local cur
47
+
local delta
48
+
local bestdelta=-1
49
+
50
+
pcieports=`grep -l -F -e "$patt" /sys/class/thermal/cooling_device*/type`
51
+
if [ -z "$pcieports" ]; then
52
+
return
53
+
fi
54
+
pcieports=${pcieports//\/type/}
55
+
# Find the port with the highest PCIe Link Speed
56
+
for port in $pcieports; do
57
+
max=`cat $port/max_state`
58
+
cur=`cat $port/cur_state`
59
+
delta=$((max-cur))
60
+
if [ $delta -gt $bestdelta ]; then
61
+
testport="$port"
62
+
bestdelta=$delta
63
+
fi
64
+
done
65
+
}
66
+
67
+
sysfspcidev=
68
+
find_sysfs_pci_dev()
69
+
{
70
+
local typefile="$1/type"
71
+
local pcidir
72
+
73
+
pcidir="$SYSFS/bus/pci/devices/`sed -e "s|^${PCIEPORTTYPE}_||g" $typefile`"
74
+
75
+
if [ -r "$pcidir/current_link_speed" ]; then
76
+
sysfspcidev="$pcidir/current_link_speed"
77
+
fi
78
+
}
79
+
80
+
usage()
81
+
{
82
+
echo "Usage $0 [ -d dev ]"
83
+
echo -e "\t-d: PCIe port BDF string (e.g., 0000:00:04.0)"
84
+
}
85
+
86
+
pattern="$PCIEPORTTYPE"
87
+
parse_arguments()
88
+
{
89
+
while getopts d:h opt; do
90
+
case $opt in
91
+
h)
92
+
usage "$0"
93
+
exit 0
94
+
;;
95
+
d)
96
+
pattern="$PCIEPORTTYPE_$OPTARG"
97
+
;;
98
+
*)
99
+
usage "$0"
100
+
exit 0
101
+
;;
102
+
esac
103
+
done
104
+
}
105
+
106
+
parse_arguments "$@"
107
+
prerequisite
108
+
find_pcie_port "$pattern"
109
+
if [ -z "$testport" ]; then
110
+
echo $skipmsg "pcie cooling device not found from sysfs" >&2
111
+
exit $ksft_skip
112
+
fi
113
+
find_sysfs_pci_dev "$testport"
114
+
if [ -z "$sysfspcidev" ]; then
115
+
echo $skipmsg "PCIe port device not found from sysfs" >&2
116
+
exit $ksft_skip
117
+
fi
118
+
119
+
./set_pcie_speed.sh "$testport" "$sysfspcidev"
120
+
retval=$?
121
+
122
+
exit $retval
+67
tools/testing/selftests/pcie_bwctrl/set_pcie_speed.sh
+67
tools/testing/selftests/pcie_bwctrl/set_pcie_speed.sh
···
1
+
#!/bin/bash
2
+
# SPDX-License-Identifier: GPL-2.0-or-later
3
+
4
+
set -e
5
+
6
+
TESTNAME=set_pcie_speed
7
+
8
+
declare -a PCIELINKSPEED=(
9
+
"2.5 GT/s PCIe"
10
+
"5.0 GT/s PCIe"
11
+
"8.0 GT/s PCIe"
12
+
"16.0 GT/s PCIe"
13
+
"32.0 GT/s PCIe"
14
+
"64.0 GT/s PCIe"
15
+
)
16
+
17
+
# Kselftest framework requirement - SKIP code is 4.
18
+
ksft_skip=4
19
+
retval=0
20
+
21
+
coolingdev="$1"
22
+
statefile="$coolingdev/cur_state"
23
+
maxfile="$coolingdev/max_state"
24
+
linkspeedfile="$2"
25
+
26
+
oldstate=`cat $statefile`
27
+
maxstate=`cat $maxfile`
28
+
29
+
set_state()
30
+
{
31
+
local state=$1
32
+
local linkspeed
33
+
local expected_linkspeed
34
+
35
+
echo $state > $statefile
36
+
37
+
sleep 1
38
+
39
+
linkspeed="`cat $linkspeedfile`"
40
+
expected_linkspeed=$((maxstate-state))
41
+
expected_str="${PCIELINKSPEED[$expected_linkspeed]}"
42
+
if [ ! "${expected_str}" = "${linkspeed}" ]; then
43
+
echo "$TESTNAME failed: expected: ${expected_str}; got ${linkspeed}"
44
+
retval=1
45
+
fi
46
+
}
47
+
48
+
cleanup_skip ()
49
+
{
50
+
set_state $oldstate
51
+
exit $ksft_skip
52
+
}
53
+
54
+
trap cleanup_skip EXIT
55
+
56
+
echo "$TESTNAME: testing states $maxstate .. $oldstate with $coolingdev"
57
+
for i in $(seq $maxstate -1 $oldstate); do
58
+
set_state "$i"
59
+
done
60
+
61
+
trap EXIT
62
+
if [ $retval -eq 0 ]; then
63
+
echo "$TESTNAME [PASS]"
64
+
else
65
+
echo "$TESTNAME [FAIL]"
66
+
fi
67
+
exit $retval