Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: fill CRTC resources in dpu_crtc.c
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
from dpu_crtc_assign_resources().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[quic_abhinavk@quicinc.com: cleaned up formatting]
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/637485/
Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-1-a44c293cf422@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+63
-37
+63
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+63
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
1230
1230
return ret;
1231
1231
}
1232
1232
1233
+
#define MAX_CHANNELS_PER_CRTC 2
1234
+
1235
+
static int dpu_crtc_assign_resources(struct drm_crtc *crtc,
1236
+
struct drm_crtc_state *crtc_state)
1237
+
{
1238
+
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC];
1239
+
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC];
1240
+
struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC];
1241
+
int i, num_lm, num_ctl, num_dspp;
1242
+
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
1243
+
struct dpu_global_state *global_state;
1244
+
struct dpu_crtc_state *cstate;
1245
+
struct drm_encoder *drm_enc;
1246
+
1247
+
/*
1248
+
* For now, grab the first encoder in the crtc state as we don't
1249
+
* support clone mode yet
1250
+
*/
1251
+
drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
1252
+
break;
1253
+
1254
+
global_state = dpu_kms_get_global_state(crtc_state->state);
1255
+
if (IS_ERR(global_state))
1256
+
return PTR_ERR(global_state);
1257
+
1258
+
if (!crtc_state->enable)
1259
+
return 0;
1260
+
1261
+
cstate = to_dpu_crtc_state(crtc_state);
1262
+
1263
+
num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1264
+
drm_enc->base.id,
1265
+
DPU_HW_BLK_CTL, hw_ctl,
1266
+
ARRAY_SIZE(hw_ctl));
1267
+
num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1268
+
drm_enc->base.id,
1269
+
DPU_HW_BLK_LM, hw_lm,
1270
+
ARRAY_SIZE(hw_lm));
1271
+
num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1272
+
drm_enc->base.id,
1273
+
DPU_HW_BLK_DSPP, hw_dspp,
1274
+
ARRAY_SIZE(hw_dspp));
1275
+
1276
+
for (i = 0; i < num_lm; i++) {
1277
+
int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1278
+
1279
+
cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1280
+
cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1281
+
if (i < num_dspp)
1282
+
cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1283
+
}
1284
+
1285
+
cstate->num_mixers = num_lm;
1286
+
1287
+
return 0;
1288
+
}
1289
+
1233
1290
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
1234
1291
struct drm_atomic_state *state)
1235
1292
{
···
1301
1244
int rc = 0;
1302
1245
1303
1246
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
1247
+
1248
+
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
1249
+
rc = dpu_crtc_assign_resources(crtc, crtc_state);
1250
+
if (rc < 0)
1251
+
return rc;
1252
+
}
1304
1253
1305
1254
if (dpu_use_virtual_planes &&
1306
1255
(crtc_state->planes_changed || crtc_state->zpos_changed)) {
-37
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
-37
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
726
726
return topology;
727
727
}
728
728
729
-
static void dpu_encoder_assign_crtc_resources(struct dpu_kms *dpu_kms,
730
-
struct drm_encoder *drm_enc,
731
-
struct dpu_global_state *global_state,
732
-
struct drm_crtc_state *crtc_state)
733
-
{
734
-
struct dpu_crtc_state *cstate;
735
-
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
736
-
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
737
-
struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC];
738
-
int num_lm, num_ctl, num_dspp, i;
739
-
740
-
cstate = to_dpu_crtc_state(crtc_state);
741
-
742
-
memset(cstate->mixers, 0, sizeof(cstate->mixers));
743
-
744
-
num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
745
-
drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
746
-
num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
747
-
drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
748
-
num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
749
-
drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
750
-
ARRAY_SIZE(hw_dspp));
751
-
752
-
for (i = 0; i < num_lm; i++) {
753
-
int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
754
-
755
-
cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
756
-
cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
757
-
cstate->mixers[i].hw_dspp = i < num_dspp ? to_dpu_hw_dspp(hw_dspp[i]) : NULL;
758
-
}
759
-
760
-
cstate->num_mixers = num_lm;
761
-
}
762
-
763
729
/**
764
730
* dpu_encoder_virt_check_mode_changed: check if full modeset is required
765
731
* @drm_enc: Pointer to drm encoder structure
···
796
830
if (crtc_state->enable)
797
831
ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
798
832
drm_enc, crtc_state, &topology);
799
-
if (!ret)
800
-
dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc,
801
-
global_state, crtc_state);
802
833
}
803
834
804
835
trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);