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clk: qcom: ipq5332: drop the mem noc clocks

Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. So drop these clocks from the GCC driver.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230710102807.1189942-2-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Kathiravan T and committed by
Bjorn Andersson 1784d031 a6f1e862

-95
-95
drivers/clk/qcom/gcc-ipq5332.c
··· 1635 1635 }, 1636 1636 }; 1637 1637 1638 - static struct clk_branch gcc_mem_noc_q6_axi_clk = { 1639 - .halt_reg = 0x19010, 1640 - .halt_check = BRANCH_HALT, 1641 - .clkr = { 1642 - .enable_reg = 0x19010, 1643 - .enable_mask = BIT(0), 1644 - .hw.init = &(const struct clk_init_data) { 1645 - .name = "gcc_mem_noc_q6_axi_clk", 1646 - .parent_hws = (const struct clk_hw*[]) { 1647 - &gcc_q6_axim_clk_src.clkr.hw, 1648 - }, 1649 - .num_parents = 1, 1650 - .flags = CLK_SET_RATE_PARENT, 1651 - .ops = &clk_branch2_ops, 1652 - }, 1653 - }, 1654 - }; 1655 - 1656 - static struct clk_branch gcc_mem_noc_ts_clk = { 1657 - .halt_reg = 0x19028, 1658 - .halt_check = BRANCH_HALT_VOTED, 1659 - .clkr = { 1660 - .enable_reg = 0x19028, 1661 - .enable_mask = BIT(0), 1662 - .hw.init = &(const struct clk_init_data) { 1663 - .name = "gcc_mem_noc_ts_clk", 1664 - .parent_hws = (const struct clk_hw*[]) { 1665 - &gcc_qdss_tsctr_div8_clk_src.hw, 1666 - }, 1667 - .num_parents = 1, 1668 - .flags = CLK_SET_RATE_PARENT, 1669 - .ops = &clk_branch2_ops, 1670 - }, 1671 - }, 1672 - }; 1673 - 1674 1638 static struct clk_branch gcc_nss_ts_clk = { 1675 1639 .halt_reg = 0x17018, 1676 1640 .halt_check = BRANCH_HALT_VOTED, ··· 3303 3339 }, 3304 3340 }; 3305 3341 3306 - static struct clk_branch gcc_mem_noc_ahb_clk = { 3307 - .halt_reg = 0x1900c, 3308 - .halt_check = BRANCH_HALT, 3309 - .clkr = { 3310 - .enable_reg = 0x1900c, 3311 - .enable_mask = BIT(0), 3312 - .hw.init = &(const struct clk_init_data) { 3313 - .name = "gcc_mem_noc_ahb_clk", 3314 - .parent_hws = (const struct clk_hw*[]) { 3315 - &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 3316 - }, 3317 - .num_parents = 1, 3318 - .flags = CLK_SET_RATE_PARENT, 3319 - .ops = &clk_branch2_ops, 3320 - }, 3321 - }, 3322 - }; 3323 - 3324 - static struct clk_branch gcc_mem_noc_apss_axi_clk = { 3325 - .halt_reg = 0x1901c, 3326 - .halt_check = BRANCH_HALT_VOTED, 3327 - .clkr = { 3328 - .enable_reg = 0xb004, 3329 - .enable_mask = BIT(6), 3330 - .hw.init = &(const struct clk_init_data) { 3331 - .name = "gcc_mem_noc_apss_axi_clk", 3332 - .parent_hws = (const struct clk_hw*[]) { 3333 - &gcc_apss_axi_clk_src.clkr.hw, 3334 - }, 3335 - .num_parents = 1, 3336 - .flags = CLK_SET_RATE_PARENT, 3337 - .ops = &clk_branch2_ops, 3338 - }, 3339 - }, 3340 - }; 3341 - 3342 3342 static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = { 3343 3343 .reg = 0x2e010, 3344 3344 .shift = 0, ··· 3315 3387 .num_parents = 1, 3316 3388 .flags = CLK_SET_RATE_PARENT, 3317 3389 .ops = &clk_regmap_div_ro_ops, 3318 - }, 3319 - }; 3320 - 3321 - static struct clk_branch gcc_mem_noc_qosgen_extref_clk = { 3322 - .halt_reg = 0x19024, 3323 - .halt_check = BRANCH_HALT, 3324 - .clkr = { 3325 - .enable_reg = 0x19024, 3326 - .enable_mask = BIT(0), 3327 - .hw.init = &(const struct clk_init_data) { 3328 - .name = "gcc_mem_noc_qosgen_extref_clk", 3329 - .parent_hws = (const struct clk_hw*[]) { 3330 - &gcc_snoc_qosgen_extref_div_clk_src.clkr.hw, 3331 - }, 3332 - .num_parents = 1, 3333 - .flags = CLK_SET_RATE_PARENT, 3334 - .ops = &clk_branch2_ops, 3335 - }, 3336 3390 }, 3337 3391 }; 3338 3392 ··· 3361 3451 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr, 3362 3452 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 3363 3453 [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr, 3364 - [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, 3365 - [GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr, 3366 3454 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 3367 3455 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, 3368 3456 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, ··· 3481 3573 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, 3482 3574 [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr, 3483 3575 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 3484 - [GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr, 3485 - [GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr, 3486 3576 [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr, 3487 - [GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr, 3488 3577 [GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr, 3489 3578 [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, 3490 3579 [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,