tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'x86_urgent_for_v5.11_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Borislav Petkov:

- Add a new Intel model number for Alder Lake

- Differentiate which aspects of the FPU state get saved/restored when
the FPU is used in-kernel and fix a boot crash on K7 due to early
MXCSR access before CR4.OSFXSR is even set.

- A couple of noinstr annotation fixes

- Correct die ID setting on AMD for users of topology information which
need the correct die ID

- A SEV-ES fix to handle string port IO to/from kernel memory properly

* tag 'x86_urgent_for_v5.11_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/cpu: Add another Alder Lake CPU to the Intel family
x86/mmx: Use KFPU_387 for MMX string operations
x86/fpu: Add kernel_fpu_begin_mask() to selectively initialize state
x86/topology: Make __max_die_per_package available unconditionally
x86: __always_inline __{rd,wr}msr()
x86/mce: Remove explicit/superfluous tracing
locking/lockdep: Avoid noinstr warning for DEBUG_LOCKDEP
locking/lockdep: Cure noinstr fail
x86/sev: Fix nonistr violation
x86/entry: Fix noinstr fail
x86/cpu/amd: Set __max_die_per_package on AMD
x86/sev-es: Handle string port IO to kernel memory properly

Linus Torvalds 17b6c49d 14c50a66

+72 -27
+7 -3
arch/x86/entry/common.c
··· 73 73 unsigned int nr) 74 74 { 75 75 if (likely(nr < IA32_NR_syscalls)) { 76 - instrumentation_begin(); 77 76 nr = array_index_nospec(nr, IA32_NR_syscalls); 78 77 regs->ax = ia32_sys_call_table[nr](regs); 79 - instrumentation_end(); 80 78 } 81 79 } 82 80 ··· 89 91 * or may not be necessary, but it matches the old asm behavior. 90 92 */ 91 93 nr = (unsigned int)syscall_enter_from_user_mode(regs, nr); 94 + instrumentation_begin(); 92 95 93 96 do_syscall_32_irqs_on(regs, nr); 97 + 98 + instrumentation_end(); 94 99 syscall_exit_to_user_mode(regs); 95 100 } 96 101 ··· 122 121 res = get_user(*(u32 *)&regs->bp, 123 122 (u32 __user __force *)(unsigned long)(u32)regs->sp); 124 123 } 125 - instrumentation_end(); 126 124 127 125 if (res) { 128 126 /* User code screwed up. */ 129 127 regs->ax = -EFAULT; 128 + 129 + instrumentation_end(); 130 130 syscall_exit_to_user_mode(regs); 131 131 return false; 132 132 } ··· 137 135 138 136 /* Now this is just like a normal syscall. */ 139 137 do_syscall_32_irqs_on(regs, nr); 138 + 139 + instrumentation_end(); 140 140 syscall_exit_to_user_mode(regs); 141 141 return true; 142 142 }
+13 -2
arch/x86/include/asm/fpu/api.h
··· 16 16 * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It 17 17 * disables preemption so be careful if you intend to use it for long periods 18 18 * of time. 19 - * If you intend to use the FPU in softirq you need to check first with 19 + * If you intend to use the FPU in irq/softirq you need to check first with 20 20 * irq_fpu_usable() if it is possible. 21 21 */ 22 - extern void kernel_fpu_begin(void); 22 + 23 + /* Kernel FPU states to initialize in kernel_fpu_begin_mask() */ 24 + #define KFPU_387 _BITUL(0) /* 387 state will be initialized */ 25 + #define KFPU_MXCSR _BITUL(1) /* MXCSR will be initialized */ 26 + 27 + extern void kernel_fpu_begin_mask(unsigned int kfpu_mask); 23 28 extern void kernel_fpu_end(void); 24 29 extern bool irq_fpu_usable(void); 25 30 extern void fpregs_mark_activate(void); 31 + 32 + /* Code that is unaware of kernel_fpu_begin_mask() can use this */ 33 + static inline void kernel_fpu_begin(void) 34 + { 35 + kernel_fpu_begin_mask(KFPU_387 | KFPU_MXCSR); 36 + } 26 37 27 38 /* 28 39 * Use fpregs_lock() while editing CPU's FPU registers or fpu->state.
+1
arch/x86/include/asm/intel-family.h
··· 97 97 98 98 #define INTEL_FAM6_LAKEFIELD 0x8A 99 99 #define INTEL_FAM6_ALDERLAKE 0x97 100 + #define INTEL_FAM6_ALDERLAKE_L 0x9A 100 101 101 102 /* "Small Core" Processors (Atom) */ 102 103
+2 -2
arch/x86/include/asm/msr.h
··· 86 86 * think of extending them - you will be slapped with a stinking trout or a frozen 87 87 * shark will reach you, wherever you are! You've been warned. 88 88 */ 89 - static inline unsigned long long notrace __rdmsr(unsigned int msr) 89 + static __always_inline unsigned long long __rdmsr(unsigned int msr) 90 90 { 91 91 DECLARE_ARGS(val, low, high); 92 92 ··· 98 98 return EAX_EDX_VAL(val, low, high); 99 99 } 100 100 101 - static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high) 101 + static __always_inline void __wrmsr(unsigned int msr, u32 low, u32 high) 102 102 { 103 103 asm volatile("1: wrmsr\n" 104 104 "2:\n"
+2 -2
arch/x86/include/asm/topology.h
··· 110 110 #define topology_die_id(cpu) (cpu_data(cpu).cpu_die_id) 111 111 #define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) 112 112 113 + extern unsigned int __max_die_per_package; 114 + 113 115 #ifdef CONFIG_SMP 114 116 #define topology_die_cpumask(cpu) (per_cpu(cpu_die_map, cpu)) 115 117 #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) ··· 119 117 120 118 extern unsigned int __max_logical_packages; 121 119 #define topology_max_packages() (__max_logical_packages) 122 - 123 - extern unsigned int __max_die_per_package; 124 120 125 121 static inline int topology_max_die_per_package(void) 126 122 {
+2 -2
arch/x86/kernel/cpu/amd.c
··· 542 542 u32 ecx; 543 543 544 544 ecx = cpuid_ecx(0x8000001e); 545 - nodes_per_socket = ((ecx >> 8) & 7) + 1; 545 + __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1; 546 546 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 547 547 u64 value; 548 548 549 549 rdmsrl(MSR_FAM10H_NODE_ID, value); 550 - nodes_per_socket = ((value >> 3) & 7) + 1; 550 + __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1; 551 551 } 552 552 553 553 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
+4 -3
arch/x86/kernel/cpu/mce/core.c
··· 1992 1992 * that out because it's an indirect call. Annotate it. 1993 1993 */ 1994 1994 instrumentation_begin(); 1995 - trace_hardirqs_off_finish(); 1995 + 1996 1996 machine_check_vector(regs); 1997 - if (regs->flags & X86_EFLAGS_IF) 1998 - trace_hardirqs_on_prepare(); 1997 + 1999 1998 instrumentation_end(); 2000 1999 irqentry_nmi_exit(regs, irq_state); 2001 2000 } ··· 2003 2004 { 2004 2005 irqentry_enter_from_user_mode(regs); 2005 2006 instrumentation_begin(); 2007 + 2006 2008 machine_check_vector(regs); 2009 + 2007 2010 instrumentation_end(); 2008 2011 irqentry_exit_to_user_mode(regs); 2009 2012 }
+1 -1
arch/x86/kernel/cpu/topology.c
··· 25 25 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 26 26 #define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) 27 27 28 - #ifdef CONFIG_SMP 29 28 unsigned int __max_die_per_package __read_mostly = 1; 30 29 EXPORT_SYMBOL(__max_die_per_package); 31 30 31 + #ifdef CONFIG_SMP 32 32 /* 33 33 * Check if given CPUID extended toplogy "leaf" is implemented 34 34 */
+5 -4
arch/x86/kernel/fpu/core.c
··· 121 121 } 122 122 EXPORT_SYMBOL(copy_fpregs_to_fpstate); 123 123 124 - void kernel_fpu_begin(void) 124 + void kernel_fpu_begin_mask(unsigned int kfpu_mask) 125 125 { 126 126 preempt_disable(); 127 127 ··· 141 141 } 142 142 __cpu_invalidate_fpregs_state(); 143 143 144 - if (boot_cpu_has(X86_FEATURE_XMM)) 144 + /* Put sane initial values into the control registers. */ 145 + if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM)) 145 146 ldmxcsr(MXCSR_DEFAULT); 146 147 147 - if (boot_cpu_has(X86_FEATURE_FPU)) 148 + if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU)) 148 149 asm volatile ("fninit"); 149 150 } 150 - EXPORT_SYMBOL_GPL(kernel_fpu_begin); 151 + EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask); 151 152 152 153 void kernel_fpu_end(void) 153 154 {
+13 -1
arch/x86/kernel/sev-es.c
··· 225 225 return __rdmsr(MSR_AMD64_SEV_ES_GHCB); 226 226 } 227 227 228 - static inline void sev_es_wr_ghcb_msr(u64 val) 228 + static __always_inline void sev_es_wr_ghcb_msr(u64 val) 229 229 { 230 230 u32 low, high; 231 231 ··· 286 286 u16 d2; 287 287 u8 d1; 288 288 289 + /* If instruction ran in kernel mode and the I/O buffer is in kernel space */ 290 + if (!user_mode(ctxt->regs) && !access_ok(target, size)) { 291 + memcpy(dst, buf, size); 292 + return ES_OK; 293 + } 294 + 289 295 switch (size) { 290 296 case 1: 291 297 memcpy(&d1, buf, 1); ··· 340 334 u32 d4; 341 335 u16 d2; 342 336 u8 d1; 337 + 338 + /* If instruction ran in kernel mode and the I/O buffer is in kernel space */ 339 + if (!user_mode(ctxt->regs) && !access_ok(s, size)) { 340 + memcpy(buf, src, size); 341 + return ES_OK; 342 + } 343 343 344 344 switch (size) { 345 345 case 1:
+15 -5
arch/x86/lib/mmx_32.c
··· 26 26 #include <asm/fpu/api.h> 27 27 #include <asm/asm.h> 28 28 29 + /* 30 + * Use KFPU_387. MMX instructions are not affected by MXCSR, 31 + * but both AMD and Intel documentation states that even integer MMX 32 + * operations will result in #MF if an exception is pending in FCW. 33 + * 34 + * EMMS is not needed afterwards because, after calling kernel_fpu_end(), 35 + * any subsequent user of the 387 stack will reinitialize it using 36 + * KFPU_387. 37 + */ 38 + 29 39 void *_mmx_memcpy(void *to, const void *from, size_t len) 30 40 { 31 41 void *p; ··· 47 37 p = to; 48 38 i = len >> 6; /* len/64 */ 49 39 50 - kernel_fpu_begin(); 40 + kernel_fpu_begin_mask(KFPU_387); 51 41 52 42 __asm__ __volatile__ ( 53 43 "1: prefetch (%0)\n" /* This set is 28 bytes */ ··· 137 127 { 138 128 int i; 139 129 140 - kernel_fpu_begin(); 130 + kernel_fpu_begin_mask(KFPU_387); 141 131 142 132 __asm__ __volatile__ ( 143 133 " pxor %%mm0, %%mm0\n" : : ··· 170 160 { 171 161 int i; 172 162 173 - kernel_fpu_begin(); 163 + kernel_fpu_begin_mask(KFPU_387); 174 164 175 165 /* 176 166 * maybe the prefetch stuff can go before the expensive fnsave... ··· 257 247 { 258 248 int i; 259 249 260 - kernel_fpu_begin(); 250 + kernel_fpu_begin_mask(KFPU_387); 261 251 262 252 __asm__ __volatile__ ( 263 253 " pxor %%mm0, %%mm0\n" : : ··· 292 282 { 293 283 int i; 294 284 295 - kernel_fpu_begin(); 285 + kernel_fpu_begin_mask(KFPU_387); 296 286 297 287 __asm__ __volatile__ ( 298 288 "1: prefetch (%0)\n"
+7 -2
kernel/locking/lockdep.c
··· 79 79 DEFINE_PER_CPU(unsigned int, lockdep_recursion); 80 80 EXPORT_PER_CPU_SYMBOL_GPL(lockdep_recursion); 81 81 82 - static inline bool lockdep_enabled(void) 82 + static __always_inline bool lockdep_enabled(void) 83 83 { 84 84 if (!debug_locks) 85 85 return false; ··· 5271 5271 /* 5272 5272 * Check whether we follow the irq-flags state precisely: 5273 5273 */ 5274 - static void check_flags(unsigned long flags) 5274 + static noinstr void check_flags(unsigned long flags) 5275 5275 { 5276 5276 #if defined(CONFIG_PROVE_LOCKING) && defined(CONFIG_DEBUG_LOCKDEP) 5277 5277 if (!debug_locks) 5278 5278 return; 5279 + 5280 + /* Get the warning out.. */ 5281 + instrumentation_begin(); 5279 5282 5280 5283 if (irqs_disabled_flags(flags)) { 5281 5284 if (DEBUG_LOCKS_WARN_ON(lockdep_hardirqs_enabled())) { ··· 5307 5304 5308 5305 if (!debug_locks) 5309 5306 print_irqtrace_events(current); 5307 + 5308 + instrumentation_end(); 5310 5309 #endif 5311 5310 } 5312 5311