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media: qcom: camss: Add support for regulator init_load_uA in CSIPHY

Some Qualcomm regulators are configured with initial mode as
HPM (High Power Mode), which may lead to higher power consumption.
To reduce power usage, it's preferable to set the initial mode
to LPM (Low Power Mode).

To ensure the regulator can switch from LPM to HPM when needed,
this patch adds current load configuration for CAMSS CSIPHY.
This allows the regulator framework to scale the mode dynamically
based on the load requirement.

The current default value for current is uninitialized or random.
To address this, initial current values are added for the
following platforms:
MSM8916, MSM8939, MSM8953, MSM8996, QCM2290, SDM670, SM8250, SC7280,
SM8550, SM8650, QCS8300, SA8775P and X1E80100.

For SDM660, SDM845, SC8280XP the value is set to 0,
indicating that no default current value is configured,
the other values are derived from the power grid.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

authored by

Wenmeng Liu and committed by
Hans Verkuil 17bc0e28 26efe43f

+265 -102
+3 -15
drivers/media/platform/qcom/camss/camss-csid.c
··· 1187 1187 1188 1188 /* Regulator */ 1189 1189 for (i = 0; i < ARRAY_SIZE(res->regulators); i++) { 1190 - if (res->regulators[i]) 1190 + if (res->regulators[i].supply) 1191 1191 csid->num_supplies++; 1192 1192 } 1193 1193 1194 - if (csid->num_supplies) { 1195 - csid->supplies = devm_kmalloc_array(camss->dev, 1196 - csid->num_supplies, 1197 - sizeof(*csid->supplies), 1198 - GFP_KERNEL); 1199 - if (!csid->supplies) 1200 - return -ENOMEM; 1201 - } 1202 - 1203 - for (i = 0; i < csid->num_supplies; i++) 1204 - csid->supplies[i].supply = res->regulators[i]; 1205 - 1206 - ret = devm_regulator_bulk_get(camss->dev, csid->num_supplies, 1207 - csid->supplies); 1194 + ret = devm_regulator_bulk_get_const(camss->dev, csid->num_supplies, 1195 + res->regulators, &csid->supplies); 1208 1196 if (ret) 1209 1197 return ret; 1210 1198
+4 -15
drivers/media/platform/qcom/camss/camss-csiphy.c
··· 695 695 696 696 /* CSIPHY supplies */ 697 697 for (i = 0; i < ARRAY_SIZE(res->regulators); i++) { 698 - if (res->regulators[i]) 698 + if (res->regulators[i].supply) 699 699 csiphy->num_supplies++; 700 700 } 701 701 702 - if (csiphy->num_supplies) { 703 - csiphy->supplies = devm_kmalloc_array(camss->dev, 704 - csiphy->num_supplies, 705 - sizeof(*csiphy->supplies), 706 - GFP_KERNEL); 707 - if (!csiphy->supplies) 708 - return -ENOMEM; 709 - } 710 - 711 - for (i = 0; i < csiphy->num_supplies; i++) 712 - csiphy->supplies[i].supply = res->regulators[i]; 713 - 714 - ret = devm_regulator_bulk_get(camss->dev, csiphy->num_supplies, 715 - csiphy->supplies); 702 + if (csiphy->num_supplies > 0) 703 + ret = devm_regulator_bulk_get_const(camss->dev, csiphy->num_supplies, 704 + res->regulators, &csiphy->supplies); 716 705 return ret; 717 706 } 718 707
+257 -71
drivers/media/platform/qcom/camss/camss.c
··· 73 73 static const struct camss_subdev_resources csid_res_8x16[] = { 74 74 /* CSID0 */ 75 75 { 76 - .regulators = { "vdda" }, 76 + .regulators = { 77 + { .supply = "vdda", .init_load_uA = 40000 } 78 + }, 77 79 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 78 80 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 79 81 .clock_rate = { { 0 }, ··· 97 95 98 96 /* CSID1 */ 99 97 { 100 - .regulators = { "vdda" }, 98 + .regulators = { 99 + { .supply = "vdda", .init_load_uA = 40000 } 100 + }, 101 101 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 102 102 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 103 103 .clock_rate = { { 0 }, ··· 161 157 static const struct camss_subdev_resources csiphy_res_8x39[] = { 162 158 /* CSIPHY0 */ 163 159 { 164 - .regulators = { "vdda" }, 160 + .regulators = { 161 + { .supply = "vdda", .init_load_uA = 40000 } 162 + }, 165 163 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 166 164 .clock_rate = { { 0 }, 167 165 { 40000000, 80000000 }, ··· 180 174 181 175 /* CSIPHY1 */ 182 176 { 183 - .regulators = { "vdda" }, 177 + .regulators = { 178 + { .supply = "vdda", .init_load_uA = 40000 } 179 + }, 184 180 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 185 181 .clock_rate = { { 0 }, 186 182 { 40000000, 80000000 }, ··· 308 300 static const struct camss_subdev_resources csid_res_8x53[] = { 309 301 /* CSID0 */ 310 302 { 311 - .regulators = { "vdda" }, 303 + .regulators = { 304 + { .supply = "vdda", .init_load_uA = 9900 } 305 + }, 312 306 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 313 307 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 314 308 .clock_rate = { { 0 }, ··· 333 323 334 324 /* CSID1 */ 335 325 { 336 - .regulators = { "vdda" }, 326 + .regulators = { 327 + { .supply = "vdda", .init_load_uA = 9900 } 328 + }, 337 329 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 338 330 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 339 331 .clock_rate = { { 0 }, ··· 358 346 359 347 /* CSID2 */ 360 348 { 361 - .regulators = { "vdda" }, 349 + .regulators = { 350 + { .supply = "vdda", .init_load_uA = 9900 } 351 + }, 362 352 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 363 353 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, 364 354 .clock_rate = { { 0 }, ··· 521 507 static const struct camss_subdev_resources csid_res_8x96[] = { 522 508 /* CSID0 */ 523 509 { 524 - .regulators = { "vdda" }, 510 + .regulators = { 511 + { .supply = "vdda", .init_load_uA = 80160 } 512 + }, 525 513 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 526 514 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 527 515 .clock_rate = { { 0 }, ··· 545 529 546 530 /* CSID1 */ 547 531 { 548 - .regulators = { "vdda" }, 532 + .regulators = { 533 + { .supply = "vdda", .init_load_uA = 80160 } 534 + }, 549 535 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 550 536 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 551 537 .clock_rate = { { 0 }, ··· 569 551 570 552 /* CSID2 */ 571 553 { 572 - .regulators = { "vdda" }, 554 + .regulators = { 555 + { .supply = "vdda", .init_load_uA = 80160 } 556 + }, 573 557 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 574 558 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, 575 559 .clock_rate = { { 0 }, ··· 593 573 594 574 /* CSID3 */ 595 575 { 596 - .regulators = { "vdda" }, 576 + .regulators = { 577 + { .supply = "vdda", .init_load_uA = 80160 } 578 + }, 597 579 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 598 580 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" }, 599 581 .clock_rate = { { 0 }, ··· 683 661 static const struct camss_subdev_resources csiphy_res_2290[] = { 684 662 /* CSIPHY0 */ 685 663 { 686 - .regulators = { "vdd-csiphy-1p2", "vdd-csiphy-1p8" }, 664 + .regulators = { 665 + { .supply = "vdd-csiphy-1p2", .init_load_uA = 26700 }, 666 + { .supply = "vdd-csiphy-1p8", .init_load_uA = 2600 } 667 + }, 687 668 .clock = { "top_ahb", "ahb", "csiphy0", "csiphy0_timer" }, 688 669 .clock_rate = { { 0 }, 689 670 { 0 }, ··· 703 678 704 679 /* CSIPHY1 */ 705 680 { 706 - .regulators = { "vdd-csiphy-1p2", "vdd-csiphy-1p8" }, 681 + .regulators = { 682 + { .supply = "vdd-csiphy-1p2", .init_load_uA = 26700 }, 683 + { .supply = "vdd-csiphy-1p8", .init_load_uA = 2600 } 684 + }, 707 685 .clock = { "top_ahb", "ahb", "csiphy1", "csiphy1_timer" }, 708 686 .clock_rate = { { 0 }, 709 687 { 0 }, ··· 882 854 static const struct camss_subdev_resources csid_res_660[] = { 883 855 /* CSID0 */ 884 856 { 885 - .regulators = { "vdda", "vdd_sec" }, 857 + .regulators = { 858 + { .supply = "vdda", .init_load_uA = 0 }, 859 + { .supply = "vdd_sec", .init_load_uA = 0 } 860 + }, 886 861 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 887 862 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", 888 863 "cphy_csid0" }, ··· 910 879 911 880 /* CSID1 */ 912 881 { 913 - .regulators = { "vdda", "vdd_sec" }, 882 + .regulators = { 883 + { .supply = "vdda", .init_load_uA = 0 }, 884 + { .supply = "vdd_sec", .init_load_uA = 0 } 885 + }, 914 886 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 915 887 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", 916 888 "cphy_csid1" }, ··· 938 904 939 905 /* CSID2 */ 940 906 { 941 - .regulators = { "vdda", "vdd_sec" }, 907 + .regulators = { 908 + { .supply = "vdda", .init_load_uA = 0 }, 909 + { .supply = "vdd_sec", .init_load_uA = 0 } 910 + }, 942 911 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 943 912 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", 944 913 "cphy_csid2" }, ··· 966 929 967 930 /* CSID3 */ 968 931 { 969 - .regulators = { "vdda", "vdd_sec" }, 932 + .regulators = { 933 + { .supply = "vdda", .init_load_uA = 0 }, 934 + { .supply = "vdd_sec", .init_load_uA = 0 } 935 + }, 970 936 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 971 937 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", 972 938 "cphy_csid3" }, ··· 1066 1026 static const struct camss_subdev_resources csiphy_res_670[] = { 1067 1027 /* CSIPHY0 */ 1068 1028 { 1069 - .regulators = { "vdda-phy", "vdda-pll" }, 1029 + .regulators = { 1030 + { .supply = "vdda-phy", .init_load_uA = 42800 }, 1031 + { .supply = "vdda-pll", .init_load_uA = 13900 } 1032 + }, 1070 1033 .clock = { "soc_ahb", "cpas_ahb", 1071 1034 "csiphy0", "csiphy0_timer" }, 1072 1035 .clock_rate = { { 0 }, ··· 1087 1044 1088 1045 /* CSIPHY1 */ 1089 1046 { 1090 - .regulators = { "vdda-phy", "vdda-pll" }, 1047 + .regulators = { 1048 + { .supply = "vdda-phy", .init_load_uA = 42800 }, 1049 + { .supply = "vdda-pll", .init_load_uA = 13900 } 1050 + }, 1091 1051 .clock = { "soc_ahb", "cpas_ahb", 1092 1052 "csiphy1", "csiphy1_timer" }, 1093 1053 .clock_rate = { { 0 }, ··· 1108 1062 1109 1063 /* CSIPHY2 */ 1110 1064 { 1111 - .regulators = { "vdda-phy", "vdda-pll" }, 1065 + .regulators = { 1066 + { .supply = "vdda-phy", .init_load_uA = 42800 }, 1067 + { .supply = "vdda-pll", .init_load_uA = 13900 } 1068 + }, 1112 1069 .clock = { "soc_ahb", "cpas_ahb", 1113 1070 "csiphy2", "csiphy2_timer" }, 1114 1071 .clock_rate = { { 0 }, ··· 1351 1302 static const struct camss_subdev_resources csid_res_845[] = { 1352 1303 /* CSID0 */ 1353 1304 { 1354 - .regulators = { "vdda-phy", "vdda-pll" }, 1305 + .regulators = { 1306 + { .supply = "vdda-phy", .init_load_uA = 0 }, 1307 + { .supply = "vdda-pll", .init_load_uA = 0 } 1308 + }, 1355 1309 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 1356 1310 "soc_ahb", "vfe0", "vfe0_src", 1357 1311 "vfe0_cphy_rx", "csi0", ··· 1379 1327 1380 1328 /* CSID1 */ 1381 1329 { 1382 - .regulators = { "vdda-phy", "vdda-pll" }, 1330 + .regulators = { 1331 + { .supply = "vdda-phy", .init_load_uA = 0 }, 1332 + { .supply = "vdda-pll", .init_load_uA = 0 } 1333 + }, 1383 1334 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 1384 1335 "soc_ahb", "vfe1", "vfe1_src", 1385 1336 "vfe1_cphy_rx", "csi1", ··· 1407 1352 1408 1353 /* CSID2 */ 1409 1354 { 1410 - .regulators = { "vdda-phy", "vdda-pll" }, 1355 + .regulators = { 1356 + { .supply = "vdda-phy", .init_load_uA = 0 }, 1357 + { .supply = "vdda-pll", .init_load_uA = 0 } 1358 + }, 1411 1359 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 1412 1360 "soc_ahb", "vfe_lite", "vfe_lite_src", 1413 1361 "vfe_lite_cphy_rx", "csi2", ··· 1522 1464 static const struct camss_subdev_resources csiphy_res_8250[] = { 1523 1465 /* CSIPHY0 */ 1524 1466 { 1525 - .regulators = { "vdda-phy", "vdda-pll" }, 1467 + .regulators = { 1468 + { .supply = "vdda-phy", .init_load_uA = 17500 }, 1469 + { .supply = "vdda-pll", .init_load_uA = 10000 } 1470 + }, 1526 1471 .clock = { "csiphy0", "csiphy0_timer" }, 1527 1472 .clock_rate = { { 400000000 }, 1528 1473 { 300000000 } }, ··· 1539 1478 }, 1540 1479 /* CSIPHY1 */ 1541 1480 { 1542 - .regulators = { "vdda-phy", "vdda-pll" }, 1481 + .regulators = { 1482 + { .supply = "vdda-phy", .init_load_uA = 17500 }, 1483 + { .supply = "vdda-pll", .init_load_uA = 10000 } 1484 + }, 1543 1485 .clock = { "csiphy1", "csiphy1_timer" }, 1544 1486 .clock_rate = { { 400000000 }, 1545 1487 { 300000000 } }, ··· 1556 1492 }, 1557 1493 /* CSIPHY2 */ 1558 1494 { 1559 - .regulators = { "vdda-phy", "vdda-pll" }, 1495 + .regulators = { 1496 + { .supply = "vdda-phy", .init_load_uA = 17500 }, 1497 + { .supply = "vdda-pll", .init_load_uA = 10000 } 1498 + }, 1560 1499 .clock = { "csiphy2", "csiphy2_timer" }, 1561 1500 .clock_rate = { { 400000000 }, 1562 1501 { 300000000 } }, ··· 1573 1506 }, 1574 1507 /* CSIPHY3 */ 1575 1508 { 1576 - .regulators = { "vdda-phy", "vdda-pll" }, 1509 + .regulators = { 1510 + { .supply = "vdda-phy", .init_load_uA = 17500 }, 1511 + { .supply = "vdda-pll", .init_load_uA = 10000 } 1512 + }, 1577 1513 .clock = { "csiphy3", "csiphy3_timer" }, 1578 1514 .clock_rate = { { 400000000 }, 1579 1515 { 300000000 } }, ··· 1590 1520 }, 1591 1521 /* CSIPHY4 */ 1592 1522 { 1593 - .regulators = { "vdda-phy", "vdda-pll" }, 1523 + .regulators = { 1524 + { .supply = "vdda-phy", .init_load_uA = 17500 }, 1525 + { .supply = "vdda-pll", .init_load_uA = 10000 } 1526 + }, 1594 1527 .clock = { "csiphy4", "csiphy4_timer" }, 1595 1528 .clock_rate = { { 400000000 }, 1596 1529 { 300000000 } }, ··· 1607 1534 }, 1608 1535 /* CSIPHY5 */ 1609 1536 { 1610 - .regulators = { "vdda-phy", "vdda-pll" }, 1537 + .regulators = { 1538 + { .supply = "vdda-phy", .init_load_uA = 17500 }, 1539 + { .supply = "vdda-pll", .init_load_uA = 10000 } 1540 + }, 1611 1541 .clock = { "csiphy5", "csiphy5_timer" }, 1612 1542 .clock_rate = { { 400000000 }, 1613 1543 { 300000000 } }, ··· 1824 1748 static const struct camss_subdev_resources csiphy_res_7280[] = { 1825 1749 /* CSIPHY0 */ 1826 1750 { 1827 - .regulators = { "vdda-phy", "vdda-pll" }, 1751 + .regulators = { 1752 + { .supply = "vdda-phy", .init_load_uA = 16100 }, 1753 + { .supply = "vdda-pll", .init_load_uA = 9000 } 1754 + }, 1828 1755 1829 1756 .clock = { "csiphy0", "csiphy0_timer" }, 1830 1757 .clock_rate = { { 300000000, 400000000 }, ··· 1842 1763 }, 1843 1764 /* CSIPHY1 */ 1844 1765 { 1845 - .regulators = { "vdda-phy", "vdda-pll" }, 1766 + .regulators = { 1767 + { .supply = "vdda-phy", .init_load_uA = 16100 }, 1768 + { .supply = "vdda-pll", .init_load_uA = 9000 } 1769 + }, 1846 1770 1847 1771 .clock = { "csiphy1", "csiphy1_timer" }, 1848 1772 .clock_rate = { { 300000000, 400000000 }, ··· 1860 1778 }, 1861 1779 /* CSIPHY2 */ 1862 1780 { 1863 - .regulators = { "vdda-phy", "vdda-pll" }, 1781 + .regulators = { 1782 + { .supply = "vdda-phy", .init_load_uA = 16100 }, 1783 + { .supply = "vdda-pll", .init_load_uA = 9000 } 1784 + }, 1864 1785 1865 1786 .clock = { "csiphy2", "csiphy2_timer" }, 1866 1787 .clock_rate = { { 300000000, 400000000 }, ··· 1878 1793 }, 1879 1794 /* CSIPHY3 */ 1880 1795 { 1881 - .regulators = { "vdda-phy", "vdda-pll" }, 1796 + .regulators = { 1797 + { .supply = "vdda-phy", .init_load_uA = 16100 }, 1798 + { .supply = "vdda-pll", .init_load_uA = 9000 } 1799 + }, 1882 1800 1883 1801 .clock = { "csiphy3", "csiphy3_timer" }, 1884 1802 .clock_rate = { { 300000000, 400000000 }, ··· 1896 1808 }, 1897 1809 /* CSIPHY4 */ 1898 1810 { 1899 - .regulators = { "vdda-phy", "vdda-pll" }, 1811 + .regulators = { 1812 + { .supply = "vdda-phy", .init_load_uA = 16100 }, 1813 + { .supply = "vdda-pll", .init_load_uA = 9000 } 1814 + }, 1900 1815 1901 1816 .clock = { "csiphy4", "csiphy4_timer" }, 1902 1817 .clock_rate = { { 300000000, 400000000 }, ··· 2212 2121 static const struct camss_subdev_resources csid_res_sc8280xp[] = { 2213 2122 /* CSID0 */ 2214 2123 { 2215 - .regulators = { "vdda-phy", "vdda-pll" }, 2124 + .regulators = { 2125 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2126 + { .supply = "vdda-pll", .init_load_uA = 0 } 2127 + }, 2216 2128 .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" }, 2217 2129 .clock_rate = { { 400000000, 480000000, 600000000 }, 2218 2130 { 0 }, ··· 2231 2137 }, 2232 2138 /* CSID1 */ 2233 2139 { 2234 - .regulators = { "vdda-phy", "vdda-pll" }, 2140 + .regulators = { 2141 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2142 + { .supply = "vdda-pll", .init_load_uA = 0 } 2143 + }, 2235 2144 .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" }, 2236 2145 .clock_rate = { { 400000000, 480000000, 600000000 }, 2237 2146 { 0 }, ··· 2250 2153 }, 2251 2154 /* CSID2 */ 2252 2155 { 2253 - .regulators = { "vdda-phy", "vdda-pll" }, 2156 + .regulators = { 2157 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2158 + { .supply = "vdda-pll", .init_load_uA = 0 } 2159 + }, 2254 2160 .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi" }, 2255 2161 .clock_rate = { { 400000000, 480000000, 600000000 }, 2256 2162 { 0 }, ··· 2269 2169 }, 2270 2170 /* CSID3 */ 2271 2171 { 2272 - .regulators = { "vdda-phy", "vdda-pll" }, 2172 + .regulators = { 2173 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2174 + { .supply = "vdda-pll", .init_load_uA = 0 } 2175 + }, 2273 2176 .clock = { "vfe3_csid", "vfe3_cphy_rx", "vfe3", "vfe3_axi" }, 2274 2177 .clock_rate = { { 400000000, 480000000, 600000000 }, 2275 2178 { 0 }, ··· 2288 2185 }, 2289 2186 /* CSID_LITE0 */ 2290 2187 { 2291 - .regulators = { "vdda-phy", "vdda-pll" }, 2188 + .regulators = { 2189 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2190 + { .supply = "vdda-pll", .init_load_uA = 0 } 2191 + }, 2292 2192 .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, 2293 2193 .clock_rate = { { 400000000, 480000000, 600000000 }, 2294 2194 { 0 }, ··· 2307 2201 }, 2308 2202 /* CSID_LITE1 */ 2309 2203 { 2310 - .regulators = { "vdda-phy", "vdda-pll" }, 2204 + .regulators = { 2205 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2206 + { .supply = "vdda-pll", .init_load_uA = 0 } 2207 + }, 2311 2208 .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, 2312 2209 .clock_rate = { { 400000000, 480000000, 600000000 }, 2313 2210 { 0 }, ··· 2326 2217 }, 2327 2218 /* CSID_LITE2 */ 2328 2219 { 2329 - .regulators = { "vdda-phy", "vdda-pll" }, 2220 + .regulators = { 2221 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2222 + { .supply = "vdda-pll", .init_load_uA = 0 } 2223 + }, 2330 2224 .clock = { "vfe_lite2_csid", "vfe_lite2_cphy_rx", "vfe_lite2" }, 2331 2225 .clock_rate = { { 400000000, 480000000, 600000000 }, 2332 2226 { 0 }, ··· 2345 2233 }, 2346 2234 /* CSID_LITE3 */ 2347 2235 { 2348 - .regulators = { "vdda-phy", "vdda-pll" }, 2236 + .regulators = { 2237 + { .supply = "vdda-phy", .init_load_uA = 0 }, 2238 + { .supply = "vdda-pll", .init_load_uA = 0 } 2239 + }, 2349 2240 .clock = { "vfe_lite3_csid", "vfe_lite3_cphy_rx", "vfe_lite3" }, 2350 2241 .clock_rate = { { 400000000, 480000000, 600000000 }, 2351 2242 { 0 }, ··· 2549 2434 static const struct camss_subdev_resources csiphy_res_8550[] = { 2550 2435 /* CSIPHY0 */ 2551 2436 { 2552 - .regulators = { "vdda-phy", "vdda-pll" }, 2437 + .regulators = { 2438 + { .supply = "vdda-phy", .init_load_uA = 32200 }, 2439 + { .supply = "vdda-pll", .init_load_uA = 18000 } 2440 + }, 2553 2441 .clock = { "csiphy0", "csiphy0_timer" }, 2554 2442 .clock_rate = { { 400000000, 480000000 }, 2555 2443 { 400000000 } }, ··· 2566 2448 }, 2567 2449 /* CSIPHY1 */ 2568 2450 { 2569 - .regulators = { "vdda-phy", "vdda-pll" }, 2451 + .regulators = { 2452 + { .supply = "vdda-phy", .init_load_uA = 32200 }, 2453 + { .supply = "vdda-pll", .init_load_uA = 18000 } 2454 + }, 2570 2455 .clock = { "csiphy1", "csiphy1_timer" }, 2571 2456 .clock_rate = { { 400000000, 480000000 }, 2572 2457 { 400000000 } }, ··· 2583 2462 }, 2584 2463 /* CSIPHY2 */ 2585 2464 { 2586 - .regulators = { "vdda-phy", "vdda-pll" }, 2465 + .regulators = { 2466 + { .supply = "vdda-phy", .init_load_uA = 32200 }, 2467 + { .supply = "vdda-pll", .init_load_uA = 18000 } 2468 + }, 2587 2469 .clock = { "csiphy2", "csiphy2_timer" }, 2588 2470 .clock_rate = { { 400000000, 480000000 }, 2589 2471 { 400000000 } }, ··· 2600 2476 }, 2601 2477 /* CSIPHY3 */ 2602 2478 { 2603 - .regulators = { "vdda-phy", "vdda-pll" }, 2479 + .regulators = { 2480 + { .supply = "vdda-phy", .init_load_uA = 32200 }, 2481 + { .supply = "vdda-pll", .init_load_uA = 18000 } 2482 + }, 2604 2483 .clock = { "csiphy3", "csiphy3_timer" }, 2605 2484 .clock_rate = { { 400000000, 480000000 }, 2606 2485 { 400000000 } }, ··· 2617 2490 }, 2618 2491 /* CSIPHY4 */ 2619 2492 { 2620 - .regulators = { "vdda-phy", "vdda-pll" }, 2493 + .regulators = { 2494 + { .supply = "vdda-phy", .init_load_uA = 37900 }, 2495 + { .supply = "vdda-pll", .init_load_uA = 18600 } 2496 + }, 2621 2497 .clock = { "csiphy4", "csiphy4_timer" }, 2622 2498 .clock_rate = { { 400000000, 480000000 }, 2623 2499 { 400000000 } }, ··· 2634 2504 }, 2635 2505 /* CSIPHY5 */ 2636 2506 { 2637 - .regulators = { "vdda-phy", "vdda-pll" }, 2507 + .regulators = { 2508 + { .supply = "vdda-phy", .init_load_uA = 32200 }, 2509 + { .supply = "vdda-pll", .init_load_uA = 18000 } 2510 + }, 2638 2511 .clock = { "csiphy5", "csiphy5_timer" }, 2639 2512 .clock_rate = { { 400000000, 480000000 }, 2640 2513 { 400000000 } }, ··· 2651 2518 }, 2652 2519 /* CSIPHY6 */ 2653 2520 { 2654 - .regulators = { "vdda-phy", "vdda-pll" }, 2521 + .regulators = { 2522 + { .supply = "vdda-phy", .init_load_uA = 37900 }, 2523 + { .supply = "vdda-pll", .init_load_uA = 18600 } 2524 + }, 2655 2525 .clock = { "csiphy6", "csiphy6_timer" }, 2656 2526 .clock_rate = { { 400000000, 480000000 }, 2657 2527 { 400000000 } }, ··· 2668 2532 }, 2669 2533 /* CSIPHY7 */ 2670 2534 { 2671 - .regulators = { "vdda-phy", "vdda-pll" }, 2535 + .regulators = { 2536 + { .supply = "vdda-phy", .init_load_uA = 32200 }, 2537 + { .supply = "vdda-pll", .init_load_uA = 18000 } 2538 + }, 2672 2539 .clock = { "csiphy7", "csiphy7_timer" }, 2673 2540 .clock_rate = { { 400000000, 480000000 }, 2674 2541 { 400000000 } }, ··· 2902 2763 static const struct camss_subdev_resources csiphy_res_sm8650[] = { 2903 2764 /* CSIPHY0 */ 2904 2765 { 2905 - .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", }, 2766 + .regulators = { 2767 + { .supply = "vdd-csiphy01-0p9", .init_load_uA = 88000 }, 2768 + { .supply = "vdd-csiphy01-1p2", .init_load_uA = 17800 }, 2769 + }, 2906 2770 .clock = { "csiphy0", "csiphy0_timer" }, 2907 2771 .clock_rate = { { 400000000 }, 2908 2772 { 400000000 } }, ··· 2919 2777 }, 2920 2778 /* CSIPHY1 */ 2921 2779 { 2922 - .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", }, 2780 + .regulators = { 2781 + { .supply = "vdd-csiphy01-0p9", .init_load_uA = 88000 }, 2782 + { .supply = "vdd-csiphy01-1p2", .init_load_uA = 17800 }, 2783 + }, 2923 2784 .clock = { "csiphy1", "csiphy1_timer" }, 2924 2785 .clock_rate = { { 400000000 }, 2925 2786 { 400000000 } }, ··· 2936 2791 }, 2937 2792 /* CSIPHY2 */ 2938 2793 { 2939 - .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", }, 2794 + .regulators = { 2795 + { .supply = "vdd-csiphy24-0p9", .init_load_uA = 147000 }, 2796 + { .supply = "vdd-csiphy24-1p2", .init_load_uA = 24400 }, 2797 + }, 2940 2798 .clock = { "csiphy2", "csiphy2_timer" }, 2941 2799 .clock_rate = { { 400000000 }, 2942 2800 { 400000000 } }, ··· 2953 2805 }, 2954 2806 /* CSIPHY3 */ 2955 2807 { 2956 - .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", }, 2808 + .regulators = { 2809 + { .supply = "vdd-csiphy35-0p9", .init_load_uA = 88000 }, 2810 + { .supply = "vdd-csiphy35-1p2", .init_load_uA = 17800 }, 2811 + }, 2957 2812 .clock = { "csiphy3", "csiphy3_timer" }, 2958 2813 .clock_rate = { { 400000000 }, 2959 2814 { 400000000 } }, ··· 2970 2819 }, 2971 2820 /* CSIPHY4 */ 2972 2821 { 2973 - .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", }, 2822 + .regulators = { 2823 + { .supply = "vdd-csiphy24-0p9", .init_load_uA = 147000 }, 2824 + { .supply = "vdd-csiphy24-1p2", .init_load_uA = 24400 }, 2825 + }, 2974 2826 .clock = { "csiphy4", "csiphy4_timer" }, 2975 2827 .clock_rate = { { 400000000 }, 2976 2828 { 400000000 } }, ··· 2987 2833 }, 2988 2834 /* CSIPHY5 */ 2989 2835 { 2990 - .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", }, 2836 + .regulators = { 2837 + { .supply = "vdd-csiphy35-0p9", .init_load_uA = 88000 }, 2838 + { .supply = "vdd-csiphy35-1p2", .init_load_uA = 17800 }, 2839 + }, 2991 2840 .clock = { "csiphy5", "csiphy5_timer" }, 2992 2841 .clock_rate = { { 400000000 }, 2993 2842 { 400000000 } }, ··· 3231 3074 static const struct camss_subdev_resources csiphy_res_8300[] = { 3232 3075 /* CSIPHY0 */ 3233 3076 { 3234 - .regulators = { "vdda-phy", "vdda-pll" }, 3077 + .regulators = { 3078 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3079 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3080 + }, 3235 3081 3236 3082 .clock = { "csiphy_rx", "csiphy0", "csiphy0_timer" }, 3237 3083 .clock_rate = { ··· 3252 3092 }, 3253 3093 /* CSIPHY1 */ 3254 3094 { 3255 - .regulators = { "vdda-phy", "vdda-pll" }, 3095 + .regulators = { 3096 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3097 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3098 + }, 3256 3099 3257 3100 .clock = { "csiphy_rx", "csiphy1", "csiphy1_timer" }, 3258 3101 .clock_rate = { ··· 3273 3110 }, 3274 3111 /* CSIPHY2 */ 3275 3112 { 3276 - .regulators = { "vdda-phy", "vdda-pll" }, 3113 + .regulators = { 3114 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3115 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3116 + }, 3277 3117 3278 3118 .clock = { "csiphy_rx", "csiphy2", "csiphy2_timer" }, 3279 3119 .clock_rate = { ··· 3297 3131 static const struct camss_subdev_resources csiphy_res_8775p[] = { 3298 3132 /* CSIPHY0 */ 3299 3133 { 3300 - .regulators = { "vdda-phy", "vdda-pll" }, 3134 + .regulators = { 3135 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3136 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3137 + }, 3301 3138 .clock = { "csiphy_rx", "csiphy0", "csiphy0_timer"}, 3302 3139 .clock_rate = { 3303 3140 { 400000000 }, ··· 3317 3148 }, 3318 3149 /* CSIPHY1 */ 3319 3150 { 3320 - .regulators = { "vdda-phy", "vdda-pll" }, 3151 + .regulators = { 3152 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3153 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3154 + }, 3321 3155 .clock = { "csiphy_rx", "csiphy1", "csiphy1_timer"}, 3322 3156 .clock_rate = { 3323 3157 { 400000000 }, ··· 3337 3165 }, 3338 3166 /* CSIPHY2 */ 3339 3167 { 3340 - .regulators = { "vdda-phy", "vdda-pll" }, 3168 + .regulators = { 3169 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3170 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3171 + }, 3341 3172 .clock = { "csiphy_rx", "csiphy2", "csiphy2_timer"}, 3342 3173 .clock_rate = { 3343 3174 { 400000000 }, ··· 3357 3182 }, 3358 3183 /* CSIPHY3 */ 3359 3184 { 3360 - .regulators = { "vdda-phy", "vdda-pll" }, 3185 + .regulators = { 3186 + { .supply = "vdda-phy", .init_load_uA = 15900 }, 3187 + { .supply = "vdda-pll", .init_load_uA = 8900 } 3188 + }, 3361 3189 .clock = { "csiphy_rx", "csiphy3", "csiphy3_timer"}, 3362 3190 .clock_rate = { 3363 3191 { 400000000 }, ··· 3713 3535 static const struct camss_subdev_resources csiphy_res_x1e80100[] = { 3714 3536 /* CSIPHY0 */ 3715 3537 { 3716 - .regulators = { "vdd-csiphy-0p8", 3717 - "vdd-csiphy-1p2" }, 3538 + .regulators = { 3539 + { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, 3540 + { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } 3541 + }, 3718 3542 .clock = { "csiphy0", "csiphy0_timer" }, 3719 3543 .clock_rate = { { 300000000, 400000000, 480000000 }, 3720 3544 { 266666667, 400000000 } }, ··· 3730 3550 }, 3731 3551 /* CSIPHY1 */ 3732 3552 { 3733 - .regulators = { "vdd-csiphy-0p8", 3734 - "vdd-csiphy-1p2" }, 3553 + .regulators = { 3554 + { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, 3555 + { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } 3556 + }, 3735 3557 .clock = { "csiphy1", "csiphy1_timer" }, 3736 3558 .clock_rate = { { 300000000, 400000000, 480000000 }, 3737 3559 { 266666667, 400000000 } }, ··· 3747 3565 }, 3748 3566 /* CSIPHY2 */ 3749 3567 { 3750 - .regulators = { "vdd-csiphy-0p8", 3751 - "vdd-csiphy-1p2" }, 3568 + .regulators = { 3569 + { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, 3570 + { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } 3571 + }, 3752 3572 .clock = { "csiphy2", "csiphy2_timer" }, 3753 3573 .clock_rate = { { 300000000, 400000000, 480000000 }, 3754 3574 { 266666667, 400000000 } }, ··· 3764 3580 }, 3765 3581 /* CSIPHY4 */ 3766 3582 { 3767 - .regulators = { "vdd-csiphy-0p8", 3768 - "vdd-csiphy-1p2" }, 3583 + .regulators = { 3584 + { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, 3585 + { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } 3586 + }, 3769 3587 .clock = { "csiphy4", "csiphy4_timer" }, 3770 3588 .clock_rate = { { 300000000, 400000000, 480000000 }, 3771 3589 { 266666667, 400000000 } },
+1 -1
drivers/media/platform/qcom/camss/camss.h
··· 44 44 #define CAMSS_INIT_BUF_COUNT 2 45 45 46 46 struct camss_subdev_resources { 47 - char *regulators[CAMSS_RES_MAX]; 47 + struct regulator_bulk_data regulators[CAMSS_RES_MAX]; 48 48 char *clock[CAMSS_RES_MAX]; 49 49 char *clock_for_reset[CAMSS_RES_MAX]; 50 50 u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX];