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KVM: arm64: Add KVM_PGTABLE_S2_AS_S1 flag

Plumb the MT_S2{,_FWB}_AS_S1 memory types into the KVM_S2_MEMATTR()
macro with a new KVM_PGTABLE_S2_AS_S1 flag.

Nobody selects it yet.

Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Link: https://patch.msgid.link/20260123191637.715429-3-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

+15 -1
+2
arch/arm64/include/asm/kvm_pgtable.h
··· 232 232 * @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have 233 233 * ARM64_HAS_STAGE2_FWB. 234 234 * @KVM_PGTABLE_S2_IDMAP: Only use identity mappings. 235 + * @KVM_PGTABLE_S2_AS_S1: Final memory attributes are that of Stage-1. 235 236 */ 236 237 enum kvm_pgtable_stage2_flags { 237 238 KVM_PGTABLE_S2_NOFWB = BIT(0), 238 239 KVM_PGTABLE_S2_IDMAP = BIT(1), 240 + KVM_PGTABLE_S2_AS_S1 = BIT(2), 239 241 }; 240 242 241 243 /**
+13 -1
arch/arm64/kvm/hyp/pgtable.c
··· 659 659 } 660 660 } 661 661 662 - #define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt)) 662 + #define KVM_S2_MEMATTR(pgt, attr) \ 663 + ({ \ 664 + kvm_pte_t __attr; \ 665 + \ 666 + if ((pgt)->flags & KVM_PGTABLE_S2_AS_S1) \ 667 + __attr = PAGE_S2_MEMATTR(AS_S1, \ 668 + stage2_has_fwb(pgt)); \ 669 + else \ 670 + __attr = PAGE_S2_MEMATTR(attr, \ 671 + stage2_has_fwb(pgt)); \ 672 + \ 673 + __attr; \ 674 + }) 663 675 664 676 static int stage2_set_xn_attr(enum kvm_pgtable_prot prot, kvm_pte_t *attr) 665 677 {