Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-dts-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.4 (take two)
- Add PWM support for the R-Car H1 and H2 SoCs,
- Add slide switch and I2C support for the Marzen development board,
- Add SCI (serial) and Camera support for the RZ/G2L SoC and the
RZ/G2L SMARC EVK development board,
- Add IOMMU support for the R-Car V4H SoC,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r8a779a0: Revise renesas,ipmmu-main
arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712
arm64: dts: renesas: r8a779g0: Add iommus to MMC node
arm64: dts: renesas: r8a779g0: Add iommus to DMAC nodes
arm64: dts: renesas: r8a779g0: Add IPMMU nodes
arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-main
arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI support
arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes
arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlay
ARM: dts: r8a7790: Add PWM device nodes
ARM: dts: r8a7790: Add TPU device node
ARM: dts: marzen: Enable I2C support
ARM: dts: marzen: Add slide switches
ARM: dts: r8a7779: Add PWM support
dt-bindings: clock: r8a7779: Add PWM module clock
arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes
Link: https://lore.kernel.org/r/cover.1681113117.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+608
-28
+69
arch/arm/boot/dts/r8a7779-marzen.dts
+69
arch/arm/boot/dts/r8a7779-marzen.dts
···
9
9
/dts-v1/;
10
10
#include "r8a7779.dtsi"
11
11
#include <dt-bindings/gpio/gpio.h>
12
+
#include <dt-bindings/input/input.h>
12
13
#include <dt-bindings/interrupt-controller/irq.h>
13
14
14
15
/ {
···
65
64
reg-io-width = <4>;
66
65
vddvario-supply = <&fixedregulator3v3>;
67
66
vdd33a-supply = <&fixedregulator3v3>;
67
+
};
68
+
69
+
keyboard-irq {
70
+
compatible = "gpio-keys";
71
+
72
+
pinctrl-0 = <&keyboard_irq_pins>;
73
+
pinctrl-names = "default";
74
+
75
+
interrupt-parent = <&gpio0>;
76
+
77
+
key-1 {
78
+
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
79
+
linux,code = <KEY_1>;
80
+
label = "SW1-1";
81
+
wakeup-source;
82
+
debounce-interval = <20>;
83
+
};
84
+
key-2 {
85
+
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
86
+
linux,code = <KEY_2>;
87
+
label = "SW1-2";
88
+
wakeup-source;
89
+
debounce-interval = <20>;
90
+
};
91
+
};
92
+
93
+
keyboard-gpio {
94
+
compatible = "gpio-keys-polled";
95
+
poll-interval = <50>;
96
+
97
+
pinctrl-0 = <&keyboard_gpio_pins>;
98
+
pinctrl-names = "default";
99
+
100
+
key-3 {
101
+
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
102
+
linux,code = <KEY_3>;
103
+
label = "SW1-3";
104
+
debounce-interval = <20>;
105
+
};
106
+
key-4 {
107
+
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
108
+
linux,code = <KEY_4>;
109
+
label = "SW1-4";
110
+
debounce-interval = <20>;
111
+
};
68
112
};
69
113
70
114
leds {
···
207
161
};
208
162
};
209
163
164
+
&gpio0 {
165
+
keyboard-irq-hog {
166
+
gpio-hog;
167
+
gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>;
168
+
input;
169
+
};
170
+
};
171
+
172
+
&i2c0 {
173
+
status = "okay";
174
+
175
+
clock-frequency = <100000>;
176
+
};
177
+
210
178
&irqpin0 {
211
179
status = "okay";
212
180
};
···
282
222
hspi0_pins: hspi0 {
283
223
groups = "hspi0";
284
224
function = "hspi0";
225
+
};
226
+
227
+
keyboard_irq_pins: keyboard-irq {
228
+
pins = "GP_0_17", "GP_0_18";
229
+
bias-pull-up;
230
+
};
231
+
keyboard_gpio_pins: keyboard-gpio {
232
+
pins = "GP_0_19", "GP_0_20";
233
+
bias-pull-up;
285
234
};
286
235
};
287
236
+78
-13
arch/arm/boot/dts/r8a7779.dtsi
+78
-13
arch/arm/boot/dts/r8a7779.dtsi
···
324
324
status = "disabled";
325
325
};
326
326
327
+
pwm0: pwm@ffe50000 {
328
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
329
+
reg = <0xffe50000 0x8>;
330
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
331
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
332
+
#pwm-cells = <2>;
333
+
status = "disabled";
334
+
};
335
+
336
+
pwm1: pwm@ffe51000 {
337
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
338
+
reg = <0xffe51000 0x8>;
339
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
340
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
341
+
#pwm-cells = <2>;
342
+
status = "disabled";
343
+
};
344
+
345
+
pwm2: pwm@ffe52000 {
346
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
347
+
reg = <0xffe52000 0x8>;
348
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
349
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
350
+
#pwm-cells = <2>;
351
+
status = "disabled";
352
+
};
353
+
354
+
pwm3: pwm@ffe53000 {
355
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
356
+
reg = <0xffe53000 0x8>;
357
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
358
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
359
+
#pwm-cells = <2>;
360
+
status = "disabled";
361
+
};
362
+
363
+
pwm4: pwm@ffe54000 {
364
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
365
+
reg = <0xffe54000 0x8>;
366
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
367
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
368
+
#pwm-cells = <2>;
369
+
status = "disabled";
370
+
};
371
+
372
+
pwm5: pwm@ffe55000 {
373
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
374
+
reg = <0xffe55000 0x8>;
375
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
376
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
377
+
#pwm-cells = <2>;
378
+
status = "disabled";
379
+
};
380
+
381
+
pwm6: pwm@ffe56000 {
382
+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
383
+
reg = <0xffe56000 0x8>;
384
+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
385
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
386
+
#pwm-cells = <2>;
387
+
status = "disabled";
388
+
};
389
+
327
390
pfc: pinctrl@fffc0000 {
328
391
compatible = "renesas,pfc-r8a7779";
329
392
reg = <0xfffc0000 0x23c>;
···
617
554
compatible = "renesas,r8a7779-mstp-clocks",
618
555
"renesas,cpg-mstp-clocks";
619
556
reg = <0xffc80030 4>;
620
-
clocks = <&cpg_clocks R8A7779_CLK_S>,
557
+
clocks = <&cpg_clocks R8A7779_CLK_P>,
558
+
<&cpg_clocks R8A7779_CLK_S>,
621
559
<&cpg_clocks R8A7779_CLK_P>,
622
560
<&cpg_clocks R8A7779_CLK_P>,
623
561
<&cpg_clocks R8A7779_CLK_P>,
···
636
572
<&cpg_clocks R8A7779_CLK_P>;
637
573
#clock-cells = <1>;
638
574
clock-indices = <
639
-
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
640
-
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
641
-
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
642
-
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
643
-
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
644
-
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
645
-
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
646
-
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
575
+
R8A7779_CLK_PWM R8A7779_CLK_HSPI
576
+
R8A7779_CLK_TMU2 R8A7779_CLK_TMU1
577
+
R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1
578
+
R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5
579
+
R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
580
+
R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
581
+
R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3
582
+
R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
583
+
R8A7779_CLK_I2C0
647
584
>;
648
585
clock-output-names =
649
-
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
650
-
"hscif0", "scif5", "scif4", "scif3", "scif2",
651
-
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
652
-
"i2c0";
586
+
"pwm", "hspi", "tmu2", "tmu1", "tmu0",
587
+
"hscif1", "hscif0", "scif5", "scif4", "scif3",
588
+
"scif2", "scif1", "scif0", "i2c3", "i2c2",
589
+
"i2c1", "i2c0";
653
590
};
654
591
mstp1_clks: clocks@ffc80034 {
655
592
compatible = "renesas,r8a7779-mstp-clocks",
+81
arch/arm/boot/dts/r8a7790.dtsi
+81
arch/arm/boot/dts/r8a7790.dtsi
···
376
376
reg = <0 0xe6060000 0 0x250>;
377
377
};
378
378
379
+
tpu: pwm@e60f0000 {
380
+
compatible = "renesas,tpu-r8a7790", "renesas,tpu";
381
+
reg = <0 0xe60f0000 0 0x148>;
382
+
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
383
+
clocks = <&cpg CPG_MOD 304>;
384
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
385
+
resets = <&cpg 304>;
386
+
#pwm-cells = <3>;
387
+
status = "disabled";
388
+
};
389
+
379
390
cpg: clock-controller@e6150000 {
380
391
compatible = "renesas,r8a7790-cpg-mssr";
381
392
reg = <0 0xe6150000 0 0x1000>;
···
1045
1034
resets = <&cpg 215>;
1046
1035
#address-cells = <1>;
1047
1036
#size-cells = <0>;
1037
+
status = "disabled";
1038
+
};
1039
+
1040
+
pwm0: pwm@e6e30000 {
1041
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1042
+
reg = <0 0xe6e30000 0 0x8>;
1043
+
clocks = <&cpg CPG_MOD 523>;
1044
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1045
+
resets = <&cpg 523>;
1046
+
#pwm-cells = <2>;
1047
+
status = "disabled";
1048
+
};
1049
+
1050
+
pwm1: pwm@e6e31000 {
1051
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1052
+
reg = <0 0xe6e31000 0 0x8>;
1053
+
clocks = <&cpg CPG_MOD 523>;
1054
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1055
+
resets = <&cpg 523>;
1056
+
#pwm-cells = <2>;
1057
+
status = "disabled";
1058
+
};
1059
+
1060
+
pwm2: pwm@e6e32000 {
1061
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1062
+
reg = <0 0xe6e32000 0 0x8>;
1063
+
clocks = <&cpg CPG_MOD 523>;
1064
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1065
+
resets = <&cpg 523>;
1066
+
#pwm-cells = <2>;
1067
+
status = "disabled";
1068
+
};
1069
+
1070
+
pwm3: pwm@e6e33000 {
1071
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1072
+
reg = <0 0xe6e33000 0 0x8>;
1073
+
clocks = <&cpg CPG_MOD 523>;
1074
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1075
+
resets = <&cpg 523>;
1076
+
#pwm-cells = <2>;
1077
+
status = "disabled";
1078
+
};
1079
+
1080
+
pwm4: pwm@e6e34000 {
1081
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1082
+
reg = <0 0xe6e34000 0 0x8>;
1083
+
clocks = <&cpg CPG_MOD 523>;
1084
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1085
+
resets = <&cpg 523>;
1086
+
#pwm-cells = <2>;
1087
+
status = "disabled";
1088
+
};
1089
+
1090
+
pwm5: pwm@e6e35000 {
1091
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1092
+
reg = <0 0xe6e35000 0 0x8>;
1093
+
clocks = <&cpg CPG_MOD 523>;
1094
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1095
+
resets = <&cpg 523>;
1096
+
#pwm-cells = <2>;
1097
+
status = "disabled";
1098
+
};
1099
+
1100
+
pwm6: pwm@e6e36000 {
1101
+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1102
+
reg = <0 0xe6e36000 0 0x8>;
1103
+
clocks = <&cpg CPG_MOD 523>;
1104
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1105
+
resets = <&cpg 523>;
1106
+
#pwm-cells = <2>;
1048
1107
status = "disabled";
1049
1108
};
1050
1109
+2
arch/arm64/boot/dts/renesas/Makefile
+2
arch/arm64/boot/dts/renesas/Makefile
···
76
76
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
77
77
78
78
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
79
+
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo
79
80
80
81
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
81
82
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
83
+
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
82
84
83
85
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
84
86
+5
arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
+5
arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
···
5
5
* Copyright (C) 2021 Glider bv
6
6
*/
7
7
8
+
#include <dt-bindings/media/video-interfaces.h>
9
+
8
10
&csi40 {
9
11
status = "okay";
10
12
···
107
105
port@4 {
108
106
reg = <4>;
109
107
max96712_out0: endpoint {
108
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
110
109
clock-lanes = <0>;
111
110
data-lanes = <1 2 3 4>;
112
111
remote-endpoint = <&csi40_in>;
···
128
125
port@4 {
129
126
reg = <4>;
130
127
max96712_out1: endpoint {
128
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
131
129
clock-lanes = <0>;
132
130
data-lanes = <1 2 3 4>;
133
131
lane-polarities = <0 0 0 0 1>;
···
150
146
port@4 {
151
147
reg = <4>;
152
148
max96712_out2: endpoint {
149
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
153
150
clock-lanes = <0>;
154
151
data-lanes = <1 2 3 4>;
155
152
lane-polarities = <0 0 0 0 1>;
+11
-11
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+11
-11
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
···
2098
2098
compatible = "renesas,ipmmu-r8a779a0",
2099
2099
"renesas,rcar-gen4-ipmmu-vmsa";
2100
2100
reg = <0 0xee480000 0 0x20000>;
2101
-
renesas,ipmmu-main = <&ipmmu_mm 10>;
2101
+
renesas,ipmmu-main = <&ipmmu_mm>;
2102
2102
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2103
2103
#iommu-cells = <1>;
2104
2104
};
···
2107
2107
compatible = "renesas,ipmmu-r8a779a0",
2108
2108
"renesas,rcar-gen4-ipmmu-vmsa";
2109
2109
reg = <0 0xee4c0000 0 0x20000>;
2110
-
renesas,ipmmu-main = <&ipmmu_mm 19>;
2110
+
renesas,ipmmu-main = <&ipmmu_mm>;
2111
2111
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2112
2112
#iommu-cells = <1>;
2113
2113
};
···
2116
2116
compatible = "renesas,ipmmu-r8a779a0",
2117
2117
"renesas,rcar-gen4-ipmmu-vmsa";
2118
2118
reg = <0 0xeed00000 0 0x20000>;
2119
-
renesas,ipmmu-main = <&ipmmu_mm 0>;
2119
+
renesas,ipmmu-main = <&ipmmu_mm>;
2120
2120
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2121
2121
#iommu-cells = <1>;
2122
2122
};
···
2125
2125
compatible = "renesas,ipmmu-r8a779a0",
2126
2126
"renesas,rcar-gen4-ipmmu-vmsa";
2127
2127
reg = <0 0xeed40000 0 0x20000>;
2128
-
renesas,ipmmu-main = <&ipmmu_mm 1>;
2128
+
renesas,ipmmu-main = <&ipmmu_mm>;
2129
2129
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2130
2130
#iommu-cells = <1>;
2131
2131
};
···
2134
2134
compatible = "renesas,ipmmu-r8a779a0",
2135
2135
"renesas,rcar-gen4-ipmmu-vmsa";
2136
2136
reg = <0 0xeed80000 0 0x20000>;
2137
-
renesas,ipmmu-main = <&ipmmu_mm 3>;
2137
+
renesas,ipmmu-main = <&ipmmu_mm>;
2138
2138
power-domains = <&sysc R8A779A0_PD_A3IR>;
2139
2139
#iommu-cells = <1>;
2140
2140
};
···
2143
2143
compatible = "renesas,ipmmu-r8a779a0",
2144
2144
"renesas,rcar-gen4-ipmmu-vmsa";
2145
2145
reg = <0 0xeedc0000 0 0x20000>;
2146
-
renesas,ipmmu-main = <&ipmmu_mm 12>;
2146
+
renesas,ipmmu-main = <&ipmmu_mm>;
2147
2147
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2148
2148
#iommu-cells = <1>;
2149
2149
};
···
2152
2152
compatible = "renesas,ipmmu-r8a779a0",
2153
2153
"renesas,rcar-gen4-ipmmu-vmsa";
2154
2154
reg = <0 0xeee80000 0 0x20000>;
2155
-
renesas,ipmmu-main = <&ipmmu_mm 14>;
2155
+
renesas,ipmmu-main = <&ipmmu_mm>;
2156
2156
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2157
2157
#iommu-cells = <1>;
2158
2158
};
···
2161
2161
compatible = "renesas,ipmmu-r8a779a0",
2162
2162
"renesas,rcar-gen4-ipmmu-vmsa";
2163
2163
reg = <0 0xeeec0000 0 0x20000>;
2164
-
renesas,ipmmu-main = <&ipmmu_mm 15>;
2164
+
renesas,ipmmu-main = <&ipmmu_mm>;
2165
2165
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2166
2166
#iommu-cells = <1>;
2167
2167
};
···
2170
2170
compatible = "renesas,ipmmu-r8a779a0",
2171
2171
"renesas,rcar-gen4-ipmmu-vmsa";
2172
2172
reg = <0 0xeee00000 0 0x20000>;
2173
-
renesas,ipmmu-main = <&ipmmu_mm 6>;
2173
+
renesas,ipmmu-main = <&ipmmu_mm>;
2174
2174
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2175
2175
#iommu-cells = <1>;
2176
2176
};
···
2179
2179
compatible = "renesas,ipmmu-r8a779a0",
2180
2180
"renesas,rcar-gen4-ipmmu-vmsa";
2181
2181
reg = <0 0xeef00000 0 0x20000>;
2182
-
renesas,ipmmu-main = <&ipmmu_mm 5>;
2182
+
renesas,ipmmu-main = <&ipmmu_mm>;
2183
2183
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2184
2184
#iommu-cells = <1>;
2185
2185
};
···
2188
2188
compatible = "renesas,ipmmu-r8a779a0",
2189
2189
"renesas,rcar-gen4-ipmmu-vmsa";
2190
2190
reg = <0 0xeef40000 0 0x20000>;
2191
-
renesas,ipmmu-main = <&ipmmu_mm 11>;
2191
+
renesas,ipmmu-main = <&ipmmu_mm>;
2192
2192
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2193
2193
#iommu-cells = <1>;
2194
2194
};
+4
-4
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+4
-4
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
···
1059
1059
compatible = "renesas,ipmmu-r8a779f0",
1060
1060
"renesas,rcar-gen4-ipmmu-vmsa";
1061
1061
reg = <0 0xee480000 0 0x20000>;
1062
-
renesas,ipmmu-main = <&ipmmu_mm 10>;
1062
+
renesas,ipmmu-main = <&ipmmu_mm>;
1063
1063
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1064
1064
#iommu-cells = <1>;
1065
1065
};
···
1068
1068
compatible = "renesas,ipmmu-r8a779f0",
1069
1069
"renesas,rcar-gen4-ipmmu-vmsa";
1070
1070
reg = <0 0xee4c0000 0 0x20000>;
1071
-
renesas,ipmmu-main = <&ipmmu_mm 19>;
1071
+
renesas,ipmmu-main = <&ipmmu_mm>;
1072
1072
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1073
1073
#iommu-cells = <1>;
1074
1074
};
···
1077
1077
compatible = "renesas,ipmmu-r8a779f0",
1078
1078
"renesas,rcar-gen4-ipmmu-vmsa";
1079
1079
reg = <0 0xeed00000 0 0x20000>;
1080
-
renesas,ipmmu-main = <&ipmmu_mm 0>;
1080
+
renesas,ipmmu-main = <&ipmmu_mm>;
1081
1081
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1082
1082
#iommu-cells = <1>;
1083
1083
};
···
1086
1086
compatible = "renesas,ipmmu-r8a779f0",
1087
1087
"renesas,rcar-gen4-ipmmu-vmsa";
1088
1088
reg = <0 0xeed40000 0 0x20000>;
1089
-
renesas,ipmmu-main = <&ipmmu_mm 2>;
1089
+
renesas,ipmmu-main = <&ipmmu_mm>;
1090
1090
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1091
1091
#iommu-cells = <1>;
1092
1092
};
+126
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+126
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
···
1655
1655
resets = <&cpg 709>;
1656
1656
#dma-cells = <1>;
1657
1657
dma-channels = <16>;
1658
+
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1659
+
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1660
+
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1661
+
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1662
+
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1663
+
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1664
+
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1665
+
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1658
1666
};
1659
1667
1660
1668
dmac1: dma-controller@e7351000 {
···
1698
1690
resets = <&cpg 710>;
1699
1691
#dma-cells = <1>;
1700
1692
dma-channels = <16>;
1693
+
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1694
+
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1695
+
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1696
+
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
1697
+
<&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
1698
+
<&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
1699
+
<&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
1700
+
<&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
1701
1701
};
1702
1702
1703
1703
rcar_sound: sound@ec5a0000 {
···
1777
1761
};
1778
1762
};
1779
1763
1764
+
ipmmu_rt0: iommu@ee480000 {
1765
+
compatible = "renesas,ipmmu-r8a779g0",
1766
+
"renesas,rcar-gen4-ipmmu-vmsa";
1767
+
reg = <0 0xee480000 0 0x20000>;
1768
+
renesas,ipmmu-main = <&ipmmu_mm>;
1769
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1770
+
#iommu-cells = <1>;
1771
+
};
1772
+
1773
+
ipmmu_rt1: iommu@ee4c0000 {
1774
+
compatible = "renesas,ipmmu-r8a779g0",
1775
+
"renesas,rcar-gen4-ipmmu-vmsa";
1776
+
reg = <0 0xee4c0000 0 0x20000>;
1777
+
renesas,ipmmu-main = <&ipmmu_mm>;
1778
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1779
+
#iommu-cells = <1>;
1780
+
};
1781
+
1782
+
ipmmu_ds0: iommu@eed00000 {
1783
+
compatible = "renesas,ipmmu-r8a779g0",
1784
+
"renesas,rcar-gen4-ipmmu-vmsa";
1785
+
reg = <0 0xeed00000 0 0x20000>;
1786
+
renesas,ipmmu-main = <&ipmmu_mm>;
1787
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1788
+
#iommu-cells = <1>;
1789
+
};
1790
+
1791
+
ipmmu_hc: iommu@eed40000 {
1792
+
compatible = "renesas,ipmmu-r8a779g0",
1793
+
"renesas,rcar-gen4-ipmmu-vmsa";
1794
+
reg = <0 0xeed40000 0 0x20000>;
1795
+
renesas,ipmmu-main = <&ipmmu_mm>;
1796
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1797
+
#iommu-cells = <1>;
1798
+
};
1799
+
1800
+
ipmmu_ir: iommu@eed80000 {
1801
+
compatible = "renesas,ipmmu-r8a779g0",
1802
+
"renesas,rcar-gen4-ipmmu-vmsa";
1803
+
reg = <0 0xeed80000 0 0x20000>;
1804
+
renesas,ipmmu-main = <&ipmmu_mm>;
1805
+
power-domains = <&sysc R8A779G0_PD_A3IR>;
1806
+
#iommu-cells = <1>;
1807
+
};
1808
+
1809
+
ipmmu_vc: iommu@eedc0000 {
1810
+
compatible = "renesas,ipmmu-r8a779g0",
1811
+
"renesas,rcar-gen4-ipmmu-vmsa";
1812
+
reg = <0 0xeedc0000 0 0x20000>;
1813
+
renesas,ipmmu-main = <&ipmmu_mm>;
1814
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1815
+
#iommu-cells = <1>;
1816
+
};
1817
+
1818
+
ipmmu_3dg: iommu@eee00000 {
1819
+
compatible = "renesas,ipmmu-r8a779g0",
1820
+
"renesas,rcar-gen4-ipmmu-vmsa";
1821
+
reg = <0 0xeee00000 0 0x20000>;
1822
+
renesas,ipmmu-main = <&ipmmu_mm>;
1823
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1824
+
#iommu-cells = <1>;
1825
+
};
1826
+
1827
+
ipmmu_vi0: iommu@eee80000 {
1828
+
compatible = "renesas,ipmmu-r8a779g0",
1829
+
"renesas,rcar-gen4-ipmmu-vmsa";
1830
+
reg = <0 0xeee80000 0 0x20000>;
1831
+
renesas,ipmmu-main = <&ipmmu_mm>;
1832
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1833
+
#iommu-cells = <1>;
1834
+
};
1835
+
1836
+
ipmmu_vi1: iommu@eeec0000 {
1837
+
compatible = "renesas,ipmmu-r8a779g0",
1838
+
"renesas,rcar-gen4-ipmmu-vmsa";
1839
+
reg = <0 0xeeec0000 0 0x20000>;
1840
+
renesas,ipmmu-main = <&ipmmu_mm>;
1841
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1842
+
#iommu-cells = <1>;
1843
+
};
1844
+
1845
+
ipmmu_vip0: iommu@eef00000 {
1846
+
compatible = "renesas,ipmmu-r8a779g0",
1847
+
"renesas,rcar-gen4-ipmmu-vmsa";
1848
+
reg = <0 0xeef00000 0 0x20000>;
1849
+
renesas,ipmmu-main = <&ipmmu_mm>;
1850
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1851
+
#iommu-cells = <1>;
1852
+
};
1853
+
1854
+
ipmmu_vip1: iommu@eef40000 {
1855
+
compatible = "renesas,ipmmu-r8a779g0",
1856
+
"renesas,rcar-gen4-ipmmu-vmsa";
1857
+
reg = <0 0xeef40000 0 0x20000>;
1858
+
renesas,ipmmu-main = <&ipmmu_mm>;
1859
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1860
+
#iommu-cells = <1>;
1861
+
};
1862
+
1863
+
ipmmu_mm: iommu@eefc0000 {
1864
+
compatible = "renesas,ipmmu-r8a779g0",
1865
+
"renesas,rcar-gen4-ipmmu-vmsa";
1866
+
reg = <0 0xeefc0000 0 0x20000>;
1867
+
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1868
+
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1869
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1870
+
#iommu-cells = <1>;
1871
+
};
1872
+
1780
1873
mmc0: mmc@ee140000 {
1781
1874
compatible = "renesas,sdhi-r8a779g0",
1782
1875
"renesas,rcar-gen4-sdhi";
···
1897
1772
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1898
1773
resets = <&cpg 706>;
1899
1774
max-frequency = <200000000>;
1775
+
iommus = <&ipmmu_ds0 32>;
1900
1776
status = "disabled";
1901
1777
};
1902
1778
+45
arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso
+45
arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree Source for the RZ/{G2UL, Five} SMARC EVK PMOD parts
4
+
*
5
+
* Copyright (C) 2023 Renesas Electronics Corp.
6
+
*
7
+
*
8
+
* [Connection]
9
+
*
10
+
* SMARC EVK
11
+
* +----------------------------+
12
+
* |CN7 (PMOD1 PIN HEADER) |
13
+
* | SCI0_TXD pin7 |
14
+
* | SCI0_RXD pin8 |
15
+
* | Gnd pin11 |
16
+
* | Vcc pin12 |
17
+
* +----------------------------+
18
+
*
19
+
*/
20
+
21
+
/dts-v1/;
22
+
/plugin/;
23
+
24
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
25
+
26
+
&pinctrl {
27
+
can0-stb-hog {
28
+
status = "disabled";
29
+
};
30
+
31
+
can1-stb-hog {
32
+
status = "disabled";
33
+
};
34
+
35
+
sci0_pins: sci0-pins {
36
+
pinmux = <RZG2L_PORT_PINMUX(2, 2, 5)>, /* TxD */
37
+
<RZG2L_PORT_PINMUX(2, 3, 5)>; /* RxD */
38
+
};
39
+
};
40
+
41
+
&sci0 {
42
+
pinctrl-0 = <&sci0_pins>;
43
+
pinctrl-names = "default";
44
+
status = "okay";
45
+
};
+2
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+2
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
···
564
564
"ch12", "ch13", "ch14", "ch15";
565
565
clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
566
566
<&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
567
+
clock-names = "main", "register";
567
568
power-domains = <&cpg>;
568
569
resets = <&cpg R9A07G043_DMAC_ARESETN>,
569
570
<&cpg R9A07G043_DMAC_RST_ASYNC>;
571
+
reset-names = "arst", "rst_async";
570
572
#dma-cells = <1>;
571
573
dma-channels = <16>;
572
574
};
+81
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+81
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
···
618
618
status = "disabled";
619
619
};
620
620
621
+
cru: video@10830000 {
622
+
compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
623
+
reg = <0 0x10830000 0 0x400>;
624
+
clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
625
+
<&cpg CPG_MOD R9A07G044_CRU_PCLK>,
626
+
<&cpg CPG_MOD R9A07G044_CRU_ACLK>;
627
+
clock-names = "video", "apb", "axi";
628
+
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
629
+
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
630
+
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
631
+
interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
632
+
resets = <&cpg R9A07G044_CRU_PRESETN>,
633
+
<&cpg R9A07G044_CRU_ARESETN>;
634
+
reset-names = "presetn", "aresetn";
635
+
power-domains = <&cpg>;
636
+
status = "disabled";
637
+
638
+
ports {
639
+
#address-cells = <1>;
640
+
#size-cells = <0>;
641
+
642
+
port@0 {
643
+
#address-cells = <1>;
644
+
#size-cells = <0>;
645
+
646
+
reg = <0>;
647
+
cruparallel: endpoint@0 {
648
+
reg = <0>;
649
+
};
650
+
};
651
+
652
+
port@1 {
653
+
#address-cells = <1>;
654
+
#size-cells = <0>;
655
+
656
+
reg = <1>;
657
+
crucsi2: endpoint@0 {
658
+
reg = <0>;
659
+
remote-endpoint = <&csi2cru>;
660
+
};
661
+
};
662
+
};
663
+
};
664
+
665
+
csi2: csi2@10830400 {
666
+
compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
667
+
reg = <0 0x10830400 0 0xfc00>;
668
+
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
669
+
clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
670
+
<&cpg CPG_MOD R9A07G044_CRU_VCLK>,
671
+
<&cpg CPG_MOD R9A07G044_CRU_PCLK>;
672
+
clock-names = "system", "video", "apb";
673
+
resets = <&cpg R9A07G044_CRU_PRESETN>,
674
+
<&cpg R9A07G044_CRU_CMN_RSTB>;
675
+
reset-names = "presetn", "cmn-rstb";
676
+
power-domains = <&cpg>;
677
+
status = "disabled";
678
+
679
+
ports {
680
+
#address-cells = <1>;
681
+
#size-cells = <0>;
682
+
683
+
port@0 {
684
+
reg = <0>;
685
+
};
686
+
687
+
port@1 {
688
+
#address-cells = <1>;
689
+
#size-cells = <0>;
690
+
reg = <1>;
691
+
692
+
csi2cru: endpoint@0 {
693
+
reg = <0>;
694
+
remote-endpoint = <&crucsi2>;
695
+
};
696
+
};
697
+
};
698
+
};
699
+
621
700
cpg: clock-controller@11010000 {
622
701
compatible = "renesas,r9a07g044-cpg";
623
702
reg = <0 0x11010000 0 0x10000>;
···
819
740
"ch12", "ch13", "ch14", "ch15";
820
741
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
821
742
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
743
+
clock-names = "main", "register";
822
744
power-domains = <&cpg>;
823
745
resets = <&cpg R9A07G044_DMAC_ARESETN>,
824
746
<&cpg R9A07G044_DMAC_RST_ASYNC>;
747
+
reset-names = "arst", "rst_async";
825
748
#dma-cells = <1>;
826
749
dma-channels = <16>;
827
750
};
+21
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso
+21
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree overlay for the RZ/G2L SMARC EVK with OV5645 camera
4
+
* connected to CSI and CRU enabled.
5
+
*
6
+
* Copyright (C) 2023 Renesas Electronics Corp.
7
+
*/
8
+
9
+
/dts-v1/;
10
+
/plugin/;
11
+
12
+
#include <dt-bindings/gpio/gpio.h>
13
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
14
+
15
+
#define OV5645_PARENT_I2C i2c0
16
+
#include "rz-smarc-cru-csi-ov5645.dtsi"
17
+
18
+
&ov5645 {
19
+
enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>;
20
+
reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
21
+
};
+2
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+2
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
···
746
746
"ch12", "ch13", "ch14", "ch15";
747
747
clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
748
748
<&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
749
+
clock-names = "main", "register";
749
750
power-domains = <&cpg>;
750
751
resets = <&cpg R9A07G054_DMAC_ARESETN>,
751
752
<&cpg R9A07G054_DMAC_RST_ASYNC>;
753
+
reset-names = "arst", "rst_async";
752
754
#dma-cells = <1>;
753
755
dma-channels = <16>;
754
756
};
+80
arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi
+80
arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Common Device Tree for the RZ/G2L SMARC EVK (and alike EVKs) with
4
+
* OV5645 camera connected to CSI and CRU enabled.
5
+
*
6
+
* Copyright (C) 2023 Renesas Electronics Corp.
7
+
*/
8
+
9
+
&{/} {
10
+
ov5645_vdddo_1v8: 1p8v {
11
+
compatible = "regulator-fixed";
12
+
regulator-name = "camera_vdddo";
13
+
regulator-min-microvolt = <1800000>;
14
+
regulator-max-microvolt = <1800000>;
15
+
regulator-always-on;
16
+
};
17
+
18
+
ov5645_vdda_2v8: 2p8v {
19
+
compatible = "regulator-fixed";
20
+
regulator-name = "camera_vdda";
21
+
regulator-min-microvolt = <2800000>;
22
+
regulator-max-microvolt = <2800000>;
23
+
regulator-always-on;
24
+
};
25
+
26
+
ov5645_vddd_1v5: 1p5v {
27
+
compatible = "regulator-fixed";
28
+
regulator-name = "camera_vddd";
29
+
regulator-min-microvolt = <1500000>;
30
+
regulator-max-microvolt = <1500000>;
31
+
regulator-always-on;
32
+
};
33
+
34
+
ov5645_fixed_clk: osc25250-clk {
35
+
compatible = "fixed-clock";
36
+
#clock-cells = <0>;
37
+
clock-frequency = <24000000>;
38
+
};
39
+
};
40
+
41
+
&cru {
42
+
status = "okay";
43
+
};
44
+
45
+
&csi2 {
46
+
status = "okay";
47
+
48
+
ports {
49
+
port@0 {
50
+
csi2_in: endpoint {
51
+
clock-lanes = <0>;
52
+
data-lanes = <1 2>;
53
+
remote-endpoint = <&ov5645_ep>;
54
+
};
55
+
};
56
+
};
57
+
};
58
+
59
+
&OV5645_PARENT_I2C {
60
+
#address-cells = <1>;
61
+
#size-cells = <0>;
62
+
63
+
ov5645: camera@3c {
64
+
compatible = "ovti,ov5645";
65
+
reg = <0x3c>;
66
+
clocks = <&ov5645_fixed_clk>;
67
+
clock-frequency = <24000000>;
68
+
vdddo-supply = <&ov5645_vdddo_1v8>;
69
+
vdda-supply = <&ov5645_vdda_2v8>;
70
+
vddd-supply = <&ov5645_vddd_1v5>;
71
+
72
+
port {
73
+
ov5645_ep: endpoint {
74
+
clock-lanes = <0>;
75
+
data-lanes = <1 2>;
76
+
remote-endpoint = <&csi2_in>;
77
+
};
78
+
};
79
+
};
80
+
};