gpiolib: add support to register sparse pin range

Add support to register for GPIO<->pin mapping using a list of non
consecutive pins. The core already supports sparse pin range (pins member
of struct pinctrl_gpio_range), but it was not possible to register one. If
pins is not NULL the core uses it, otherwise it assumes that a consecutive
pin range was registered and it uses pin_base.

The function gpiochip_add_pin_range() which allocates and fills the struct
pinctrl_gpio_range was renamed to gpiochip_add_pin_range_with_pins() and
the pins parameter was added.

Two new functions were added, gpiochip_add_pin_range() and
gpiochip_add_sparse_pin_range() to register a consecutive or sparse pins
range. Both use gpiochip_add_pin_range_with_pins().

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20250811-aaeon-up-board-pinctrl-support-v9-1-29f0cbbdfb30@bootlin.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

authored by

Thomas Richard and committed by

Bartosz Golaszewski 10 months ago 181fe022 8f5ae30d

+68 -12

2 changed files

expand all

drivers

gpio

gpiolib.c

include

linux

gpio

driver.h

+20 -9

drivers/gpio/gpiolib.c

··· 2349 2349 EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range); 2350 2350 2351 2351 /** 2352 - * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping 2352 + * gpiochip_add_pin_range_with_pins() - add a range for GPIO <-> pin mapping 2353 2353 * @gc: the gpiochip to add the range for 2354 2354 * @pinctl_name: the dev_name() of the pin controller to map to 2355 2355 * @gpio_offset: the start offset in the current gpio_chip number space 2356 2356 * @pin_offset: the start offset in the pin controller number space 2357 + * @pins: the list of non consecutive pins to accumulate in this range (if not 2358 + * NULL, pin_offset is ignored by pinctrl core) 2357 2359 * @npins: the number of pins from the offset of each pin space (GPIO and 2358 2360 * pin controller) to accumulate in this range 2359 2361 * ··· 2367 2365 * Returns: 2368 2366 * 0 on success, or a negative errno on failure. 2369 2367 */ 2370 - int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 2371 - unsigned int gpio_offset, unsigned int pin_offset, 2372 - unsigned int npins) 2368 + int gpiochip_add_pin_range_with_pins(struct gpio_chip *gc, 2369 + const char *pinctl_name, 2370 + unsigned int gpio_offset, 2371 + unsigned int pin_offset, 2372 + unsigned int const *pins, 2373 + unsigned int npins) 2373 2374 { 2374 2375 struct gpio_pin_range *pin_range; 2375 2376 struct gpio_device *gdev = gc->gpiodev; ··· 2390 2385 pin_range->range.name = gc->label; 2391 2386 pin_range->range.base = gdev->base + gpio_offset; 2392 2387 pin_range->range.pin_base = pin_offset; 2388 + pin_range->range.pins = pins; 2393 2389 pin_range->range.npins = npins; 2394 2390 pin_range->pctldev = pinctrl_find_and_add_gpio_range(pinctl_name, 2395 2391 &pin_range->range); ··· 2400 2394 kfree(pin_range); 2401 2395 return ret; 2402 2396 } 2403 - chip_dbg(gc, "created GPIO range %d->%d ==> %s PIN %d->%d\n", 2404 - gpio_offset, gpio_offset + npins - 1, 2405 - pinctl_name, 2406 - pin_offset, pin_offset + npins - 1); 2397 + if (pin_range->range.pins) 2398 + chip_dbg(gc, "created GPIO range %d->%d ==> %s %d sparse PIN range { %d, ... }", 2399 + gpio_offset, gpio_offset + npins - 1, 2400 + pinctl_name, npins, pins[0]); 2401 + else 2402 + chip_dbg(gc, "created GPIO range %d->%d ==> %s PIN %d->%d\n", 2403 + gpio_offset, gpio_offset + npins - 1, 2404 + pinctl_name, 2405 + pin_offset, pin_offset + npins - 1); 2407 2406 2408 2407 list_add_tail(&pin_range->node, &gdev->pin_ranges); 2409 2408 2410 2409 return 0; 2411 2410 } 2412 - EXPORT_SYMBOL_GPL(gpiochip_add_pin_range); 2411 + EXPORT_SYMBOL_GPL(gpiochip_add_pin_range_with_pins); 2413 2412 2414 2413 /** 2415 2414 * gpiochip_remove_pin_ranges() - remove all the GPIO <-> pin mappings

+48 -3

include/linux/gpio/driver.h

··· 772 772 773 773 #ifdef CONFIG_PINCTRL 774 774 775 - int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 776 - unsigned int gpio_offset, unsigned int pin_offset, 777 - unsigned int npins); 775 + int gpiochip_add_pin_range_with_pins(struct gpio_chip *gc, 776 + const char *pinctl_name, 777 + unsigned int gpio_offset, 778 + unsigned int pin_offset, 779 + unsigned int const *pins, 780 + unsigned int npins); 778 781 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 779 782 struct pinctrl_dev *pctldev, 780 783 unsigned int gpio_offset, const char *pin_group); 781 784 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 782 785 786 + static inline int 787 + gpiochip_add_pin_range(struct gpio_chip *gc, 788 + const char *pinctl_name, 789 + unsigned int gpio_offset, 790 + unsigned int pin_offset, 791 + unsigned int npins) 792 + { 793 + return gpiochip_add_pin_range_with_pins(gc, pinctl_name, gpio_offset, 794 + pin_offset, NULL, npins); 795 + } 796 + 797 + static inline int 798 + gpiochip_add_sparse_pin_range(struct gpio_chip *gc, 799 + const char *pinctl_name, 800 + unsigned int gpio_offset, 801 + unsigned int const *pins, 802 + unsigned int npins) 803 + { 804 + return gpiochip_add_pin_range_with_pins(gc, pinctl_name, gpio_offset, 0, 805 + pins, npins); 806 + } 783 807 #else /* ! CONFIG_PINCTRL */ 808 + 809 + static inline int 810 + gpiochip_add_pin_range_with_pins(struct gpio_chip *gc, 811 + const char *pinctl_name, 812 + unsigned int gpio_offset, 813 + unsigned int pin_offset, 814 + unsigned int npins) 815 + { 816 + return 0; 817 + } 784 818 785 819 static inline int 786 820 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, ··· 823 789 { 824 790 return 0; 825 791 } 792 + 793 + static inline int 794 + gpiochip_add_sparse_pin_range(struct gpio_chip *gc, 795 + const char *pinctl_name, 796 + unsigned int gpio_offset, 797 + unsigned int const *pins, 798 + unsigned int npins) 799 + { 800 + return 0; 801 + } 802 + 826 803 static inline int 827 804 gpiochip_add_pingroup_range(struct gpio_chip *gc, 828 805 struct pinctrl_dev *pctldev,

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