Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'edac_updates_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
Pull EDAC updates from Borislav Petkov:
- amd64_edac: Add support for AMD Zen 3 (family 19h, models 40h–4fh)
- i10nm: Add GNR error information decoder support as an alternative to
the firmware decoder
- versalnet: Restructure the init/teardown logic for correct and more
readable error handling. Also, fix two memory leaks and a resource
leak
- Convert several internal structs to use bounded flex arrays, enabling
the kernel's runtime checker to catch out-of-bounds memory accesses
- Mark various sysfs attribute tables read-only, preventing accidental
modification at runtime
- The usual fixes and cleanups across the subsystem
* tag 'edac_updates_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
EDAC/mc: Use kzalloc_flex()
EDAC/ie31200: Make rpl_s_cfg static
EDAC/i10nm: Fix spelling mistake "readd" -> "read"
EDAC/versalnet: Fix device_node leak in mc_probe()
EDAC/versalnet: Fix memory leak in remove and probe error paths
EDAC/amd64: Add support for family 19h, models 40h-4fh
EDAC/i10nm: Add driver decoder for Granite Rapids server
EDAC/sb: Use kzalloc_flex()
EDAC/i7core: Use kzalloc_flex()
EDAC/mpc85xx: Constify device sysfs attributes
EDAC/device: Allow addition of const sysfs attributes
EDAC/pci_sysfs: Constify instance sysfs attributes
EDAC/device: Constify info sysfs attributes
EDAC/device: Drop unnecessary and dangerous casts of attributes
EDAC/device: Drop unused macro to_edacdev_attr()
EDAC/altera: Drop unused field eccmgr_sysfs_attr
EDAC/versalnet: Refactor memory controller initialization and cleanup
+165
-149
-1
drivers/edac/altera_edac.h
-1
drivers/edac/altera_edac.h
+3
drivers/edac/amd64_edac.c
+3
drivers/edac/amd64_edac.c
+1
-1
drivers/edac/edac_device.h
+1
-1
drivers/edac/edac_device.h
···
163
163
* If attributes are desired, then set to array of attributes
164
164
* If no attributes are desired, leave NULL
165
165
*/
166
-
struct edac_dev_sysfs_attribute *sysfs_attributes;
166
+
const struct edac_dev_sysfs_attribute *sysfs_attributes;
167
167
168
168
/* pointer to main 'edac' subsys in sysfs */
169
169
const struct bus_type *edac_subsys;
+10
-14
drivers/edac/edac_device_sysfs.c
+10
-14
drivers/edac/edac_device_sysfs.c
···
21
21
#define EDAC_DEVICE_SYMLINK "device"
22
22
23
23
#define to_edacdev(k) container_of(k, struct edac_device_ctl_info, kobj)
24
-
#define to_edacdev_attr(a) container_of(a, struct edacdev_attribute, attr)
25
-
26
24
27
25
/*
28
26
* Set of edac_device_ctl_info attribute store/show functions
···
109
111
};
110
112
111
113
#define to_ctl_info(k) container_of(k, struct edac_device_ctl_info, kobj)
112
-
#define to_ctl_info_attr(a) container_of(a,struct ctl_info_attribute,attr)
114
+
#define to_ctl_info_attr(a) container_of_const(a, struct ctl_info_attribute, attr)
113
115
114
116
/* Function to 'show' fields from the edac_dev 'ctl_info' structure */
115
117
static ssize_t edac_dev_ctl_info_show(struct kobject *kobj,
116
118
struct attribute *attr, char *buffer)
117
119
{
118
120
struct edac_device_ctl_info *edac_dev = to_ctl_info(kobj);
119
-
struct ctl_info_attribute *ctl_info_attr = to_ctl_info_attr(attr);
121
+
const struct ctl_info_attribute *ctl_info_attr = to_ctl_info_attr(attr);
120
122
121
123
if (ctl_info_attr->show)
122
124
return ctl_info_attr->show(edac_dev, buffer);
···
129
131
const char *buffer, size_t count)
130
132
{
131
133
struct edac_device_ctl_info *edac_dev = to_ctl_info(kobj);
132
-
struct ctl_info_attribute *ctl_info_attr = to_ctl_info_attr(attr);
134
+
const struct ctl_info_attribute *ctl_info_attr = to_ctl_info_attr(attr);
133
135
134
136
if (ctl_info_attr->store)
135
137
return ctl_info_attr->store(edac_dev, buffer, count);
···
143
145
};
144
146
145
147
#define CTL_INFO_ATTR(_name,_mode,_show,_store) \
146
-
static struct ctl_info_attribute attr_ctl_info_##_name = { \
148
+
static const struct ctl_info_attribute attr_ctl_info_##_name = { \
147
149
.attr = {.name = __stringify(_name), .mode = _mode }, \
148
150
.show = _show, \
149
151
.store = _store, \
···
161
163
edac_device_ctl_poll_msec_show, edac_device_ctl_poll_msec_store);
162
164
163
165
/* Base Attributes of the EDAC_DEVICE ECC object */
164
-
static struct attribute *device_ctrl_attrs[] = {
166
+
static const struct attribute *const device_ctrl_attrs[] = {
165
167
&attr_ctl_info_panic_on_ue.attr,
166
168
&attr_ctl_info_log_ue.attr,
167
169
&attr_ctl_info_log_ce.attr,
···
573
575
for (i = 0; i < block->nr_attribs; i++, sysfs_attrib++) {
574
576
575
577
/* remove each block_attrib file */
576
-
sysfs_remove_file(&block->kobj,
577
-
(struct attribute *) sysfs_attrib);
578
+
sysfs_remove_file(&block->kobj, &sysfs_attrib->attr);
578
579
}
579
580
}
580
581
···
723
726
static int edac_device_add_main_sysfs_attributes(
724
727
struct edac_device_ctl_info *edac_dev)
725
728
{
726
-
struct edac_dev_sysfs_attribute *sysfs_attrib;
729
+
const struct edac_dev_sysfs_attribute *sysfs_attrib;
727
730
int err = 0;
728
731
729
732
sysfs_attrib = edac_dev->sysfs_attributes;
···
733
736
*/
734
737
while (sysfs_attrib->attr.name != NULL) {
735
738
err = sysfs_create_file(&edac_dev->kobj,
736
-
(struct attribute*) sysfs_attrib);
739
+
&sysfs_attrib->attr);
737
740
if (err)
738
741
goto err_out;
739
742
···
752
755
static void edac_device_remove_main_sysfs_attributes(
753
756
struct edac_device_ctl_info *edac_dev)
754
757
{
755
-
struct edac_dev_sysfs_attribute *sysfs_attrib;
758
+
const struct edac_dev_sysfs_attribute *sysfs_attrib;
756
759
757
760
/* if there are main attributes, defined, remove them. First,
758
761
* point to the start of the array and iterate over it
···
761
764
sysfs_attrib = edac_dev->sysfs_attributes;
762
765
if (sysfs_attrib) {
763
766
while (sysfs_attrib->attr.name != NULL) {
764
-
sysfs_remove_file(&edac_dev->kobj,
765
-
(struct attribute *) sysfs_attrib);
767
+
sysfs_remove_file(&edac_dev->kobj, &sysfs_attrib->attr);
766
768
sysfs_attrib++;
767
769
}
768
770
}
+3
-7
drivers/edac/edac_mc.c
+3
-7
drivers/edac/edac_mc.c
···
203
203
kfree(mci->csrows);
204
204
}
205
205
kfree(mci->pvt_info);
206
-
kfree(mci->layers);
207
206
kfree(mci);
208
207
}
209
208
···
360
361
per_rank = true;
361
362
}
362
363
363
-
mci = kzalloc_obj(struct mem_ctl_info);
364
+
mci = kzalloc_flex(*mci, layers, n_layers);
364
365
if (!mci)
365
366
return NULL;
366
367
367
-
mci->layers = kzalloc_objs(struct edac_mc_layer, n_layers);
368
-
if (!mci->layers)
369
-
goto error;
368
+
mci->n_layers = n_layers;
369
+
memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
370
370
371
371
mci->dev.release = mci_release;
372
372
device_initialize(&mci->dev);
···
377
379
/* setup index and various internal pointers */
378
380
mci->mc_idx = mc_num;
379
381
mci->tot_dimms = tot_dimms;
380
-
mci->n_layers = n_layers;
381
-
memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
382
382
mci->nr_csrows = tot_csrows;
383
383
mci->num_cschannel = tot_channels;
384
384
mci->csbased = per_rank;
+5
-5
drivers/edac/edac_pci_sysfs.c
+5
-5
drivers/edac/edac_pci_sysfs.c
···
68
68
}
69
69
70
70
#define to_instance(k) container_of(k, struct edac_pci_ctl_info, kobj)
71
-
#define to_instance_attr(a) container_of(a, struct instance_attribute, attr)
71
+
#define to_instance_attr(a) container_of_const(a, struct instance_attribute, attr)
72
72
73
73
/* DEVICE instance kobject release() function */
74
74
static void edac_pci_instance_release(struct kobject *kobj)
···
98
98
struct attribute *attr, char *buffer)
99
99
{
100
100
struct edac_pci_ctl_info *pci = to_instance(kobj);
101
-
struct instance_attribute *instance_attr = to_instance_attr(attr);
101
+
const struct instance_attribute *instance_attr = to_instance_attr(attr);
102
102
103
103
if (instance_attr->show)
104
104
return instance_attr->show(pci, buffer);
···
111
111
const char *buffer, size_t count)
112
112
{
113
113
struct edac_pci_ctl_info *pci = to_instance(kobj);
114
-
struct instance_attribute *instance_attr = to_instance_attr(attr);
114
+
const struct instance_attribute *instance_attr = to_instance_attr(attr);
115
115
116
116
if (instance_attr->store)
117
117
return instance_attr->store(pci, buffer, count);
···
125
125
};
126
126
127
127
#define INSTANCE_ATTR(_name, _mode, _show, _store) \
128
-
static struct instance_attribute attr_instance_##_name = { \
128
+
static const struct instance_attribute attr_instance_##_name = { \
129
129
.attr = {.name = __stringify(_name), .mode = _mode }, \
130
130
.show = _show, \
131
131
.store = _store, \
···
135
135
INSTANCE_ATTR(npe_count, S_IRUGO, instance_npe_count_show, NULL);
136
136
137
137
/* pci instance attributes */
138
-
static struct attribute *pci_instance_attrs[] = {
138
+
static const struct attribute *const pci_instance_attrs[] = {
139
139
&attr_instance_pe_count.attr,
140
140
&attr_instance_npe_count.attr,
141
141
NULL
+15
-1
drivers/edac/i10nm_base.c
+15
-1
drivers/edac/i10nm_base.c
···
196
196
case 8:
197
197
return I10NM_GET_REG64(imc, chan, offset);
198
198
default:
199
-
i10nm_printk(KERN_ERR, "Invalid readd RRL 0x%x width %d\n", offset, width);
199
+
i10nm_printk(KERN_ERR, "Invalid read RRL 0x%x width %d\n", offset, width);
200
200
return 0;
201
201
}
202
202
}
···
580
580
if (bank < 13 || bank > 20)
581
581
return false;
582
582
break;
583
+
case GNR:
584
+
if (bank < 13 || bank > 24)
585
+
return false;
586
+
break;
583
587
default:
584
588
return false;
585
589
}
···
640
636
res->bank_group |= GET_BITFIELD(m->misc, 41, 41) << 2;
641
637
res->rank = GET_BITFIELD(m->misc, 57, 57);
642
638
res->dimm = GET_BITFIELD(m->misc, 58, 58);
639
+
break;
640
+
case GNR:
641
+
res->imc = m->bank - 13;
642
+
res->channel = 0;
643
+
res->column = GET_BITFIELD(m->misc, 9, 18) << 2;
644
+
res->row = GET_BITFIELD(m->misc, 19, 36);
645
+
res->bank_group = GET_BITFIELD(m->misc, 39, 41);
646
+
res->bank_address = GET_BITFIELD(m->misc, 37, 38);
647
+
res->rank = GET_BITFIELD(m->misc, 55, 56);
648
+
res->dimm = GET_BITFIELD(m->misc, 57, 57);
643
649
break;
644
650
default:
645
651
return false;
+4
-11
drivers/edac/i7core_edac.c
+4
-11
drivers/edac/i7core_edac.c
···
240
240
struct i7core_dev {
241
241
struct list_head list;
242
242
u8 socket;
243
-
struct pci_dev **pdev;
244
-
int n_devs;
245
243
struct mem_ctl_info *mci;
244
+
int n_devs;
245
+
struct pci_dev *pdev[] __counted_by(n_devs);
246
246
};
247
247
248
248
struct i7core_pvt {
···
455
455
{
456
456
struct i7core_dev *i7core_dev;
457
457
458
-
i7core_dev = kzalloc_obj(*i7core_dev);
458
+
i7core_dev = kzalloc_flex(*i7core_dev, pdev, table->n_devs);
459
459
if (!i7core_dev)
460
460
return NULL;
461
461
462
-
i7core_dev->pdev = kzalloc_objs(*i7core_dev->pdev, table->n_devs);
463
-
if (!i7core_dev->pdev) {
464
-
kfree(i7core_dev);
465
-
return NULL;
466
-
}
467
-
468
-
i7core_dev->socket = socket;
469
462
i7core_dev->n_devs = table->n_devs;
463
+
i7core_dev->socket = socket;
470
464
list_add_tail(&i7core_dev->list, &i7core_edac_list);
471
465
472
466
return i7core_dev;
···
469
475
static void free_i7core_dev(struct i7core_dev *i7core_dev)
470
476
{
471
477
list_del(&i7core_dev->list);
472
-
kfree(i7core_dev->pdev);
473
478
kfree(i7core_dev);
474
479
}
475
480
+1
-1
drivers/edac/ie31200_edac.c
+1
-1
drivers/edac/ie31200_edac.c
+1
-1
drivers/edac/mpc85xx_edac.c
+1
-1
drivers/edac/mpc85xx_edac.c
+3
-11
drivers/edac/sb_edac.c
+3
-11
drivers/edac/sb_edac.c
···
364
364
int seg;
365
365
u8 bus, mc;
366
366
u8 node_id, source_id;
367
-
struct pci_dev **pdev;
368
367
enum domain dom;
369
368
int n_devs;
370
369
int i_devs;
371
370
struct mem_ctl_info *mci;
371
+
struct pci_dev *pdev[] __counted_by(n_devs);
372
372
};
373
373
374
374
struct knl_pvt {
···
771
771
{
772
772
struct sbridge_dev *sbridge_dev;
773
773
774
-
sbridge_dev = kzalloc_obj(*sbridge_dev);
774
+
sbridge_dev = kzalloc_flex(*sbridge_dev, pdev, table->n_devs_per_imc);
775
775
if (!sbridge_dev)
776
776
return NULL;
777
777
778
-
sbridge_dev->pdev = kzalloc_objs(*sbridge_dev->pdev,
779
-
table->n_devs_per_imc);
780
-
if (!sbridge_dev->pdev) {
781
-
kfree(sbridge_dev);
782
-
return NULL;
783
-
}
784
-
778
+
sbridge_dev->n_devs = table->n_devs_per_imc;
785
779
sbridge_dev->seg = seg;
786
780
sbridge_dev->bus = bus;
787
781
sbridge_dev->dom = dom;
788
-
sbridge_dev->n_devs = table->n_devs_per_imc;
789
782
list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
790
783
791
784
return sbridge_dev;
···
787
794
static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
788
795
{
789
796
list_del(&sbridge_dev->list);
790
-
kfree(sbridge_dev->pdev);
791
797
kfree(sbridge_dev);
792
798
}
793
799
+107
-85
drivers/edac/versalnet_edac.c
+107
-85
drivers/edac/versalnet_edac.c
···
70
70
#define XDDR5_BUS_WIDTH_32 1
71
71
#define XDDR5_BUS_WIDTH_16 2
72
72
73
+
#define MC_NAME_LEN 32
74
+
73
75
/**
74
76
* struct ecc_error_info - ECC error log information.
75
77
* @burstpos: Burst position.
···
762
760
kfree(dev);
763
761
}
764
762
765
-
static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
763
+
static void remove_one_mc(struct mc_priv *priv, int i)
764
+
{
765
+
struct mem_ctl_info *mci;
766
+
767
+
mci = priv->mci[i];
768
+
device_unregister(mci->pdev);
769
+
edac_mc_del_mc(mci->pdev);
770
+
edac_mc_free(mci);
771
+
}
772
+
773
+
static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i)
766
774
{
767
775
u32 num_chans, rank, dwidth, config;
768
776
struct edac_mc_layer layers[2];
···
780
768
struct device *dev;
781
769
enum dev_type dt;
782
770
char *name;
783
-
int rc, i;
771
+
int rc;
784
772
785
-
for (i = 0; i < NUM_CONTROLLERS; i++) {
786
-
config = priv->adec[CONF + i * ADEC_NUM];
787
-
num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
788
-
rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
789
-
dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
773
+
config = priv->adec[CONF + i * ADEC_NUM];
774
+
num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
775
+
rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
776
+
dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
790
777
791
-
switch (dwidth) {
792
-
case XDDR5_BUS_WIDTH_16:
793
-
dt = DEV_X16;
794
-
break;
795
-
case XDDR5_BUS_WIDTH_32:
796
-
dt = DEV_X32;
797
-
break;
798
-
case XDDR5_BUS_WIDTH_64:
799
-
dt = DEV_X64;
800
-
break;
801
-
default:
802
-
dt = DEV_UNKNOWN;
803
-
}
804
-
805
-
if (dt == DEV_UNKNOWN)
806
-
continue;
807
-
808
-
/* Find the first enabled device and register that one. */
809
-
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
810
-
layers[0].size = rank;
811
-
layers[0].is_virt_csrow = true;
812
-
layers[1].type = EDAC_MC_LAYER_CHANNEL;
813
-
layers[1].size = num_chans;
814
-
layers[1].is_virt_csrow = false;
815
-
816
-
rc = -ENOMEM;
817
-
mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers,
818
-
sizeof(struct mc_priv));
819
-
if (!mci) {
820
-
edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
821
-
goto err_alloc;
822
-
}
823
-
824
-
priv->mci[i] = mci;
825
-
priv->dwidth = dt;
826
-
827
-
dev = kzalloc_obj(*dev);
828
-
dev->release = versal_edac_release;
829
-
name = kmalloc(32, GFP_KERNEL);
830
-
sprintf(name, "versal-net-ddrmc5-edac-%d", i);
831
-
dev->init_name = name;
832
-
rc = device_register(dev);
833
-
if (rc)
834
-
goto err_alloc;
835
-
836
-
mci->pdev = dev;
837
-
838
-
platform_set_drvdata(pdev, priv);
839
-
840
-
mc_init(mci, dev);
841
-
rc = edac_mc_add_mc(mci);
842
-
if (rc) {
843
-
edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
844
-
goto err_alloc;
845
-
}
778
+
switch (dwidth) {
779
+
case XDDR5_BUS_WIDTH_16:
780
+
dt = DEV_X16;
781
+
break;
782
+
case XDDR5_BUS_WIDTH_32:
783
+
dt = DEV_X32;
784
+
break;
785
+
case XDDR5_BUS_WIDTH_64:
786
+
dt = DEV_X64;
787
+
break;
788
+
default:
789
+
dt = DEV_UNKNOWN;
846
790
}
791
+
792
+
if (dt == DEV_UNKNOWN)
793
+
return 0;
794
+
795
+
/* Find the first enabled device and register that one. */
796
+
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
797
+
layers[0].size = rank;
798
+
layers[0].is_virt_csrow = true;
799
+
layers[1].type = EDAC_MC_LAYER_CHANNEL;
800
+
layers[1].size = num_chans;
801
+
layers[1].is_virt_csrow = false;
802
+
803
+
rc = -ENOMEM;
804
+
name = kzalloc(MC_NAME_LEN, GFP_KERNEL);
805
+
if (!name)
806
+
return rc;
807
+
808
+
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
809
+
if (!dev)
810
+
goto err_name_free;
811
+
812
+
mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers, sizeof(struct mc_priv));
813
+
if (!mci) {
814
+
edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
815
+
goto err_dev_free;
816
+
}
817
+
818
+
sprintf(name, "versal-net-ddrmc5-edac-%d", i);
819
+
820
+
dev->init_name = name;
821
+
dev->release = versal_edac_release;
822
+
823
+
rc = device_register(dev);
824
+
if (rc)
825
+
goto err_mc_free;
826
+
827
+
mci->pdev = dev;
828
+
mc_init(mci, dev);
829
+
830
+
rc = edac_mc_add_mc(mci);
831
+
if (rc) {
832
+
edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
833
+
goto err_unreg;
834
+
}
835
+
836
+
priv->mci[i] = mci;
837
+
priv->dwidth = dt;
838
+
839
+
platform_set_drvdata(pdev, priv);
840
+
847
841
return 0;
848
842
849
-
err_alloc:
850
-
while (i--) {
851
-
mci = priv->mci[i];
852
-
if (!mci)
853
-
continue;
854
-
855
-
if (mci->pdev) {
856
-
device_unregister(mci->pdev);
857
-
edac_mc_del_mc(mci->pdev);
858
-
}
859
-
860
-
edac_mc_free(mci);
861
-
}
843
+
err_unreg:
844
+
device_unregister(mci->pdev);
845
+
err_mc_free:
846
+
edac_mc_free(mci);
847
+
err_dev_free:
848
+
kfree(dev);
849
+
err_name_free:
850
+
kfree(name);
862
851
863
852
return rc;
864
853
}
865
854
866
-
static void remove_versalnet(struct mc_priv *priv)
855
+
static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
867
856
{
868
-
struct mem_ctl_info *mci;
869
-
int i;
857
+
int rc, i;
870
858
871
859
for (i = 0; i < NUM_CONTROLLERS; i++) {
872
-
device_unregister(priv->mci[i]->pdev);
873
-
mci = edac_mc_del_mc(priv->mci[i]->pdev);
874
-
if (!mci)
875
-
return;
860
+
rc = init_one_mc(priv, pdev, i);
861
+
if (rc) {
862
+
while (i--)
863
+
remove_one_mc(priv, i);
876
864
877
-
edac_mc_free(mci);
865
+
return rc;
866
+
}
878
867
}
868
+
return 0;
869
+
}
870
+
871
+
static void remove_versalnet(struct mc_priv *priv)
872
+
{
873
+
for (int i = 0; i < NUM_CONTROLLERS; i++)
874
+
remove_one_mc(priv, i);
879
875
}
880
876
881
877
static int mc_probe(struct platform_device *pdev)
882
878
{
883
-
struct device_node *r5_core_node;
884
879
struct mc_priv *priv;
885
880
struct rproc *rp;
886
881
int rc;
887
882
888
-
r5_core_node = of_parse_phandle(pdev->dev.of_node, "amd,rproc", 0);
883
+
struct device_node *r5_core_node __free(device_node) =
884
+
of_parse_phandle(pdev->dev.of_node, "amd,rproc", 0);
889
885
if (!r5_core_node) {
890
886
dev_err(&pdev->dev, "amd,rproc: invalid phandle\n");
891
887
return -EINVAL;
···
937
917
938
918
err_init:
939
919
cdx_mcdi_finish(priv->mcdi);
920
+
kfree(priv->mcdi);
940
921
941
922
err_unreg:
942
923
unregister_rpmsg_driver(&amd_rpmsg_driver);
···
959
938
remove_versalnet(priv);
960
939
rproc_shutdown(priv->mcdi->r5_rproc);
961
940
cdx_mcdi_finish(priv->mcdi);
941
+
kfree(priv->mcdi);
962
942
}
963
943
964
944
static const struct of_device_id amd_edac_match[] = {
+12
-11
include/linux/edac.h
+12
-11
include/linux/edac.h
···
541
541
struct csrow_info **csrows;
542
542
unsigned int nr_csrows, num_cschannel;
543
543
544
-
/*
545
-
* Memory Controller hierarchy
546
-
*
547
-
* There are basically two types of memory controller: the ones that
548
-
* sees memory sticks ("dimms"), and the ones that sees memory ranks.
549
-
* All old memory controllers enumerate memories per rank, but most
550
-
* of the recent drivers enumerate memories per DIMM, instead.
551
-
* When the memory controller is per rank, csbased is true.
552
-
*/
553
-
unsigned int n_layers;
554
-
struct edac_mc_layer *layers;
555
544
bool csbased;
556
545
557
546
/*
···
598
609
u8 fake_inject_layer[EDAC_MAX_LAYERS];
599
610
bool fake_inject_ue;
600
611
u16 fake_inject_count;
612
+
613
+
/*
614
+
* Memory Controller hierarchy
615
+
*
616
+
* There are basically two types of memory controller: the ones that
617
+
* sees memory sticks ("dimms"), and the ones that sees memory ranks.
618
+
* All old memory controllers enumerate memories per rank, but most
619
+
* of the recent drivers enumerate memories per DIMM, instead.
620
+
* When the memory controller is per rank, csbased is true.
621
+
*/
622
+
unsigned int n_layers;
623
+
struct edac_mc_layer layers[] __counted_by(n_layers);
601
624
};
602
625
603
626
#define mci_for_each_dimm(mci, dimm) \