Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Nothing stands out, apart from maybe the interesting Eswin EIC7700, a
RISC-V SoC I've never seen before.
Core changes:
- Open code PINCTRL_FUNCTION_DESC() instead of defining a complex
macro only used in one place
- Add pinmux_generic_add_pinfunction() helper and use this in a few
drivers
New drivers:
- Amlogic S7, S7D and S6 pin control support
- Eswin EIC7700 pin control support
- Qualcomm PMIV0104, PM7550 and Milos pin control support
Because of unhelpful numbering schemes, the Qualcomm driver now
needs to start to rely on SoC codenames
- STM32 HDP pin control support
- Mediatek MT8189 pin control support
Improvements:
- Switch remaining pin control drivers over to the new GPIO set
callback that provides a return value
- Support RSVD (reserved) pins in the STM32 driver
- Move many fixed assignments over to pinctrl_desc definitions
- Handle multiple TLMM regions in the Qualcomm driver"
* tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
pinctrl: mediatek: Add pinctrl driver for mt8189
dt-bindings: pinctrl: mediatek: Add support for mt8189
pinctrl: aspeed-g6: Add PCIe RC PERST pin group
pinctrl: ingenic: use pinmux_generic_add_pinfunction()
pinctrl: keembay: use pinmux_generic_add_pinfunction()
pinctrl: mediatek: moore: use pinmux_generic_add_pinfunction()
pinctrl: airoha: use pinmux_generic_add_pinfunction()
pinctrl: equilibrium: use pinmux_generic_add_pinfunction()
pinctrl: provide pinmux_generic_add_pinfunction()
pinctrl: pinmux: open-code PINCTRL_FUNCTION_DESC()
pinctrl: ma35: use new GPIO line value setter callbacks
MAINTAINERS: add Clément Le Goffic as STM32 HDP maintainer
pinctrl: stm32: Introduce HDP driver
dt-bindings: pinctrl: stm32: Introduce HDP
pinctrl: qcom: Add Milos pinctrl driver
dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
pinctrl: qcom: spmi: Add PM7550
dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
pinctrl: qcom: spmi: Add PMIV0104
dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
...
+8736
-558
+8
-1
Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
+8
-1
Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
···
15
15
properties:
16
16
compatible:
17
17
oneOf:
18
-
- const: amlogic,pinctrl-a4
18
+
- enum:
19
+
- amlogic,pinctrl-a4
20
+
- amlogic,pinctrl-s6
21
+
- amlogic,pinctrl-s7
19
22
- items:
20
23
- enum:
21
24
- amlogic,pinctrl-a5
22
25
- const: amlogic,pinctrl-a4
26
+
- items:
27
+
- enum:
28
+
- amlogic,pinctrl-s7d
29
+
- const: amlogic,pinctrl-s7
23
30
24
31
"#address-cells":
25
32
const: 2
+156
Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml
+156
Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/eswin,eic7700-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Eswin Eic7700 Pinctrl
8
+
9
+
maintainers:
10
+
- Yulin Lu <luyulin@eswincomputing.com>
11
+
12
+
allOf:
13
+
- $ref: pinctrl.yaml#
14
+
15
+
description: |
16
+
eic7700 pin configuration nodes act as a container for an arbitrary number of
17
+
subnodes. Each of these subnodes represents some desired configuration for one or
18
+
more pins. This configuration can include the mux function to select on those pin(s),
19
+
and various pin configuration parameters, such as input-enable, pull-up, etc.
20
+
21
+
properties:
22
+
compatible:
23
+
const: eswin,eic7700-pinctrl
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
vrgmii-supply:
29
+
description:
30
+
Regulator supply for the RGMII interface IO power domain.
31
+
This property should reference a regulator that provides either 1.8V or 3.3V,
32
+
depending on the board-level voltage configuration required by the RGMII interface.
33
+
34
+
patternProperties:
35
+
'-grp$':
36
+
type: object
37
+
additionalProperties: false
38
+
39
+
patternProperties:
40
+
'-pins$':
41
+
type: object
42
+
43
+
properties:
44
+
pins:
45
+
description:
46
+
For eic7700, specifies the name(s) of one or more pins to be configured by
47
+
this node.
48
+
items:
49
+
enum: [ chip_mode, mode_set0, mode_set1, mode_set2, mode_set3, xin,
50
+
rst_out_n, key_reset_n, gpio0, por_sel, jtag0_tck, jtag0_tms,
51
+
jtag0_tdi, jtag0_tdo, gpio5, spi2_cs0_n, jtag1_tck, jtag1_tms,
52
+
jtag1_tdi, jtag1_tdo, gpio11, spi2_cs1_n, pcie_clkreq_n,
53
+
pcie_wake_n, pcie_perst_n, hdmi_scl, hdmi_sda, hdmi_cec,
54
+
jtag2_trst, rgmii0_clk_125, rgmii0_txen, rgmii0_txclk,
55
+
rgmii0_txd0, rgmii0_txd1, rgmii0_txd2, rgmii0_txd3, i2s0_bclk,
56
+
i2s0_wclk, i2s0_sdi, i2s0_sdo, i2s_mclk, rgmii0_rxclk,
57
+
rgmii0_rxdv, rgmii0_rxd0, rgmii0_rxd1, rgmii0_rxd2, rgmii0_rxd3,
58
+
i2s2_bclk, i2s2_wclk, i2s2_sdi, i2s2_sdo, gpio27, gpio28, gpio29,
59
+
rgmii0_mdc, rgmii0_mdio, rgmii0_intb, rgmii1_clk_125, rgmii1_txen,
60
+
rgmii1_txclk, rgmii1_txd0, rgmii1_txd1, rgmii1_txd2, rgmii1_txd3,
61
+
i2s1_bclk, i2s1_wclk, i2s1_sdi, i2s1_sdo, gpio34, rgmii1_rxclk,
62
+
rgmii1_rxdv, rgmii1_rxd0, rgmii1_rxd1, rgmii1_rxd2, rgmii1_rxd3,
63
+
spi1_cs0_n, spi1_clk, spi1_d0, spi1_d1, spi1_d2, spi1_d3, spi1_cs1_n,
64
+
rgmii1_mdc, rgmii1_mdio, rgmii1_intb, usb0_pwren, usb1_pwren,
65
+
i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c2_scl, i2c2_sda,
66
+
i2c3_scl, i2c3_sda, i2c4_scl, i2c4_sda, i2c5_scl, i2c5_sda,
67
+
uart0_tx, uart0_rx, uart1_tx, uart1_rx, uart1_cts, uart1_rts,
68
+
uart2_tx, uart2_rx, jtag2_tck, jtag2_tms, jtag2_tdi, jtag2_tdo,
69
+
fan_pwm, fan_tach, mipi_csi0_xvs, mipi_csi0_xhs, mipi_csi0_mclk,
70
+
mipi_csi1_xvs, mipi_csi1_xhs, mipi_csi1_mclk, mipi_csi2_xvs,
71
+
mipi_csi2_xhs, mipi_csi2_mclk, mipi_csi3_xvs, mipi_csi3_xhs,
72
+
mipi_csi3_mclk, mipi_csi4_xvs, mipi_csi4_xhs, mipi_csi4_mclk,
73
+
mipi_csi5_xvs, mipi_csi5_xhs, mipi_csi5_mclk, spi3_cs_n, spi3_clk,
74
+
spi3_di, spi3_do, gpio92, gpio93, s_mode, gpio95, spi0_cs_n,
75
+
spi0_clk, spi0_d0, spi0_d1, spi0_d2, spi0_d3, i2c10_scl,
76
+
i2c10_sda, i2c11_scl, i2c11_sda, gpio106, boot_sel0, boot_sel1,
77
+
boot_sel2, boot_sel3, gpio111, lpddr_ref_clk ]
78
+
79
+
function:
80
+
description:
81
+
Specify the alternative function to be configured for the
82
+
given pins.
83
+
enum: [ disabled, boot_sel, chip_mode, emmc, fan_tach,
84
+
gpio, hdmi, i2c, i2s, jtag, ddr_ref_clk_sel,
85
+
lpddr_ref_clk, mipi_csi, osc, pcie, pwm,
86
+
rgmii, reset, sata, sdio, spi, s_mode, uart, usb ]
87
+
88
+
input-schmitt-enable: true
89
+
90
+
input-schmitt-disable: true
91
+
92
+
bias-disable: true
93
+
94
+
bias-pull-down: true
95
+
96
+
bias-pull-up: true
97
+
98
+
input-enable: true
99
+
100
+
input-disable: true
101
+
102
+
drive-strength-microamp: true
103
+
104
+
required:
105
+
- pins
106
+
107
+
additionalProperties: false
108
+
109
+
allOf:
110
+
- $ref: pincfg-node.yaml#
111
+
- $ref: pinmux-node.yaml#
112
+
113
+
- if:
114
+
properties:
115
+
pins:
116
+
anyOf:
117
+
- pattern: '^rgmii'
118
+
- const: lpddr_ref_clk
119
+
then:
120
+
properties:
121
+
drive-strength-microamp:
122
+
enum: [3000, 6000, 9000, 12000, 15000, 18000, 21000, 24000]
123
+
else:
124
+
properties:
125
+
drive-strength-microamp:
126
+
enum: [6000, 9000, 12000, 15000, 18000, 21000, 24000, 27000]
127
+
128
+
required:
129
+
- compatible
130
+
- reg
131
+
132
+
unevaluatedProperties: false
133
+
134
+
examples:
135
+
- |
136
+
pinctrl@51600080 {
137
+
compatible = "eswin,eic7700-pinctrl";
138
+
reg = <0x51600080 0x1fff80>;
139
+
vrgmii-supply = <&vcc_1v8>;
140
+
141
+
dev-active-grp {
142
+
/* group node defining 1 standard pin */
143
+
gpio10-pins {
144
+
pins = "jtag1_tdo";
145
+
function = "gpio";
146
+
input-enable;
147
+
bias-pull-up;
148
+
};
149
+
150
+
/* group node defining 2 I2C pins */
151
+
i2c6-pins {
152
+
pins = "uart1_cts", "uart1_rts";
153
+
function = "i2c";
154
+
};
155
+
};
156
+
};
+213
Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml
+213
Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MT8189 Pin Controller
8
+
9
+
maintainers:
10
+
- Lei Xue <lei.xue@mediatek.com>
11
+
- Cathy Xu <ot_cathy.xu@mediatek.com>
12
+
13
+
description:
14
+
The MediaTek's MT8189 Pin controller is used to control SoC pins.
15
+
16
+
properties:
17
+
compatible:
18
+
const: mediatek,mt8189-pinctrl
19
+
20
+
reg:
21
+
items:
22
+
- description: gpio base
23
+
- description: lm group IO
24
+
- description: rb0 group IO
25
+
- description: rb1 group IO
26
+
- description: bm0 group IO
27
+
- description: bm1 group IO
28
+
- description: bm2 group IO
29
+
- description: lt0 group IO
30
+
- description: lt1 group IO
31
+
- description: rt group IO
32
+
- description: eint0 group IO
33
+
- description: eint1 group IO
34
+
- description: eint2 group IO
35
+
- description: eint3 group IO
36
+
- description: eint4 group IO
37
+
38
+
reg-names:
39
+
items:
40
+
- const: base
41
+
- const: lm
42
+
- const: rb0
43
+
- const: rb1
44
+
- const: bm0
45
+
- const: bm1
46
+
- const: bm2
47
+
- const: lt0
48
+
- const: lt1
49
+
- const: rt
50
+
- const: eint0
51
+
- const: eint1
52
+
- const: eint2
53
+
- const: eint3
54
+
- const: eint4
55
+
56
+
interrupts:
57
+
maxItems: 1
58
+
59
+
interrupt-controller: true
60
+
61
+
'#interrupt-cells':
62
+
const: 2
63
+
64
+
gpio-controller: true
65
+
66
+
'#gpio-cells':
67
+
const: 2
68
+
69
+
gpio-ranges:
70
+
maxItems: 1
71
+
72
+
gpio-line-names: true
73
+
74
+
# PIN CONFIGURATION NODES
75
+
patternProperties:
76
+
'-pins$':
77
+
type: object
78
+
additionalProperties: false
79
+
80
+
patternProperties:
81
+
'^pins':
82
+
type: object
83
+
$ref: /schemas/pinctrl/pincfg-node.yaml
84
+
additionalProperties: false
85
+
description:
86
+
A pinctrl node should contain at least one subnode representing the
87
+
pinctrl groups available on the machine. Each subnode will list the
88
+
pins it needs, and how they should be configured, with regard to muxer
89
+
configuration, pullups, drive strength, input enable/disable and input
90
+
schmitt.
91
+
92
+
properties:
93
+
pinmux:
94
+
description:
95
+
Integer array, represents gpio pin number and mux setting.
96
+
Supported pin number and mux varies for different SoCs, and are
97
+
defined as macros in arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
98
+
directly, for this SoC.
99
+
100
+
drive-strength:
101
+
enum: [2, 4, 6, 8, 10, 12, 14, 16]
102
+
103
+
bias-pull-down:
104
+
oneOf:
105
+
- type: boolean
106
+
- enum: [100, 101, 102, 103]
107
+
description: mt8189 pull down PUPD/R0/R1 type define value.
108
+
- enum: [75000, 5000]
109
+
description: mt8189 pull down RSEL type si unit value(ohm).
110
+
description: |
111
+
For pull down type is normal, it doesn't need add R1R0 define
112
+
and resistance value.
113
+
114
+
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
115
+
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
116
+
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
117
+
"MTK_PUPD_SET_R1R0_11" define in mt8189.
118
+
119
+
For pull down type is PD/RSEL, it can add resistance value(ohm)
120
+
to set different resistance by identifying property
121
+
"mediatek,rsel-resistance-in-si-unit".
122
+
123
+
bias-pull-up:
124
+
oneOf:
125
+
- type: boolean
126
+
- enum: [100, 101, 102, 103]
127
+
description: mt8189 pull up PUPD/R0/R1 type define value.
128
+
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
129
+
description: mt8189 pull up RSEL type si unit value(ohm).
130
+
description: |
131
+
For pull up type is normal, it don't need add R1R0 define
132
+
and resistance value.
133
+
134
+
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
135
+
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
136
+
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
137
+
"MTK_PUPD_SET_R1R0_11" define in mt8189.
138
+
139
+
For pull up type is PU/RSEL, it can add resistance value(ohm)
140
+
to set different resistance by identifying property
141
+
"mediatek,rsel-resistance-in-si-unit".
142
+
143
+
bias-disable: true
144
+
145
+
output-high: true
146
+
147
+
output-low: true
148
+
149
+
input-enable: true
150
+
151
+
input-disable: true
152
+
153
+
input-schmitt-enable: true
154
+
155
+
input-schmitt-disable: true
156
+
157
+
required:
158
+
- pinmux
159
+
160
+
required:
161
+
- compatible
162
+
- reg
163
+
- interrupts
164
+
- interrupt-controller
165
+
- '#interrupt-cells'
166
+
- gpio-controller
167
+
- '#gpio-cells'
168
+
- gpio-ranges
169
+
170
+
additionalProperties: false
171
+
172
+
examples:
173
+
- |
174
+
#include <dt-bindings/pinctrl/mt65xx.h>
175
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
176
+
#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
177
+
#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
178
+
179
+
pio: pinctrl@10005000 {
180
+
compatible = "mediatek,mt8189-pinctrl";
181
+
reg = <0x10005000 0x1000>,
182
+
<0x11b50000 0x1000>,
183
+
<0x11c50000 0x1000>,
184
+
<0x11c60000 0x1000>,
185
+
<0x11d20000 0x1000>,
186
+
<0x11d30000 0x1000>,
187
+
<0x11d40000 0x1000>,
188
+
<0x11e20000 0x1000>,
189
+
<0x11e30000 0x1000>,
190
+
<0x11f20000 0x1000>,
191
+
<0x11ce0000 0x1000>,
192
+
<0x11de0000 0x1000>,
193
+
<0x11e60000 0x1000>,
194
+
<0x1c01e000 0x1000>,
195
+
<0x11f00000 0x1000>;
196
+
reg-names = "base", "lm", "rb0", "rb1", "bm0" , "bm1",
197
+
"bm2", "lt0", "lt1", "rt", "eint0", "eint1",
198
+
"eint2", "eint3", "eint4";
199
+
gpio-controller;
200
+
#gpio-cells = <2>;
201
+
gpio-ranges = <&pio 0 0 182>;
202
+
interrupt-controller;
203
+
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
204
+
#interrupt-cells = <2>;
205
+
206
+
i2c0-pins {
207
+
pins {
208
+
pinmux = <PINMUX_GPIO51__FUNC_SCL0>,
209
+
<PINMUX_GPIO52__FUNC_SDA0>;
210
+
bias-disable;
211
+
};
212
+
};
213
+
};
-71
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
-71
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
···
1
-
NXP LPC18xx/43xx SCU pin controller Device Tree Bindings
2
-
--------------------------------------------------------
3
-
4
-
Required properties:
5
-
- compatible : Should be "nxp,lpc1850-scu"
6
-
- reg : Address and length of the register set for the device
7
-
- clocks : Clock specifier (see clock bindings for details)
8
-
9
-
The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10
-
configuration documented in pinctrl-bindings.txt.
11
-
12
-
The following generic nodes are supported:
13
-
- function
14
-
- pins
15
-
- bias-disable
16
-
- bias-pull-up
17
-
- bias-pull-down
18
-
- drive-strength
19
-
- input-enable
20
-
- input-disable
21
-
- input-schmitt-enable
22
-
- input-schmitt-disable
23
-
- slew-rate
24
-
25
-
NXP specific properties:
26
-
- nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller
27
-
irq number 0 to 7. See example below.
28
-
29
-
Not all pins support all properties so either refer to the NXP 1850/4350
30
-
user manual or the pin table in the pinctrl-lpc18xx driver for supported
31
-
pin properties.
32
-
33
-
Example:
34
-
pinctrl: pinctrl@40086000 {
35
-
compatible = "nxp,lpc1850-scu";
36
-
reg = <0x40086000 0x1000>;
37
-
clocks = <&ccu1 CLK_CPU_SCU>;
38
-
39
-
i2c0_pins: i2c0-pins {
40
-
i2c0_pins_cfg {
41
-
pins = "i2c0_scl", "i2c0_sda";
42
-
function = "i2c0";
43
-
input-enable;
44
-
};
45
-
};
46
-
47
-
uart0_pins: uart0-pins {
48
-
uart0_rx_cfg {
49
-
pins = "pf_11";
50
-
function = "uart0";
51
-
bias-disable;
52
-
input-enable;
53
-
};
54
-
55
-
uart0_tx_cfg {
56
-
pins = "pf_10";
57
-
function = "uart0";
58
-
bias-disable;
59
-
};
60
-
};
61
-
62
-
gpio_joystick_pins: gpio-joystick-pins {
63
-
gpio_joystick_1_cfg {
64
-
pins = "p9_0";
65
-
function = "gpio";
66
-
nxp,gpio-pin-interrupt = <0>;
67
-
input-enable;
68
-
bias-disable;
69
-
};
70
-
};
71
-
};
+79
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.yaml
+79
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP LPC18xx/43xx SCU pin controller
8
+
9
+
description:
10
+
Not all pins support all pin generic node properties so either refer to
11
+
the NXP 1850/4350 user manual or the pin table in the pinctrl-lpc18xx
12
+
driver for supported pin properties.
13
+
14
+
maintainers:
15
+
- Frank Li <Frank.Li@nxp.com>
16
+
17
+
properties:
18
+
compatible:
19
+
const: nxp,lpc1850-scu
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
maxItems: 1
26
+
27
+
patternProperties:
28
+
'-pins$':
29
+
type: object
30
+
additionalProperties: false
31
+
32
+
patternProperties:
33
+
'_cfg$':
34
+
type: object
35
+
36
+
allOf:
37
+
- $ref: pincfg-node.yaml#
38
+
- $ref: pinmux-node.yaml#
39
+
40
+
unevaluatedProperties: false
41
+
42
+
properties:
43
+
nxp,gpio-pin-interrupt:
44
+
$ref: /schemas/types.yaml#/definitions/uint32
45
+
minimum: 0
46
+
maximum: 7
47
+
description:
48
+
Assign pin to gpio pin interrupt controller
49
+
irq number 0 to 7. See example below.
50
+
51
+
required:
52
+
- compatible
53
+
- reg
54
+
- clocks
55
+
56
+
allOf:
57
+
- $ref: pinctrl.yaml#
58
+
59
+
unevaluatedProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/clock/lpc18xx-ccu.h>
64
+
65
+
pinctrl@40086000 {
66
+
compatible = "nxp,lpc1850-scu";
67
+
reg = <0x40086000 0x1000>;
68
+
clocks = <&ccu1 CLK_CPU_SCU>;
69
+
70
+
gpio-joystick-pins {
71
+
gpio-joystick-1_cfg {
72
+
pins = "p9_0";
73
+
function = "gpio";
74
+
nxp,gpio-pin-interrupt = <0>;
75
+
input-enable;
76
+
bias-disable;
77
+
};
78
+
};
79
+
};
+133
Documentation/devicetree/bindings/pinctrl/qcom,milos-tlmm.yaml
+133
Documentation/devicetree/bindings/pinctrl/qcom,milos-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,milos-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. Milos TLMM block
8
+
9
+
maintainers:
10
+
- Luca Weiss <luca.weiss@fairphone.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm Milos SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,milos-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges:
29
+
minItems: 1
30
+
maxItems: 84
31
+
32
+
gpio-line-names:
33
+
maxItems: 167
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-milos-tlmm-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-milos-tlmm-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-milos-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
oneOf:
60
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-7])$"
61
+
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
70
+
audio_ext_mclk1, audio_ref_clk, cam_mclk, cci_async_in0,
71
+
cci_i2c_scl, cci_i2c_sda, cci_timer, coex_uart1_rx,
72
+
coex_uart1_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
73
+
ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot,
74
+
egpio, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2s0_data0,
75
+
i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
76
+
mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
77
+
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req_n,
78
+
pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
79
+
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
80
+
qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss,
81
+
qlink1_enable, qlink1_request, qlink1_wmss, qspi0, qup0_se0,
82
+
qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, qup0_se6,
83
+
qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
84
+
qup1_se6, resout_gpio_n, sd_write_protect, sdc1_clk, sdc1_cmd,
85
+
sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data,
86
+
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tgu_ch0_trigout,
87
+
tgu_ch1_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
88
+
tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
89
+
uim0_present, uim0_reset, uim1_clk_mira, uim1_clk_mirb,
90
+
uim1_data_mira, uim1_data_mirb, uim1_present_mira,
91
+
uim1_present_mirb, uim1_reset_mira, uim1_reset_mirb, usb0_hs,
92
+
usb0_phy_ps, vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw,
93
+
wcn_sw_ctrl ]
94
+
95
+
required:
96
+
- pins
97
+
98
+
required:
99
+
- compatible
100
+
- reg
101
+
102
+
unevaluatedProperties: false
103
+
104
+
examples:
105
+
- |
106
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
107
+
tlmm: pinctrl@f100000 {
108
+
compatible = "qcom,milos-tlmm";
109
+
reg = <0x0f100000 0x300000>;
110
+
111
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
112
+
113
+
gpio-controller;
114
+
#gpio-cells = <2>;
115
+
116
+
interrupt-controller;
117
+
#interrupt-cells = <2>;
118
+
119
+
gpio-ranges = <&tlmm 0 0 168>;
120
+
121
+
gpio-wo-state {
122
+
pins = "gpio1";
123
+
function = "gpio";
124
+
};
125
+
126
+
qup-uart5-default-state {
127
+
pins = "gpio25", "gpio26";
128
+
function = "qup0_se5";
129
+
drive-strength = <2>;
130
+
bias-disable;
131
+
};
132
+
};
133
+
...
+4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
···
27
27
- qcom,pm6450-gpio
28
28
- qcom,pm7250b-gpio
29
29
- qcom,pm7325-gpio
30
+
- qcom,pm7550-gpio
30
31
- qcom,pm7550ba-gpio
31
32
- qcom,pm8005-gpio
32
33
- qcom,pm8018-gpio
···
65
64
- qcom,pmi8994-gpio
66
65
- qcom,pmi8998-gpio
67
66
- qcom,pmih0108-gpio
67
+
- qcom,pmiv0104-gpio
68
68
- qcom,pmk8350-gpio
69
69
- qcom,pmk8550-gpio
70
70
- qcom,pmm8155au-gpio
···
230
228
- qcom,pmc8180-gpio
231
229
- qcom,pmc8380-gpio
232
230
- qcom,pmi8994-gpio
231
+
- qcom,pmiv0104-gpio
233
232
- qcom,pmm8155au-gpio
234
233
then:
235
234
properties:
···
264
261
- qcom,pm660l-gpio
265
262
- qcom,pm6150l-gpio
266
263
- qcom,pm7250b-gpio
264
+
- qcom,pm7550-gpio
267
265
- qcom,pm8038-gpio
268
266
- qcom,pm8150b-gpio
269
267
- qcom,pm8150l-gpio
+1
-1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+187
Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
+187
Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright (C) STMicroelectronics 2025.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: STM32 Hardware Debug Port Mux/Config
9
+
10
+
maintainers:
11
+
- Clément LE GOFFIC <legoffic.clement@gmail.com>
12
+
13
+
description:
14
+
STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP).
15
+
It allows to output internal signals on SoC's GPIO.
16
+
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- st,stm32mp131-hdp
21
+
- st,stm32mp151-hdp
22
+
- st,stm32mp251-hdp
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
maxItems: 1
29
+
30
+
patternProperties:
31
+
"^hdp[0-7]-pins$":
32
+
type: object
33
+
$ref: pinmux-node.yaml#
34
+
additionalProperties: false
35
+
36
+
properties:
37
+
pins:
38
+
pattern: '^HDP[0-7]$'
39
+
40
+
function: true
41
+
42
+
required:
43
+
- function
44
+
- pins
45
+
46
+
allOf:
47
+
- $ref: pinctrl.yaml#
48
+
- if:
49
+
properties:
50
+
compatible:
51
+
contains:
52
+
const: st,stm32mp131-hdp
53
+
then:
54
+
patternProperties:
55
+
"^hdp[0-7]-pins$":
56
+
properties:
57
+
function:
58
+
enum: [ pwr_pwrwake_sys, pwr_stop_forbidden, pwr_stdby_wakeup, pwr_encomp_vddcore,
59
+
bsec_out_sec_niden, aiec_sys_wakeup, none, ddrctrl_lp_req,
60
+
pwr_ddr_ret_enable_n, dts_clk_ptat, sram3ctrl_tamp_erase_act, gpoval0,
61
+
pwr_sel_vth_vddcpu, pwr_mpu_ram_lowspeed, ca7_naxierrirq, pwr_okin_mr,
62
+
bsec_out_sec_dbgen, aiec_c1_wakeup, rcc_pwrds_mpu, ddrctrl_dfi_ctrlupd_req,
63
+
ddrctrl_cactive_ddrc_asr, sram3ctrl_hw_erase_act, nic400_s0_bready, gpoval1,
64
+
pwr_pwrwake_mpu, pwr_mpu_clock_disable_ack, ca7_ndbgreset_i,
65
+
bsec_in_rstcore_n, bsec_out_sec_bsc_dis, ddrctrl_dfi_init_complete,
66
+
ddrctrl_perf_op_is_refresh, ddrctrl_gskp_dfi_lp_req, sram3ctrl_sw_erase_act,
67
+
nic400_s0_bvalid, gpoval2, pwr_sel_vth_vddcore, pwr_mpu_clock_disable_req,
68
+
ca7_npmuirq0, ca7_nfiqout0, bsec_out_sec_dftlock, bsec_out_sec_jtag_dis,
69
+
rcc_pwrds_sys, sram3ctrl_tamp_erase_req, ddrctrl_stat_ddrc_reg_selfref_type0,
70
+
dts_valobus1_0, dts_valobus2_0, tamp_potential_tamp_erfcfg, nic400_s0_wready,
71
+
nic400_s0_rready, gpoval3, pwr_stop2_active, ca7_nl2reset_i,
72
+
ca7_npreset_varm_i, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
73
+
eth1_out_pmt_intr_o, eth2_out_pmt_intr_o, ddrctrl_stat_ddrc_reg_selfref_type1,
74
+
ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, tamp_nreset_sram_ercfg,
75
+
nic400_s0_wlast, nic400_s0_rlast, gpoval4, ca7_standbywfil2,
76
+
pwr_vth_vddcore_ack, ca7_ncorereset_i, ca7_nirqout0, bsec_in_pwrok,
77
+
bsec_out_sec_deviceen, eth1_out_lpi_intr_o, eth2_out_lpi_intr_o,
78
+
ddrctrl_cactive_ddrc, ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2,
79
+
pka_pka_itamp_out, nic400_s0_wvalid, nic400_s0_rvalid, gpoval5,
80
+
ca7_standbywfe0, pwr_vth_vddcpu_ack, ca7_evento, bsec_in_tamper_det,
81
+
bsec_out_sec_spniden, eth1_out_mac_speed_o1, eth2_out_mac_speed_o1,
82
+
ddrctrl_csysack_ddrc, ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3,
83
+
saes_tamper_out, nic400_s0_awready, nic400_s0_arready, gpoval6,
84
+
ca7_standbywfi0, pwr_rcc_vcpu_rdy, ca7_eventi, ca7_dbgack0, bsec_out_fuse_ok,
85
+
bsec_out_sec_spiden, eth1_out_mac_speed_o0, eth2_out_mac_speed_o0,
86
+
ddrctrl_csysreq_ddrc, ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4,
87
+
rng_tamper_out, nic400_s0_awavalid, nic400_s0_aravalid, gpoval7 ]
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
const: st,stm32mp151-hdp
93
+
then:
94
+
patternProperties:
95
+
"^hdp[0-7]-pins$":
96
+
properties:
97
+
function:
98
+
enum: [ pwr_pwrwake_sys, cm4_sleepdeep, pwr_stdby_wkup, pwr_encomp_vddcore,
99
+
bsec_out_sec_niden, none, rcc_cm4_sleepdeep, gpu_dbg7, ddrctrl_lp_req,
100
+
pwr_ddr_ret_enable_n, dts_clk_ptat, gpoval0, pwr_pwrwake_mcu, cm4_halted,
101
+
ca7_naxierrirq, pwr_okin_mr, bsec_out_sec_dbgen, exti_sys_wakeup,
102
+
rcc_pwrds_mpu, gpu_dbg6, ddrctrl_dfi_ctrlupd_req, ddrctrl_cactive_ddrc_asr,
103
+
gpoval1, pwr_pwrwake_mpu, cm4_rxev, ca7_npmuirq1, ca7_nfiqout1,
104
+
bsec_in_rstcore_n, exti_c2_wakeup, rcc_pwrds_mcu, gpu_dbg5,
105
+
ddrctrl_dfi_init_complete, ddrctrl_perf_op_is_refresh,
106
+
ddrctrl_gskp_dfi_lp_req, gpoval2, pwr_sel_vth_vddcore, cm4_txev, ca7_npmuirq0,
107
+
ca7_nfiqout0, bsec_out_sec_dftlock, exti_c1_wakeup, rcc_pwrds_sys, gpu_dbg4,
108
+
ddrctrl_stat_ddrc_reg_selfref_type0, ddrctrl_cactive_1, dts_valobus1_0,
109
+
dts_valobus2_0, gpoval3, pwr_mpu_pdds_not_cstbydis, cm4_sleeping, ca7_nreset1,
110
+
ca7_nirqout1, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
111
+
eth_out_pmt_intr_o, gpu_dbg3, ddrctrl_stat_ddrc_reg_selfref_type1,
112
+
ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, gpoval4, ca7_standbywfil2,
113
+
pwr_vth_vddcore_ack, ca7_nreset0, ca7_nirqout0, bsec_in_pwrok,
114
+
bsec_out_sec_deviceen, eth_out_lpi_intr_o, gpu_dbg2, ddrctrl_cactive_ddrc,
115
+
ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, gpoval5,
116
+
ca7_standbywfi1, ca7_standbywfe1, ca7_evento, ca7_dbgack1,
117
+
bsec_out_sec_spniden, eth_out_mac_speed_o1, gpu_dbg1, ddrctrl_csysack_ddrc,
118
+
ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, gpoval6,
119
+
ca7_standbywfi0, ca7_standbywfe0, ca7_dbgack0, bsec_out_fuse_ok,
120
+
bsec_out_sec_spiden, eth_out_mac_speed_o0, gpu_dbg0, ddrctrl_csysreq_ddrc,
121
+
ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, gpoval7 ]
122
+
- if:
123
+
properties:
124
+
compatible:
125
+
contains:
126
+
const: st,stm32mp251-hdp
127
+
then:
128
+
patternProperties:
129
+
"^hdp[0-7]-pins$":
130
+
properties:
131
+
function:
132
+
enum: [ pwr_pwrwake_sys, cpu2_sleep_deep, bsec_out_tst_sdr_unlock_or_disable_scan,
133
+
bsec_out_nidenm, bsec_out_nidena, cpu2_state_0, rcc_pwrds_sys, gpu_dbg7,
134
+
ddrss_csysreq_ddrc, ddrss_dfi_phyupd_req, cpu3_sleep_deep,
135
+
d2_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_0,
136
+
pcie_usb_cxpl_debug_info_ei_8, d3_state_0, gpoval0, pwr_pwrwake_cpu2,
137
+
cpu2_halted, cpu2_state_1, bsec_out_dbgenm, bsec_out_dbgena, exti1_sys_wakeup,
138
+
rcc_pwrds_cpu2, gpu_dbg6, ddrss_csysack_ddrc, ddrss_dfi_phymstr_req,
139
+
cpu3_halted, d2_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_1,
140
+
pcie_usb_cxpl_debug_info_ei_9, d3_state_1, gpoval1, pwr_pwrwake_cpu1,
141
+
cpu2_rxev, cpu1_npumirq1, cpu1_nfiqout1, bsec_out_shdbgen, exti1_cpu2_wakeup,
142
+
rcc_pwrds_cpu1, gpu_dbg5, ddrss_cactive_ddrc, ddrss_dfi_lp_req, cpu3_rxev,
143
+
hpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_2,
144
+
pcie_usb_cxpl_debug_info_ei_10, d3_state_2, gpoval2, pwr_sel_vth_vddcpu,
145
+
cpu2_txev, cpu1_npumirq0, cpu1_nfiqout0, bsec_out_ddbgen, exti1_cpu1_wakeup,
146
+
cpu3_state_0, gpu_dbg4, ddrss_mcdcg_en, ddrss_dfi_freq_0, cpu3_txev,
147
+
hpdma2_clk_bus_req, pcie_usb_cxpl_debug_info_ei_3,
148
+
pcie_usb_cxpl_debug_info_ei_11, d1_state_0, gpoval3, pwr_sel_vth_vddcore,
149
+
cpu2_sleeping, cpu1_evento, cpu1_nirqout1, bsec_out_spnidena, exti2_d3_wakeup,
150
+
eth1_out_pmt_intr_o, gpu_dbg3, ddrss_dphycg_en, ddrss_obsp0, cpu3_sleeping,
151
+
hpdma3_clk_bus_req, pcie_usb_cxpl_debug_info_ei_4,
152
+
pcie_usb_cxpl_debug_info_ei_12, d1_state_1, gpoval4, cpu1_standby_wfil2,
153
+
none, cpu1_nirqout0, bsec_out_spidena, exti2_cpu3_wakeup, eth1_out_lpi_intr_o,
154
+
gpu_dbg2, ddrctrl_dfi_init_start, ddrss_obsp1, cpu3_state_1,
155
+
d3_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_5,
156
+
pcie_usb_cxpl_debug_info_ei_13, d1_state_2, gpoval5, cpu1_standby_wfi1,
157
+
cpu1_standby_wfe1, cpu1_halted1, cpu1_naxierrirq, bsec_out_spnidenm,
158
+
exti2_cpu2_wakeup, eth2_out_pmt_intr_o, gpu_dbg1, ddrss_dfi_init_complete,
159
+
ddrss_obsp2, d2_state_0, d3_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_6,
160
+
pcie_usb_cxpl_debug_info_ei_14, cpu1_state_0, gpoval6, cpu1_standby_wfi0,
161
+
cpu1_standby_wfe0, cpu1_halted0, bsec_out_spidenm, exti2_cpu1__wakeup,
162
+
eth2_out_lpi_intr_o, gpu_dbg0, ddrss_dfi_ctrlupd_req, ddrss_obsp3, d2_state_1,
163
+
lpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_7,
164
+
pcie_usb_cxpl_debug_info_ei_15, cpu1_state_1, gpoval7 ]
165
+
166
+
required:
167
+
- compatible
168
+
- reg
169
+
- clocks
170
+
171
+
additionalProperties: false
172
+
173
+
examples:
174
+
- |
175
+
#include <dt-bindings/clock/stm32mp1-clks.h>
176
+
177
+
pinctrl@54090000 {
178
+
compatible = "st,stm32mp151-hdp";
179
+
reg = <0x54090000 0x400>;
180
+
clocks = <&rcc HDP>;
181
+
pinctrl-names = "default";
182
+
pinctrl-0 = <&hdp2_gpo>;
183
+
hdp2_gpo: hdp2-pins {
184
+
function = "gpoval2";
185
+
pins = "HDP2";
186
+
};
187
+
};
+25
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+25
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
···
32
32
33
33
'#address-cells':
34
34
const: 1
35
+
35
36
'#size-cells':
36
37
const: 1
37
38
38
39
ranges: true
40
+
39
41
pins-are-numbered:
40
42
$ref: /schemas/types.yaml#/definitions/flag
41
43
deprecated: true
44
+
42
45
hwlocks: true
43
46
44
47
interrupts:
···
70
67
additionalProperties: false
71
68
properties:
72
69
gpio-controller: true
70
+
73
71
'#gpio-cells':
74
72
const: 2
73
+
75
74
interrupt-controller: true
76
75
'#interrupt-cells':
77
76
const: 2
78
77
79
78
reg:
80
79
maxItems: 1
80
+
81
81
clocks:
82
82
maxItems: 1
83
+
83
84
resets:
84
85
maxItems: 1
86
+
85
87
gpio-line-names: true
88
+
86
89
gpio-ranges:
87
90
minItems: 1
88
91
maxItems: 16
92
+
89
93
ngpios:
90
94
description:
91
95
Number of available gpios in a bank.
···
170
160
* ...
171
161
* 16 : Alternate Function 15
172
162
* 17 : Analog
163
+
* 18 : Reserved
173
164
To simplify the usage, macro is available to generate "pinmux" field.
174
165
This macro is available here:
175
166
- include/dt-bindings/pinctrl/stm32-pinfunc.h
167
+
Setting the pinmux's function to the Reserved (RSVD) value is used to inform
168
+
the driver that it shall not apply the mux setting. This can be used to
169
+
reserve some pins, for example to a co-processor not running Linux.
176
170
Some examples of using macro:
177
171
/* GPIO A9 set as alternate function 2 */
178
172
... {
···
190
176
... {
191
177
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
192
178
};
179
+
/* GPIO A9 reserved for co-processor */
180
+
... {
181
+
pinmux = <STM32_PINMUX('A', 9, RSVD)>;
182
+
};
193
183
194
184
bias-disable:
195
185
type: boolean
186
+
196
187
bias-pull-down:
197
188
type: boolean
189
+
198
190
bias-pull-up:
199
191
type: boolean
192
+
200
193
drive-push-pull:
201
194
type: boolean
195
+
202
196
drive-open-drain:
203
197
type: boolean
198
+
204
199
output-low:
205
200
type: boolean
201
+
206
202
output-high:
207
203
type: boolean
204
+
208
205
slew-rate:
209
206
description: |
210
207
0: Low speed
+14
MAINTAINERS
+14
MAINTAINERS
···
23814
23814
F: drivers/bus/stm32_firewall.c
23815
23815
F: drivers/bus/stm32_rifsc.c
23816
23816
23817
+
ST STM32 HDP PINCTRL DRIVER
23818
+
M: Clément Le Goffic <legoffic.clement@gmail.com>
23819
+
S: Maintained
23820
+
F: Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
23821
+
F: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
23822
+
23817
23823
ST STM32 I2C/SMBUS DRIVER
23818
23824
M: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
23819
23825
M: Alain Volmat <alain.volmat@foss.st.com>
···
23832
23826
S: Maintained
23833
23827
F: Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml
23834
23828
F: drivers/memory/stm32_omm.c
23829
+
23830
+
ST STM32 PINCTRL DRIVER
23831
+
M: Antonio Borneo <antonio.borneo@foss.st.com>
23832
+
S: Maintained
23833
+
F: Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
23834
+
F: drivers/pinctrl/stm32/
23835
+
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
23836
+
X: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
23835
23837
23836
23838
ST STM32 SPI DRIVER
23837
23839
M: Alain Volmat <alain.volmat@foss.st.com>
-1
arch/arm64/Kconfig.platforms
-1
arch/arm64/Kconfig.platforms
+17
-4
drivers/pinctrl/Kconfig
+17
-4
drivers/pinctrl/Kconfig
···
206
206
select PINMUX
207
207
select GENERIC_PINCONF
208
208
209
+
config PINCTRL_EIC7700
210
+
tristate "EIC7700 PINCTRL driver"
211
+
depends on ARCH_ESWIN || COMPILE_TEST
212
+
select PINMUX
213
+
select GENERIC_PINCONF
214
+
help
215
+
This driver support for the pin controller in ESWIN's EIC7700 SoC,
216
+
which supports pin multiplexing, pin configuration,and rgmii voltage
217
+
control.
218
+
Say Y here to enable the eic7700 pinctrl driver
219
+
209
220
config PINCTRL_EP93XX
210
221
bool
211
222
depends on ARCH_EP93XX || COMPILE_TEST
···
280
269
281
270
config PINCTRL_K210
282
271
bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
283
-
depends on RISCV && SOC_CANAAN_K210 && OF
272
+
depends on RISCV && SOC_CANAAN_K210 || COMPILE_TEST
273
+
depends on OF
284
274
select GENERIC_PINMUX_FUNCTIONS
285
275
select GENERIC_PINCONF
286
276
select GPIOLIB
···
566
554
- 16 bits: sx1509q, sx1506q
567
555
568
556
config PINCTRL_TB10X
569
-
bool
570
-
depends on OF && ARC_PLAT_TB10X
557
+
bool "Pinctrl for TB10X" if COMPILE_TEST
558
+
depends on OF && ARC_PLAT_TB10X || COMPILE_TEST
571
559
select GPIOLIB
572
560
573
561
config PINCTRL_TPS6594
···
602
590
603
591
config PINCTRL_ZYNQ
604
592
bool "Pinctrl driver for Xilinx Zynq"
605
-
depends on ARCH_ZYNQ
593
+
depends on ARCH_ZYNQ || COMPILE_TEST
594
+
depends on OF
606
595
select PINMUX
607
596
select GENERIC_PINCONF
608
597
help
+2
-1
drivers/pinctrl/Makefile
+2
-1
drivers/pinctrl/Makefile
···
23
23
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
24
24
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
25
25
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
26
+
obj-$(CONFIG_PINCTRL_EIC7700) += pinctrl-eic7700.o
26
27
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
27
28
obj-$(CONFIG_PINCTRL_EP93XX) += pinctrl-ep93xx.o
28
29
obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
···
84
83
obj-y += spacemit/
85
84
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
86
85
obj-y += sprd/
87
-
obj-$(CONFIG_SOC_STARFIVE) += starfive/
86
+
obj-y += starfive/
88
87
obj-$(CONFIG_PINCTRL_STM32) += stm32/
89
88
obj-y += sunplus/
90
89
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
···
2653
2653
.pin_config_group_set = aspeed_pin_config_group_set,
2654
2654
};
2655
2655
2656
-
static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
2656
+
static const struct pinctrl_desc aspeed_g4_pinctrl_desc = {
2657
2657
.name = "aspeed-g4-pinctrl",
2658
2658
.pins = aspeed_g4_pins,
2659
2659
.npins = ARRAY_SIZE(aspeed_g4_pins),
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
···
2845
2845
.pin_config_group_set = aspeed_pin_config_group_set,
2846
2846
};
2847
2847
2848
-
static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
2848
+
static const struct pinctrl_desc aspeed_g5_pinctrl_desc = {
2849
2849
.name = "aspeed-g5-pinctrl",
2850
2850
.pins = aspeed_g5_pins,
2851
2851
.npins = ARRAY_SIZE(aspeed_g5_pins),
+12
-2
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+12
-2
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
···
17
17
#include "../pinctrl-utils.h"
18
18
#include "pinctrl-aspeed.h"
19
19
20
+
#define SCU040 0x040 /* Reset Control Set 1 */
20
21
#define SCU400 0x400 /* Multi-function Pin Control #1 */
21
22
#define SCU404 0x404 /* Multi-function Pin Control #2 */
22
23
#define SCU40C 0x40C /* Multi-function Pin Control #3 */
···
53
52
#define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */
54
53
#define SCUC20 0xC20 /* PCIE configuration Setting Control */
55
54
56
-
#define ASPEED_G6_NR_PINS 256
55
+
#define ASPEED_G6_NR_PINS 258
57
56
58
57
#define M24 0
59
58
SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
···
1637
1636
FUNC_DECL_1(USB2BD, USBB);
1638
1637
FUNC_DECL_1(USB2BH, USBB);
1639
1638
1639
+
#define D7 257
1640
+
SIG_EXPR_LIST_DECL_SESG(D7, RCRST, PCIERC1, SIG_DESC_SET(SCU040, 19),
1641
+
SIG_DESC_SET(SCU500, 24));
1642
+
PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, RCRST));
1643
+
FUNC_GROUP_DECL(PCIERC1, D7);
1644
+
1640
1645
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1641
1646
1642
1647
static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
···
1813
1806
ASPEED_PINCTRL_PIN(D4),
1814
1807
ASPEED_PINCTRL_PIN(D5),
1815
1808
ASPEED_PINCTRL_PIN(D6),
1809
+
ASPEED_PINCTRL_PIN(D7),
1816
1810
ASPEED_PINCTRL_PIN(E1),
1817
1811
ASPEED_PINCTRL_PIN(E11),
1818
1812
ASPEED_PINCTRL_PIN(E12),
···
2081
2073
ASPEED_PINCTRL_GROUP(SALT9G1),
2082
2074
ASPEED_PINCTRL_GROUP(SD1),
2083
2075
ASPEED_PINCTRL_GROUP(SD2),
2076
+
ASPEED_PINCTRL_GROUP(PCIERC1),
2084
2077
ASPEED_PINCTRL_GROUP(EMMCG1),
2085
2078
ASPEED_PINCTRL_GROUP(EMMCG4),
2086
2079
ASPEED_PINCTRL_GROUP(EMMCG8),
···
2323
2314
ASPEED_PINCTRL_FUNC(SPI2),
2324
2315
ASPEED_PINCTRL_FUNC(SPI2CS1),
2325
2316
ASPEED_PINCTRL_FUNC(SPI2CS2),
2317
+
ASPEED_PINCTRL_FUNC(PCIERC1),
2326
2318
ASPEED_PINCTRL_FUNC(TACH0),
2327
2319
ASPEED_PINCTRL_FUNC(TACH1),
2328
2320
ASPEED_PINCTRL_FUNC(TACH10),
···
2773
2763
.pin_config_group_set = aspeed_pin_config_group_set,
2774
2764
};
2775
2765
2776
-
static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
2766
+
static const struct pinctrl_desc aspeed_g6_pinctrl_desc = {
2777
2767
.name = "aspeed-g6-pinctrl",
2778
2768
.pins = aspeed_g6_pins,
2779
2769
.npins = ARRAY_SIZE(aspeed_g6_pins),
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed.c
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed.c
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed.h
+1
-1
drivers/pinctrl/aspeed/pinctrl-aspeed.h
···
102
102
struct pinctrl_gpio_range *range,
103
103
unsigned int offset);
104
104
int aspeed_pinctrl_probe(struct platform_device *pdev,
105
-
struct pinctrl_desc *pdesc,
105
+
const struct pinctrl_desc *pdesc,
106
106
struct aspeed_pinctrl_data *pdata);
107
107
int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
108
108
unsigned long *config);
+1
-1
drivers/pinctrl/bcm/pinctrl-bcm4908.c
+1
-1
drivers/pinctrl/bcm/pinctrl-bcm4908.c
+4
-4
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
+4
-4
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
···
903
903
.name = "cygnus-pinmux",
904
904
.pctlops = &cygnus_pinctrl_ops,
905
905
.pmxops = &cygnus_pinmux_ops,
906
+
.npins = ARRAY_SIZE(cygnus_pins),
906
907
};
907
908
908
909
static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
···
936
935
struct cygnus_pinctrl *pinctrl;
937
936
int i, ret;
938
937
struct pinctrl_pin_desc *pins;
939
-
unsigned num_pins = ARRAY_SIZE(cygnus_pins);
940
938
941
939
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
942
940
if (!pinctrl)
···
963
963
return ret;
964
964
}
965
965
966
-
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
966
+
pins = devm_kcalloc(&pdev->dev, ARRAY_SIZE(cygnus_pins), sizeof(*pins),
967
+
GFP_KERNEL);
967
968
if (!pins)
968
969
return -ENOMEM;
969
970
970
-
for (i = 0; i < num_pins; i++) {
971
+
for (i = 0; i < ARRAY_SIZE(cygnus_pins); i++) {
971
972
pins[i].number = cygnus_pins[i].pin;
972
973
pins[i].name = cygnus_pins[i].name;
973
974
pins[i].drv_data = &cygnus_pins[i].gpio_mux;
···
979
978
pinctrl->functions = cygnus_pin_functions;
980
979
pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
981
980
cygnus_pinctrl_desc.pins = pins;
982
-
cygnus_pinctrl_desc.npins = num_pins;
983
981
984
982
pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,
985
983
pinctrl);
+1
-1
drivers/pinctrl/bcm/pinctrl-ns.c
+1
-1
drivers/pinctrl/bcm/pinctrl-ns.c
+4
-4
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
+4
-4
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
···
971
971
.pctlops = &ns2_pinctrl_ops,
972
972
.pmxops = &ns2_pinmux_ops,
973
973
.confops = &ns2_pinconf_ops,
974
+
.npins = ARRAY_SIZE(ns2_pins),
974
975
};
975
976
976
977
static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
···
1027
1026
struct resource *res;
1028
1027
int i, ret;
1029
1028
struct pinctrl_pin_desc *pins;
1030
-
unsigned int num_pins = ARRAY_SIZE(ns2_pins);
1031
1029
1032
1030
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1033
1031
if (!pinctrl)
···
1060
1060
return ret;
1061
1061
}
1062
1062
1063
-
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
1063
+
pins = devm_kcalloc(&pdev->dev, ARRAY_SIZE(ns2_pins), sizeof(*pins),
1064
+
GFP_KERNEL);
1064
1065
if (!pins)
1065
1066
return -ENOMEM;
1066
1067
1067
-
for (i = 0; i < num_pins; i++) {
1068
+
for (i = 0; i < ARRAY_SIZE(ns2_pins); i++) {
1068
1069
pins[i].number = ns2_pins[i].pin;
1069
1070
pins[i].name = ns2_pins[i].name;
1070
1071
pins[i].drv_data = &ns2_pins[i];
···
1076
1075
pinctrl->functions = ns2_pin_functions;
1077
1076
pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1078
1077
ns2_pinctrl_desc.pins = pins;
1079
-
ns2_pinctrl_desc.npins = num_pins;
1080
1078
1081
1079
pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1082
1080
pinctrl);
+4
-4
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+4
-4
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
···
525
525
.name = "nsp-pinmux",
526
526
.pctlops = &nsp_pinctrl_ops,
527
527
.pmxops = &nsp_pinmux_ops,
528
+
.npins = ARRAY_SIZE(nsp_pins),
528
529
};
529
530
530
531
static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
···
557
556
struct resource *res;
558
557
int i, ret;
559
558
struct pinctrl_pin_desc *pins;
560
-
unsigned int num_pins = ARRAY_SIZE(nsp_pins);
561
559
562
560
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
563
561
if (!pinctrl)
···
589
589
return ret;
590
590
}
591
591
592
-
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
592
+
pins = devm_kcalloc(&pdev->dev, ARRAY_SIZE(nsp_pins), sizeof(*pins),
593
+
GFP_KERNEL);
593
594
if (!pins)
594
595
return -ENOMEM;
595
596
596
-
for (i = 0; i < num_pins; i++) {
597
+
for (i = 0; i < ARRAY_SIZE(nsp_pins); i++) {
597
598
pins[i].number = nsp_pins[i].pin;
598
599
pins[i].name = nsp_pins[i].name;
599
600
pins[i].drv_data = &nsp_pins[i].gpio_select;
···
605
604
pinctrl->functions = nsp_pin_functions;
606
605
pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
607
606
nsp_pinctrl_desc.pins = pins;
608
-
nsp_pinctrl_desc.npins = num_pins;
609
607
610
608
pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
611
609
pinctrl);
+7
-3
drivers/pinctrl/berlin/berlin.c
+7
-3
drivers/pinctrl/berlin/berlin.c
···
204
204
const struct berlin_desc_group *desc_group;
205
205
const struct berlin_desc_function *desc_function;
206
206
int i, max_functions = 0;
207
+
struct pinfunction *new_functions;
207
208
208
209
pctrl->nfunctions = 0;
209
210
···
230
229
}
231
230
}
232
231
233
-
pctrl->functions = krealloc(pctrl->functions,
232
+
new_functions = krealloc(pctrl->functions,
234
233
pctrl->nfunctions * sizeof(*pctrl->functions),
235
234
GFP_KERNEL);
236
-
if (!pctrl->functions)
235
+
if (!new_functions) {
236
+
kfree(pctrl->functions);
237
237
return -ENOMEM;
238
+
}
238
239
240
+
pctrl->functions = new_functions;
239
241
/* map functions to theirs groups */
240
242
for (i = 0; i < pctrl->desc->ngroups; i++) {
241
243
desc_group = pctrl->desc->groups + i;
···
287
283
return 0;
288
284
}
289
285
290
-
static struct pinctrl_desc berlin_pctrl_desc = {
286
+
static const struct pinctrl_desc berlin_pctrl_desc = {
291
287
.name = "berlin-pinctrl",
292
288
.pctlops = &berlin_pinctrl_ops,
293
289
.pmxops = &berlin_pinmux_ops,
+14
-9
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
+14
-9
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
···
448
448
.pin_config_group_set = cs42l43_pin_config_group_set,
449
449
};
450
450
451
-
static struct pinctrl_desc cs42l43_pin_desc = {
451
+
static const struct pinctrl_desc cs42l43_pin_desc = {
452
452
.name = "cs42l43-pinctrl",
453
453
.owner = THIS_MODULE,
454
454
···
483
483
return ret;
484
484
}
485
485
486
-
static void cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
486
+
static int cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset,
487
+
int value)
487
488
{
488
489
struct cs42l43_pin *priv = gpiochip_get_data(chip);
489
490
unsigned int shift = offset + CS42L43_GPIO1_LVL_SHIFT;
···
494
493
offset + 1, str_high_low(value));
495
494
496
495
ret = pm_runtime_resume_and_get(priv->dev);
497
-
if (ret) {
498
-
dev_err(priv->dev, "Failed to resume for set: %d\n", ret);
499
-
return;
500
-
}
496
+
if (ret)
497
+
return ret;
501
498
502
499
ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,
503
500
BIT(shift), value << shift);
504
501
if (ret)
505
-
dev_err(priv->dev, "Failed to set gpio%d: %d\n", offset + 1, ret);
502
+
return ret;
506
503
507
504
pm_runtime_put(priv->dev);
505
+
506
+
return 0;
508
507
}
509
508
510
509
static int cs42l43_gpio_direction_out(struct gpio_chip *chip,
511
510
unsigned int offset, int value)
512
511
{
513
-
cs42l43_gpio_set(chip, offset, value);
512
+
int ret;
513
+
514
+
ret = cs42l43_gpio_set(chip, offset, value);
515
+
if (ret)
516
+
return ret;
514
517
515
518
return pinctrl_gpio_direction_output(chip, offset);
516
519
}
···
555
550
priv->gpio_chip.direction_output = cs42l43_gpio_direction_out;
556
551
priv->gpio_chip.add_pin_ranges = cs42l43_gpio_add_pin_ranges;
557
552
priv->gpio_chip.get = cs42l43_gpio_get;
558
-
priv->gpio_chip.set = cs42l43_gpio_set;
553
+
priv->gpio_chip.set_rv = cs42l43_gpio_set;
559
554
priv->gpio_chip.label = dev_name(priv->dev);
560
555
priv->gpio_chip.parent = priv->dev;
561
556
priv->gpio_chip.can_sleep = true;
+13
-12
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
+13
-12
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
···
1058
1058
.confops = &lochnagar_pin_conf_ops,
1059
1059
};
1060
1060
1061
-
static void lochnagar_gpio_set(struct gpio_chip *chip,
1062
-
unsigned int offset, int value)
1061
+
static int lochnagar_gpio_set(struct gpio_chip *chip,
1062
+
unsigned int offset, int value)
1063
1063
{
1064
1064
struct lochnagar_pin_priv *priv = gpiochip_get_data(chip);
1065
1065
struct lochnagar *lochnagar = priv->lochnagar;
1066
1066
const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
1067
-
int ret;
1068
1067
1069
1068
value = !!value;
1070
1069
···
1074
1075
case LN_PTYPE_MUX:
1075
1076
value |= LN2_OP_GPIO;
1076
1077
1077
-
ret = lochnagar_pin_set_mux(priv, pin, value);
1078
+
return lochnagar_pin_set_mux(priv, pin, value);
1078
1079
break;
1079
1080
case LN_PTYPE_GPIO:
1080
1081
if (pin->invert)
1081
1082
value = !value;
1082
1083
1083
-
ret = regmap_update_bits(lochnagar->regmap, pin->reg,
1084
-
BIT(pin->shift), value << pin->shift);
1084
+
return regmap_update_bits(lochnagar->regmap, pin->reg,
1085
+
BIT(pin->shift),
1086
+
value << pin->shift);
1085
1087
break;
1086
1088
default:
1087
-
ret = -EINVAL;
1088
1089
break;
1089
1090
}
1090
1091
1091
-
if (ret < 0)
1092
-
dev_err(chip->parent, "Failed to set %s value: %d\n",
1093
-
pin->name, ret);
1092
+
return -EINVAL;
1094
1093
}
1095
1094
1096
1095
static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
1097
1096
unsigned int offset, int value)
1098
1097
{
1099
-
lochnagar_gpio_set(chip, offset, value);
1098
+
int ret;
1099
+
1100
+
ret = lochnagar_gpio_set(chip, offset, value);
1101
+
if (ret)
1102
+
return ret;
1100
1103
1101
1104
return pinctrl_gpio_direction_output(chip, offset);
1102
1105
}
···
1161
1160
priv->gpio_chip.request = gpiochip_generic_request;
1162
1161
priv->gpio_chip.free = gpiochip_generic_free;
1163
1162
priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
1164
-
priv->gpio_chip.set = lochnagar_gpio_set;
1163
+
priv->gpio_chip.set_rv = lochnagar_gpio_set;
1165
1164
priv->gpio_chip.can_sleep = true;
1166
1165
priv->gpio_chip.parent = dev;
1167
1166
priv->gpio_chip.base = -1;
+3
-11
drivers/pinctrl/cirrus/pinctrl-madera-core.c
+3
-11
drivers/pinctrl/cirrus/pinctrl-madera-core.c
···
1061
1061
1062
1062
/* if the configuration is provided through pdata, apply it */
1063
1063
if (pdata->gpio_configs) {
1064
-
ret = pinctrl_register_mappings(pdata->gpio_configs,
1065
-
pdata->n_gpio_configs);
1064
+
ret = devm_pinctrl_register_mappings(priv->dev,
1065
+
pdata->gpio_configs,
1066
+
pdata->n_gpio_configs);
1066
1067
if (ret)
1067
1068
return dev_err_probe(priv->dev, ret,
1068
1069
"Failed to register pdata mappings\n");
···
1082
1081
return 0;
1083
1082
}
1084
1083
1085
-
static void madera_pin_remove(struct platform_device *pdev)
1086
-
{
1087
-
struct madera_pin_private *priv = platform_get_drvdata(pdev);
1088
-
1089
-
if (priv->madera->pdata.gpio_configs)
1090
-
pinctrl_unregister_mappings(priv->madera->pdata.gpio_configs);
1091
-
}
1092
-
1093
1084
static struct platform_driver madera_pin_driver = {
1094
1085
.probe = madera_pin_probe,
1095
-
.remove = madera_pin_remove,
1096
1086
.driver = {
1097
1087
.name = "madera-pinctrl",
1098
1088
},
+7
-6
drivers/pinctrl/core.c
+7
-6
drivers/pinctrl/core.c
···
2062
2062
* @driver_data: private pin controller data for this pin controller
2063
2063
*/
2064
2064
static struct pinctrl_dev *
2065
-
pinctrl_init_controller(struct pinctrl_desc *pctldesc, struct device *dev,
2065
+
pinctrl_init_controller(const struct pinctrl_desc *pctldesc, struct device *dev,
2066
2066
void *driver_data)
2067
2067
{
2068
2068
struct pinctrl_dev *pctldev;
···
2132
2132
return ERR_PTR(ret);
2133
2133
}
2134
2134
2135
-
static void pinctrl_uninit_controller(struct pinctrl_dev *pctldev, struct pinctrl_desc *pctldesc)
2135
+
static void pinctrl_uninit_controller(struct pinctrl_dev *pctldev,
2136
+
const struct pinctrl_desc *pctldesc)
2136
2137
{
2137
2138
pinctrl_free_pindescs(pctldev, pctldesc->pins,
2138
2139
pctldesc->npins);
···
2210
2209
* struct pinctrl_dev handle. To avoid issues later on, please use the
2211
2210
* new pinctrl_register_and_init() below instead.
2212
2211
*/
2213
-
struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
2212
+
struct pinctrl_dev *pinctrl_register(const struct pinctrl_desc *pctldesc,
2214
2213
struct device *dev, void *driver_data)
2215
2214
{
2216
2215
struct pinctrl_dev *pctldev;
···
2240
2239
* Note that pinctrl_enable() still needs to be manually called after
2241
2240
* this once the driver is ready.
2242
2241
*/
2243
-
int pinctrl_register_and_init(struct pinctrl_desc *pctldesc,
2242
+
int pinctrl_register_and_init(const struct pinctrl_desc *pctldesc,
2244
2243
struct device *dev, void *driver_data,
2245
2244
struct pinctrl_dev **pctldev)
2246
2245
{
···
2331
2330
* The pinctrl device will be automatically released when the device is unbound.
2332
2331
*/
2333
2332
struct pinctrl_dev *devm_pinctrl_register(struct device *dev,
2334
-
struct pinctrl_desc *pctldesc,
2333
+
const struct pinctrl_desc *pctldesc,
2335
2334
void *driver_data)
2336
2335
{
2337
2336
struct pinctrl_dev **ptr, *pctldev;
···
2365
2364
* The pinctrl device will be automatically released when the device is unbound.
2366
2365
*/
2367
2366
int devm_pinctrl_register_and_init(struct device *dev,
2368
-
struct pinctrl_desc *pctldesc,
2367
+
const struct pinctrl_desc *pctldesc,
2369
2368
void *driver_data,
2370
2369
struct pinctrl_dev **pctldev)
2371
2370
{
+1
-1
drivers/pinctrl/core.h
+1
-1
drivers/pinctrl/core.h
+5
-3
drivers/pinctrl/intel/pinctrl-baytrail.c
+5
-3
drivers/pinctrl/intel/pinctrl-baytrail.c
···
1045
1045
return !!(val & BYT_LEVEL);
1046
1046
}
1047
1047
1048
-
static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1048
+
static int byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1049
1049
{
1050
1050
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1051
1051
void __iomem *reg;
···
1053
1053
1054
1054
reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1055
1055
if (!reg)
1056
-
return;
1056
+
return -EINVAL;
1057
1057
1058
1058
guard(raw_spinlock_irqsave)(&byt_lock);
1059
1059
···
1062
1062
writel(old_val | BYT_LEVEL, reg);
1063
1063
else
1064
1064
writel(old_val & ~BYT_LEVEL, reg);
1065
+
1066
+
return 0;
1065
1067
}
1066
1068
1067
1069
static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
···
1231
1229
.direction_input = byt_gpio_direction_input,
1232
1230
.direction_output = byt_gpio_direction_output,
1233
1231
.get = byt_gpio_get,
1234
-
.set = byt_gpio_set,
1232
+
.set_rv = byt_gpio_set,
1235
1233
.set_config = gpiochip_generic_config,
1236
1234
.dbg_show = byt_gpio_dbg_show,
1237
1235
};
+4
-2
drivers/pinctrl/intel/pinctrl-cherryview.c
+4
-2
drivers/pinctrl/intel/pinctrl-cherryview.c
···
1112
1112
return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1113
1113
}
1114
1114
1115
-
static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1115
+
static int chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1116
1116
{
1117
1117
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1118
1118
u32 ctrl0;
···
1127
1127
ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1128
1128
1129
1129
chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1130
+
1131
+
return 0;
1130
1132
}
1131
1133
1132
1134
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
···
1168
1166
.direction_input = chv_gpio_direction_input,
1169
1167
.direction_output = chv_gpio_direction_output,
1170
1168
.get = chv_gpio_get,
1171
-
.set = chv_gpio_set,
1169
+
.set_rv = chv_gpio_set,
1172
1170
};
1173
1171
1174
1172
static void chv_gpio_irq_ack(struct irq_data *d)
+14
-6
drivers/pinctrl/intel/pinctrl-intel.c
+14
-6
drivers/pinctrl/intel/pinctrl-intel.c
···
9
9
10
10
#include <linux/acpi.h>
11
11
#include <linux/cleanup.h>
12
+
#include <linux/export.h>
12
13
#include <linux/gpio/driver.h>
13
14
#include <linux/interrupt.h>
14
15
#include <linux/log2.h>
···
1034
1033
return !!(padcfg0 & PADCFG0_GPIORXSTATE);
1035
1034
}
1036
1035
1037
-
static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
1038
-
int value)
1036
+
static int intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
1037
+
int value)
1039
1038
{
1040
1039
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1041
1040
void __iomem *reg;
···
1044
1043
1045
1044
pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1046
1045
if (pin < 0)
1047
-
return;
1046
+
return -EINVAL;
1048
1047
1049
1048
reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1050
1049
if (!reg)
1051
-
return;
1050
+
return -EINVAL;
1052
1051
1053
1052
guard(raw_spinlock_irqsave)(&pctrl->lock);
1054
1053
···
1058
1057
else
1059
1058
padcfg0 &= ~PADCFG0_GPIOTXSTATE;
1060
1059
writel(padcfg0, reg);
1060
+
1061
+
return 0;
1061
1062
}
1062
1063
1063
1064
static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
···
1097
1094
static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1098
1095
int value)
1099
1096
{
1100
-
intel_gpio_set(chip, offset, value);
1097
+
int ret;
1098
+
1099
+
ret = intel_gpio_set(chip, offset, value);
1100
+
if (ret)
1101
+
return ret;
1102
+
1101
1103
return pinctrl_gpio_direction_output(chip, offset);
1102
1104
}
1103
1105
···
1114
1106
.direction_input = intel_gpio_direction_input,
1115
1107
.direction_output = intel_gpio_direction_output,
1116
1108
.get = intel_gpio_get,
1117
-
.set = intel_gpio_set,
1109
+
.set_rv = intel_gpio_set,
1118
1110
.set_config = gpiochip_generic_config,
1119
1111
};
1120
1112
+4
-2
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+4
-2
drivers/pinctrl/intel/pinctrl-lynxpoint.c
···
503
503
return !!(ioread32(reg) & IN_LVL_BIT);
504
504
}
505
505
506
-
static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
506
+
static int lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
507
507
{
508
508
struct intel_pinctrl *lg = gpiochip_get_data(chip);
509
509
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
···
514
514
iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
515
515
else
516
516
iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
517
+
518
+
return 0;
517
519
}
518
520
519
521
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
···
777
775
gc->direction_input = lp_gpio_direction_input;
778
776
gc->direction_output = lp_gpio_direction_output;
779
777
gc->get = lp_gpio_get;
780
-
gc->set = lp_gpio_set;
778
+
gc->set_rv = lp_gpio_set;
781
779
gc->set_config = gpiochip_generic_config;
782
780
gc->get_direction = lp_gpio_get_direction;
783
781
gc->base = -1;
+12
drivers/pinctrl/mediatek/Kconfig
+12
drivers/pinctrl/mediatek/Kconfig
···
259
259
In MTK platform, we support virtual gpio and use it to
260
260
map specific eint which doesn't have real gpio pin.
261
261
262
+
config PINCTRL_MT8189
263
+
bool "MediaTek MT8189 pin control"
264
+
depends on OF
265
+
depends on ARM64 || COMPILE_TEST
266
+
default ARM64 && ARCH_MEDIATEK
267
+
select PINCTRL_MTK_PARIS
268
+
help
269
+
Say yes here to support pin controller and gpio driver
270
+
on MediaTek MT8189 SoC.
271
+
In MTK platform, we support virtual gpio and use it to
272
+
map specific eint which doesn't have real gpio pin.
273
+
262
274
config PINCTRL_MT8192
263
275
bool "MediaTek MT8192 pin control"
264
276
depends on OF
+1
drivers/pinctrl/mediatek/Makefile
+1
drivers/pinctrl/mediatek/Makefile
···
35
35
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
36
36
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
37
37
obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o
38
+
obj-$(CONFIG_PINCTRL_MT8189) += pinctrl-mt8189.o
38
39
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
39
40
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
40
41
obj-$(CONFIG_PINCTRL_MT8196) += pinctrl-mt8196.o
+2
-2
drivers/pinctrl/mediatek/mtk-eint.c
+2
-2
drivers/pinctrl/mediatek/mtk-eint.c
···
561
561
goto err_eint;
562
562
}
563
563
564
-
eint->domain = irq_domain_create_linear(of_fwnode_handle(eint->dev->of_node),
565
-
eint->hw->ap_num, &irq_domain_simple_ops, NULL);
564
+
eint->domain = irq_domain_create_linear(dev_fwnode(eint->dev), eint->hw->ap_num,
565
+
&irq_domain_simple_ops, NULL);
566
566
if (!eint->domain)
567
567
goto err_eint;
568
568
+4
-6
drivers/pinctrl/mediatek/pinctrl-airoha.c
+4
-6
drivers/pinctrl/mediatek/pinctrl-airoha.c
···
2852
2852
.dt_free_map = pinconf_generic_dt_free_map,
2853
2853
};
2854
2854
2855
-
static struct pinctrl_desc airoha_pinctrl_desc = {
2855
+
static const struct pinctrl_desc airoha_pinctrl_desc = {
2856
2856
.name = KBUILD_MODNAME,
2857
2857
.owner = THIS_MODULE,
2858
2858
.pctlops = &airoha_pctlops,
···
2907
2907
const struct airoha_pinctrl_func *func;
2908
2908
2909
2909
func = &airoha_pinctrl_funcs[i];
2910
-
err = pinmux_generic_add_function(pinctrl->ctrl,
2911
-
func->desc.func.name,
2912
-
func->desc.func.groups,
2913
-
func->desc.func.ngroups,
2914
-
(void *)func);
2910
+
err = pinmux_generic_add_pinfunction(pinctrl->ctrl,
2911
+
&func->desc.func,
2912
+
(void *)func);
2915
2913
if (err < 0) {
2916
2914
dev_err(dev, "Failed to register function %s\n",
2917
2915
func->desc.func.name);
+2
-3
drivers/pinctrl/mediatek/pinctrl-moore.c
+2
-3
drivers/pinctrl/mediatek/pinctrl-moore.c
···
625
625
const struct function_desc *function = hw->soc->funcs + i;
626
626
const struct pinfunction *func = &function->func;
627
627
628
-
err = pinmux_generic_add_function(hw->pctrl, func->name,
629
-
func->groups, func->ngroups,
630
-
function->data);
628
+
err = pinmux_generic_add_pinfunction(hw->pctrl, func,
629
+
function->data);
631
630
if (err < 0) {
632
631
dev_err(hw->dev, "Failed to register function %s\n",
633
632
func->name);
+1700
drivers/pinctrl/mediatek/pinctrl-mt8189.c
+1700
drivers/pinctrl/mediatek/pinctrl-mt8189.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2025 MediaTek Inc.
4
+
* Author: Lei Xue <lei.xue@mediatek.com>
5
+
* Cathy Xu <ot_cathy.xu@mediatek.com>
6
+
*/
7
+
8
+
#include "pinctrl-mtk-mt8189.h"
9
+
#include "pinctrl-paris.h"
10
+
11
+
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
12
+
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
13
+
32, 0)
14
+
15
+
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
16
+
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
17
+
32, 1)
18
+
19
+
static const struct mtk_pin_field_calc mt8189_pin_mode_range[] = {
20
+
PIN_FIELD(0, 182, 0x0300, 0x10, 0, 4),
21
+
};
22
+
23
+
static const struct mtk_pin_field_calc mt8189_pin_dir_range[] = {
24
+
PIN_FIELD(0, 182, 0x0000, 0x10, 0, 1),
25
+
};
26
+
27
+
static const struct mtk_pin_field_calc mt8189_pin_di_range[] = {
28
+
PIN_FIELD(0, 182, 0x0200, 0x10, 0, 1),
29
+
};
30
+
31
+
static const struct mtk_pin_field_calc mt8189_pin_do_range[] = {
32
+
PIN_FIELD(0, 182, 0x0100, 0x10, 0, 1),
33
+
};
34
+
35
+
static const struct mtk_pin_field_calc mt8189_pin_smt_range[] = {
36
+
PIN_FIELD_BASE(0, 0, 7, 0x00e0, 0x10, 5, 1),
37
+
PIN_FIELD_BASE(1, 1, 8, 0x00c0, 0x10, 3, 1),
38
+
PIN_FIELD_BASE(2, 2, 8, 0x00c0, 0x10, 4, 1),
39
+
PIN_FIELD_BASE(3, 3, 8, 0x00c0, 0x10, 5, 1),
40
+
PIN_FIELD_BASE(4, 4, 8, 0x00c0, 0x10, 6, 1),
41
+
PIN_FIELD_BASE(5, 5, 8, 0x00c0, 0x10, 7, 1),
42
+
PIN_FIELD_BASE(6, 6, 7, 0x00e0, 0x10, 6, 1),
43
+
PIN_FIELD_BASE(7, 7, 7, 0x00e0, 0x10, 7, 1),
44
+
PIN_FIELD_BASE(8, 8, 7, 0x00e0, 0x10, 8, 1),
45
+
PIN_FIELD_BASE(9, 9, 7, 0x00e0, 0x10, 9, 1),
46
+
PIN_FIELD_BASE(10, 10, 7, 0x00e0, 0x10, 10, 1),
47
+
PIN_FIELD_BASE(11, 11, 7, 0x00e0, 0x10, 11, 1),
48
+
PIN_FIELD_BASE(12, 12, 2, 0x00e0, 0x10, 5, 1),
49
+
PIN_FIELD_BASE(13, 13, 2, 0x00e0, 0x10, 6, 1),
50
+
PIN_FIELD_BASE(14, 14, 3, 0x00f0, 0x10, 0, 1),
51
+
PIN_FIELD_BASE(15, 15, 3, 0x00f0, 0x10, 1, 1),
52
+
PIN_FIELD_BASE(16, 16, 2, 0x00e0, 0x10, 7, 1),
53
+
PIN_FIELD_BASE(17, 17, 2, 0x00e0, 0x10, 8, 1),
54
+
PIN_FIELD_BASE(18, 18, 7, 0x00e0, 0x10, 0, 1),
55
+
PIN_FIELD_BASE(19, 19, 7, 0x00e0, 0x10, 2, 1),
56
+
PIN_FIELD_BASE(20, 20, 7, 0x00e0, 0x10, 1, 1),
57
+
PIN_FIELD_BASE(21, 21, 7, 0x00e0, 0x10, 3, 1),
58
+
PIN_FIELD_BASE(22, 22, 9, 0x00f0, 0x10, 0, 1),
59
+
PIN_FIELD_BASE(23, 23, 9, 0x00f0, 0x10, 1, 1),
60
+
PIN_FIELD_BASE(24, 24, 9, 0x00f0, 0x10, 2, 1),
61
+
PIN_FIELD_BASE(25, 25, 4, 0x00c0, 0x10, 2, 1),
62
+
PIN_FIELD_BASE(26, 26, 4, 0x00c0, 0x10, 1, 1),
63
+
PIN_FIELD_BASE(27, 27, 2, 0x00e0, 0x10, 1, 1),
64
+
PIN_FIELD_BASE(28, 28, 2, 0x00e0, 0x10, 2, 1),
65
+
PIN_FIELD_BASE(29, 29, 4, 0x00c0, 0x10, 0, 1),
66
+
PIN_FIELD_BASE(30, 30, 2, 0x00e0, 0x10, 0, 1),
67
+
PIN_FIELD_BASE(31, 31, 3, 0x00f0, 0x10, 19, 1),
68
+
PIN_FIELD_BASE(32, 32, 1, 0x00c0, 0x10, 30, 1),
69
+
PIN_FIELD_BASE(33, 33, 3, 0x00f0, 0x10, 21, 1),
70
+
PIN_FIELD_BASE(34, 34, 3, 0x00f0, 0x10, 20, 1),
71
+
PIN_FIELD_BASE(35, 35, 3, 0x00f0, 0x10, 23, 1),
72
+
PIN_FIELD_BASE(36, 36, 3, 0x00f0, 0x10, 22, 1),
73
+
PIN_FIELD_BASE(37, 37, 3, 0x00f0, 0x10, 25, 1),
74
+
PIN_FIELD_BASE(38, 38, 3, 0x00f0, 0x10, 24, 1),
75
+
PIN_FIELD_BASE(39, 39, 3, 0x00f0, 0x10, 5, 1),
76
+
PIN_FIELD_BASE(40, 40, 3, 0x00f0, 0x10, 2, 1),
77
+
PIN_FIELD_BASE(41, 41, 3, 0x00f0, 0x10, 3, 1),
78
+
PIN_FIELD_BASE(42, 42, 3, 0x00f0, 0x10, 4, 1),
79
+
PIN_FIELD_BASE(43, 43, 3, 0x00f0, 0x10, 6, 1),
80
+
PIN_FIELD_BASE(44, 44, 7, 0x00e0, 0x10, 20, 1),
81
+
PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 21, 1),
82
+
PIN_FIELD_BASE(46, 46, 7, 0x00e0, 0x10, 22, 1),
83
+
PIN_FIELD_BASE(47, 47, 7, 0x00e0, 0x10, 23, 1),
84
+
PIN_FIELD_BASE(48, 48, 4, 0x00c0, 0x10, 5, 1),
85
+
PIN_FIELD_BASE(49, 49, 4, 0x00c0, 0x10, 4, 1),
86
+
PIN_FIELD_BASE(50, 50, 4, 0x00c0, 0x10, 3, 1),
87
+
PIN_FIELD_BASE(51, 51, 8, 0x00c0, 0x10, 8, 1),
88
+
PIN_FIELD_BASE(52, 52, 8, 0x00c0, 0x10, 10, 1),
89
+
PIN_FIELD_BASE(53, 53, 8, 0x00c0, 0x10, 9, 1),
90
+
PIN_FIELD_BASE(54, 54, 8, 0x00c0, 0x10, 11, 1),
91
+
PIN_FIELD_BASE(55, 55, 4, 0x00c0, 0x10, 6, 1),
92
+
PIN_FIELD_BASE(56, 56, 4, 0x00c0, 0x10, 7, 1),
93
+
PIN_FIELD_BASE(57, 57, 2, 0x00e0, 0x10, 13, 1),
94
+
PIN_FIELD_BASE(58, 58, 2, 0x00e0, 0x10, 17, 1),
95
+
PIN_FIELD_BASE(59, 59, 2, 0x00e0, 0x10, 14, 1),
96
+
PIN_FIELD_BASE(60, 60, 2, 0x00e0, 0x10, 18, 1),
97
+
PIN_FIELD_BASE(61, 61, 2, 0x00e0, 0x10, 15, 1),
98
+
PIN_FIELD_BASE(62, 62, 2, 0x00e0, 0x10, 19, 1),
99
+
PIN_FIELD_BASE(63, 63, 2, 0x00e0, 0x10, 16, 1),
100
+
PIN_FIELD_BASE(64, 64, 2, 0x00e0, 0x10, 20, 1),
101
+
PIN_FIELD_BASE(65, 65, 9, 0x00f0, 0x10, 10, 1),
102
+
PIN_FIELD_BASE(66, 66, 9, 0x00f0, 0x10, 12, 1),
103
+
PIN_FIELD_BASE(67, 67, 9, 0x00f0, 0x10, 11, 1),
104
+
PIN_FIELD_BASE(68, 68, 9, 0x00f0, 0x10, 13, 1),
105
+
PIN_FIELD_BASE(69, 69, 2, 0x00e0, 0x10, 22, 1),
106
+
PIN_FIELD_BASE(70, 70, 2, 0x00e0, 0x10, 21, 1),
107
+
PIN_FIELD_BASE(71, 71, 2, 0x00e0, 0x10, 24, 1),
108
+
PIN_FIELD_BASE(72, 72, 2, 0x00e0, 0x10, 23, 1),
109
+
PIN_FIELD_BASE(73, 73, 2, 0x00e0, 0x10, 26, 1),
110
+
PIN_FIELD_BASE(74, 74, 2, 0x00e0, 0x10, 25, 1),
111
+
PIN_FIELD_BASE(75, 75, 3, 0x00f0, 0x10, 13, 1),
112
+
PIN_FIELD_BASE(76, 76, 2, 0x00e0, 0x10, 27, 1),
113
+
PIN_FIELD_BASE(77, 77, 8, 0x00c0, 0x10, 13, 1),
114
+
PIN_FIELD_BASE(78, 78, 8, 0x00c0, 0x10, 12, 1),
115
+
PIN_FIELD_BASE(79, 79, 8, 0x00c0, 0x10, 15, 1),
116
+
PIN_FIELD_BASE(80, 80, 8, 0x00c0, 0x10, 14, 1),
117
+
PIN_FIELD_BASE(81, 81, 2, 0x00e0, 0x10, 29, 1),
118
+
PIN_FIELD_BASE(82, 82, 2, 0x00e0, 0x10, 28, 1),
119
+
PIN_FIELD_BASE(83, 83, 2, 0x00e0, 0x10, 30, 1),
120
+
PIN_FIELD_BASE(84, 84, 7, 0x00e0, 0x10, 24, 1),
121
+
PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 25, 1),
122
+
PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 26, 1),
123
+
PIN_FIELD_BASE(87, 87, 7, 0x00e0, 0x10, 27, 1),
124
+
PIN_FIELD_BASE(88, 88, 5, 0x0120, 0x10, 20, 1),
125
+
PIN_FIELD_BASE(89, 89, 5, 0x0120, 0x10, 19, 1),
126
+
PIN_FIELD_BASE(90, 90, 5, 0x0120, 0x10, 22, 1),
127
+
PIN_FIELD_BASE(91, 91, 5, 0x0120, 0x10, 21, 1),
128
+
PIN_FIELD_BASE(92, 92, 5, 0x0120, 0x10, 16, 1),
129
+
PIN_FIELD_BASE(93, 93, 5, 0x0120, 0x10, 17, 1),
130
+
PIN_FIELD_BASE(94, 94, 5, 0x0120, 0x10, 23, 1),
131
+
PIN_FIELD_BASE(95, 95, 5, 0x0120, 0x10, 15, 1),
132
+
PIN_FIELD_BASE(96, 96, 5, 0x0120, 0x10, 18, 1),
133
+
PIN_FIELD_BASE(97, 97, 5, 0x0120, 0x10, 0, 1),
134
+
PIN_FIELD_BASE(98, 98, 5, 0x0120, 0x10, 5, 1),
135
+
PIN_FIELD_BASE(99, 99, 5, 0x0120, 0x10, 3, 1),
136
+
PIN_FIELD_BASE(100, 100, 5, 0x0120, 0x10, 4, 1),
137
+
PIN_FIELD_BASE(101, 101, 5, 0x0120, 0x10, 1, 1),
138
+
PIN_FIELD_BASE(102, 102, 5, 0x0120, 0x10, 2, 1),
139
+
PIN_FIELD_BASE(103, 103, 7, 0x00e0, 0x10, 15, 1),
140
+
PIN_FIELD_BASE(104, 104, 7, 0x00e0, 0x10, 12, 1),
141
+
PIN_FIELD_BASE(105, 105, 7, 0x00e0, 0x10, 14, 1),
142
+
PIN_FIELD_BASE(106, 106, 7, 0x00e0, 0x10, 13, 1),
143
+
PIN_FIELD_BASE(107, 107, 7, 0x00e0, 0x10, 19, 1),
144
+
PIN_FIELD_BASE(108, 108, 7, 0x00e0, 0x10, 16, 1),
145
+
PIN_FIELD_BASE(109, 109, 7, 0x00e0, 0x10, 18, 1),
146
+
PIN_FIELD_BASE(110, 110, 7, 0x00e0, 0x10, 17, 1),
147
+
PIN_FIELD_BASE(111, 111, 7, 0x00e0, 0x10, 4, 1),
148
+
PIN_FIELD_BASE(112, 112, 8, 0x00c0, 0x10, 0, 1),
149
+
PIN_FIELD_BASE(113, 113, 8, 0x00c0, 0x10, 1, 1),
150
+
PIN_FIELD_BASE(114, 114, 8, 0x00c0, 0x10, 2, 1),
151
+
PIN_FIELD_BASE(115, 115, 2, 0x00e0, 0x10, 9, 1),
152
+
PIN_FIELD_BASE(116, 116, 2, 0x00e0, 0x10, 12, 1),
153
+
PIN_FIELD_BASE(117, 117, 2, 0x00e0, 0x10, 10, 1),
154
+
PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 11, 1),
155
+
PIN_FIELD_BASE(119, 119, 1, 0x00c0, 0x10, 26, 1),
156
+
PIN_FIELD_BASE(120, 120, 1, 0x00c0, 0x10, 25, 1),
157
+
PIN_FIELD_BASE(121, 121, 1, 0x00c0, 0x10, 24, 1),
158
+
PIN_FIELD_BASE(122, 122, 1, 0x00c0, 0x10, 23, 1),
159
+
PIN_FIELD_BASE(123, 123, 1, 0x00c0, 0x10, 19, 1),
160
+
PIN_FIELD_BASE(124, 124, 1, 0x00c0, 0x10, 18, 1),
161
+
PIN_FIELD_BASE(125, 125, 1, 0x00c0, 0x10, 17, 1),
162
+
PIN_FIELD_BASE(126, 126, 1, 0x00c0, 0x10, 16, 1),
163
+
PIN_FIELD_BASE(127, 127, 1, 0x00c0, 0x10, 22, 1),
164
+
PIN_FIELD_BASE(128, 128, 1, 0x00c0, 0x10, 15, 1),
165
+
PIN_FIELD_BASE(129, 129, 1, 0x00c0, 0x10, 20, 1),
166
+
PIN_FIELD_BASE(130, 130, 1, 0x00c0, 0x10, 27, 1),
167
+
PIN_FIELD_BASE(131, 131, 1, 0x00c0, 0x10, 13, 1),
168
+
PIN_FIELD_BASE(132, 132, 1, 0x00c0, 0x10, 14, 1),
169
+
PIN_FIELD_BASE(133, 133, 1, 0x00c0, 0x10, 28, 1),
170
+
PIN_FIELD_BASE(134, 134, 1, 0x00c0, 0x10, 21, 1),
171
+
PIN_FIELD_BASE(135, 135, 1, 0x00c0, 0x10, 11, 1),
172
+
PIN_FIELD_BASE(136, 136, 1, 0x00c0, 0x10, 12, 1),
173
+
PIN_FIELD_BASE(137, 137, 2, 0x00e0, 0x10, 3, 1),
174
+
PIN_FIELD_BASE(138, 138, 2, 0x00e0, 0x10, 4, 1),
175
+
PIN_FIELD_BASE(139, 139, 1, 0x00c0, 0x10, 3, 1),
176
+
PIN_FIELD_BASE(140, 140, 1, 0x00c0, 0x10, 4, 1),
177
+
PIN_FIELD_BASE(141, 141, 1, 0x00c0, 0x10, 0, 1),
178
+
PIN_FIELD_BASE(142, 142, 1, 0x00c0, 0x10, 1, 1),
179
+
PIN_FIELD_BASE(143, 143, 1, 0x00c0, 0x10, 2, 1),
180
+
PIN_FIELD_BASE(144, 144, 1, 0x00c0, 0x10, 5, 1),
181
+
PIN_FIELD_BASE(145, 145, 1, 0x00c0, 0x10, 6, 1),
182
+
PIN_FIELD_BASE(146, 146, 1, 0x00c0, 0x10, 7, 1),
183
+
PIN_FIELD_BASE(147, 147, 1, 0x00c0, 0x10, 8, 1),
184
+
PIN_FIELD_BASE(148, 148, 1, 0x00c0, 0x10, 9, 1),
185
+
PIN_FIELD_BASE(149, 149, 1, 0x00c0, 0x10, 10, 1),
186
+
PIN_FIELD_BASE(150, 150, 3, 0x00f0, 0x10, 14, 1),
187
+
PIN_FIELD_BASE(151, 151, 1, 0x00c0, 0x10, 29, 1),
188
+
PIN_FIELD_BASE(152, 152, 3, 0x00f0, 0x10, 15, 1),
189
+
PIN_FIELD_BASE(153, 153, 3, 0x00f0, 0x10, 16, 1),
190
+
PIN_FIELD_BASE(154, 154, 3, 0x00f0, 0x10, 17, 1),
191
+
PIN_FIELD_BASE(155, 155, 3, 0x00f0, 0x10, 18, 1),
192
+
PIN_FIELD_BASE(156, 156, 5, 0x0120, 0x10, 12, 1),
193
+
PIN_FIELD_BASE(157, 157, 5, 0x0120, 0x10, 11, 1),
194
+
PIN_FIELD_BASE(158, 158, 5, 0x0120, 0x10, 10, 1),
195
+
PIN_FIELD_BASE(159, 159, 6, 0x0090, 0x10, 2, 1),
196
+
PIN_FIELD_BASE(160, 160, 5, 0x0120, 0x10, 14, 1),
197
+
PIN_FIELD_BASE(161, 161, 5, 0x0120, 0x10, 7, 1),
198
+
PIN_FIELD_BASE(162, 162, 5, 0x0120, 0x10, 6, 1),
199
+
PIN_FIELD_BASE(163, 163, 6, 0x0090, 0x10, 1, 1),
200
+
PIN_FIELD_BASE(164, 164, 5, 0x0120, 0x10, 9, 1),
201
+
PIN_FIELD_BASE(165, 165, 5, 0x0120, 0x10, 8, 1),
202
+
PIN_FIELD_BASE(166, 166, 6, 0x0090, 0x10, 0, 1),
203
+
PIN_FIELD_BASE(167, 167, 5, 0x0120, 0x10, 13, 1),
204
+
PIN_FIELD_BASE(168, 168, 3, 0x00f0, 0x10, 8, 1),
205
+
PIN_FIELD_BASE(169, 169, 3, 0x00f0, 0x10, 7, 1),
206
+
PIN_FIELD_BASE(170, 170, 3, 0x00f0, 0x10, 9, 1),
207
+
PIN_FIELD_BASE(171, 171, 3, 0x00f0, 0x10, 10, 1),
208
+
PIN_FIELD_BASE(172, 172, 3, 0x00f0, 0x10, 11, 1),
209
+
PIN_FIELD_BASE(173, 173, 3, 0x00f0, 0x10, 12, 1),
210
+
PIN_FIELD_BASE(174, 174, 9, 0x00f0, 0x10, 5, 1),
211
+
PIN_FIELD_BASE(175, 175, 9, 0x00f0, 0x10, 4, 1),
212
+
PIN_FIELD_BASE(176, 176, 9, 0x00f0, 0x10, 6, 1),
213
+
PIN_FIELD_BASE(177, 177, 9, 0x00f0, 0x10, 7, 1),
214
+
PIN_FIELD_BASE(178, 178, 9, 0x00f0, 0x10, 8, 1),
215
+
PIN_FIELD_BASE(179, 179, 9, 0x00f0, 0x10, 9, 1),
216
+
PIN_FIELD_BASE(180, 180, 5, 0x0120, 0x10, 24, 1),
217
+
PIN_FIELD_BASE(181, 181, 5, 0x0120, 0x10, 25, 1),
218
+
PIN_FIELD_BASE(182, 182, 9, 0x00f0, 0x10, 3, 1),
219
+
};
220
+
221
+
static const struct mtk_pin_field_calc mt8189_pin_ies_range[] = {
222
+
PIN_FIELD_BASE(0, 0, 7, 0x0050, 0x10, 5, 1),
223
+
PIN_FIELD_BASE(1, 1, 8, 0x0050, 0x10, 3, 1),
224
+
PIN_FIELD_BASE(2, 2, 8, 0x0050, 0x10, 4, 1),
225
+
PIN_FIELD_BASE(3, 3, 8, 0x0050, 0x10, 5, 1),
226
+
PIN_FIELD_BASE(4, 4, 8, 0x0050, 0x10, 6, 1),
227
+
PIN_FIELD_BASE(5, 5, 8, 0x0050, 0x10, 7, 1),
228
+
PIN_FIELD_BASE(6, 6, 7, 0x0050, 0x10, 6, 1),
229
+
PIN_FIELD_BASE(7, 7, 7, 0x0050, 0x10, 7, 1),
230
+
PIN_FIELD_BASE(8, 8, 7, 0x0050, 0x10, 8, 1),
231
+
PIN_FIELD_BASE(9, 9, 7, 0x0050, 0x10, 9, 1),
232
+
PIN_FIELD_BASE(10, 10, 7, 0x0050, 0x10, 10, 1),
233
+
PIN_FIELD_BASE(11, 11, 7, 0x0050, 0x10, 11, 1),
234
+
PIN_FIELD_BASE(12, 12, 2, 0x0070, 0x10, 5, 1),
235
+
PIN_FIELD_BASE(13, 13, 2, 0x0070, 0x10, 6, 1),
236
+
PIN_FIELD_BASE(14, 14, 3, 0x0050, 0x10, 0, 1),
237
+
PIN_FIELD_BASE(15, 15, 3, 0x0050, 0x10, 1, 1),
238
+
PIN_FIELD_BASE(16, 16, 2, 0x0070, 0x10, 7, 1),
239
+
PIN_FIELD_BASE(17, 17, 2, 0x0070, 0x10, 8, 1),
240
+
PIN_FIELD_BASE(18, 18, 7, 0x0050, 0x10, 0, 1),
241
+
PIN_FIELD_BASE(19, 19, 7, 0x0050, 0x10, 2, 1),
242
+
PIN_FIELD_BASE(20, 20, 7, 0x0050, 0x10, 1, 1),
243
+
PIN_FIELD_BASE(21, 21, 7, 0x0050, 0x10, 3, 1),
244
+
PIN_FIELD_BASE(22, 22, 9, 0x0040, 0x10, 0, 1),
245
+
PIN_FIELD_BASE(23, 23, 9, 0x0040, 0x10, 1, 1),
246
+
PIN_FIELD_BASE(24, 24, 9, 0x0040, 0x10, 2, 1),
247
+
PIN_FIELD_BASE(25, 25, 4, 0x0050, 0x10, 2, 1),
248
+
PIN_FIELD_BASE(26, 26, 4, 0x0050, 0x10, 1, 1),
249
+
PIN_FIELD_BASE(27, 27, 2, 0x0070, 0x10, 1, 1),
250
+
PIN_FIELD_BASE(28, 28, 2, 0x0070, 0x10, 2, 1),
251
+
PIN_FIELD_BASE(29, 29, 4, 0x0050, 0x10, 0, 1),
252
+
PIN_FIELD_BASE(30, 30, 2, 0x0070, 0x10, 0, 1),
253
+
PIN_FIELD_BASE(31, 31, 3, 0x0050, 0x10, 19, 1),
254
+
PIN_FIELD_BASE(32, 32, 1, 0x0050, 0x10, 30, 1),
255
+
PIN_FIELD_BASE(33, 33, 3, 0x0050, 0x10, 21, 1),
256
+
PIN_FIELD_BASE(34, 34, 3, 0x0050, 0x10, 20, 1),
257
+
PIN_FIELD_BASE(35, 35, 3, 0x0050, 0x10, 23, 1),
258
+
PIN_FIELD_BASE(36, 36, 3, 0x0050, 0x10, 22, 1),
259
+
PIN_FIELD_BASE(37, 37, 3, 0x0050, 0x10, 25, 1),
260
+
PIN_FIELD_BASE(38, 38, 3, 0x0050, 0x10, 24, 1),
261
+
PIN_FIELD_BASE(39, 39, 3, 0x0050, 0x10, 5, 1),
262
+
PIN_FIELD_BASE(40, 40, 3, 0x0050, 0x10, 2, 1),
263
+
PIN_FIELD_BASE(41, 41, 3, 0x0050, 0x10, 3, 1),
264
+
PIN_FIELD_BASE(42, 42, 3, 0x0050, 0x10, 4, 1),
265
+
PIN_FIELD_BASE(43, 43, 3, 0x0050, 0x10, 6, 1),
266
+
PIN_FIELD_BASE(44, 44, 7, 0x0050, 0x10, 20, 1),
267
+
PIN_FIELD_BASE(45, 45, 7, 0x0050, 0x10, 21, 1),
268
+
PIN_FIELD_BASE(46, 46, 7, 0x0050, 0x10, 22, 1),
269
+
PIN_FIELD_BASE(47, 47, 7, 0x0050, 0x10, 23, 1),
270
+
PIN_FIELD_BASE(48, 48, 4, 0x0050, 0x10, 5, 1),
271
+
PIN_FIELD_BASE(49, 49, 4, 0x0050, 0x10, 4, 1),
272
+
PIN_FIELD_BASE(50, 50, 4, 0x0050, 0x10, 3, 1),
273
+
PIN_FIELD_BASE(51, 51, 8, 0x0050, 0x10, 8, 1),
274
+
PIN_FIELD_BASE(52, 52, 8, 0x0050, 0x10, 10, 1),
275
+
PIN_FIELD_BASE(53, 53, 8, 0x0050, 0x10, 9, 1),
276
+
PIN_FIELD_BASE(54, 54, 8, 0x0050, 0x10, 11, 1),
277
+
PIN_FIELD_BASE(55, 55, 4, 0x0050, 0x10, 6, 1),
278
+
PIN_FIELD_BASE(56, 56, 4, 0x0050, 0x10, 7, 1),
279
+
PIN_FIELD_BASE(57, 57, 2, 0x0070, 0x10, 13, 1),
280
+
PIN_FIELD_BASE(58, 58, 2, 0x0070, 0x10, 17, 1),
281
+
PIN_FIELD_BASE(59, 59, 2, 0x0070, 0x10, 14, 1),
282
+
PIN_FIELD_BASE(60, 60, 2, 0x0070, 0x10, 18, 1),
283
+
PIN_FIELD_BASE(61, 61, 2, 0x0070, 0x10, 15, 1),
284
+
PIN_FIELD_BASE(62, 62, 2, 0x0070, 0x10, 19, 1),
285
+
PIN_FIELD_BASE(63, 63, 2, 0x0070, 0x10, 16, 1),
286
+
PIN_FIELD_BASE(64, 64, 2, 0x0070, 0x10, 20, 1),
287
+
PIN_FIELD_BASE(65, 65, 9, 0x0040, 0x10, 10, 1),
288
+
PIN_FIELD_BASE(66, 66, 9, 0x0040, 0x10, 12, 1),
289
+
PIN_FIELD_BASE(67, 67, 9, 0x0040, 0x10, 11, 1),
290
+
PIN_FIELD_BASE(68, 68, 9, 0x0040, 0x10, 13, 1),
291
+
PIN_FIELD_BASE(69, 69, 2, 0x0070, 0x10, 22, 1),
292
+
PIN_FIELD_BASE(70, 70, 2, 0x0070, 0x10, 21, 1),
293
+
PIN_FIELD_BASE(71, 71, 2, 0x0070, 0x10, 24, 1),
294
+
PIN_FIELD_BASE(72, 72, 2, 0x0070, 0x10, 23, 1),
295
+
PIN_FIELD_BASE(73, 73, 2, 0x0070, 0x10, 26, 1),
296
+
PIN_FIELD_BASE(74, 74, 2, 0x0070, 0x10, 25, 1),
297
+
PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 13, 1),
298
+
PIN_FIELD_BASE(76, 76, 2, 0x0070, 0x10, 27, 1),
299
+
PIN_FIELD_BASE(77, 77, 8, 0x0050, 0x10, 13, 1),
300
+
PIN_FIELD_BASE(78, 78, 8, 0x0050, 0x10, 12, 1),
301
+
PIN_FIELD_BASE(79, 79, 8, 0x0050, 0x10, 15, 1),
302
+
PIN_FIELD_BASE(80, 80, 8, 0x0050, 0x10, 14, 1),
303
+
PIN_FIELD_BASE(81, 81, 2, 0x0070, 0x10, 29, 1),
304
+
PIN_FIELD_BASE(82, 82, 2, 0x0070, 0x10, 28, 1),
305
+
PIN_FIELD_BASE(83, 83, 2, 0x0070, 0x10, 30, 1),
306
+
PIN_FIELD_BASE(84, 84, 7, 0x0050, 0x10, 24, 1),
307
+
PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 25, 1),
308
+
PIN_FIELD_BASE(86, 86, 7, 0x0050, 0x10, 26, 1),
309
+
PIN_FIELD_BASE(87, 87, 7, 0x0050, 0x10, 27, 1),
310
+
PIN_FIELD_BASE(88, 88, 5, 0x0060, 0x10, 20, 1),
311
+
PIN_FIELD_BASE(89, 89, 5, 0x0060, 0x10, 19, 1),
312
+
PIN_FIELD_BASE(90, 90, 5, 0x0060, 0x10, 22, 1),
313
+
PIN_FIELD_BASE(91, 91, 5, 0x0060, 0x10, 21, 1),
314
+
PIN_FIELD_BASE(92, 92, 5, 0x0060, 0x10, 16, 1),
315
+
PIN_FIELD_BASE(93, 93, 5, 0x0060, 0x10, 17, 1),
316
+
PIN_FIELD_BASE(94, 94, 5, 0x0060, 0x10, 23, 1),
317
+
PIN_FIELD_BASE(95, 95, 5, 0x0060, 0x10, 15, 1),
318
+
PIN_FIELD_BASE(96, 96, 5, 0x0060, 0x10, 18, 1),
319
+
PIN_FIELD_BASE(97, 97, 5, 0x0060, 0x10, 0, 1),
320
+
PIN_FIELD_BASE(98, 98, 5, 0x0060, 0x10, 5, 1),
321
+
PIN_FIELD_BASE(99, 99, 5, 0x0060, 0x10, 3, 1),
322
+
PIN_FIELD_BASE(100, 100, 5, 0x0060, 0x10, 4, 1),
323
+
PIN_FIELD_BASE(101, 101, 5, 0x0060, 0x10, 1, 1),
324
+
PIN_FIELD_BASE(102, 102, 5, 0x0060, 0x10, 2, 1),
325
+
PIN_FIELD_BASE(103, 103, 7, 0x0050, 0x10, 15, 1),
326
+
PIN_FIELD_BASE(104, 104, 7, 0x0050, 0x10, 12, 1),
327
+
PIN_FIELD_BASE(105, 105, 7, 0x0050, 0x10, 14, 1),
328
+
PIN_FIELD_BASE(106, 106, 7, 0x0050, 0x10, 13, 1),
329
+
PIN_FIELD_BASE(107, 107, 7, 0x0050, 0x10, 19, 1),
330
+
PIN_FIELD_BASE(108, 108, 7, 0x0050, 0x10, 16, 1),
331
+
PIN_FIELD_BASE(109, 109, 7, 0x0050, 0x10, 18, 1),
332
+
PIN_FIELD_BASE(110, 110, 7, 0x0050, 0x10, 17, 1),
333
+
PIN_FIELD_BASE(111, 111, 7, 0x0050, 0x10, 4, 1),
334
+
PIN_FIELD_BASE(112, 112, 8, 0x0050, 0x10, 0, 1),
335
+
PIN_FIELD_BASE(113, 113, 8, 0x0050, 0x10, 1, 1),
336
+
PIN_FIELD_BASE(114, 114, 8, 0x0050, 0x10, 2, 1),
337
+
PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 9, 1),
338
+
PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 12, 1),
339
+
PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 10, 1),
340
+
PIN_FIELD_BASE(118, 118, 2, 0x0070, 0x10, 11, 1),
341
+
PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 26, 1),
342
+
PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 25, 1),
343
+
PIN_FIELD_BASE(121, 121, 1, 0x0050, 0x10, 24, 1),
344
+
PIN_FIELD_BASE(122, 122, 1, 0x0050, 0x10, 23, 1),
345
+
PIN_FIELD_BASE(123, 123, 1, 0x0050, 0x10, 19, 1),
346
+
PIN_FIELD_BASE(124, 124, 1, 0x0050, 0x10, 18, 1),
347
+
PIN_FIELD_BASE(125, 125, 1, 0x0050, 0x10, 17, 1),
348
+
PIN_FIELD_BASE(126, 126, 1, 0x0050, 0x10, 16, 1),
349
+
PIN_FIELD_BASE(127, 127, 1, 0x0050, 0x10, 22, 1),
350
+
PIN_FIELD_BASE(128, 128, 1, 0x0050, 0x10, 15, 1),
351
+
PIN_FIELD_BASE(129, 129, 1, 0x0050, 0x10, 20, 1),
352
+
PIN_FIELD_BASE(130, 130, 1, 0x0050, 0x10, 27, 1),
353
+
PIN_FIELD_BASE(131, 131, 1, 0x0050, 0x10, 13, 1),
354
+
PIN_FIELD_BASE(132, 132, 1, 0x0050, 0x10, 14, 1),
355
+
PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 28, 1),
356
+
PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 21, 1),
357
+
PIN_FIELD_BASE(135, 135, 1, 0x0050, 0x10, 11, 1),
358
+
PIN_FIELD_BASE(136, 136, 1, 0x0050, 0x10, 12, 1),
359
+
PIN_FIELD_BASE(137, 137, 2, 0x0070, 0x10, 3, 1),
360
+
PIN_FIELD_BASE(138, 138, 2, 0x0070, 0x10, 4, 1),
361
+
PIN_FIELD_BASE(139, 139, 1, 0x0050, 0x10, 3, 1),
362
+
PIN_FIELD_BASE(140, 140, 1, 0x0050, 0x10, 4, 1),
363
+
PIN_FIELD_BASE(141, 141, 1, 0x0050, 0x10, 0, 1),
364
+
PIN_FIELD_BASE(142, 142, 1, 0x0050, 0x10, 1, 1),
365
+
PIN_FIELD_BASE(143, 143, 1, 0x0050, 0x10, 2, 1),
366
+
PIN_FIELD_BASE(144, 144, 1, 0x0050, 0x10, 5, 1),
367
+
PIN_FIELD_BASE(145, 145, 1, 0x0050, 0x10, 6, 1),
368
+
PIN_FIELD_BASE(146, 146, 1, 0x0050, 0x10, 7, 1),
369
+
PIN_FIELD_BASE(147, 147, 1, 0x0050, 0x10, 8, 1),
370
+
PIN_FIELD_BASE(148, 148, 1, 0x0050, 0x10, 9, 1),
371
+
PIN_FIELD_BASE(149, 149, 1, 0x0050, 0x10, 10, 1),
372
+
PIN_FIELD_BASE(150, 150, 3, 0x0050, 0x10, 14, 1),
373
+
PIN_FIELD_BASE(151, 151, 1, 0x0050, 0x10, 29, 1),
374
+
PIN_FIELD_BASE(152, 152, 3, 0x0050, 0x10, 15, 1),
375
+
PIN_FIELD_BASE(153, 153, 3, 0x0050, 0x10, 16, 1),
376
+
PIN_FIELD_BASE(154, 154, 3, 0x0050, 0x10, 17, 1),
377
+
PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 18, 1),
378
+
PIN_FIELD_BASE(156, 156, 5, 0x0060, 0x10, 12, 1),
379
+
PIN_FIELD_BASE(157, 157, 5, 0x0060, 0x10, 11, 1),
380
+
PIN_FIELD_BASE(158, 158, 5, 0x0060, 0x10, 10, 1),
381
+
PIN_FIELD_BASE(159, 159, 6, 0x0020, 0x10, 2, 1),
382
+
PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 14, 1),
383
+
PIN_FIELD_BASE(161, 161, 5, 0x0060, 0x10, 7, 1),
384
+
PIN_FIELD_BASE(162, 162, 5, 0x0060, 0x10, 6, 1),
385
+
PIN_FIELD_BASE(163, 163, 6, 0x0020, 0x10, 1, 1),
386
+
PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 9, 1),
387
+
PIN_FIELD_BASE(165, 165, 5, 0x0060, 0x10, 8, 1),
388
+
PIN_FIELD_BASE(166, 166, 6, 0x0020, 0x10, 0, 1),
389
+
PIN_FIELD_BASE(167, 167, 5, 0x0060, 0x10, 13, 1),
390
+
PIN_FIELD_BASE(168, 168, 3, 0x0050, 0x10, 8, 1),
391
+
PIN_FIELD_BASE(169, 169, 3, 0x0050, 0x10, 7, 1),
392
+
PIN_FIELD_BASE(170, 170, 3, 0x0050, 0x10, 9, 1),
393
+
PIN_FIELD_BASE(171, 171, 3, 0x0050, 0x10, 10, 1),
394
+
PIN_FIELD_BASE(172, 172, 3, 0x0050, 0x10, 11, 1),
395
+
PIN_FIELD_BASE(173, 173, 3, 0x0050, 0x10, 12, 1),
396
+
PIN_FIELD_BASE(174, 174, 9, 0x0040, 0x10, 5, 1),
397
+
PIN_FIELD_BASE(175, 175, 9, 0x0040, 0x10, 4, 1),
398
+
PIN_FIELD_BASE(176, 176, 9, 0x0040, 0x10, 6, 1),
399
+
PIN_FIELD_BASE(177, 177, 9, 0x0040, 0x10, 7, 1),
400
+
PIN_FIELD_BASE(178, 178, 9, 0x0040, 0x10, 8, 1),
401
+
PIN_FIELD_BASE(179, 179, 9, 0x0040, 0x10, 9, 1),
402
+
PIN_FIELD_BASE(180, 180, 5, 0x0060, 0x10, 24, 1),
403
+
PIN_FIELD_BASE(181, 181, 5, 0x0060, 0x10, 25, 1),
404
+
PIN_FIELD_BASE(182, 182, 9, 0x0040, 0x10, 3, 1),
405
+
};
406
+
407
+
static const struct mtk_pin_field_calc mt8189_pin_tdsel_range[] = {
408
+
PIN_FIELD_BASE(0, 0, 7, 0x00f0, 0x10, 0, 4),
409
+
PIN_FIELD_BASE(1, 1, 8, 0x00d0, 0x10, 0, 4),
410
+
PIN_FIELD_BASE(2, 2, 8, 0x00d0, 0x10, 4, 4),
411
+
PIN_FIELD_BASE(3, 3, 8, 0x00d0, 0x10, 8, 4),
412
+
PIN_FIELD_BASE(4, 4, 8, 0x00d0, 0x10, 12, 4),
413
+
PIN_FIELD_BASE(5, 5, 8, 0x00d0, 0x10, 16, 4),
414
+
PIN_FIELD_BASE(6, 6, 7, 0x00f0, 0x10, 4, 4),
415
+
PIN_FIELD_BASE(7, 7, 7, 0x00f0, 0x10, 8, 4),
416
+
PIN_FIELD_BASE(8, 8, 7, 0x00f0, 0x10, 12, 4),
417
+
PIN_FIELD_BASE(9, 9, 7, 0x00f0, 0x10, 16, 4),
418
+
PIN_FIELD_BASE(10, 10, 7, 0x00f0, 0x10, 20, 4),
419
+
PIN_FIELD_BASE(11, 11, 7, 0x00f0, 0x10, 24, 4),
420
+
PIN_FIELD_BASE(12, 12, 2, 0x00f0, 0x10, 12, 4),
421
+
PIN_FIELD_BASE(13, 13, 2, 0x00f0, 0x10, 16, 4),
422
+
PIN_FIELD_BASE(14, 14, 3, 0x0110, 0x10, 0, 4),
423
+
PIN_FIELD_BASE(15, 15, 3, 0x0110, 0x10, 4, 4),
424
+
PIN_FIELD_BASE(16, 16, 2, 0x00f0, 0x10, 20, 4),
425
+
PIN_FIELD_BASE(17, 17, 2, 0x00f0, 0x10, 28, 4),
426
+
PIN_FIELD_BASE(18, 18, 7, 0x0100, 0x10, 28, 4),
427
+
PIN_FIELD_BASE(19, 19, 7, 0x0110, 0x10, 0, 4),
428
+
PIN_FIELD_BASE(20, 20, 7, 0x0110, 0x10, 0, 4),
429
+
PIN_FIELD_BASE(21, 21, 7, 0x0110, 0x10, 0, 4),
430
+
PIN_FIELD_BASE(22, 22, 9, 0x0110, 0x10, 0, 4),
431
+
PIN_FIELD_BASE(23, 23, 9, 0x0110, 0x10, 4, 4),
432
+
PIN_FIELD_BASE(24, 24, 9, 0x0110, 0x10, 8, 4),
433
+
PIN_FIELD_BASE(25, 25, 4, 0x00d0, 0x10, 12, 4),
434
+
PIN_FIELD_BASE(26, 26, 4, 0x00d0, 0x10, 8, 4),
435
+
PIN_FIELD_BASE(27, 27, 2, 0x00f0, 0x10, 4, 4),
436
+
PIN_FIELD_BASE(28, 28, 2, 0x00f0, 0x10, 8, 4),
437
+
PIN_FIELD_BASE(29, 29, 4, 0x00d0, 0x10, 8, 4),
438
+
PIN_FIELD_BASE(30, 30, 2, 0x00f0, 0x10, 0, 4),
439
+
PIN_FIELD_BASE(31, 31, 3, 0x0120, 0x10, 8, 4),
440
+
PIN_FIELD_BASE(32, 32, 1, 0x00f0, 0x10, 16, 4),
441
+
PIN_FIELD_BASE(33, 33, 3, 0x0120, 0x10, 16, 4),
442
+
PIN_FIELD_BASE(34, 34, 3, 0x0120, 0x10, 4, 4),
443
+
PIN_FIELD_BASE(35, 35, 3, 0x0120, 0x10, 0, 4),
444
+
PIN_FIELD_BASE(36, 36, 3, 0x0120, 0x10, 8, 4),
445
+
PIN_FIELD_BASE(37, 37, 3, 0x0120, 0x10, 4, 4),
446
+
PIN_FIELD_BASE(38, 38, 3, 0x0120, 0x10, 4, 4),
447
+
PIN_FIELD_BASE(39, 39, 3, 0x0120, 0x10, 8, 4),
448
+
PIN_FIELD_BASE(40, 40, 3, 0x0120, 0x10, 8, 4),
449
+
PIN_FIELD_BASE(41, 41, 3, 0x0120, 0x10, 8, 4),
450
+
PIN_FIELD_BASE(42, 42, 3, 0x0120, 0x10, 8, 4),
451
+
PIN_FIELD_BASE(43, 43, 3, 0x0120, 0x10, 8, 4),
452
+
PIN_FIELD_BASE(44, 44, 7, 0x0110, 0x10, 0, 4),
453
+
PIN_FIELD_BASE(45, 45, 7, 0x0110, 0x10, 0, 4),
454
+
PIN_FIELD_BASE(46, 46, 7, 0x0110, 0x10, 0, 4),
455
+
PIN_FIELD_BASE(47, 47, 7, 0x0110, 0x10, 0, 4),
456
+
PIN_FIELD_BASE(48, 48, 4, 0x00d0, 0x10, 8, 4),
457
+
PIN_FIELD_BASE(49, 49, 4, 0x00d0, 0x10, 4, 4),
458
+
PIN_FIELD_BASE(50, 50, 4, 0x00d0, 0x10, 0, 4),
459
+
PIN_FIELD_BASE(51, 51, 8, 0x00d0, 0x10, 20, 4),
460
+
PIN_FIELD_BASE(52, 52, 8, 0x00d0, 0x10, 20, 4),
461
+
PIN_FIELD_BASE(53, 53, 8, 0x00d0, 0x10, 20, 4),
462
+
PIN_FIELD_BASE(54, 54, 8, 0x00d0, 0x10, 20, 4),
463
+
PIN_FIELD_BASE(55, 55, 4, 0x00d0, 0x10, 12, 4),
464
+
PIN_FIELD_BASE(56, 56, 4, 0x00d0, 0x10, 12, 4),
465
+
PIN_FIELD_BASE(57, 57, 2, 0x00f0, 0x10, 28, 4),
466
+
PIN_FIELD_BASE(58, 58, 2, 0x00f0, 0x10, 28, 4),
467
+
PIN_FIELD_BASE(59, 59, 2, 0x00f0, 0x10, 28, 4),
468
+
PIN_FIELD_BASE(60, 60, 2, 0x00f0, 0x10, 28, 4),
469
+
PIN_FIELD_BASE(61, 61, 2, 0x00f0, 0x10, 28, 4),
470
+
PIN_FIELD_BASE(62, 62, 2, 0x00f0, 0x10, 28, 4),
471
+
PIN_FIELD_BASE(63, 63, 2, 0x00f0, 0x10, 28, 4),
472
+
PIN_FIELD_BASE(64, 64, 2, 0x00f0, 0x10, 28, 4),
473
+
PIN_FIELD_BASE(65, 65, 9, 0x0120, 0x10, 4, 4),
474
+
PIN_FIELD_BASE(66, 66, 9, 0x0120, 0x10, 4, 4),
475
+
PIN_FIELD_BASE(67, 67, 9, 0x0120, 0x10, 4, 4),
476
+
PIN_FIELD_BASE(68, 68, 9, 0x0120, 0x10, 4, 4),
477
+
PIN_FIELD_BASE(69, 69, 2, 0x0100, 0x10, 4, 4),
478
+
PIN_FIELD_BASE(70, 70, 2, 0x0100, 0x10, 0, 4),
479
+
PIN_FIELD_BASE(71, 71, 2, 0x0100, 0x10, 12, 4),
480
+
PIN_FIELD_BASE(72, 72, 2, 0x0100, 0x10, 8, 4),
481
+
PIN_FIELD_BASE(73, 73, 2, 0x0100, 0x10, 20, 4),
482
+
PIN_FIELD_BASE(74, 74, 2, 0x0100, 0x10, 16, 4),
483
+
PIN_FIELD_BASE(75, 75, 3, 0x0120, 0x10, 12, 4),
484
+
PIN_FIELD_BASE(76, 76, 2, 0x0100, 0x10, 24, 4),
485
+
PIN_FIELD_BASE(77, 77, 8, 0x00d0, 0x10, 28, 4),
486
+
PIN_FIELD_BASE(78, 78, 8, 0x00d0, 0x10, 24, 4),
487
+
PIN_FIELD_BASE(79, 79, 8, 0x00e0, 0x10, 4, 4),
488
+
PIN_FIELD_BASE(80, 80, 8, 0x00e0, 0x10, 0, 4),
489
+
PIN_FIELD_BASE(81, 81, 2, 0x00f0, 0x10, 28, 4),
490
+
PIN_FIELD_BASE(82, 82, 2, 0x00f0, 0x10, 28, 4),
491
+
PIN_FIELD_BASE(83, 83, 2, 0x00f0, 0x10, 28, 4),
492
+
PIN_FIELD_BASE(84, 84, 7, 0x0110, 0x10, 0, 4),
493
+
PIN_FIELD_BASE(85, 85, 7, 0x0110, 0x10, 0, 4),
494
+
PIN_FIELD_BASE(86, 86, 7, 0x0110, 0x10, 0, 4),
495
+
PIN_FIELD_BASE(87, 87, 7, 0x0110, 0x10, 0, 4),
496
+
PIN_FIELD_BASE(88, 88, 5, 0x0140, 0x10, 4, 4),
497
+
PIN_FIELD_BASE(89, 89, 5, 0x0140, 0x10, 4, 4),
498
+
PIN_FIELD_BASE(90, 90, 5, 0x0140, 0x10, 4, 4),
499
+
PIN_FIELD_BASE(91, 91, 5, 0x0140, 0x10, 4, 4),
500
+
PIN_FIELD_BASE(92, 92, 5, 0x0140, 0x10, 8, 4),
501
+
PIN_FIELD_BASE(93, 93, 5, 0x0140, 0x10, 8, 4),
502
+
PIN_FIELD_BASE(94, 94, 5, 0x0140, 0x10, 8, 4),
503
+
PIN_FIELD_BASE(95, 95, 5, 0x0140, 0x10, 8, 4),
504
+
PIN_FIELD_BASE(96, 96, 5, 0x0140, 0x10, 12, 4),
505
+
PIN_FIELD_BASE(97, 97, 5, 0x0140, 0x10, 8, 4),
506
+
PIN_FIELD_BASE(98, 98, 5, 0x0140, 0x10, 8, 4),
507
+
PIN_FIELD_BASE(99, 99, 5, 0x0140, 0x10, 8, 4),
508
+
PIN_FIELD_BASE(100, 100, 5, 0x0140, 0x10, 8, 4),
509
+
PIN_FIELD_BASE(101, 101, 5, 0x0140, 0x10, 8, 4),
510
+
PIN_FIELD_BASE(102, 102, 5, 0x0140, 0x10, 8, 4),
511
+
PIN_FIELD_BASE(103, 103, 7, 0x0100, 0x10, 8, 4),
512
+
PIN_FIELD_BASE(104, 104, 7, 0x00f0, 0x10, 28, 4),
513
+
PIN_FIELD_BASE(105, 105, 7, 0x0100, 0x10, 4, 4),
514
+
PIN_FIELD_BASE(106, 106, 7, 0x0100, 0x10, 0, 4),
515
+
PIN_FIELD_BASE(107, 107, 7, 0x0100, 0x10, 24, 4),
516
+
PIN_FIELD_BASE(108, 108, 7, 0x0100, 0x10, 12, 4),
517
+
PIN_FIELD_BASE(109, 109, 7, 0x0100, 0x10, 20, 4),
518
+
PIN_FIELD_BASE(110, 110, 7, 0x0100, 0x10, 16, 4),
519
+
PIN_FIELD_BASE(111, 111, 7, 0x0110, 0x10, 0, 4),
520
+
PIN_FIELD_BASE(112, 112, 8, 0x00d0, 0x10, 20, 4),
521
+
PIN_FIELD_BASE(113, 113, 8, 0x00d0, 0x10, 20, 4),
522
+
PIN_FIELD_BASE(114, 114, 8, 0x00d0, 0x10, 20, 4),
523
+
PIN_FIELD_BASE(115, 115, 2, 0x00f0, 0x10, 24, 4),
524
+
PIN_FIELD_BASE(116, 116, 2, 0x00f0, 0x10, 28, 4),
525
+
PIN_FIELD_BASE(117, 117, 2, 0x00f0, 0x10, 28, 4),
526
+
PIN_FIELD_BASE(118, 118, 2, 0x00f0, 0x10, 28, 4),
527
+
PIN_FIELD_BASE(119, 119, 1, 0x00e0, 0x10, 24, 4),
528
+
PIN_FIELD_BASE(120, 120, 1, 0x00e0, 0x10, 20, 4),
529
+
PIN_FIELD_BASE(121, 121, 1, 0x00e0, 0x10, 16, 4),
530
+
PIN_FIELD_BASE(122, 122, 1, 0x00e0, 0x10, 12, 4),
531
+
PIN_FIELD_BASE(123, 123, 1, 0x00d0, 0x10, 28, 4),
532
+
PIN_FIELD_BASE(124, 124, 1, 0x00d0, 0x10, 24, 4),
533
+
PIN_FIELD_BASE(125, 125, 1, 0x00d0, 0x10, 20, 4),
534
+
PIN_FIELD_BASE(126, 126, 1, 0x00d0, 0x10, 16, 4),
535
+
PIN_FIELD_BASE(127, 127, 1, 0x00e0, 0x10, 8, 4),
536
+
PIN_FIELD_BASE(128, 128, 1, 0x00d0, 0x10, 12, 4),
537
+
PIN_FIELD_BASE(129, 129, 1, 0x00e0, 0x10, 0, 4),
538
+
PIN_FIELD_BASE(130, 130, 1, 0x00e0, 0x10, 28, 4),
539
+
PIN_FIELD_BASE(131, 131, 1, 0x00d0, 0x10, 4, 4),
540
+
PIN_FIELD_BASE(132, 132, 1, 0x00d0, 0x10, 8, 4),
541
+
PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 0, 4),
542
+
PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 4),
543
+
PIN_FIELD_BASE(135, 135, 1, 0x00d0, 0x10, 0, 4),
544
+
PIN_FIELD_BASE(136, 136, 1, 0x00f0, 0x10, 4, 4),
545
+
PIN_FIELD_BASE(137, 137, 2, 0x00f0, 0x10, 28, 4),
546
+
PIN_FIELD_BASE(138, 138, 2, 0x00f0, 0x10, 28, 4),
547
+
PIN_FIELD_BASE(139, 139, 1, 0x00f0, 0x10, 12, 4),
548
+
PIN_FIELD_BASE(140, 140, 1, 0x00f0, 0x10, 12, 4),
549
+
PIN_FIELD_BASE(141, 141, 1, 0x00f0, 0x10, 12, 4),
550
+
PIN_FIELD_BASE(142, 142, 1, 0x00f0, 0x10, 12, 4),
551
+
PIN_FIELD_BASE(143, 143, 1, 0x00f0, 0x10, 12, 4),
552
+
PIN_FIELD_BASE(144, 144, 1, 0x00f0, 0x10, 12, 4),
553
+
PIN_FIELD_BASE(145, 145, 1, 0x00f0, 0x10, 8, 4),
554
+
PIN_FIELD_BASE(146, 146, 1, 0x00f0, 0x10, 8, 4),
555
+
PIN_FIELD_BASE(147, 147, 1, 0x00f0, 0x10, 8, 4),
556
+
PIN_FIELD_BASE(148, 148, 1, 0x00f0, 0x10, 8, 4),
557
+
PIN_FIELD_BASE(149, 149, 1, 0x00f0, 0x10, 8, 4),
558
+
PIN_FIELD_BASE(150, 150, 3, 0x0120, 0x10, 8, 4),
559
+
PIN_FIELD_BASE(151, 151, 1, 0x00f0, 0x10, 16, 4),
560
+
PIN_FIELD_BASE(152, 152, 3, 0x0120, 0x10, 8, 4),
561
+
PIN_FIELD_BASE(153, 153, 3, 0x0120, 0x10, 8, 4),
562
+
PIN_FIELD_BASE(154, 154, 3, 0x0120, 0x10, 8, 4),
563
+
PIN_FIELD_BASE(155, 155, 3, 0x0120, 0x10, 8, 4),
564
+
PIN_FIELD_BASE(156, 156, 5, 0x0130, 0x10, 24, 4),
565
+
PIN_FIELD_BASE(157, 157, 5, 0x0130, 0x10, 20, 4),
566
+
PIN_FIELD_BASE(158, 158, 5, 0x0130, 0x10, 16, 4),
567
+
PIN_FIELD_BASE(159, 159, 6, 0x00a0, 0x10, 8, 4),
568
+
PIN_FIELD_BASE(160, 160, 5, 0x0140, 0x10, 0, 4),
569
+
PIN_FIELD_BASE(161, 161, 5, 0x0130, 0x10, 4, 4),
570
+
PIN_FIELD_BASE(162, 162, 5, 0x0130, 0x10, 0, 4),
571
+
PIN_FIELD_BASE(163, 163, 6, 0x00a0, 0x10, 4, 4),
572
+
PIN_FIELD_BASE(164, 164, 5, 0x0130, 0x10, 12, 4),
573
+
PIN_FIELD_BASE(165, 165, 5, 0x0130, 0x10, 8, 4),
574
+
PIN_FIELD_BASE(166, 166, 6, 0x00a0, 0x10, 0, 4),
575
+
PIN_FIELD_BASE(167, 167, 5, 0x0130, 0x10, 28, 4),
576
+
PIN_FIELD_BASE(168, 168, 3, 0x0110, 0x10, 12, 4),
577
+
PIN_FIELD_BASE(169, 169, 3, 0x0110, 0x10, 8, 4),
578
+
PIN_FIELD_BASE(170, 170, 3, 0x0110, 0x10, 16, 4),
579
+
PIN_FIELD_BASE(171, 171, 3, 0x0110, 0x10, 20, 4),
580
+
PIN_FIELD_BASE(172, 172, 3, 0x0110, 0x10, 24, 4),
581
+
PIN_FIELD_BASE(173, 173, 3, 0x0110, 0x10, 28, 4),
582
+
PIN_FIELD_BASE(174, 174, 9, 0x0110, 0x10, 16, 4),
583
+
PIN_FIELD_BASE(175, 175, 9, 0x0110, 0x10, 12, 4),
584
+
PIN_FIELD_BASE(176, 176, 9, 0x0110, 0x10, 20, 4),
585
+
PIN_FIELD_BASE(177, 177, 9, 0x0110, 0x10, 24, 4),
586
+
PIN_FIELD_BASE(178, 178, 9, 0x0110, 0x10, 28, 4),
587
+
PIN_FIELD_BASE(179, 179, 9, 0x0120, 0x10, 0, 4),
588
+
PIN_FIELD_BASE(180, 180, 5, 0x0140, 0x10, 16, 4),
589
+
PIN_FIELD_BASE(181, 181, 5, 0x0140, 0x10, 20, 4),
590
+
PIN_FIELD_BASE(182, 182, 9, 0x0120, 0x10, 8, 4),
591
+
};
592
+
593
+
static const struct mtk_pin_field_calc mt8189_pin_rdsel_range[] = {
594
+
PIN_FIELD_BASE(0, 0, 7, 0x00d0, 0x10, 0, 2),
595
+
PIN_FIELD_BASE(1, 1, 8, 0x00a0, 0x10, 0, 2),
596
+
PIN_FIELD_BASE(2, 2, 8, 0x00a0, 0x10, 2, 2),
597
+
PIN_FIELD_BASE(3, 3, 8, 0x00a0, 0x10, 4, 2),
598
+
PIN_FIELD_BASE(4, 4, 8, 0x00a0, 0x10, 6, 2),
599
+
PIN_FIELD_BASE(5, 5, 8, 0x00a0, 0x10, 8, 2),
600
+
PIN_FIELD_BASE(6, 6, 7, 0x00d0, 0x10, 2, 2),
601
+
PIN_FIELD_BASE(7, 7, 7, 0x00d0, 0x10, 4, 2),
602
+
PIN_FIELD_BASE(8, 8, 7, 0x00d0, 0x10, 6, 2),
603
+
PIN_FIELD_BASE(9, 9, 7, 0x00d0, 0x10, 8, 2),
604
+
PIN_FIELD_BASE(10, 10, 7, 0x00d0, 0x10, 10, 2),
605
+
PIN_FIELD_BASE(11, 11, 7, 0x00d0, 0x10, 12, 2),
606
+
PIN_FIELD_BASE(12, 12, 2, 0x00c0, 0x10, 6, 2),
607
+
PIN_FIELD_BASE(13, 13, 2, 0x00c0, 0x10, 8, 2),
608
+
PIN_FIELD_BASE(14, 14, 3, 0x00d0, 0x10, 0, 2),
609
+
PIN_FIELD_BASE(15, 15, 3, 0x00d0, 0x10, 2, 2),
610
+
PIN_FIELD_BASE(16, 16, 2, 0x00c0, 0x10, 10, 2),
611
+
PIN_FIELD_BASE(17, 17, 2, 0x00c0, 0x10, 12, 2),
612
+
PIN_FIELD_BASE(18, 18, 7, 0x00d0, 0x10, 30, 2),
613
+
PIN_FIELD_BASE(19, 19, 7, 0x00d0, 0x10, 30, 2),
614
+
PIN_FIELD_BASE(20, 20, 7, 0x00d0, 0x10, 30, 2),
615
+
PIN_FIELD_BASE(21, 21, 7, 0x00d0, 0x10, 30, 2),
616
+
PIN_FIELD_BASE(22, 22, 9, 0x00c0, 0x10, 0, 2),
617
+
PIN_FIELD_BASE(23, 23, 9, 0x00c0, 0x10, 2, 2),
618
+
PIN_FIELD_BASE(24, 24, 9, 0x00c0, 0x10, 4, 2),
619
+
PIN_FIELD_BASE(25, 25, 4, 0x00a0, 0x10, 6, 2),
620
+
PIN_FIELD_BASE(26, 26, 4, 0x00a0, 0x10, 4, 2),
621
+
PIN_FIELD_BASE(27, 27, 2, 0x00c0, 0x10, 2, 2),
622
+
PIN_FIELD_BASE(28, 28, 2, 0x00c0, 0x10, 4, 2),
623
+
PIN_FIELD_BASE(29, 29, 4, 0x00a0, 0x10, 4, 2),
624
+
PIN_FIELD_BASE(30, 30, 2, 0x00c0, 0x10, 0, 2),
625
+
PIN_FIELD_BASE(31, 31, 3, 0x00e0, 0x10, 16, 2),
626
+
PIN_FIELD_BASE(32, 32, 1, 0x00b0, 0x10, 8, 2),
627
+
PIN_FIELD_BASE(33, 33, 3, 0x00e0, 0x10, 20, 2),
628
+
PIN_FIELD_BASE(34, 34, 3, 0x00e0, 0x10, 14, 2),
629
+
PIN_FIELD_BASE(35, 35, 3, 0x00e0, 0x10, 12, 2),
630
+
PIN_FIELD_BASE(36, 36, 3, 0x00e0, 0x10, 16, 2),
631
+
PIN_FIELD_BASE(37, 37, 3, 0x00e0, 0x10, 14, 2),
632
+
PIN_FIELD_BASE(38, 38, 3, 0x00e0, 0x10, 14, 2),
633
+
PIN_FIELD_BASE(39, 39, 3, 0x00e0, 0x10, 16, 2),
634
+
PIN_FIELD_BASE(40, 40, 3, 0x00e0, 0x10, 16, 2),
635
+
PIN_FIELD_BASE(41, 41, 3, 0x00e0, 0x10, 16, 2),
636
+
PIN_FIELD_BASE(42, 42, 3, 0x00e0, 0x10, 16, 2),
637
+
PIN_FIELD_BASE(43, 43, 3, 0x00e0, 0x10, 16, 2),
638
+
PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 30, 2),
639
+
PIN_FIELD_BASE(45, 45, 7, 0x00d0, 0x10, 30, 2),
640
+
PIN_FIELD_BASE(46, 46, 7, 0x00d0, 0x10, 30, 2),
641
+
PIN_FIELD_BASE(47, 47, 7, 0x00d0, 0x10, 30, 2),
642
+
PIN_FIELD_BASE(48, 48, 4, 0x00a0, 0x10, 4, 2),
643
+
PIN_FIELD_BASE(49, 49, 4, 0x00a0, 0x10, 2, 2),
644
+
PIN_FIELD_BASE(50, 50, 4, 0x00a0, 0x10, 0, 2),
645
+
PIN_FIELD_BASE(51, 51, 8, 0x00a0, 0x10, 10, 2),
646
+
PIN_FIELD_BASE(52, 52, 8, 0x00a0, 0x10, 10, 2),
647
+
PIN_FIELD_BASE(53, 53, 8, 0x00a0, 0x10, 10, 2),
648
+
PIN_FIELD_BASE(54, 54, 8, 0x00a0, 0x10, 10, 2),
649
+
PIN_FIELD_BASE(55, 55, 4, 0x00a0, 0x10, 6, 2),
650
+
PIN_FIELD_BASE(56, 56, 4, 0x00a0, 0x10, 6, 2),
651
+
PIN_FIELD_BASE(57, 57, 2, 0x00c0, 0x10, 12, 2),
652
+
PIN_FIELD_BASE(58, 58, 2, 0x00c0, 0x10, 12, 2),
653
+
PIN_FIELD_BASE(59, 59, 2, 0x00c0, 0x10, 12, 2),
654
+
PIN_FIELD_BASE(60, 60, 2, 0x00c0, 0x10, 12, 2),
655
+
PIN_FIELD_BASE(61, 61, 2, 0x00c0, 0x10, 12, 2),
656
+
PIN_FIELD_BASE(62, 62, 2, 0x00c0, 0x10, 12, 2),
657
+
PIN_FIELD_BASE(63, 63, 2, 0x00c0, 0x10, 12, 2),
658
+
PIN_FIELD_BASE(64, 64, 2, 0x00c0, 0x10, 12, 2),
659
+
PIN_FIELD_BASE(65, 65, 9, 0x00d0, 0x10, 12, 2),
660
+
PIN_FIELD_BASE(66, 66, 9, 0x00d0, 0x10, 12, 2),
661
+
PIN_FIELD_BASE(67, 67, 9, 0x00d0, 0x10, 12, 2),
662
+
PIN_FIELD_BASE(68, 68, 9, 0x00d0, 0x10, 12, 2),
663
+
PIN_FIELD_BASE(69, 69, 2, 0x00c0, 0x10, 16, 2),
664
+
PIN_FIELD_BASE(70, 70, 2, 0x00c0, 0x10, 14, 2),
665
+
PIN_FIELD_BASE(71, 71, 2, 0x00c0, 0x10, 20, 2),
666
+
PIN_FIELD_BASE(72, 72, 2, 0x00c0, 0x10, 18, 2),
667
+
PIN_FIELD_BASE(73, 73, 2, 0x00c0, 0x10, 24, 2),
668
+
PIN_FIELD_BASE(74, 74, 2, 0x00c0, 0x10, 22, 2),
669
+
PIN_FIELD_BASE(75, 75, 3, 0x00e0, 0x10, 18, 2),
670
+
PIN_FIELD_BASE(76, 76, 2, 0x00c0, 0x10, 26, 2),
671
+
PIN_FIELD_BASE(77, 77, 8, 0x00a0, 0x10, 14, 2),
672
+
PIN_FIELD_BASE(78, 78, 8, 0x00a0, 0x10, 12, 2),
673
+
PIN_FIELD_BASE(79, 79, 8, 0x00a0, 0x10, 18, 2),
674
+
PIN_FIELD_BASE(80, 80, 8, 0x00a0, 0x10, 16, 2),
675
+
PIN_FIELD_BASE(81, 81, 2, 0x00c0, 0x10, 12, 2),
676
+
PIN_FIELD_BASE(82, 82, 2, 0x00c0, 0x10, 12, 2),
677
+
PIN_FIELD_BASE(83, 83, 2, 0x00c0, 0x10, 12, 2),
678
+
PIN_FIELD_BASE(84, 84, 7, 0x00d0, 0x10, 30, 2),
679
+
PIN_FIELD_BASE(85, 85, 7, 0x00d0, 0x10, 30, 2),
680
+
PIN_FIELD_BASE(86, 86, 7, 0x00d0, 0x10, 30, 2),
681
+
PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 30, 2),
682
+
PIN_FIELD_BASE(88, 88, 5, 0x00f0, 0x10, 24, 2),
683
+
PIN_FIELD_BASE(89, 89, 5, 0x00f0, 0x10, 24, 2),
684
+
PIN_FIELD_BASE(90, 90, 5, 0x00f0, 0x10, 24, 2),
685
+
PIN_FIELD_BASE(91, 91, 5, 0x00f0, 0x10, 24, 2),
686
+
PIN_FIELD_BASE(92, 92, 5, 0x00f0, 0x10, 26, 2),
687
+
PIN_FIELD_BASE(93, 93, 5, 0x00f0, 0x10, 26, 2),
688
+
PIN_FIELD_BASE(94, 94, 5, 0x00f0, 0x10, 26, 2),
689
+
PIN_FIELD_BASE(95, 95, 5, 0x00f0, 0x10, 26, 2),
690
+
PIN_FIELD_BASE(96, 96, 5, 0x00f0, 0x10, 28, 2),
691
+
PIN_FIELD_BASE(97, 97, 5, 0x00f0, 0x10, 26, 2),
692
+
PIN_FIELD_BASE(98, 98, 5, 0x00f0, 0x10, 26, 2),
693
+
PIN_FIELD_BASE(99, 99, 5, 0x00f0, 0x10, 26, 2),
694
+
PIN_FIELD_BASE(100, 100, 5, 0x00f0, 0x10, 26, 2),
695
+
PIN_FIELD_BASE(101, 101, 5, 0x00f0, 0x10, 26, 2),
696
+
PIN_FIELD_BASE(102, 102, 5, 0x00f0, 0x10, 26, 2),
697
+
PIN_FIELD_BASE(103, 103, 7, 0x00d0, 0x10, 20, 2),
698
+
PIN_FIELD_BASE(104, 104, 7, 0x00d0, 0x10, 14, 2),
699
+
PIN_FIELD_BASE(105, 105, 7, 0x00d0, 0x10, 18, 2),
700
+
PIN_FIELD_BASE(106, 106, 7, 0x00d0, 0x10, 16, 2),
701
+
PIN_FIELD_BASE(107, 107, 7, 0x00d0, 0x10, 28, 2),
702
+
PIN_FIELD_BASE(108, 108, 7, 0x00d0, 0x10, 22, 2),
703
+
PIN_FIELD_BASE(109, 109, 7, 0x00d0, 0x10, 26, 2),
704
+
PIN_FIELD_BASE(110, 110, 7, 0x00d0, 0x10, 24, 2),
705
+
PIN_FIELD_BASE(111, 111, 7, 0x00d0, 0x10, 30, 2),
706
+
PIN_FIELD_BASE(112, 112, 8, 0x00a0, 0x10, 10, 2),
707
+
PIN_FIELD_BASE(113, 113, 8, 0x00a0, 0x10, 10, 2),
708
+
PIN_FIELD_BASE(114, 114, 8, 0x00a0, 0x10, 10, 2),
709
+
PIN_FIELD_BASE(115, 115, 2, 0x00c0, 0x10, 12, 2),
710
+
PIN_FIELD_BASE(116, 116, 2, 0x00c0, 0x10, 12, 2),
711
+
PIN_FIELD_BASE(117, 117, 2, 0x00c0, 0x10, 12, 2),
712
+
PIN_FIELD_BASE(118, 118, 2, 0x00c0, 0x10, 12, 2),
713
+
PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 28, 2),
714
+
PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 26, 2),
715
+
PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 24, 2),
716
+
PIN_FIELD_BASE(122, 122, 1, 0x00a0, 0x10, 22, 2),
717
+
PIN_FIELD_BASE(123, 123, 1, 0x00a0, 0x10, 14, 2),
718
+
PIN_FIELD_BASE(124, 124, 1, 0x00a0, 0x10, 12, 2),
719
+
PIN_FIELD_BASE(125, 125, 1, 0x00a0, 0x10, 10, 2),
720
+
PIN_FIELD_BASE(126, 126, 1, 0x00a0, 0x10, 8, 2),
721
+
PIN_FIELD_BASE(127, 127, 1, 0x00a0, 0x10, 20, 2),
722
+
PIN_FIELD_BASE(128, 128, 1, 0x00a0, 0x10, 6, 2),
723
+
PIN_FIELD_BASE(129, 129, 1, 0x00a0, 0x10, 16, 2),
724
+
PIN_FIELD_BASE(130, 130, 1, 0x00a0, 0x10, 30, 2),
725
+
PIN_FIELD_BASE(131, 131, 1, 0x00a0, 0x10, 2, 2),
726
+
PIN_FIELD_BASE(132, 132, 1, 0x00a0, 0x10, 4, 2),
727
+
PIN_FIELD_BASE(133, 133, 1, 0x00b0, 0x10, 0, 2),
728
+
PIN_FIELD_BASE(134, 134, 1, 0x00a0, 0x10, 18, 2),
729
+
PIN_FIELD_BASE(135, 135, 1, 0x00a0, 0x10, 0, 2),
730
+
PIN_FIELD_BASE(136, 136, 1, 0x00b0, 0x10, 2, 2),
731
+
PIN_FIELD_BASE(137, 137, 2, 0x00c0, 0x10, 12, 2),
732
+
PIN_FIELD_BASE(138, 138, 2, 0x00c0, 0x10, 12, 2),
733
+
PIN_FIELD_BASE(139, 139, 1, 0x00b0, 0x10, 6, 2),
734
+
PIN_FIELD_BASE(140, 140, 1, 0x00b0, 0x10, 6, 2),
735
+
PIN_FIELD_BASE(141, 141, 1, 0x00b0, 0x10, 6, 2),
736
+
PIN_FIELD_BASE(142, 142, 1, 0x00b0, 0x10, 6, 2),
737
+
PIN_FIELD_BASE(143, 143, 1, 0x00b0, 0x10, 6, 2),
738
+
PIN_FIELD_BASE(144, 144, 1, 0x00b0, 0x10, 6, 2),
739
+
PIN_FIELD_BASE(145, 145, 1, 0x00b0, 0x10, 4, 2),
740
+
PIN_FIELD_BASE(146, 146, 1, 0x00b0, 0x10, 4, 2),
741
+
PIN_FIELD_BASE(147, 147, 1, 0x00b0, 0x10, 4, 2),
742
+
PIN_FIELD_BASE(148, 148, 1, 0x00b0, 0x10, 4, 2),
743
+
PIN_FIELD_BASE(149, 149, 1, 0x00b0, 0x10, 4, 2),
744
+
PIN_FIELD_BASE(150, 150, 3, 0x00e0, 0x10, 16, 2),
745
+
PIN_FIELD_BASE(151, 151, 1, 0x00b0, 0x10, 8, 2),
746
+
PIN_FIELD_BASE(152, 152, 3, 0x00e0, 0x10, 16, 2),
747
+
PIN_FIELD_BASE(153, 153, 3, 0x00e0, 0x10, 16, 2),
748
+
PIN_FIELD_BASE(154, 154, 3, 0x00e0, 0x10, 16, 2),
749
+
PIN_FIELD_BASE(155, 155, 3, 0x00e0, 0x10, 16, 2),
750
+
PIN_FIELD_BASE(156, 156, 5, 0x00f0, 0x10, 6, 6),
751
+
PIN_FIELD_BASE(157, 157, 5, 0x00f0, 0x10, 0, 6),
752
+
PIN_FIELD_BASE(158, 158, 5, 0x00e0, 0x10, 24, 6),
753
+
PIN_FIELD_BASE(159, 159, 6, 0x0080, 0x10, 12, 6),
754
+
PIN_FIELD_BASE(160, 160, 5, 0x00f0, 0x10, 18, 6),
755
+
PIN_FIELD_BASE(161, 161, 5, 0x00e0, 0x10, 6, 6),
756
+
PIN_FIELD_BASE(162, 162, 5, 0x00e0, 0x10, 0, 6),
757
+
PIN_FIELD_BASE(163, 163, 6, 0x0080, 0x10, 6, 6),
758
+
PIN_FIELD_BASE(164, 164, 5, 0x00e0, 0x10, 18, 6),
759
+
PIN_FIELD_BASE(165, 165, 5, 0x00e0, 0x10, 12, 6),
760
+
PIN_FIELD_BASE(166, 166, 6, 0x0080, 0x10, 0, 6),
761
+
PIN_FIELD_BASE(167, 167, 5, 0x00f0, 0x10, 12, 6),
762
+
PIN_FIELD_BASE(168, 168, 3, 0x00d0, 0x10, 10, 6),
763
+
PIN_FIELD_BASE(169, 169, 3, 0x00d0, 0x10, 4, 6),
764
+
PIN_FIELD_BASE(170, 170, 3, 0x00d0, 0x10, 16, 6),
765
+
PIN_FIELD_BASE(171, 171, 3, 0x00d0, 0x10, 22, 6),
766
+
PIN_FIELD_BASE(172, 172, 3, 0x00e0, 0x10, 0, 6),
767
+
PIN_FIELD_BASE(173, 173, 3, 0x00e0, 0x10, 6, 6),
768
+
PIN_FIELD_BASE(174, 174, 9, 0x00c0, 0x10, 12, 6),
769
+
PIN_FIELD_BASE(175, 175, 9, 0x00c0, 0x10, 6, 6),
770
+
PIN_FIELD_BASE(176, 176, 9, 0x00c0, 0x10, 18, 6),
771
+
PIN_FIELD_BASE(177, 177, 9, 0x00c0, 0x10, 24, 6),
772
+
PIN_FIELD_BASE(178, 178, 9, 0x00d0, 0x10, 0, 6),
773
+
PIN_FIELD_BASE(179, 179, 9, 0x00d0, 0x10, 6, 6),
774
+
PIN_FIELD_BASE(180, 180, 5, 0x00f0, 0x10, 30, 2),
775
+
PIN_FIELD_BASE(181, 181, 5, 0x0100, 0x10, 0, 2),
776
+
PIN_FIELD_BASE(182, 182, 9, 0x00d0, 0x10, 14, 2),
777
+
};
778
+
779
+
static const struct mtk_pin_field_calc mt8189_pin_pupd_range[] = {
780
+
PIN_FIELD_BASE(44, 44, 7, 0x0090, 0x10, 0, 1),
781
+
PIN_FIELD_BASE(45, 45, 7, 0x0090, 0x10, 1, 1),
782
+
PIN_FIELD_BASE(46, 46, 7, 0x0090, 0x10, 2, 1),
783
+
PIN_FIELD_BASE(47, 47, 7, 0x0090, 0x10, 3, 1),
784
+
PIN_FIELD_BASE(156, 156, 5, 0x00a0, 0x10, 6, 1),
785
+
PIN_FIELD_BASE(157, 157, 5, 0x00a0, 0x10, 5, 1),
786
+
PIN_FIELD_BASE(158, 158, 5, 0x00a0, 0x10, 4, 1),
787
+
PIN_FIELD_BASE(159, 159, 6, 0x0050, 0x10, 2, 1),
788
+
PIN_FIELD_BASE(160, 160, 5, 0x00a0, 0x10, 8, 1),
789
+
PIN_FIELD_BASE(161, 161, 5, 0x00a0, 0x10, 1, 1),
790
+
PIN_FIELD_BASE(162, 162, 5, 0x00a0, 0x10, 0, 1),
791
+
PIN_FIELD_BASE(163, 163, 6, 0x0050, 0x10, 1, 1),
792
+
PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 3, 1),
793
+
PIN_FIELD_BASE(165, 165, 5, 0x00a0, 0x10, 2, 1),
794
+
PIN_FIELD_BASE(166, 166, 6, 0x0050, 0x10, 0, 1),
795
+
PIN_FIELD_BASE(167, 167, 5, 0x00a0, 0x10, 7, 1),
796
+
PIN_FIELD_BASE(168, 168, 3, 0x0090, 0x10, 1, 1),
797
+
PIN_FIELD_BASE(169, 169, 3, 0x0090, 0x10, 0, 1),
798
+
PIN_FIELD_BASE(170, 170, 3, 0x0090, 0x10, 2, 1),
799
+
PIN_FIELD_BASE(171, 171, 3, 0x0090, 0x10, 3, 1),
800
+
PIN_FIELD_BASE(172, 172, 3, 0x0090, 0x10, 4, 1),
801
+
PIN_FIELD_BASE(173, 173, 3, 0x0090, 0x10, 5, 1),
802
+
PIN_FIELD_BASE(174, 174, 9, 0x0080, 0x10, 1, 1),
803
+
PIN_FIELD_BASE(175, 175, 9, 0x0080, 0x10, 0, 1),
804
+
PIN_FIELD_BASE(176, 176, 9, 0x0080, 0x10, 2, 1),
805
+
PIN_FIELD_BASE(177, 177, 9, 0x0080, 0x10, 3, 1),
806
+
PIN_FIELD_BASE(178, 178, 9, 0x0080, 0x10, 4, 1),
807
+
PIN_FIELD_BASE(179, 179, 9, 0x0080, 0x10, 5, 1),
808
+
};
809
+
810
+
static const struct mtk_pin_field_calc mt8189_pin_r0_range[] = {
811
+
PIN_FIELD_BASE(44, 44, 7, 0x00b0, 0x10, 0, 1),
812
+
PIN_FIELD_BASE(45, 45, 7, 0x00b0, 0x10, 1, 1),
813
+
PIN_FIELD_BASE(46, 46, 7, 0x00b0, 0x10, 2, 1),
814
+
PIN_FIELD_BASE(47, 47, 7, 0x00b0, 0x10, 3, 1),
815
+
PIN_FIELD_BASE(156, 156, 5, 0x00c0, 0x10, 6, 1),
816
+
PIN_FIELD_BASE(157, 157, 5, 0x00c0, 0x10, 5, 1),
817
+
PIN_FIELD_BASE(158, 158, 5, 0x00c0, 0x10, 4, 1),
818
+
PIN_FIELD_BASE(159, 159, 6, 0x0060, 0x10, 2, 1),
819
+
PIN_FIELD_BASE(160, 160, 5, 0x00c0, 0x10, 8, 1),
820
+
PIN_FIELD_BASE(161, 161, 5, 0x00c0, 0x10, 1, 1),
821
+
PIN_FIELD_BASE(162, 162, 5, 0x00c0, 0x10, 0, 1),
822
+
PIN_FIELD_BASE(163, 163, 6, 0x0060, 0x10, 1, 1),
823
+
PIN_FIELD_BASE(164, 164, 5, 0x00c0, 0x10, 3, 1),
824
+
PIN_FIELD_BASE(165, 165, 5, 0x00c0, 0x10, 2, 1),
825
+
PIN_FIELD_BASE(166, 166, 6, 0x0060, 0x10, 0, 1),
826
+
PIN_FIELD_BASE(167, 167, 5, 0x00c0, 0x10, 7, 1),
827
+
PIN_FIELD_BASE(168, 168, 3, 0x00b0, 0x10, 1, 1),
828
+
PIN_FIELD_BASE(169, 169, 3, 0x00b0, 0x10, 0, 1),
829
+
PIN_FIELD_BASE(170, 170, 3, 0x00b0, 0x10, 2, 1),
830
+
PIN_FIELD_BASE(171, 171, 3, 0x00b0, 0x10, 3, 1),
831
+
PIN_FIELD_BASE(172, 172, 3, 0x00b0, 0x10, 4, 1),
832
+
PIN_FIELD_BASE(173, 173, 3, 0x00b0, 0x10, 5, 1),
833
+
PIN_FIELD_BASE(174, 174, 9, 0x00a0, 0x10, 1, 1),
834
+
PIN_FIELD_BASE(175, 175, 9, 0x00a0, 0x10, 0, 1),
835
+
PIN_FIELD_BASE(176, 176, 9, 0x00a0, 0x10, 2, 1),
836
+
PIN_FIELD_BASE(177, 177, 9, 0x00a0, 0x10, 3, 1),
837
+
PIN_FIELD_BASE(178, 178, 9, 0x00a0, 0x10, 4, 1),
838
+
PIN_FIELD_BASE(179, 179, 9, 0x00a0, 0x10, 5, 1),
839
+
};
840
+
841
+
static const struct mtk_pin_field_calc mt8189_pin_r1_range[] = {
842
+
PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 0, 1),
843
+
PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 1, 1),
844
+
PIN_FIELD_BASE(46, 46, 7, 0x00c0, 0x10, 2, 1),
845
+
PIN_FIELD_BASE(47, 47, 7, 0x00c0, 0x10, 3, 1),
846
+
PIN_FIELD_BASE(156, 156, 5, 0x00d0, 0x10, 6, 1),
847
+
PIN_FIELD_BASE(157, 157, 5, 0x00d0, 0x10, 5, 1),
848
+
PIN_FIELD_BASE(158, 158, 5, 0x00d0, 0x10, 4, 1),
849
+
PIN_FIELD_BASE(159, 159, 6, 0x0070, 0x10, 2, 1),
850
+
PIN_FIELD_BASE(160, 160, 5, 0x00d0, 0x10, 8, 1),
851
+
PIN_FIELD_BASE(161, 161, 5, 0x00d0, 0x10, 1, 1),
852
+
PIN_FIELD_BASE(162, 162, 5, 0x00d0, 0x10, 0, 1),
853
+
PIN_FIELD_BASE(163, 163, 6, 0x0070, 0x10, 1, 1),
854
+
PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 3, 1),
855
+
PIN_FIELD_BASE(165, 165, 5, 0x00d0, 0x10, 2, 1),
856
+
PIN_FIELD_BASE(166, 166, 6, 0x0070, 0x10, 0, 1),
857
+
PIN_FIELD_BASE(167, 167, 5, 0x00d0, 0x10, 7, 1),
858
+
PIN_FIELD_BASE(168, 168, 3, 0x00c0, 0x10, 1, 1),
859
+
PIN_FIELD_BASE(169, 169, 3, 0x00c0, 0x10, 0, 1),
860
+
PIN_FIELD_BASE(170, 170, 3, 0x00c0, 0x10, 2, 1),
861
+
PIN_FIELD_BASE(171, 171, 3, 0x00c0, 0x10, 3, 1),
862
+
PIN_FIELD_BASE(172, 172, 3, 0x00c0, 0x10, 4, 1),
863
+
PIN_FIELD_BASE(173, 173, 3, 0x00c0, 0x10, 5, 1),
864
+
PIN_FIELD_BASE(174, 174, 9, 0x00b0, 0x10, 1, 1),
865
+
PIN_FIELD_BASE(175, 175, 9, 0x00b0, 0x10, 0, 1),
866
+
PIN_FIELD_BASE(176, 176, 9, 0x00b0, 0x10, 2, 1),
867
+
PIN_FIELD_BASE(177, 177, 9, 0x00b0, 0x10, 3, 1),
868
+
PIN_FIELD_BASE(178, 178, 9, 0x00b0, 0x10, 4, 1),
869
+
PIN_FIELD_BASE(179, 179, 9, 0x00b0, 0x10, 5, 1),
870
+
};
871
+
872
+
static const struct mtk_pin_field_calc mt8189_pin_pu_range[] = {
873
+
PIN_FIELD_BASE(0, 0, 7, 0x00a0, 0x10, 5, 1),
874
+
PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 3, 1),
875
+
PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 4, 1),
876
+
PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 5, 1),
877
+
PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 6, 1),
878
+
PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 7, 1),
879
+
PIN_FIELD_BASE(6, 6, 7, 0x00a0, 0x10, 6, 1),
880
+
PIN_FIELD_BASE(7, 7, 7, 0x00a0, 0x10, 7, 1),
881
+
PIN_FIELD_BASE(8, 8, 7, 0x00a0, 0x10, 8, 1),
882
+
PIN_FIELD_BASE(9, 9, 7, 0x00a0, 0x10, 9, 1),
883
+
PIN_FIELD_BASE(10, 10, 7, 0x00a0, 0x10, 10, 1),
884
+
PIN_FIELD_BASE(11, 11, 7, 0x00a0, 0x10, 11, 1),
885
+
PIN_FIELD_BASE(12, 12, 2, 0x00b0, 0x10, 5, 1),
886
+
PIN_FIELD_BASE(13, 13, 2, 0x00b0, 0x10, 6, 1),
887
+
PIN_FIELD_BASE(14, 14, 3, 0x00a0, 0x10, 0, 1),
888
+
PIN_FIELD_BASE(15, 15, 3, 0x00a0, 0x10, 1, 1),
889
+
PIN_FIELD_BASE(16, 16, 2, 0x00b0, 0x10, 7, 1),
890
+
PIN_FIELD_BASE(17, 17, 2, 0x00b0, 0x10, 8, 1),
891
+
PIN_FIELD_BASE(18, 18, 7, 0x00a0, 0x10, 0, 1),
892
+
PIN_FIELD_BASE(19, 19, 7, 0x00a0, 0x10, 2, 1),
893
+
PIN_FIELD_BASE(20, 20, 7, 0x00a0, 0x10, 1, 1),
894
+
PIN_FIELD_BASE(21, 21, 7, 0x00a0, 0x10, 3, 1),
895
+
PIN_FIELD_BASE(22, 22, 9, 0x0090, 0x10, 0, 1),
896
+
PIN_FIELD_BASE(23, 23, 9, 0x0090, 0x10, 1, 1),
897
+
PIN_FIELD_BASE(24, 24, 9, 0x0090, 0x10, 2, 1),
898
+
PIN_FIELD_BASE(25, 25, 4, 0x0090, 0x10, 2, 1),
899
+
PIN_FIELD_BASE(26, 26, 4, 0x0090, 0x10, 1, 1),
900
+
PIN_FIELD_BASE(27, 27, 2, 0x00b0, 0x10, 1, 1),
901
+
PIN_FIELD_BASE(28, 28, 2, 0x00b0, 0x10, 2, 1),
902
+
PIN_FIELD_BASE(29, 29, 4, 0x0090, 0x10, 0, 1),
903
+
PIN_FIELD_BASE(30, 30, 2, 0x00b0, 0x10, 0, 1),
904
+
PIN_FIELD_BASE(31, 31, 3, 0x00a0, 0x10, 13, 1),
905
+
PIN_FIELD_BASE(32, 32, 1, 0x0090, 0x10, 30, 1),
906
+
PIN_FIELD_BASE(33, 33, 3, 0x00a0, 0x10, 15, 1),
907
+
PIN_FIELD_BASE(34, 34, 3, 0x00a0, 0x10, 14, 1),
908
+
PIN_FIELD_BASE(35, 35, 3, 0x00a0, 0x10, 17, 1),
909
+
PIN_FIELD_BASE(36, 36, 3, 0x00a0, 0x10, 16, 1),
910
+
PIN_FIELD_BASE(37, 37, 3, 0x00a0, 0x10, 19, 1),
911
+
PIN_FIELD_BASE(38, 38, 3, 0x00a0, 0x10, 18, 1),
912
+
PIN_FIELD_BASE(39, 39, 3, 0x00a0, 0x10, 5, 1),
913
+
PIN_FIELD_BASE(40, 40, 3, 0x00a0, 0x10, 2, 1),
914
+
PIN_FIELD_BASE(41, 41, 3, 0x00a0, 0x10, 3, 1),
915
+
PIN_FIELD_BASE(42, 42, 3, 0x00a0, 0x10, 4, 1),
916
+
PIN_FIELD_BASE(43, 43, 3, 0x00a0, 0x10, 6, 1),
917
+
PIN_FIELD_BASE(48, 48, 4, 0x0090, 0x10, 5, 1),
918
+
PIN_FIELD_BASE(49, 49, 4, 0x0090, 0x10, 4, 1),
919
+
PIN_FIELD_BASE(50, 50, 4, 0x0090, 0x10, 3, 1),
920
+
PIN_FIELD_BASE(51, 51, 8, 0x0090, 0x10, 8, 1),
921
+
PIN_FIELD_BASE(52, 52, 8, 0x0090, 0x10, 10, 1),
922
+
PIN_FIELD_BASE(53, 53, 8, 0x0090, 0x10, 9, 1),
923
+
PIN_FIELD_BASE(54, 54, 8, 0x0090, 0x10, 11, 1),
924
+
PIN_FIELD_BASE(55, 55, 4, 0x0090, 0x10, 6, 1),
925
+
PIN_FIELD_BASE(56, 56, 4, 0x0090, 0x10, 7, 1),
926
+
PIN_FIELD_BASE(57, 57, 2, 0x00b0, 0x10, 13, 1),
927
+
PIN_FIELD_BASE(58, 58, 2, 0x00b0, 0x10, 17, 1),
928
+
PIN_FIELD_BASE(59, 59, 2, 0x00b0, 0x10, 14, 1),
929
+
PIN_FIELD_BASE(60, 60, 2, 0x00b0, 0x10, 18, 1),
930
+
PIN_FIELD_BASE(61, 61, 2, 0x00b0, 0x10, 15, 1),
931
+
PIN_FIELD_BASE(62, 62, 2, 0x00b0, 0x10, 19, 1),
932
+
PIN_FIELD_BASE(63, 63, 2, 0x00b0, 0x10, 16, 1),
933
+
PIN_FIELD_BASE(64, 64, 2, 0x00b0, 0x10, 20, 1),
934
+
PIN_FIELD_BASE(65, 65, 9, 0x0090, 0x10, 4, 1),
935
+
PIN_FIELD_BASE(66, 66, 9, 0x0090, 0x10, 6, 1),
936
+
PIN_FIELD_BASE(67, 67, 9, 0x0090, 0x10, 5, 1),
937
+
PIN_FIELD_BASE(68, 68, 9, 0x0090, 0x10, 7, 1),
938
+
PIN_FIELD_BASE(69, 69, 2, 0x00b0, 0x10, 22, 1),
939
+
PIN_FIELD_BASE(70, 70, 2, 0x00b0, 0x10, 21, 1),
940
+
PIN_FIELD_BASE(71, 71, 2, 0x00b0, 0x10, 24, 1),
941
+
PIN_FIELD_BASE(72, 72, 2, 0x00b0, 0x10, 23, 1),
942
+
PIN_FIELD_BASE(73, 73, 2, 0x00b0, 0x10, 26, 1),
943
+
PIN_FIELD_BASE(74, 74, 2, 0x00b0, 0x10, 25, 1),
944
+
PIN_FIELD_BASE(75, 75, 3, 0x00a0, 0x10, 7, 1),
945
+
PIN_FIELD_BASE(76, 76, 2, 0x00b0, 0x10, 27, 1),
946
+
PIN_FIELD_BASE(77, 77, 8, 0x0090, 0x10, 13, 1),
947
+
PIN_FIELD_BASE(78, 78, 8, 0x0090, 0x10, 12, 1),
948
+
PIN_FIELD_BASE(79, 79, 8, 0x0090, 0x10, 15, 1),
949
+
PIN_FIELD_BASE(80, 80, 8, 0x0090, 0x10, 14, 1),
950
+
PIN_FIELD_BASE(81, 81, 2, 0x00b0, 0x10, 29, 1),
951
+
PIN_FIELD_BASE(82, 82, 2, 0x00b0, 0x10, 28, 1),
952
+
PIN_FIELD_BASE(83, 83, 2, 0x00b0, 0x10, 30, 1),
953
+
PIN_FIELD_BASE(84, 84, 7, 0x00a0, 0x10, 22, 1),
954
+
PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 23, 1),
955
+
PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 24, 1),
956
+
PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 25, 1),
957
+
PIN_FIELD_BASE(88, 88, 5, 0x00b0, 0x10, 11, 1),
958
+
PIN_FIELD_BASE(89, 89, 5, 0x00b0, 0x10, 10, 1),
959
+
PIN_FIELD_BASE(90, 90, 5, 0x00b0, 0x10, 13, 1),
960
+
PIN_FIELD_BASE(91, 91, 5, 0x00b0, 0x10, 12, 1),
961
+
PIN_FIELD_BASE(92, 92, 5, 0x00b0, 0x10, 7, 1),
962
+
PIN_FIELD_BASE(93, 93, 5, 0x00b0, 0x10, 8, 1),
963
+
PIN_FIELD_BASE(94, 94, 5, 0x00b0, 0x10, 14, 1),
964
+
PIN_FIELD_BASE(95, 95, 5, 0x00b0, 0x10, 6, 1),
965
+
PIN_FIELD_BASE(96, 96, 5, 0x00b0, 0x10, 9, 1),
966
+
PIN_FIELD_BASE(97, 97, 5, 0x00b0, 0x10, 0, 1),
967
+
PIN_FIELD_BASE(98, 98, 5, 0x00b0, 0x10, 5, 1),
968
+
PIN_FIELD_BASE(99, 99, 5, 0x00b0, 0x10, 3, 1),
969
+
PIN_FIELD_BASE(100, 100, 5, 0x00b0, 0x10, 4, 1),
970
+
PIN_FIELD_BASE(101, 101, 5, 0x00b0, 0x10, 1, 1),
971
+
PIN_FIELD_BASE(102, 102, 5, 0x00b0, 0x10, 2, 1),
972
+
PIN_FIELD_BASE(103, 103, 7, 0x00a0, 0x10, 15, 1),
973
+
PIN_FIELD_BASE(104, 104, 7, 0x00a0, 0x10, 12, 1),
974
+
PIN_FIELD_BASE(105, 105, 7, 0x00a0, 0x10, 14, 1),
975
+
PIN_FIELD_BASE(106, 106, 7, 0x00a0, 0x10, 13, 1),
976
+
PIN_FIELD_BASE(107, 107, 7, 0x00a0, 0x10, 19, 1),
977
+
PIN_FIELD_BASE(108, 108, 7, 0x00a0, 0x10, 16, 1),
978
+
PIN_FIELD_BASE(109, 109, 7, 0x00a0, 0x10, 18, 1),
979
+
PIN_FIELD_BASE(110, 110, 7, 0x00a0, 0x10, 17, 1),
980
+
PIN_FIELD_BASE(111, 111, 7, 0x00a0, 0x10, 4, 1),
981
+
PIN_FIELD_BASE(112, 112, 8, 0x0090, 0x10, 0, 1),
982
+
PIN_FIELD_BASE(113, 113, 8, 0x0090, 0x10, 1, 1),
983
+
PIN_FIELD_BASE(114, 114, 8, 0x0090, 0x10, 2, 1),
984
+
PIN_FIELD_BASE(115, 115, 2, 0x00b0, 0x10, 9, 1),
985
+
PIN_FIELD_BASE(116, 116, 2, 0x00b0, 0x10, 12, 1),
986
+
PIN_FIELD_BASE(117, 117, 2, 0x00b0, 0x10, 10, 1),
987
+
PIN_FIELD_BASE(118, 118, 2, 0x00b0, 0x10, 11, 1),
988
+
PIN_FIELD_BASE(119, 119, 1, 0x0090, 0x10, 26, 1),
989
+
PIN_FIELD_BASE(120, 120, 1, 0x0090, 0x10, 25, 1),
990
+
PIN_FIELD_BASE(121, 121, 1, 0x0090, 0x10, 24, 1),
991
+
PIN_FIELD_BASE(122, 122, 1, 0x0090, 0x10, 23, 1),
992
+
PIN_FIELD_BASE(123, 123, 1, 0x0090, 0x10, 19, 1),
993
+
PIN_FIELD_BASE(124, 124, 1, 0x0090, 0x10, 18, 1),
994
+
PIN_FIELD_BASE(125, 125, 1, 0x0090, 0x10, 17, 1),
995
+
PIN_FIELD_BASE(126, 126, 1, 0x0090, 0x10, 16, 1),
996
+
PIN_FIELD_BASE(127, 127, 1, 0x0090, 0x10, 22, 1),
997
+
PIN_FIELD_BASE(128, 128, 1, 0x0090, 0x10, 15, 1),
998
+
PIN_FIELD_BASE(129, 129, 1, 0x0090, 0x10, 20, 1),
999
+
PIN_FIELD_BASE(130, 130, 1, 0x0090, 0x10, 27, 1),
1000
+
PIN_FIELD_BASE(131, 131, 1, 0x0090, 0x10, 13, 1),
1001
+
PIN_FIELD_BASE(132, 132, 1, 0x0090, 0x10, 14, 1),
1002
+
PIN_FIELD_BASE(133, 133, 1, 0x0090, 0x10, 28, 1),
1003
+
PIN_FIELD_BASE(134, 134, 1, 0x0090, 0x10, 21, 1),
1004
+
PIN_FIELD_BASE(135, 135, 1, 0x0090, 0x10, 11, 1),
1005
+
PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 12, 1),
1006
+
PIN_FIELD_BASE(137, 137, 2, 0x00b0, 0x10, 3, 1),
1007
+
PIN_FIELD_BASE(138, 138, 2, 0x00b0, 0x10, 4, 1),
1008
+
PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 3, 1),
1009
+
PIN_FIELD_BASE(140, 140, 1, 0x0090, 0x10, 4, 1),
1010
+
PIN_FIELD_BASE(141, 141, 1, 0x0090, 0x10, 0, 1),
1011
+
PIN_FIELD_BASE(142, 142, 1, 0x0090, 0x10, 1, 1),
1012
+
PIN_FIELD_BASE(143, 143, 1, 0x0090, 0x10, 2, 1),
1013
+
PIN_FIELD_BASE(144, 144, 1, 0x0090, 0x10, 5, 1),
1014
+
PIN_FIELD_BASE(145, 145, 1, 0x0090, 0x10, 6, 1),
1015
+
PIN_FIELD_BASE(146, 146, 1, 0x0090, 0x10, 7, 1),
1016
+
PIN_FIELD_BASE(147, 147, 1, 0x0090, 0x10, 8, 1),
1017
+
PIN_FIELD_BASE(148, 148, 1, 0x0090, 0x10, 9, 1),
1018
+
PIN_FIELD_BASE(149, 149, 1, 0x0090, 0x10, 10, 1),
1019
+
PIN_FIELD_BASE(150, 150, 3, 0x00a0, 0x10, 8, 1),
1020
+
PIN_FIELD_BASE(151, 151, 1, 0x0090, 0x10, 29, 1),
1021
+
PIN_FIELD_BASE(152, 152, 3, 0x00a0, 0x10, 9, 1),
1022
+
PIN_FIELD_BASE(153, 153, 3, 0x00a0, 0x10, 10, 1),
1023
+
PIN_FIELD_BASE(154, 154, 3, 0x00a0, 0x10, 11, 1),
1024
+
PIN_FIELD_BASE(155, 155, 3, 0x00a0, 0x10, 12, 1),
1025
+
PIN_FIELD_BASE(180, 180, 5, 0x00b0, 0x10, 15, 1),
1026
+
PIN_FIELD_BASE(181, 181, 5, 0x00b0, 0x10, 16, 1),
1027
+
PIN_FIELD_BASE(182, 182, 9, 0x0090, 0x10, 3, 1),
1028
+
};
1029
+
1030
+
static const struct mtk_pin_field_calc mt8189_pin_pd_range[] = {
1031
+
PIN_FIELD_BASE(0, 0, 7, 0x0080, 0x10, 5, 1),
1032
+
PIN_FIELD_BASE(1, 1, 8, 0x0080, 0x10, 3, 1),
1033
+
PIN_FIELD_BASE(2, 2, 8, 0x0080, 0x10, 4, 1),
1034
+
PIN_FIELD_BASE(3, 3, 8, 0x0080, 0x10, 5, 1),
1035
+
PIN_FIELD_BASE(4, 4, 8, 0x0080, 0x10, 6, 1),
1036
+
PIN_FIELD_BASE(5, 5, 8, 0x0080, 0x10, 7, 1),
1037
+
PIN_FIELD_BASE(6, 6, 7, 0x0080, 0x10, 6, 1),
1038
+
PIN_FIELD_BASE(7, 7, 7, 0x0080, 0x10, 7, 1),
1039
+
PIN_FIELD_BASE(8, 8, 7, 0x0080, 0x10, 8, 1),
1040
+
PIN_FIELD_BASE(9, 9, 7, 0x0080, 0x10, 9, 1),
1041
+
PIN_FIELD_BASE(10, 10, 7, 0x0080, 0x10, 10, 1),
1042
+
PIN_FIELD_BASE(11, 11, 7, 0x0080, 0x10, 11, 1),
1043
+
PIN_FIELD_BASE(12, 12, 2, 0x00a0, 0x10, 5, 1),
1044
+
PIN_FIELD_BASE(13, 13, 2, 0x00a0, 0x10, 6, 1),
1045
+
PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 0, 1),
1046
+
PIN_FIELD_BASE(15, 15, 3, 0x0080, 0x10, 1, 1),
1047
+
PIN_FIELD_BASE(16, 16, 2, 0x00a0, 0x10, 7, 1),
1048
+
PIN_FIELD_BASE(17, 17, 2, 0x00a0, 0x10, 8, 1),
1049
+
PIN_FIELD_BASE(18, 18, 7, 0x0080, 0x10, 0, 1),
1050
+
PIN_FIELD_BASE(19, 19, 7, 0x0080, 0x10, 2, 1),
1051
+
PIN_FIELD_BASE(20, 20, 7, 0x0080, 0x10, 1, 1),
1052
+
PIN_FIELD_BASE(21, 21, 7, 0x0080, 0x10, 3, 1),
1053
+
PIN_FIELD_BASE(22, 22, 9, 0x0070, 0x10, 0, 1),
1054
+
PIN_FIELD_BASE(23, 23, 9, 0x0070, 0x10, 1, 1),
1055
+
PIN_FIELD_BASE(24, 24, 9, 0x0070, 0x10, 2, 1),
1056
+
PIN_FIELD_BASE(25, 25, 4, 0x0080, 0x10, 2, 1),
1057
+
PIN_FIELD_BASE(26, 26, 4, 0x0080, 0x10, 1, 1),
1058
+
PIN_FIELD_BASE(27, 27, 2, 0x00a0, 0x10, 1, 1),
1059
+
PIN_FIELD_BASE(28, 28, 2, 0x00a0, 0x10, 2, 1),
1060
+
PIN_FIELD_BASE(29, 29, 4, 0x0080, 0x10, 0, 1),
1061
+
PIN_FIELD_BASE(30, 30, 2, 0x00a0, 0x10, 0, 1),
1062
+
PIN_FIELD_BASE(31, 31, 3, 0x0080, 0x10, 13, 1),
1063
+
PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 30, 1),
1064
+
PIN_FIELD_BASE(33, 33, 3, 0x0080, 0x10, 15, 1),
1065
+
PIN_FIELD_BASE(34, 34, 3, 0x0080, 0x10, 14, 1),
1066
+
PIN_FIELD_BASE(35, 35, 3, 0x0080, 0x10, 17, 1),
1067
+
PIN_FIELD_BASE(36, 36, 3, 0x0080, 0x10, 16, 1),
1068
+
PIN_FIELD_BASE(37, 37, 3, 0x0080, 0x10, 19, 1),
1069
+
PIN_FIELD_BASE(38, 38, 3, 0x0080, 0x10, 18, 1),
1070
+
PIN_FIELD_BASE(39, 39, 3, 0x0080, 0x10, 5, 1),
1071
+
PIN_FIELD_BASE(40, 40, 3, 0x0080, 0x10, 2, 1),
1072
+
PIN_FIELD_BASE(41, 41, 3, 0x0080, 0x10, 3, 1),
1073
+
PIN_FIELD_BASE(42, 42, 3, 0x0080, 0x10, 4, 1),
1074
+
PIN_FIELD_BASE(43, 43, 3, 0x0080, 0x10, 6, 1),
1075
+
PIN_FIELD_BASE(48, 48, 4, 0x0080, 0x10, 5, 1),
1076
+
PIN_FIELD_BASE(49, 49, 4, 0x0080, 0x10, 4, 1),
1077
+
PIN_FIELD_BASE(50, 50, 4, 0x0080, 0x10, 3, 1),
1078
+
PIN_FIELD_BASE(51, 51, 8, 0x0080, 0x10, 8, 1),
1079
+
PIN_FIELD_BASE(52, 52, 8, 0x0080, 0x10, 10, 1),
1080
+
PIN_FIELD_BASE(53, 53, 8, 0x0080, 0x10, 9, 1),
1081
+
PIN_FIELD_BASE(54, 54, 8, 0x0080, 0x10, 11, 1),
1082
+
PIN_FIELD_BASE(55, 55, 4, 0x0080, 0x10, 6, 1),
1083
+
PIN_FIELD_BASE(56, 56, 4, 0x0080, 0x10, 7, 1),
1084
+
PIN_FIELD_BASE(57, 57, 2, 0x00a0, 0x10, 13, 1),
1085
+
PIN_FIELD_BASE(58, 58, 2, 0x00a0, 0x10, 17, 1),
1086
+
PIN_FIELD_BASE(59, 59, 2, 0x00a0, 0x10, 14, 1),
1087
+
PIN_FIELD_BASE(60, 60, 2, 0x00a0, 0x10, 18, 1),
1088
+
PIN_FIELD_BASE(61, 61, 2, 0x00a0, 0x10, 15, 1),
1089
+
PIN_FIELD_BASE(62, 62, 2, 0x00a0, 0x10, 19, 1),
1090
+
PIN_FIELD_BASE(63, 63, 2, 0x00a0, 0x10, 16, 1),
1091
+
PIN_FIELD_BASE(64, 64, 2, 0x00a0, 0x10, 20, 1),
1092
+
PIN_FIELD_BASE(65, 65, 9, 0x0070, 0x10, 4, 1),
1093
+
PIN_FIELD_BASE(66, 66, 9, 0x0070, 0x10, 6, 1),
1094
+
PIN_FIELD_BASE(67, 67, 9, 0x0070, 0x10, 5, 1),
1095
+
PIN_FIELD_BASE(68, 68, 9, 0x0070, 0x10, 7, 1),
1096
+
PIN_FIELD_BASE(69, 69, 2, 0x00a0, 0x10, 22, 1),
1097
+
PIN_FIELD_BASE(70, 70, 2, 0x00a0, 0x10, 21, 1),
1098
+
PIN_FIELD_BASE(71, 71, 2, 0x00a0, 0x10, 24, 1),
1099
+
PIN_FIELD_BASE(72, 72, 2, 0x00a0, 0x10, 23, 1),
1100
+
PIN_FIELD_BASE(73, 73, 2, 0x00a0, 0x10, 26, 1),
1101
+
PIN_FIELD_BASE(74, 74, 2, 0x00a0, 0x10, 25, 1),
1102
+
PIN_FIELD_BASE(75, 75, 3, 0x0080, 0x10, 7, 1),
1103
+
PIN_FIELD_BASE(76, 76, 2, 0x00a0, 0x10, 27, 1),
1104
+
PIN_FIELD_BASE(77, 77, 8, 0x0080, 0x10, 13, 1),
1105
+
PIN_FIELD_BASE(78, 78, 8, 0x0080, 0x10, 12, 1),
1106
+
PIN_FIELD_BASE(79, 79, 8, 0x0080, 0x10, 15, 1),
1107
+
PIN_FIELD_BASE(80, 80, 8, 0x0080, 0x10, 14, 1),
1108
+
PIN_FIELD_BASE(81, 81, 2, 0x00a0, 0x10, 29, 1),
1109
+
PIN_FIELD_BASE(82, 82, 2, 0x00a0, 0x10, 28, 1),
1110
+
PIN_FIELD_BASE(83, 83, 2, 0x00a0, 0x10, 30, 1),
1111
+
PIN_FIELD_BASE(84, 84, 7, 0x0080, 0x10, 22, 1),
1112
+
PIN_FIELD_BASE(85, 85, 7, 0x0080, 0x10, 23, 1),
1113
+
PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 24, 1),
1114
+
PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 25, 1),
1115
+
PIN_FIELD_BASE(88, 88, 5, 0x0090, 0x10, 11, 1),
1116
+
PIN_FIELD_BASE(89, 89, 5, 0x0090, 0x10, 10, 1),
1117
+
PIN_FIELD_BASE(90, 90, 5, 0x0090, 0x10, 13, 1),
1118
+
PIN_FIELD_BASE(91, 91, 5, 0x0090, 0x10, 12, 1),
1119
+
PIN_FIELD_BASE(92, 92, 5, 0x0090, 0x10, 7, 1),
1120
+
PIN_FIELD_BASE(93, 93, 5, 0x0090, 0x10, 8, 1),
1121
+
PIN_FIELD_BASE(94, 94, 5, 0x0090, 0x10, 14, 1),
1122
+
PIN_FIELD_BASE(95, 95, 5, 0x0090, 0x10, 6, 1),
1123
+
PIN_FIELD_BASE(96, 96, 5, 0x0090, 0x10, 9, 1),
1124
+
PIN_FIELD_BASE(97, 97, 5, 0x0090, 0x10, 0, 1),
1125
+
PIN_FIELD_BASE(98, 98, 5, 0x0090, 0x10, 5, 1),
1126
+
PIN_FIELD_BASE(99, 99, 5, 0x0090, 0x10, 3, 1),
1127
+
PIN_FIELD_BASE(100, 100, 5, 0x0090, 0x10, 4, 1),
1128
+
PIN_FIELD_BASE(101, 101, 5, 0x0090, 0x10, 1, 1),
1129
+
PIN_FIELD_BASE(102, 102, 5, 0x0090, 0x10, 2, 1),
1130
+
PIN_FIELD_BASE(103, 103, 7, 0x0080, 0x10, 15, 1),
1131
+
PIN_FIELD_BASE(104, 104, 7, 0x0080, 0x10, 12, 1),
1132
+
PIN_FIELD_BASE(105, 105, 7, 0x0080, 0x10, 14, 1),
1133
+
PIN_FIELD_BASE(106, 106, 7, 0x0080, 0x10, 13, 1),
1134
+
PIN_FIELD_BASE(107, 107, 7, 0x0080, 0x10, 19, 1),
1135
+
PIN_FIELD_BASE(108, 108, 7, 0x0080, 0x10, 16, 1),
1136
+
PIN_FIELD_BASE(109, 109, 7, 0x0080, 0x10, 18, 1),
1137
+
PIN_FIELD_BASE(110, 110, 7, 0x0080, 0x10, 17, 1),
1138
+
PIN_FIELD_BASE(111, 111, 7, 0x0080, 0x10, 4, 1),
1139
+
PIN_FIELD_BASE(112, 112, 8, 0x0080, 0x10, 0, 1),
1140
+
PIN_FIELD_BASE(113, 113, 8, 0x0080, 0x10, 1, 1),
1141
+
PIN_FIELD_BASE(114, 114, 8, 0x0080, 0x10, 2, 1),
1142
+
PIN_FIELD_BASE(115, 115, 2, 0x00a0, 0x10, 9, 1),
1143
+
PIN_FIELD_BASE(116, 116, 2, 0x00a0, 0x10, 12, 1),
1144
+
PIN_FIELD_BASE(117, 117, 2, 0x00a0, 0x10, 10, 1),
1145
+
PIN_FIELD_BASE(118, 118, 2, 0x00a0, 0x10, 11, 1),
1146
+
PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 26, 1),
1147
+
PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 25, 1),
1148
+
PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 24, 1),
1149
+
PIN_FIELD_BASE(122, 122, 1, 0x0080, 0x10, 23, 1),
1150
+
PIN_FIELD_BASE(123, 123, 1, 0x0080, 0x10, 19, 1),
1151
+
PIN_FIELD_BASE(124, 124, 1, 0x0080, 0x10, 18, 1),
1152
+
PIN_FIELD_BASE(125, 125, 1, 0x0080, 0x10, 17, 1),
1153
+
PIN_FIELD_BASE(126, 126, 1, 0x0080, 0x10, 16, 1),
1154
+
PIN_FIELD_BASE(127, 127, 1, 0x0080, 0x10, 22, 1),
1155
+
PIN_FIELD_BASE(128, 128, 1, 0x0080, 0x10, 15, 1),
1156
+
PIN_FIELD_BASE(129, 129, 1, 0x0080, 0x10, 20, 1),
1157
+
PIN_FIELD_BASE(130, 130, 1, 0x0080, 0x10, 27, 1),
1158
+
PIN_FIELD_BASE(131, 131, 1, 0x0080, 0x10, 13, 1),
1159
+
PIN_FIELD_BASE(132, 132, 1, 0x0080, 0x10, 14, 1),
1160
+
PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 28, 1),
1161
+
PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 21, 1),
1162
+
PIN_FIELD_BASE(135, 135, 1, 0x0080, 0x10, 11, 1),
1163
+
PIN_FIELD_BASE(136, 136, 1, 0x0080, 0x10, 12, 1),
1164
+
PIN_FIELD_BASE(137, 137, 2, 0x00a0, 0x10, 3, 1),
1165
+
PIN_FIELD_BASE(138, 138, 2, 0x00a0, 0x10, 4, 1),
1166
+
PIN_FIELD_BASE(139, 139, 1, 0x0080, 0x10, 3, 1),
1167
+
PIN_FIELD_BASE(140, 140, 1, 0x0080, 0x10, 4, 1),
1168
+
PIN_FIELD_BASE(141, 141, 1, 0x0080, 0x10, 0, 1),
1169
+
PIN_FIELD_BASE(142, 142, 1, 0x0080, 0x10, 1, 1),
1170
+
PIN_FIELD_BASE(143, 143, 1, 0x0080, 0x10, 2, 1),
1171
+
PIN_FIELD_BASE(144, 144, 1, 0x0080, 0x10, 5, 1),
1172
+
PIN_FIELD_BASE(145, 145, 1, 0x0080, 0x10, 6, 1),
1173
+
PIN_FIELD_BASE(146, 146, 1, 0x0080, 0x10, 7, 1),
1174
+
PIN_FIELD_BASE(147, 147, 1, 0x0080, 0x10, 8, 1),
1175
+
PIN_FIELD_BASE(148, 148, 1, 0x0080, 0x10, 9, 1),
1176
+
PIN_FIELD_BASE(149, 149, 1, 0x0080, 0x10, 10, 1),
1177
+
PIN_FIELD_BASE(150, 150, 3, 0x0080, 0x10, 8, 1),
1178
+
PIN_FIELD_BASE(151, 151, 1, 0x0080, 0x10, 29, 1),
1179
+
PIN_FIELD_BASE(152, 152, 3, 0x0080, 0x10, 9, 1),
1180
+
PIN_FIELD_BASE(153, 153, 3, 0x0080, 0x10, 10, 1),
1181
+
PIN_FIELD_BASE(154, 154, 3, 0x0080, 0x10, 11, 1),
1182
+
PIN_FIELD_BASE(155, 155, 3, 0x0080, 0x10, 12, 1),
1183
+
PIN_FIELD_BASE(180, 180, 5, 0x0090, 0x10, 15, 1),
1184
+
PIN_FIELD_BASE(181, 181, 5, 0x0090, 0x10, 16, 1),
1185
+
PIN_FIELD_BASE(182, 182, 9, 0x0070, 0x10, 3, 1),
1186
+
};
1187
+
1188
+
static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = {
1189
+
PIN_FIELD_BASE(0, 0, 7, 0x0000, 0x10, 15, 3),
1190
+
PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 9, 3),
1191
+
PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 12, 3),
1192
+
PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 15, 3),
1193
+
PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 18, 3),
1194
+
PIN_FIELD_BASE(5, 5, 8, 0x0000, 0x10, 21, 3),
1195
+
PIN_FIELD_BASE(6, 6, 7, 0x0000, 0x10, 18, 3),
1196
+
PIN_FIELD_BASE(7, 7, 7, 0x0000, 0x10, 21, 3),
1197
+
PIN_FIELD_BASE(8, 8, 7, 0x0000, 0x10, 24, 3),
1198
+
PIN_FIELD_BASE(9, 9, 7, 0x0000, 0x10, 27, 3),
1199
+
PIN_FIELD_BASE(10, 10, 7, 0x0010, 0x10, 0, 3),
1200
+
PIN_FIELD_BASE(11, 11, 7, 0x0010, 0x10, 3, 3),
1201
+
PIN_FIELD_BASE(12, 12, 2, 0x0000, 0x10, 15, 3),
1202
+
PIN_FIELD_BASE(13, 13, 2, 0x0000, 0x10, 18, 3),
1203
+
PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 0, 3),
1204
+
PIN_FIELD_BASE(15, 15, 3, 0x0000, 0x10, 3, 3),
1205
+
PIN_FIELD_BASE(16, 16, 2, 0x0000, 0x10, 21, 3),
1206
+
PIN_FIELD_BASE(17, 17, 2, 0x0000, 0x10, 24, 3),
1207
+
PIN_FIELD_BASE(18, 18, 7, 0x0000, 0x10, 0, 3),
1208
+
PIN_FIELD_BASE(19, 19, 7, 0x0000, 0x10, 6, 3),
1209
+
PIN_FIELD_BASE(20, 20, 7, 0x0000, 0x10, 3, 3),
1210
+
PIN_FIELD_BASE(21, 21, 7, 0x0000, 0x10, 9, 3),
1211
+
PIN_FIELD_BASE(22, 22, 9, 0x0000, 0x10, 0, 3),
1212
+
PIN_FIELD_BASE(23, 23, 9, 0x0000, 0x10, 3, 3),
1213
+
PIN_FIELD_BASE(24, 24, 9, 0x0000, 0x10, 6, 3),
1214
+
PIN_FIELD_BASE(25, 25, 4, 0x0000, 0x10, 6, 3),
1215
+
PIN_FIELD_BASE(26, 26, 4, 0x0000, 0x10, 3, 3),
1216
+
PIN_FIELD_BASE(27, 27, 2, 0x0000, 0x10, 3, 3),
1217
+
PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 6, 3),
1218
+
PIN_FIELD_BASE(29, 29, 4, 0x0000, 0x10, 0, 3),
1219
+
PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 0, 3),
1220
+
PIN_FIELD_BASE(31, 31, 3, 0x0010, 0x10, 27, 3),
1221
+
PIN_FIELD_BASE(32, 32, 1, 0x0030, 0x10, 0, 3),
1222
+
PIN_FIELD_BASE(33, 33, 3, 0x0020, 0x10, 3, 3),
1223
+
PIN_FIELD_BASE(34, 34, 3, 0x0020, 0x10, 0, 3),
1224
+
PIN_FIELD_BASE(35, 35, 3, 0x0020, 0x10, 9, 3),
1225
+
PIN_FIELD_BASE(36, 36, 3, 0x0020, 0x10, 6, 3),
1226
+
PIN_FIELD_BASE(37, 37, 3, 0x0020, 0x10, 15, 3),
1227
+
PIN_FIELD_BASE(38, 38, 3, 0x0020, 0x10, 12, 3),
1228
+
PIN_FIELD_BASE(39, 39, 3, 0x0000, 0x10, 15, 3),
1229
+
PIN_FIELD_BASE(40, 40, 3, 0x0000, 0x10, 6, 3),
1230
+
PIN_FIELD_BASE(41, 41, 3, 0x0000, 0x10, 9, 3),
1231
+
PIN_FIELD_BASE(42, 42, 3, 0x0000, 0x10, 12, 3),
1232
+
PIN_FIELD_BASE(43, 43, 3, 0x0000, 0x10, 18, 3),
1233
+
PIN_FIELD_BASE(44, 44, 7, 0x0020, 0x10, 0, 3),
1234
+
PIN_FIELD_BASE(45, 45, 7, 0x0020, 0x10, 3, 3),
1235
+
PIN_FIELD_BASE(46, 46, 7, 0x0020, 0x10, 6, 3),
1236
+
PIN_FIELD_BASE(47, 47, 7, 0x0020, 0x10, 9, 3),
1237
+
PIN_FIELD_BASE(48, 48, 4, 0x0000, 0x10, 15, 3),
1238
+
PIN_FIELD_BASE(49, 49, 4, 0x0000, 0x10, 12, 3),
1239
+
PIN_FIELD_BASE(50, 50, 4, 0x0000, 0x10, 9, 3),
1240
+
PIN_FIELD_BASE(51, 51, 8, 0x0000, 0x10, 24, 3),
1241
+
PIN_FIELD_BASE(52, 52, 8, 0x0010, 0x10, 0, 3),
1242
+
PIN_FIELD_BASE(53, 53, 8, 0x0000, 0x10, 27, 3),
1243
+
PIN_FIELD_BASE(54, 54, 8, 0x0010, 0x10, 3, 3),
1244
+
PIN_FIELD_BASE(55, 55, 4, 0x0000, 0x10, 18, 3),
1245
+
PIN_FIELD_BASE(56, 56, 4, 0x0000, 0x10, 21, 3),
1246
+
PIN_FIELD_BASE(57, 57, 2, 0x0010, 0x10, 9, 3),
1247
+
PIN_FIELD_BASE(58, 58, 2, 0x0010, 0x10, 21, 3),
1248
+
PIN_FIELD_BASE(59, 59, 2, 0x0010, 0x10, 12, 3),
1249
+
PIN_FIELD_BASE(60, 60, 2, 0x0010, 0x10, 24, 3),
1250
+
PIN_FIELD_BASE(61, 61, 2, 0x0010, 0x10, 15, 3),
1251
+
PIN_FIELD_BASE(62, 62, 2, 0x0010, 0x10, 27, 3),
1252
+
PIN_FIELD_BASE(63, 63, 2, 0x0010, 0x10, 18, 3),
1253
+
PIN_FIELD_BASE(64, 64, 2, 0x0020, 0x10, 0, 3),
1254
+
PIN_FIELD_BASE(65, 65, 9, 0x0010, 0x10, 0, 3),
1255
+
PIN_FIELD_BASE(66, 66, 9, 0x0010, 0x10, 6, 3),
1256
+
PIN_FIELD_BASE(67, 67, 9, 0x0010, 0x10, 3, 3),
1257
+
PIN_FIELD_BASE(68, 68, 9, 0x0010, 0x10, 9, 3),
1258
+
PIN_FIELD_BASE(69, 69, 2, 0x0020, 0x10, 6, 3),
1259
+
PIN_FIELD_BASE(70, 70, 2, 0x0020, 0x10, 3, 3),
1260
+
PIN_FIELD_BASE(71, 71, 2, 0x0020, 0x10, 12, 3),
1261
+
PIN_FIELD_BASE(72, 72, 2, 0x0020, 0x10, 9, 3),
1262
+
PIN_FIELD_BASE(73, 73, 2, 0x0020, 0x10, 18, 3),
1263
+
PIN_FIELD_BASE(74, 74, 2, 0x0020, 0x10, 15, 3),
1264
+
PIN_FIELD_BASE(75, 75, 3, 0x0010, 0x10, 9, 3),
1265
+
PIN_FIELD_BASE(76, 76, 2, 0x0020, 0x10, 21, 3),
1266
+
PIN_FIELD_BASE(77, 77, 8, 0x0010, 0x10, 9, 3),
1267
+
PIN_FIELD_BASE(78, 78, 8, 0x0010, 0x10, 6, 3),
1268
+
PIN_FIELD_BASE(79, 79, 8, 0x0010, 0x10, 15, 3),
1269
+
PIN_FIELD_BASE(80, 80, 8, 0x0010, 0x10, 12, 3),
1270
+
PIN_FIELD_BASE(81, 81, 2, 0x0020, 0x10, 27, 3),
1271
+
PIN_FIELD_BASE(82, 82, 2, 0x0020, 0x10, 24, 3),
1272
+
PIN_FIELD_BASE(83, 83, 2, 0x0030, 0x10, 0, 3),
1273
+
PIN_FIELD_BASE(84, 84, 7, 0x0020, 0x10, 12, 3),
1274
+
PIN_FIELD_BASE(85, 85, 7, 0x0020, 0x10, 15, 3),
1275
+
PIN_FIELD_BASE(86, 86, 7, 0x0020, 0x10, 18, 3),
1276
+
PIN_FIELD_BASE(87, 87, 7, 0x0020, 0x10, 21, 3),
1277
+
PIN_FIELD_BASE(88, 88, 5, 0x0020, 0x10, 0, 3),
1278
+
PIN_FIELD_BASE(89, 89, 5, 0x0010, 0x10, 27, 3),
1279
+
PIN_FIELD_BASE(90, 90, 5, 0x0020, 0x10, 6, 3),
1280
+
PIN_FIELD_BASE(91, 91, 5, 0x0020, 0x10, 3, 3),
1281
+
PIN_FIELD_BASE(92, 92, 5, 0x0010, 0x10, 18, 3),
1282
+
PIN_FIELD_BASE(93, 93, 5, 0x0010, 0x10, 21, 3),
1283
+
PIN_FIELD_BASE(94, 94, 5, 0x0020, 0x10, 9, 3),
1284
+
PIN_FIELD_BASE(95, 95, 5, 0x0010, 0x10, 15, 3),
1285
+
PIN_FIELD_BASE(96, 96, 5, 0x0010, 0x10, 24, 3),
1286
+
PIN_FIELD_BASE(97, 97, 5, 0x0000, 0x10, 0, 3),
1287
+
PIN_FIELD_BASE(98, 98, 5, 0x0000, 0x10, 15, 3),
1288
+
PIN_FIELD_BASE(99, 99, 5, 0x0000, 0x10, 9, 3),
1289
+
PIN_FIELD_BASE(100, 100, 5, 0x0000, 0x10, 12, 3),
1290
+
PIN_FIELD_BASE(101, 101, 5, 0x0000, 0x10, 3, 3),
1291
+
PIN_FIELD_BASE(102, 102, 5, 0x0000, 0x10, 6, 3),
1292
+
PIN_FIELD_BASE(103, 103, 7, 0x0010, 0x10, 15, 3),
1293
+
PIN_FIELD_BASE(104, 104, 7, 0x0010, 0x10, 6, 3),
1294
+
PIN_FIELD_BASE(105, 105, 7, 0x0010, 0x10, 12, 3),
1295
+
PIN_FIELD_BASE(106, 106, 7, 0x0010, 0x10, 9, 3),
1296
+
PIN_FIELD_BASE(107, 107, 7, 0x0010, 0x10, 27, 3),
1297
+
PIN_FIELD_BASE(108, 108, 7, 0x0010, 0x10, 18, 3),
1298
+
PIN_FIELD_BASE(109, 109, 7, 0x0010, 0x10, 24, 3),
1299
+
PIN_FIELD_BASE(110, 110, 7, 0x0010, 0x10, 21, 3),
1300
+
PIN_FIELD_BASE(111, 111, 7, 0x0000, 0x10, 12, 3),
1301
+
PIN_FIELD_BASE(112, 112, 8, 0x0000, 0x10, 0, 3),
1302
+
PIN_FIELD_BASE(113, 113, 8, 0x0000, 0x10, 3, 3),
1303
+
PIN_FIELD_BASE(114, 114, 8, 0x0000, 0x10, 6, 3),
1304
+
PIN_FIELD_BASE(115, 115, 2, 0x0000, 0x10, 27, 3),
1305
+
PIN_FIELD_BASE(116, 116, 2, 0x0010, 0x10, 6, 3),
1306
+
PIN_FIELD_BASE(117, 117, 2, 0x0010, 0x10, 0, 3),
1307
+
PIN_FIELD_BASE(118, 118, 2, 0x0010, 0x10, 3, 3),
1308
+
PIN_FIELD_BASE(119, 119, 1, 0x0020, 0x10, 18, 3),
1309
+
PIN_FIELD_BASE(120, 120, 1, 0x0020, 0x10, 15, 3),
1310
+
PIN_FIELD_BASE(121, 121, 1, 0x0020, 0x10, 12, 3),
1311
+
PIN_FIELD_BASE(122, 122, 1, 0x0020, 0x10, 9, 3),
1312
+
PIN_FIELD_BASE(123, 123, 1, 0x0010, 0x10, 27, 3),
1313
+
PIN_FIELD_BASE(124, 124, 1, 0x0010, 0x10, 24, 3),
1314
+
PIN_FIELD_BASE(125, 125, 1, 0x0010, 0x10, 21, 3),
1315
+
PIN_FIELD_BASE(126, 126, 1, 0x0010, 0x10, 18, 3),
1316
+
PIN_FIELD_BASE(127, 127, 1, 0x0020, 0x10, 6, 3),
1317
+
PIN_FIELD_BASE(128, 128, 1, 0x0010, 0x10, 15, 3),
1318
+
PIN_FIELD_BASE(129, 129, 1, 0x0020, 0x10, 0, 3),
1319
+
PIN_FIELD_BASE(130, 130, 1, 0x0020, 0x10, 21, 3),
1320
+
PIN_FIELD_BASE(131, 131, 1, 0x0010, 0x10, 9, 3),
1321
+
PIN_FIELD_BASE(132, 132, 1, 0x0010, 0x10, 12, 3),
1322
+
PIN_FIELD_BASE(133, 133, 1, 0x0020, 0x10, 24, 3),
1323
+
PIN_FIELD_BASE(134, 134, 1, 0x0020, 0x10, 3, 3),
1324
+
PIN_FIELD_BASE(135, 135, 1, 0x0010, 0x10, 3, 3),
1325
+
PIN_FIELD_BASE(136, 136, 1, 0x0010, 0x10, 6, 3),
1326
+
PIN_FIELD_BASE(137, 137, 2, 0x0000, 0x10, 9, 3),
1327
+
PIN_FIELD_BASE(138, 138, 2, 0x0000, 0x10, 12, 3),
1328
+
PIN_FIELD_BASE(139, 139, 1, 0x0000, 0x10, 9, 3),
1329
+
PIN_FIELD_BASE(140, 140, 1, 0x0000, 0x10, 12, 3),
1330
+
PIN_FIELD_BASE(141, 141, 1, 0x0000, 0x10, 0, 3),
1331
+
PIN_FIELD_BASE(142, 142, 1, 0x0000, 0x10, 3, 3),
1332
+
PIN_FIELD_BASE(143, 143, 1, 0x0000, 0x10, 6, 3),
1333
+
PIN_FIELD_BASE(144, 144, 1, 0x0000, 0x10, 15, 3),
1334
+
PIN_FIELD_BASE(145, 145, 1, 0x0000, 0x10, 18, 3),
1335
+
PIN_FIELD_BASE(146, 146, 1, 0x0000, 0x10, 21, 3),
1336
+
PIN_FIELD_BASE(147, 147, 1, 0x0000, 0x10, 24, 3),
1337
+
PIN_FIELD_BASE(148, 148, 1, 0x0000, 0x10, 27, 3),
1338
+
PIN_FIELD_BASE(149, 149, 1, 0x0010, 0x10, 0, 3),
1339
+
PIN_FIELD_BASE(150, 150, 3, 0x0010, 0x10, 12, 3),
1340
+
PIN_FIELD_BASE(151, 151, 1, 0x0020, 0x10, 27, 3),
1341
+
PIN_FIELD_BASE(152, 152, 3, 0x0010, 0x10, 15, 3),
1342
+
PIN_FIELD_BASE(153, 153, 3, 0x0010, 0x10, 18, 3),
1343
+
PIN_FIELD_BASE(154, 154, 3, 0x0010, 0x10, 21, 3),
1344
+
PIN_FIELD_BASE(155, 155, 3, 0x0010, 0x10, 24, 3),
1345
+
PIN_FIELD_BASE(156, 156, 5, 0x0010, 0x10, 6, 3),
1346
+
PIN_FIELD_BASE(157, 157, 5, 0x0010, 0x10, 3, 3),
1347
+
PIN_FIELD_BASE(158, 158, 5, 0x0010, 0x10, 0, 3),
1348
+
PIN_FIELD_BASE(159, 159, 6, 0x0000, 0x10, 6, 3),
1349
+
PIN_FIELD_BASE(160, 160, 5, 0x0010, 0x10, 12, 3),
1350
+
PIN_FIELD_BASE(161, 161, 5, 0x0000, 0x10, 21, 3),
1351
+
PIN_FIELD_BASE(162, 162, 5, 0x0000, 0x10, 18, 3),
1352
+
PIN_FIELD_BASE(163, 163, 6, 0x0000, 0x10, 3, 3),
1353
+
PIN_FIELD_BASE(164, 164, 5, 0x0000, 0x10, 27, 3),
1354
+
PIN_FIELD_BASE(165, 165, 5, 0x0000, 0x10, 24, 3),
1355
+
PIN_FIELD_BASE(166, 166, 6, 0x0000, 0x10, 0, 3),
1356
+
PIN_FIELD_BASE(167, 167, 5, 0x0010, 0x10, 9, 3),
1357
+
PIN_FIELD_BASE(168, 168, 3, 0x0000, 0x10, 24, 3),
1358
+
PIN_FIELD_BASE(169, 169, 3, 0x0000, 0x10, 21, 3),
1359
+
PIN_FIELD_BASE(170, 170, 3, 0x0000, 0x10, 27, 3),
1360
+
PIN_FIELD_BASE(171, 171, 3, 0x0010, 0x10, 0, 3),
1361
+
PIN_FIELD_BASE(172, 172, 3, 0x0010, 0x10, 3, 3),
1362
+
PIN_FIELD_BASE(173, 173, 3, 0x0010, 0x10, 6, 3),
1363
+
PIN_FIELD_BASE(174, 174, 9, 0x0000, 0x10, 15, 3),
1364
+
PIN_FIELD_BASE(175, 175, 9, 0x0000, 0x10, 12, 3),
1365
+
PIN_FIELD_BASE(176, 176, 9, 0x0000, 0x10, 18, 3),
1366
+
PIN_FIELD_BASE(177, 177, 9, 0x0000, 0x10, 21, 3),
1367
+
PIN_FIELD_BASE(178, 178, 9, 0x0000, 0x10, 24, 3),
1368
+
PIN_FIELD_BASE(179, 179, 9, 0x0000, 0x10, 27, 3),
1369
+
PIN_FIELD_BASE(180, 180, 5, 0x0020, 0x10, 12, 3),
1370
+
PIN_FIELD_BASE(181, 181, 5, 0x0020, 0x10, 15, 3),
1371
+
PIN_FIELD_BASE(182, 182, 9, 0x0000, 0x10, 9, 3),
1372
+
};
1373
+
1374
+
static const struct mtk_pin_field_calc mt8189_pin_drv_adv_range[] = {
1375
+
PIN_FIELD_BASE(51, 51, 8, 0x0020, 0x10, 0, 3),
1376
+
PIN_FIELD_BASE(52, 52, 8, 0x0020, 0x10, 6, 3),
1377
+
PIN_FIELD_BASE(53, 53, 8, 0x0020, 0x10, 3, 3),
1378
+
PIN_FIELD_BASE(54, 54, 8, 0x0020, 0x10, 9, 3),
1379
+
PIN_FIELD_BASE(55, 55, 4, 0x0020, 0x10, 0, 3),
1380
+
PIN_FIELD_BASE(56, 56, 4, 0x0020, 0x10, 3, 3),
1381
+
PIN_FIELD_BASE(57, 57, 2, 0x0040, 0x10, 0, 3),
1382
+
PIN_FIELD_BASE(58, 58, 2, 0x0040, 0x10, 12, 3),
1383
+
PIN_FIELD_BASE(59, 59, 2, 0x0040, 0x10, 3, 3),
1384
+
PIN_FIELD_BASE(60, 60, 2, 0x0040, 0x10, 15, 3),
1385
+
PIN_FIELD_BASE(61, 61, 2, 0x0040, 0x10, 6, 3),
1386
+
PIN_FIELD_BASE(62, 62, 2, 0x0040, 0x10, 18, 3),
1387
+
PIN_FIELD_BASE(63, 63, 2, 0x0040, 0x10, 9, 3),
1388
+
PIN_FIELD_BASE(64, 64, 2, 0x0040, 0x10, 21, 3),
1389
+
PIN_FIELD_BASE(65, 65, 9, 0x0020, 0x10, 0, 3),
1390
+
PIN_FIELD_BASE(66, 66, 9, 0x0020, 0x10, 6, 3),
1391
+
PIN_FIELD_BASE(67, 67, 9, 0x0020, 0x10, 3, 3),
1392
+
PIN_FIELD_BASE(68, 68, 9, 0x0020, 0x10, 9, 3),
1393
+
PIN_FIELD_BASE(180, 180, 5, 0x0030, 0x10, 0, 3),
1394
+
PIN_FIELD_BASE(181, 181, 5, 0x0030, 0x10, 3, 3),
1395
+
};
1396
+
1397
+
static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = {
1398
+
PIN_FIELD_BASE(51, 51, 8, 0x00b0, 0x10, 0, 3),
1399
+
PIN_FIELD_BASE(52, 52, 8, 0x00b0, 0x10, 6, 3),
1400
+
PIN_FIELD_BASE(53, 53, 8, 0x00b0, 0x10, 3, 3),
1401
+
PIN_FIELD_BASE(54, 54, 8, 0x00b0, 0x10, 9, 3),
1402
+
PIN_FIELD_BASE(55, 55, 4, 0x00b0, 0x10, 0, 3),
1403
+
PIN_FIELD_BASE(56, 56, 4, 0x00b0, 0x10, 3, 3),
1404
+
PIN_FIELD_BASE(57, 57, 2, 0x00d0, 0x10, 0, 3),
1405
+
PIN_FIELD_BASE(58, 58, 2, 0x00d0, 0x10, 12, 3),
1406
+
PIN_FIELD_BASE(59, 59, 2, 0x00d0, 0x10, 3, 3),
1407
+
PIN_FIELD_BASE(60, 60, 2, 0x00d0, 0x10, 15, 3),
1408
+
PIN_FIELD_BASE(61, 61, 2, 0x00d0, 0x10, 6, 3),
1409
+
PIN_FIELD_BASE(62, 62, 2, 0x00d0, 0x10, 18, 3),
1410
+
PIN_FIELD_BASE(63, 63, 2, 0x00d0, 0x10, 9, 3),
1411
+
PIN_FIELD_BASE(64, 64, 2, 0x00d0, 0x10, 21, 3),
1412
+
PIN_FIELD_BASE(65, 65, 9, 0x00e0, 0x10, 0, 3),
1413
+
PIN_FIELD_BASE(66, 66, 9, 0x00e0, 0x10, 6, 3),
1414
+
PIN_FIELD_BASE(67, 67, 9, 0x00e0, 0x10, 3, 3),
1415
+
PIN_FIELD_BASE(68, 68, 9, 0x00e0, 0x10, 9, 3),
1416
+
PIN_FIELD_BASE(180, 180, 5, 0x0110, 0x10, 0, 3),
1417
+
PIN_FIELD_BASE(181, 181, 5, 0x0110, 0x10, 3, 3),
1418
+
};
1419
+
1420
+
static const struct mtk_pin_rsel mt8189_pin_rsel_val_range[] = {
1421
+
PIN_RSEL(51, 68, 0x0, 75000, 75000),
1422
+
PIN_RSEL(51, 68, 0x1, 10000, 5000),
1423
+
PIN_RSEL(51, 68, 0x2, 5000, 75000),
1424
+
PIN_RSEL(51, 68, 0x3, 4000, 5000),
1425
+
PIN_RSEL(51, 68, 0x4, 3000, 75000),
1426
+
PIN_RSEL(51, 68, 0x5, 2000, 5000),
1427
+
PIN_RSEL(51, 68, 0x6, 1500, 75000),
1428
+
PIN_RSEL(51, 68, 0x7, 1000, 5000),
1429
+
PIN_RSEL(180, 181, 0x0, 75000, 75000),
1430
+
PIN_RSEL(180, 181, 0x1, 10000, 5000),
1431
+
PIN_RSEL(180, 181, 0x2, 5000, 75000),
1432
+
PIN_RSEL(180, 181, 0x3, 4000, 5000),
1433
+
PIN_RSEL(180, 181, 0x4, 3000, 75000),
1434
+
PIN_RSEL(180, 181, 0x5, 2000, 5000),
1435
+
PIN_RSEL(180, 181, 0x6, 1500, 75000),
1436
+
PIN_RSEL(180, 181, 0x7, 1000, 5000),
1437
+
};
1438
+
1439
+
static const unsigned int mt8189_pull_type[] = {
1440
+
MTK_PULL_PU_PD_TYPE, /*0*/
1441
+
MTK_PULL_PU_PD_TYPE, /*1*/
1442
+
MTK_PULL_PU_PD_TYPE, /*2*/
1443
+
MTK_PULL_PU_PD_TYPE, /*3*/
1444
+
MTK_PULL_PU_PD_TYPE, /*4*/
1445
+
MTK_PULL_PU_PD_TYPE, /*5*/
1446
+
MTK_PULL_PU_PD_TYPE, /*6*/
1447
+
MTK_PULL_PU_PD_TYPE, /*7*/
1448
+
MTK_PULL_PU_PD_TYPE, /*8*/
1449
+
MTK_PULL_PU_PD_TYPE, /*9*/
1450
+
MTK_PULL_PU_PD_TYPE, /*10*/
1451
+
MTK_PULL_PU_PD_TYPE, /*11*/
1452
+
MTK_PULL_PU_PD_TYPE, /*12*/
1453
+
MTK_PULL_PU_PD_TYPE, /*13*/
1454
+
MTK_PULL_PU_PD_TYPE, /*14*/
1455
+
MTK_PULL_PU_PD_TYPE, /*15*/
1456
+
MTK_PULL_PU_PD_TYPE, /*16*/
1457
+
MTK_PULL_PU_PD_TYPE, /*17*/
1458
+
MTK_PULL_PU_PD_TYPE, /*18*/
1459
+
MTK_PULL_PU_PD_TYPE, /*19*/
1460
+
MTK_PULL_PU_PD_TYPE, /*20*/
1461
+
MTK_PULL_PU_PD_TYPE, /*21*/
1462
+
MTK_PULL_PU_PD_TYPE, /*22*/
1463
+
MTK_PULL_PU_PD_TYPE, /*23*/
1464
+
MTK_PULL_PU_PD_TYPE, /*24*/
1465
+
MTK_PULL_PU_PD_TYPE, /*25*/
1466
+
MTK_PULL_PU_PD_TYPE, /*26*/
1467
+
MTK_PULL_PU_PD_TYPE, /*27*/
1468
+
MTK_PULL_PU_PD_TYPE, /*28*/
1469
+
MTK_PULL_PU_PD_TYPE, /*29*/
1470
+
MTK_PULL_PU_PD_TYPE, /*30*/
1471
+
MTK_PULL_PU_PD_TYPE, /*31*/
1472
+
MTK_PULL_PU_PD_TYPE, /*32*/
1473
+
MTK_PULL_PU_PD_TYPE, /*33*/
1474
+
MTK_PULL_PU_PD_TYPE, /*34*/
1475
+
MTK_PULL_PU_PD_TYPE, /*35*/
1476
+
MTK_PULL_PU_PD_TYPE, /*36*/
1477
+
MTK_PULL_PU_PD_TYPE, /*37*/
1478
+
MTK_PULL_PU_PD_TYPE, /*38*/
1479
+
MTK_PULL_PU_PD_TYPE, /*39*/
1480
+
MTK_PULL_PU_PD_TYPE, /*40*/
1481
+
MTK_PULL_PU_PD_TYPE, /*41*/
1482
+
MTK_PULL_PU_PD_TYPE, /*42*/
1483
+
MTK_PULL_PU_PD_TYPE, /*43*/
1484
+
MTK_PULL_PUPD_R1R0_TYPE, /*44*/
1485
+
MTK_PULL_PUPD_R1R0_TYPE, /*45*/
1486
+
MTK_PULL_PUPD_R1R0_TYPE, /*46*/
1487
+
MTK_PULL_PUPD_R1R0_TYPE, /*47*/
1488
+
MTK_PULL_PU_PD_TYPE, /*48*/
1489
+
MTK_PULL_PU_PD_TYPE, /*49*/
1490
+
MTK_PULL_PU_PD_TYPE, /*50*/
1491
+
MTK_PULL_PU_PD_RSEL_TYPE, /*51*/
1492
+
MTK_PULL_PU_PD_RSEL_TYPE, /*52*/
1493
+
MTK_PULL_PU_PD_RSEL_TYPE, /*53*/
1494
+
MTK_PULL_PU_PD_RSEL_TYPE, /*54*/
1495
+
MTK_PULL_PU_PD_RSEL_TYPE, /*55*/
1496
+
MTK_PULL_PU_PD_RSEL_TYPE, /*56*/
1497
+
MTK_PULL_PU_PD_RSEL_TYPE, /*57*/
1498
+
MTK_PULL_PU_PD_RSEL_TYPE, /*58*/
1499
+
MTK_PULL_PU_PD_RSEL_TYPE, /*59*/
1500
+
MTK_PULL_PU_PD_RSEL_TYPE, /*60*/
1501
+
MTK_PULL_PU_PD_RSEL_TYPE, /*61*/
1502
+
MTK_PULL_PU_PD_RSEL_TYPE, /*62*/
1503
+
MTK_PULL_PU_PD_RSEL_TYPE, /*63*/
1504
+
MTK_PULL_PU_PD_RSEL_TYPE, /*64*/
1505
+
MTK_PULL_PU_PD_RSEL_TYPE, /*65*/
1506
+
MTK_PULL_PU_PD_RSEL_TYPE, /*66*/
1507
+
MTK_PULL_PU_PD_RSEL_TYPE, /*67*/
1508
+
MTK_PULL_PU_PD_RSEL_TYPE, /*68*/
1509
+
MTK_PULL_PU_PD_TYPE, /*69*/
1510
+
MTK_PULL_PU_PD_TYPE, /*70*/
1511
+
MTK_PULL_PU_PD_TYPE, /*71*/
1512
+
MTK_PULL_PU_PD_TYPE, /*72*/
1513
+
MTK_PULL_PU_PD_TYPE, /*73*/
1514
+
MTK_PULL_PU_PD_TYPE, /*74*/
1515
+
MTK_PULL_PU_PD_TYPE, /*75*/
1516
+
MTK_PULL_PU_PD_TYPE, /*76*/
1517
+
MTK_PULL_PU_PD_TYPE, /*77*/
1518
+
MTK_PULL_PU_PD_TYPE, /*78*/
1519
+
MTK_PULL_PU_PD_TYPE, /*79*/
1520
+
MTK_PULL_PU_PD_TYPE, /*80*/
1521
+
MTK_PULL_PU_PD_TYPE, /*81*/
1522
+
MTK_PULL_PU_PD_TYPE, /*82*/
1523
+
MTK_PULL_PU_PD_TYPE, /*83*/
1524
+
MTK_PULL_PU_PD_TYPE, /*84*/
1525
+
MTK_PULL_PU_PD_TYPE, /*85*/
1526
+
MTK_PULL_PU_PD_TYPE, /*86*/
1527
+
MTK_PULL_PU_PD_TYPE, /*87*/
1528
+
MTK_PULL_PU_PD_TYPE, /*88*/
1529
+
MTK_PULL_PU_PD_TYPE, /*89*/
1530
+
MTK_PULL_PU_PD_TYPE, /*90*/
1531
+
MTK_PULL_PU_PD_TYPE, /*91*/
1532
+
MTK_PULL_PU_PD_TYPE, /*92*/
1533
+
MTK_PULL_PU_PD_TYPE, /*93*/
1534
+
MTK_PULL_PU_PD_TYPE, /*94*/
1535
+
MTK_PULL_PU_PD_TYPE, /*95*/
1536
+
MTK_PULL_PU_PD_TYPE, /*96*/
1537
+
MTK_PULL_PU_PD_TYPE, /*97*/
1538
+
MTK_PULL_PU_PD_TYPE, /*98*/
1539
+
MTK_PULL_PU_PD_TYPE, /*99*/
1540
+
MTK_PULL_PU_PD_TYPE, /*100*/
1541
+
MTK_PULL_PU_PD_TYPE, /*101*/
1542
+
MTK_PULL_PU_PD_TYPE, /*102*/
1543
+
MTK_PULL_PU_PD_TYPE, /*103*/
1544
+
MTK_PULL_PU_PD_TYPE, /*104*/
1545
+
MTK_PULL_PU_PD_TYPE, /*105*/
1546
+
MTK_PULL_PU_PD_TYPE, /*106*/
1547
+
MTK_PULL_PU_PD_TYPE, /*107*/
1548
+
MTK_PULL_PU_PD_TYPE, /*108*/
1549
+
MTK_PULL_PU_PD_TYPE, /*109*/
1550
+
MTK_PULL_PU_PD_TYPE, /*110*/
1551
+
MTK_PULL_PU_PD_TYPE, /*111*/
1552
+
MTK_PULL_PU_PD_TYPE, /*112*/
1553
+
MTK_PULL_PU_PD_TYPE, /*113*/
1554
+
MTK_PULL_PU_PD_TYPE, /*114*/
1555
+
MTK_PULL_PU_PD_TYPE, /*115*/
1556
+
MTK_PULL_PU_PD_TYPE, /*116*/
1557
+
MTK_PULL_PU_PD_TYPE, /*117*/
1558
+
MTK_PULL_PU_PD_TYPE, /*118*/
1559
+
MTK_PULL_PU_PD_TYPE, /*119*/
1560
+
MTK_PULL_PU_PD_TYPE, /*120*/
1561
+
MTK_PULL_PU_PD_TYPE, /*121*/
1562
+
MTK_PULL_PU_PD_TYPE, /*122*/
1563
+
MTK_PULL_PU_PD_TYPE, /*123*/
1564
+
MTK_PULL_PU_PD_TYPE, /*124*/
1565
+
MTK_PULL_PU_PD_TYPE, /*125*/
1566
+
MTK_PULL_PU_PD_TYPE, /*126*/
1567
+
MTK_PULL_PU_PD_TYPE, /*127*/
1568
+
MTK_PULL_PU_PD_TYPE, /*128*/
1569
+
MTK_PULL_PU_PD_TYPE, /*129*/
1570
+
MTK_PULL_PU_PD_TYPE, /*130*/
1571
+
MTK_PULL_PU_PD_TYPE, /*131*/
1572
+
MTK_PULL_PU_PD_TYPE, /*132*/
1573
+
MTK_PULL_PU_PD_TYPE, /*133*/
1574
+
MTK_PULL_PU_PD_TYPE, /*134*/
1575
+
MTK_PULL_PU_PD_TYPE, /*135*/
1576
+
MTK_PULL_PU_PD_TYPE, /*136*/
1577
+
MTK_PULL_PU_PD_TYPE, /*137*/
1578
+
MTK_PULL_PU_PD_TYPE, /*138*/
1579
+
MTK_PULL_PU_PD_TYPE, /*139*/
1580
+
MTK_PULL_PU_PD_TYPE, /*140*/
1581
+
MTK_PULL_PU_PD_TYPE, /*141*/
1582
+
MTK_PULL_PU_PD_TYPE, /*142*/
1583
+
MTK_PULL_PU_PD_TYPE, /*143*/
1584
+
MTK_PULL_PU_PD_TYPE, /*144*/
1585
+
MTK_PULL_PU_PD_TYPE, /*145*/
1586
+
MTK_PULL_PU_PD_TYPE, /*146*/
1587
+
MTK_PULL_PU_PD_TYPE, /*147*/
1588
+
MTK_PULL_PU_PD_TYPE, /*148*/
1589
+
MTK_PULL_PU_PD_TYPE, /*149*/
1590
+
MTK_PULL_PU_PD_TYPE, /*150*/
1591
+
MTK_PULL_PU_PD_TYPE, /*151*/
1592
+
MTK_PULL_PU_PD_TYPE, /*152*/
1593
+
MTK_PULL_PU_PD_TYPE, /*153*/
1594
+
MTK_PULL_PU_PD_TYPE, /*154*/
1595
+
MTK_PULL_PU_PD_TYPE, /*155*/
1596
+
MTK_PULL_PUPD_R1R0_TYPE, /*156*/
1597
+
MTK_PULL_PUPD_R1R0_TYPE, /*157*/
1598
+
MTK_PULL_PUPD_R1R0_TYPE, /*158*/
1599
+
MTK_PULL_PUPD_R1R0_TYPE, /*159*/
1600
+
MTK_PULL_PUPD_R1R0_TYPE, /*160*/
1601
+
MTK_PULL_PUPD_R1R0_TYPE, /*161*/
1602
+
MTK_PULL_PUPD_R1R0_TYPE, /*162*/
1603
+
MTK_PULL_PUPD_R1R0_TYPE, /*163*/
1604
+
MTK_PULL_PUPD_R1R0_TYPE, /*164*/
1605
+
MTK_PULL_PUPD_R1R0_TYPE, /*165*/
1606
+
MTK_PULL_PUPD_R1R0_TYPE, /*166*/
1607
+
MTK_PULL_PUPD_R1R0_TYPE, /*167*/
1608
+
MTK_PULL_PUPD_R1R0_TYPE, /*168*/
1609
+
MTK_PULL_PUPD_R1R0_TYPE, /*169*/
1610
+
MTK_PULL_PUPD_R1R0_TYPE, /*170*/
1611
+
MTK_PULL_PUPD_R1R0_TYPE, /*171*/
1612
+
MTK_PULL_PUPD_R1R0_TYPE, /*172*/
1613
+
MTK_PULL_PUPD_R1R0_TYPE, /*173*/
1614
+
MTK_PULL_PUPD_R1R0_TYPE, /*174*/
1615
+
MTK_PULL_PUPD_R1R0_TYPE, /*175*/
1616
+
MTK_PULL_PUPD_R1R0_TYPE, /*176*/
1617
+
MTK_PULL_PUPD_R1R0_TYPE, /*177*/
1618
+
MTK_PULL_PUPD_R1R0_TYPE, /*178*/
1619
+
MTK_PULL_PUPD_R1R0_TYPE, /*179*/
1620
+
MTK_PULL_PU_PD_RSEL_TYPE, /*180*/
1621
+
MTK_PULL_PU_PD_RSEL_TYPE, /*181*/
1622
+
MTK_PULL_PU_PD_TYPE, /*182*/
1623
+
};
1624
+
1625
+
static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
1626
+
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range),
1627
+
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range),
1628
+
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8189_pin_di_range),
1629
+
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8189_pin_do_range),
1630
+
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8189_pin_smt_range),
1631
+
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8189_pin_ies_range),
1632
+
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt8189_pin_tdsel_range),
1633
+
[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt8189_pin_rdsel_range),
1634
+
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8189_pin_pupd_range),
1635
+
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8189_pin_r0_range),
1636
+
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8189_pin_r1_range),
1637
+
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range),
1638
+
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range),
1639
+
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range),
1640
+
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8189_pin_drv_adv_range),
1641
+
[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range),
1642
+
};
1643
+
1644
+
static const char * const mt8189_pinctrl_register_base_names[] = {
1645
+
"gpio_base", "iocfg_bm0_base", "iocfg_bm1_base", "iocfg_bm2_base", "iocfg_lm_base",
1646
+
"iocfg_lt0_base", "iocfg_lt1_base", "iocfg_rb0_base", "iocfg_rb1_base",
1647
+
"iocfg_rt_base"
1648
+
};
1649
+
1650
+
static const struct mtk_eint_hw mt8189_eint_hw = {
1651
+
.port_mask = 0xf,
1652
+
.ports = 3,
1653
+
.ap_num = 210,
1654
+
.db_cnt = 32,
1655
+
.db_time = debounce_time_mt6765,
1656
+
};
1657
+
1658
+
static const struct mtk_pin_soc mt8189_data = {
1659
+
.reg_cal = mt8189_reg_cals,
1660
+
.pins = mtk_pins_mt8189,
1661
+
.npins = ARRAY_SIZE(mtk_pins_mt8189),
1662
+
.ngrps = ARRAY_SIZE(mtk_pins_mt8189),
1663
+
.eint_pin = eint_pins_mt8189,
1664
+
.eint_hw = &mt8189_eint_hw,
1665
+
.nfuncs = 8,
1666
+
.gpio_m = 0,
1667
+
.base_names = mt8189_pinctrl_register_base_names,
1668
+
.nbase_names = ARRAY_SIZE(mt8189_pinctrl_register_base_names),
1669
+
.bias_set_combo = mtk_pinconf_bias_set_combo,
1670
+
.bias_get_combo = mtk_pinconf_bias_get_combo,
1671
+
.pull_type = mt8189_pull_type,
1672
+
.pin_rsel = mt8189_pin_rsel_val_range,
1673
+
.npin_rsel = ARRAY_SIZE(mt8189_pin_rsel_val_range),
1674
+
.drive_set = mtk_pinconf_drive_set_rev1,
1675
+
.drive_get = mtk_pinconf_drive_get_rev1,
1676
+
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
1677
+
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
1678
+
};
1679
+
1680
+
static const struct of_device_id mt8189_pinctrl_of_match[] = {
1681
+
{ .compatible = "mediatek,mt8189-pinctrl", .data = &mt8189_data },
1682
+
{ /* sentinel */ }
1683
+
};
1684
+
1685
+
static struct platform_driver mt8189_pinctrl_driver = {
1686
+
.driver = {
1687
+
.name = "mt8189-pinctrl",
1688
+
.of_match_table = mt8189_pinctrl_of_match,
1689
+
.pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops),
1690
+
},
1691
+
.probe = mtk_paris_pinctrl_probe,
1692
+
};
1693
+
1694
+
static int __init mt8189_pinctrl_init(void)
1695
+
{
1696
+
return platform_driver_register(&mt8189_pinctrl_driver);
1697
+
}
1698
+
arch_initcall(mt8189_pinctrl_init);
1699
+
1700
+
MODULE_DESCRIPTION("MediaTek MT8189 Pinctrl Driver");
+2452
drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h
+2452
drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2025 MediaTek Inc.
4
+
* Author: Lei Xue <lei.xue@mediatek.com>
5
+
* Cathy Xu <ot_cathy.xu@mediatek.com>
6
+
*/
7
+
8
+
#ifndef __PINCTRL_MTK_MT8189_H
9
+
#define __PINCTRL_MTK_MT8189_H
10
+
11
+
#include "pinctrl-paris.h"
12
+
13
+
static const struct mtk_pin_desc mtk_pins_mt8189[] = {
14
+
MTK_PIN(
15
+
0, "GPIO0",
16
+
MTK_EINT_FUNCTION(0, 0),
17
+
DRV_GRP4,
18
+
MTK_FUNCTION(0, "GPIO0"),
19
+
MTK_FUNCTION(1, "TP_GPIO0_AO"),
20
+
MTK_FUNCTION(2, "SPIM3_A_CSB"),
21
+
MTK_FUNCTION(3, "I2SOUT0_MCK"),
22
+
MTK_FUNCTION(4, "SCP_SPI0_CS"),
23
+
MTK_FUNCTION(6, "CONN_BPI_BUS6"),
24
+
MTK_FUNCTION(7, "DBG_MON_A0")
25
+
),
26
+
27
+
MTK_PIN(
28
+
1, "GPIO1",
29
+
MTK_EINT_FUNCTION(0, 1),
30
+
DRV_GRP4,
31
+
MTK_FUNCTION(0, "GPIO1"),
32
+
MTK_FUNCTION(1, "TP_GPIO1_AO"),
33
+
MTK_FUNCTION(2, "SPIM3_A_CLK"),
34
+
MTK_FUNCTION(3, "I2SOUT0_BCK"),
35
+
MTK_FUNCTION(4, "SCP_SPI0_CK"),
36
+
MTK_FUNCTION(6, "CONN_BPI_BUS7"),
37
+
MTK_FUNCTION(7, "DBG_MON_A1")
38
+
),
39
+
40
+
MTK_PIN(
41
+
2, "GPIO2",
42
+
MTK_EINT_FUNCTION(0, 2),
43
+
DRV_GRP4,
44
+
MTK_FUNCTION(0, "GPIO2"),
45
+
MTK_FUNCTION(1, "TP_GPIO2_AO"),
46
+
MTK_FUNCTION(2, "SPIM3_A_MO"),
47
+
MTK_FUNCTION(3, "I2SOUT0_LRCK"),
48
+
MTK_FUNCTION(4, "SCP_SPI0_MO"),
49
+
MTK_FUNCTION(6, "CONN_BPI_BUS8"),
50
+
MTK_FUNCTION(7, "DBG_MON_A2")
51
+
),
52
+
53
+
MTK_PIN(
54
+
3, "GPIO3",
55
+
MTK_EINT_FUNCTION(0, 3),
56
+
DRV_GRP4,
57
+
MTK_FUNCTION(0, "GPIO3"),
58
+
MTK_FUNCTION(1, "TP_GPIO3_AO"),
59
+
MTK_FUNCTION(2, "SPIM3_A_MI"),
60
+
MTK_FUNCTION(3, "I2SOUT0_DO"),
61
+
MTK_FUNCTION(4, "SCP_SPI0_MI"),
62
+
MTK_FUNCTION(6, "CONN_BPI_BUS9"),
63
+
MTK_FUNCTION(7, "DBG_MON_A3")
64
+
),
65
+
66
+
MTK_PIN(
67
+
4, "GPIO4",
68
+
MTK_EINT_FUNCTION(0, 4),
69
+
DRV_GRP4,
70
+
MTK_FUNCTION(0, "GPIO4"),
71
+
MTK_FUNCTION(1, "TP_GPIO4_AO"),
72
+
MTK_FUNCTION(2, "SPIM4_A_CSB"),
73
+
MTK_FUNCTION(3, "I2SIN0_DI"),
74
+
MTK_FUNCTION(4, "SCP_SPI1_CS"),
75
+
MTK_FUNCTION(6, "CONN_BPI_BUS10"),
76
+
MTK_FUNCTION(7, "DBG_MON_A4")
77
+
),
78
+
79
+
MTK_PIN(
80
+
5, "GPIO5",
81
+
MTK_EINT_FUNCTION(0, 5),
82
+
DRV_GRP4,
83
+
MTK_FUNCTION(0, "GPIO5"),
84
+
MTK_FUNCTION(1, "TP_GPIO5_AO"),
85
+
MTK_FUNCTION(2, "SPIM4_A_CLK"),
86
+
MTK_FUNCTION(3, "I2SIN0_BCK"),
87
+
MTK_FUNCTION(4, "SCP_SPI1_CK"),
88
+
MTK_FUNCTION(6, "CONN_BPI_BUS11_OLAT0"),
89
+
MTK_FUNCTION(7, "DBG_MON_A5")
90
+
),
91
+
92
+
MTK_PIN(
93
+
6, "GPIO6",
94
+
MTK_EINT_FUNCTION(0, 6),
95
+
DRV_GRP4,
96
+
MTK_FUNCTION(0, "GPIO6"),
97
+
MTK_FUNCTION(1, "TP_GPIO6_AO"),
98
+
MTK_FUNCTION(2, "SPIM4_A_MO"),
99
+
MTK_FUNCTION(3, "I2SIN0_LRCK"),
100
+
MTK_FUNCTION(4, "SCP_SPI1_MO"),
101
+
MTK_FUNCTION(6, "CONN_BPI_BUS12_OLAT1"),
102
+
MTK_FUNCTION(7, "DBG_MON_A6")
103
+
),
104
+
105
+
MTK_PIN(
106
+
7, "GPIO7",
107
+
MTK_EINT_FUNCTION(0, 7),
108
+
DRV_GRP4,
109
+
MTK_FUNCTION(0, "GPIO7"),
110
+
MTK_FUNCTION(1, "TP_GPIO7_AO"),
111
+
MTK_FUNCTION(2, "SPIM4_A_MI"),
112
+
MTK_FUNCTION(3, "I2SIN0_MCK"),
113
+
MTK_FUNCTION(4, "SCP_SPI1_MI"),
114
+
MTK_FUNCTION(6, "CONN_BPI_BUS13_OLAT2"),
115
+
MTK_FUNCTION(7, "DBG_MON_A7")
116
+
),
117
+
118
+
MTK_PIN(
119
+
8, "GPIO8",
120
+
MTK_EINT_FUNCTION(0, 8),
121
+
DRV_GRP4,
122
+
MTK_FUNCTION(0, "GPIO8"),
123
+
MTK_FUNCTION(1, "TP_UTXD1_VLP"),
124
+
MTK_FUNCTION(2, "SPIM5_A_CSB"),
125
+
MTK_FUNCTION(3, "I2SOUT1_MCK"),
126
+
MTK_FUNCTION(4, "VADSP_UTXD0"),
127
+
MTK_FUNCTION(6, "CONN_BPI_BUS14_OLAT3"),
128
+
MTK_FUNCTION(7, "DBG_MON_A8")
129
+
),
130
+
131
+
MTK_PIN(
132
+
9, "GPIO9",
133
+
MTK_EINT_FUNCTION(0, 9),
134
+
DRV_GRP4,
135
+
MTK_FUNCTION(0, "GPIO9"),
136
+
MTK_FUNCTION(1, "TP_URXD1_VLP"),
137
+
MTK_FUNCTION(2, "SPIM5_A_CLK"),
138
+
MTK_FUNCTION(3, "I2SOUT1_BCK"),
139
+
MTK_FUNCTION(4, "VADSP_URXD0"),
140
+
MTK_FUNCTION(6, "CONN_BPI_BUS15_OLAT4"),
141
+
MTK_FUNCTION(7, "DBG_MON_A9")
142
+
),
143
+
144
+
MTK_PIN(
145
+
10, "GPIO10",
146
+
MTK_EINT_FUNCTION(0, 10),
147
+
DRV_GRP4,
148
+
MTK_FUNCTION(0, "GPIO10"),
149
+
MTK_FUNCTION(1, "TP_UCTS1_VLP"),
150
+
MTK_FUNCTION(2, "SPIM5_A_MO"),
151
+
MTK_FUNCTION(3, "I2SOUT1_LRCK"),
152
+
MTK_FUNCTION(4, "SRCLKENAI0"),
153
+
MTK_FUNCTION(6, "CONN_BPI_BUS16_OLAT5"),
154
+
MTK_FUNCTION(7, "DBG_MON_A10")
155
+
),
156
+
157
+
MTK_PIN(
158
+
11, "GPIO11",
159
+
MTK_EINT_FUNCTION(0, 11),
160
+
DRV_GRP4,
161
+
MTK_FUNCTION(0, "GPIO11"),
162
+
MTK_FUNCTION(1, "TP_URTS1_VLP"),
163
+
MTK_FUNCTION(2, "SPIM5_A_MI"),
164
+
MTK_FUNCTION(3, "I2SOUT1_DO"),
165
+
MTK_FUNCTION(4, "SRCLKENAI1"),
166
+
MTK_FUNCTION(5, "PWM_vlp"),
167
+
MTK_FUNCTION(7, "DBG_MON_A11")
168
+
),
169
+
170
+
MTK_PIN(
171
+
12, "GPIO12",
172
+
MTK_EINT_FUNCTION(0, 12),
173
+
DRV_GRP4,
174
+
MTK_FUNCTION(0, "GPIO12"),
175
+
MTK_FUNCTION(1, "TP_UTXD1_VCORE"),
176
+
MTK_FUNCTION(2, "UTXD3"),
177
+
MTK_FUNCTION(3, "CLKM0"),
178
+
MTK_FUNCTION(4, "CMFLASH0"),
179
+
MTK_FUNCTION(6, "ANT_SEL0"),
180
+
MTK_FUNCTION(7, "DBG_MON_B20")
181
+
),
182
+
183
+
MTK_PIN(
184
+
13, "GPIO13",
185
+
MTK_EINT_FUNCTION(0, 13),
186
+
DRV_GRP4,
187
+
MTK_FUNCTION(0, "GPIO13"),
188
+
MTK_FUNCTION(1, "TP_URXD1_VCORE"),
189
+
MTK_FUNCTION(2, "URXD3"),
190
+
MTK_FUNCTION(3, "CLKM1"),
191
+
MTK_FUNCTION(4, "CMFLASH1"),
192
+
MTK_FUNCTION(6, "ANT_SEL1"),
193
+
MTK_FUNCTION(7, "DBG_MON_B21")
194
+
),
195
+
196
+
MTK_PIN(
197
+
14, "GPIO14",
198
+
MTK_EINT_FUNCTION(0, 14),
199
+
DRV_GRP4,
200
+
MTK_FUNCTION(0, "GPIO14"),
201
+
MTK_FUNCTION(1, "TP_UCTS1_VCORE"),
202
+
MTK_FUNCTION(2, "UCTS3"),
203
+
MTK_FUNCTION(3, "CLKM2"),
204
+
MTK_FUNCTION(4, "CMFLASH2"),
205
+
MTK_FUNCTION(6, "ANT_SEL2"),
206
+
MTK_FUNCTION(7, "DBG_MON_B22")
207
+
),
208
+
209
+
MTK_PIN(
210
+
15, "GPIO15",
211
+
MTK_EINT_FUNCTION(0, 15),
212
+
DRV_GRP4,
213
+
MTK_FUNCTION(0, "GPIO15"),
214
+
MTK_FUNCTION(1, "TP_URTS1_VCORE"),
215
+
MTK_FUNCTION(2, "URTS3"),
216
+
MTK_FUNCTION(3, "CLKM3"),
217
+
MTK_FUNCTION(4, "CMVREF0"),
218
+
MTK_FUNCTION(6, "ANT_SEL3"),
219
+
MTK_FUNCTION(7, "DBG_MON_B23")
220
+
),
221
+
222
+
MTK_PIN(
223
+
16, "GPIO16",
224
+
MTK_EINT_FUNCTION(0, 16),
225
+
DRV_GRP4,
226
+
MTK_FUNCTION(0, "GPIO16"),
227
+
MTK_FUNCTION(1, "PWM_0"),
228
+
MTK_FUNCTION(2, "UCTS2"),
229
+
MTK_FUNCTION(3, "DP_TX_HPD"),
230
+
MTK_FUNCTION(4, "CMVREF1"),
231
+
MTK_FUNCTION(5, "MD32_0_GPIO0"),
232
+
MTK_FUNCTION(6, "ANT_SEL4"),
233
+
MTK_FUNCTION(7, "DBG_MON_B24")
234
+
),
235
+
236
+
MTK_PIN(
237
+
17, "GPIO17",
238
+
MTK_EINT_FUNCTION(0, 17),
239
+
DRV_GRP4,
240
+
MTK_FUNCTION(0, "GPIO17"),
241
+
MTK_FUNCTION(1, "PWM_1"),
242
+
MTK_FUNCTION(2, "URTS2"),
243
+
MTK_FUNCTION(3, "EDP_TX_HPD"),
244
+
MTK_FUNCTION(4, "CMVREF2"),
245
+
MTK_FUNCTION(5, "MD32_1_GPIO0"),
246
+
MTK_FUNCTION(6, "PMSR_SMAP"),
247
+
MTK_FUNCTION(7, "DBG_MON_B25")
248
+
),
249
+
250
+
MTK_PIN(
251
+
18, "GPIO18",
252
+
MTK_EINT_FUNCTION(0, 18),
253
+
DRV_GRP4,
254
+
MTK_FUNCTION(0, "GPIO18"),
255
+
MTK_FUNCTION(1, "CMFLASH0"),
256
+
MTK_FUNCTION(2, "CMVREF3"),
257
+
MTK_FUNCTION(3, "UTXD2"),
258
+
MTK_FUNCTION(4, "DISP_PWM1"),
259
+
MTK_FUNCTION(5, "I2SIN1_MCK"),
260
+
MTK_FUNCTION(6, "mbistreaden_trigger"),
261
+
MTK_FUNCTION(7, "DBG_MON_A12")
262
+
),
263
+
264
+
MTK_PIN(
265
+
19, "GPIO19",
266
+
MTK_EINT_FUNCTION(0, 19),
267
+
DRV_GRP4,
268
+
MTK_FUNCTION(0, "GPIO19"),
269
+
MTK_FUNCTION(1, "CMFLASH1"),
270
+
MTK_FUNCTION(2, "CMVREF2"),
271
+
MTK_FUNCTION(3, "URXD2"),
272
+
MTK_FUNCTION(4, "USB_DRVVBUS_1P"),
273
+
MTK_FUNCTION(5, "I2SIN1_BCK"),
274
+
MTK_FUNCTION(6, "mbistwriteen_trigger"),
275
+
MTK_FUNCTION(7, "DBG_MON_A13")
276
+
),
277
+
278
+
MTK_PIN(
279
+
20, "GPIO20",
280
+
MTK_EINT_FUNCTION(0, 20),
281
+
DRV_GRP4,
282
+
MTK_FUNCTION(0, "GPIO20"),
283
+
MTK_FUNCTION(1, "CMFLASH2"),
284
+
MTK_FUNCTION(2, "CMVREF1"),
285
+
MTK_FUNCTION(3, "UCTS2"),
286
+
MTK_FUNCTION(4, "PERSTN"),
287
+
MTK_FUNCTION(5, "I2SIN1_LRCK"),
288
+
MTK_FUNCTION(6, "DMIC0_DAT1"),
289
+
MTK_FUNCTION(7, "DBG_MON_A14")
290
+
),
291
+
292
+
MTK_PIN(
293
+
21, "GPIO21",
294
+
MTK_EINT_FUNCTION(0, 21),
295
+
DRV_GRP4,
296
+
MTK_FUNCTION(0, "GPIO21"),
297
+
MTK_FUNCTION(1, "CMFLASH3"),
298
+
MTK_FUNCTION(2, "CMVREF0"),
299
+
MTK_FUNCTION(3, "URTS2"),
300
+
MTK_FUNCTION(4, "CLKREQN"),
301
+
MTK_FUNCTION(5, "I2SIN1_DI"),
302
+
MTK_FUNCTION(6, "DMIC1_DAT1"),
303
+
MTK_FUNCTION(7, "DBG_MON_A15")
304
+
),
305
+
306
+
MTK_PIN(
307
+
22, "GPIO22",
308
+
MTK_EINT_FUNCTION(0, 22),
309
+
DRV_GRP4,
310
+
MTK_FUNCTION(0, "GPIO22"),
311
+
MTK_FUNCTION(1, "CMMCLK0"),
312
+
MTK_FUNCTION(2, "TP_GPIO4_AO")
313
+
),
314
+
315
+
MTK_PIN(
316
+
23, "GPIO23",
317
+
MTK_EINT_FUNCTION(0, 23),
318
+
DRV_GRP4,
319
+
MTK_FUNCTION(0, "GPIO23"),
320
+
MTK_FUNCTION(1, "CMMCLK1"),
321
+
MTK_FUNCTION(2, "TP_GPIO5_AO"),
322
+
MTK_FUNCTION(3, "SSPM_UTXD_AO_VLP"),
323
+
MTK_FUNCTION(4, "PWM_vlp"),
324
+
MTK_FUNCTION(6, "SRCLKENAI0")
325
+
),
326
+
327
+
MTK_PIN(
328
+
24, "GPIO24",
329
+
MTK_EINT_FUNCTION(0, 24),
330
+
DRV_GRP4,
331
+
MTK_FUNCTION(0, "GPIO24"),
332
+
MTK_FUNCTION(1, "CMMCLK2"),
333
+
MTK_FUNCTION(2, "TP_GPIO6_AO"),
334
+
MTK_FUNCTION(3, "SSPM_URXD_AO_VLP"),
335
+
MTK_FUNCTION(4, "WAKEN"),
336
+
MTK_FUNCTION(5, "SPMI_P_TRIG_FLAG"),
337
+
MTK_FUNCTION(6, "SRCLKENAI1")
338
+
),
339
+
340
+
MTK_PIN(
341
+
25, "GPIO25",
342
+
MTK_EINT_FUNCTION(0, 25),
343
+
DRV_GRP4,
344
+
MTK_FUNCTION(0, "GPIO25"),
345
+
MTK_FUNCTION(1, "LCM_RST"),
346
+
MTK_FUNCTION(2, "DP_TX_HPD"),
347
+
MTK_FUNCTION(3, "CMFLASH3"),
348
+
MTK_FUNCTION(4, "MD32_0_GPIO0"),
349
+
MTK_FUNCTION(5, "USB_DRVVBUS_2P")
350
+
),
351
+
352
+
MTK_PIN(
353
+
26, "GPIO26",
354
+
MTK_EINT_FUNCTION(0, 26),
355
+
DRV_GRP4,
356
+
MTK_FUNCTION(0, "GPIO26"),
357
+
MTK_FUNCTION(1, "DSI_TE"),
358
+
MTK_FUNCTION(2, "EDP_TX_HPD"),
359
+
MTK_FUNCTION(3, "CMVREF3"),
360
+
MTK_FUNCTION(4, "MD32_1_GPIO0"),
361
+
MTK_FUNCTION(5, "USB_DRVVBUS_3P")
362
+
),
363
+
364
+
MTK_PIN(
365
+
27, "GPIO27",
366
+
MTK_EINT_FUNCTION(0, 27),
367
+
DRV_GRP4,
368
+
MTK_FUNCTION(0, "GPIO27"),
369
+
MTK_FUNCTION(1, "DP_TX_HPD"),
370
+
MTK_FUNCTION(2, "mbistreaden_trigger"),
371
+
MTK_FUNCTION(3, "MD32_0_GPIO0"),
372
+
MTK_FUNCTION(4, "TP_UCTS1_VCORE"),
373
+
MTK_FUNCTION(5, "CMVREF4"),
374
+
MTK_FUNCTION(6, "EXTIF0_ACT"),
375
+
MTK_FUNCTION(7, "ANT_SEL0")
376
+
),
377
+
378
+
MTK_PIN(
379
+
28, "GPIO28",
380
+
MTK_EINT_FUNCTION(0, 28),
381
+
DRV_GRP4,
382
+
MTK_FUNCTION(0, "GPIO28"),
383
+
MTK_FUNCTION(1, "EDP_TX_HPD"),
384
+
MTK_FUNCTION(2, "mbistwriteen_trigger"),
385
+
MTK_FUNCTION(3, "MD32_1_GPIO0"),
386
+
MTK_FUNCTION(4, "TP_URTS1_VCORE"),
387
+
MTK_FUNCTION(6, "EXTIF0_PRI"),
388
+
MTK_FUNCTION(7, "ANT_SEL1")
389
+
),
390
+
391
+
MTK_PIN(
392
+
29, "GPIO29",
393
+
MTK_EINT_FUNCTION(0, 29),
394
+
DRV_GRP4,
395
+
MTK_FUNCTION(0, "GPIO29"),
396
+
MTK_FUNCTION(1, "DISP_PWM0"),
397
+
MTK_FUNCTION(2, "MD32_1_TXD"),
398
+
MTK_FUNCTION(3, "SSPM_UTXD_AO_VCORE"),
399
+
MTK_FUNCTION(5, "USB_DRVVBUS_4P")
400
+
),
401
+
402
+
MTK_PIN(
403
+
30, "GPIO30",
404
+
MTK_EINT_FUNCTION(0, 30),
405
+
DRV_GRP4,
406
+
MTK_FUNCTION(0, "GPIO30"),
407
+
MTK_FUNCTION(1, "DISP_PWM1"),
408
+
MTK_FUNCTION(2, "MD32_1_RXD"),
409
+
MTK_FUNCTION(3, "SSPM_URXD_AO_VCORE"),
410
+
MTK_FUNCTION(5, "PMSR_SMAP"),
411
+
MTK_FUNCTION(6, "EXTIF0_GNT_B"),
412
+
MTK_FUNCTION(7, "ANT_SEL2")
413
+
),
414
+
415
+
MTK_PIN(
416
+
31, "GPIO31",
417
+
MTK_EINT_FUNCTION(0, 31),
418
+
DRV_GRP4,
419
+
MTK_FUNCTION(0, "GPIO31"),
420
+
MTK_FUNCTION(1, "UTXD0"),
421
+
MTK_FUNCTION(2, "MD32_0_TXD")
422
+
),
423
+
424
+
MTK_PIN(
425
+
32, "GPIO32",
426
+
MTK_EINT_FUNCTION(0, 32),
427
+
DRV_GRP4,
428
+
MTK_FUNCTION(0, "GPIO32"),
429
+
MTK_FUNCTION(1, "URXD0"),
430
+
MTK_FUNCTION(2, "MD32_0_RXD")
431
+
),
432
+
433
+
MTK_PIN(
434
+
33, "GPIO33",
435
+
MTK_EINT_FUNCTION(0, 33),
436
+
DRV_GRP4,
437
+
MTK_FUNCTION(0, "GPIO33"),
438
+
MTK_FUNCTION(1, "UTXD1"),
439
+
MTK_FUNCTION(2, "VADSP_UTXD0"),
440
+
MTK_FUNCTION(3, "TP_UTXD1_VLP"),
441
+
MTK_FUNCTION(4, "MD32_1_TXD"),
442
+
MTK_FUNCTION(5, "CONN_BGF_UART0_TXD"),
443
+
MTK_FUNCTION(6, "CONN_WIFI_TXD")
444
+
),
445
+
446
+
MTK_PIN(
447
+
34, "GPIO34",
448
+
MTK_EINT_FUNCTION(0, 34),
449
+
DRV_GRP4,
450
+
MTK_FUNCTION(0, "GPIO34"),
451
+
MTK_FUNCTION(1, "URXD1"),
452
+
MTK_FUNCTION(2, "VADSP_URXD0"),
453
+
MTK_FUNCTION(3, "TP_URXD1_VLP"),
454
+
MTK_FUNCTION(4, "MD32_1_RXD"),
455
+
MTK_FUNCTION(5, "CONN_BGF_UART0_RXD")
456
+
),
457
+
458
+
MTK_PIN(
459
+
35, "GPIO35",
460
+
MTK_EINT_FUNCTION(0, 35),
461
+
DRV_GRP4,
462
+
MTK_FUNCTION(0, "GPIO35"),
463
+
MTK_FUNCTION(1, "UTXD2"),
464
+
MTK_FUNCTION(2, "UCTS1"),
465
+
MTK_FUNCTION(3, "TP_UCTS1_VLP"),
466
+
MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"),
467
+
MTK_FUNCTION(5, "VADSP_UTXD0"),
468
+
MTK_FUNCTION(6, "CONN_BT_TXD")
469
+
),
470
+
471
+
MTK_PIN(
472
+
36, "GPIO36",
473
+
MTK_EINT_FUNCTION(0, 36),
474
+
DRV_GRP4,
475
+
MTK_FUNCTION(0, "GPIO36"),
476
+
MTK_FUNCTION(1, "URXD2"),
477
+
MTK_FUNCTION(2, "URTS1"),
478
+
MTK_FUNCTION(3, "TP_URTS1_VLP"),
479
+
MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"),
480
+
MTK_FUNCTION(5, "VADSP_URXD0")
481
+
),
482
+
483
+
MTK_PIN(
484
+
37, "GPIO37",
485
+
MTK_EINT_FUNCTION(0, 37),
486
+
DRV_GRP4,
487
+
MTK_FUNCTION(0, "GPIO37"),
488
+
MTK_FUNCTION(1, "UTXD3"),
489
+
MTK_FUNCTION(2, "UCTS0"),
490
+
MTK_FUNCTION(3, "TP_UTXD1_VCORE"),
491
+
MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"),
492
+
MTK_FUNCTION(6, "MD32_0_TXD"),
493
+
MTK_FUNCTION(7, "CONN_BGF_UART0_TXD")
494
+
),
495
+
496
+
MTK_PIN(
497
+
38, "GPIO38",
498
+
MTK_EINT_FUNCTION(0, 38),
499
+
DRV_GRP4,
500
+
MTK_FUNCTION(0, "GPIO38"),
501
+
MTK_FUNCTION(1, "URXD3"),
502
+
MTK_FUNCTION(2, "URTS0"),
503
+
MTK_FUNCTION(3, "TP_URXD1_VCORE"),
504
+
MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"),
505
+
MTK_FUNCTION(6, "MD32_0_RXD"),
506
+
MTK_FUNCTION(7, "CONN_BGF_UART0_RXD")
507
+
),
508
+
509
+
MTK_PIN(
510
+
39, "GPIO39",
511
+
MTK_EINT_FUNCTION(0, 39),
512
+
DRV_GRP4,
513
+
MTK_FUNCTION(0, "GPIO39"),
514
+
MTK_FUNCTION(1, "JTMS_SEL1")
515
+
),
516
+
517
+
MTK_PIN(
518
+
40, "GPIO40",
519
+
MTK_EINT_FUNCTION(0, 40),
520
+
DRV_GRP4,
521
+
MTK_FUNCTION(0, "GPIO40"),
522
+
MTK_FUNCTION(1, "JTCK_SEL1")
523
+
),
524
+
525
+
MTK_PIN(
526
+
41, "GPIO41",
527
+
MTK_EINT_FUNCTION(0, 41),
528
+
DRV_GRP4,
529
+
MTK_FUNCTION(0, "GPIO41"),
530
+
MTK_FUNCTION(1, "JTDI_SEL1")
531
+
),
532
+
533
+
MTK_PIN(
534
+
42, "GPIO42",
535
+
MTK_EINT_FUNCTION(0, 42),
536
+
DRV_GRP4,
537
+
MTK_FUNCTION(0, "GPIO42"),
538
+
MTK_FUNCTION(1, "JTDO_SEL1")
539
+
),
540
+
541
+
MTK_PIN(
542
+
43, "GPIO43",
543
+
MTK_EINT_FUNCTION(0, 43),
544
+
DRV_GRP4,
545
+
MTK_FUNCTION(0, "GPIO43"),
546
+
MTK_FUNCTION(1, "JTRSTn_SEL1")
547
+
),
548
+
549
+
MTK_PIN(
550
+
44, "GPIO44",
551
+
MTK_EINT_FUNCTION(0, 44),
552
+
DRV_GRP4,
553
+
MTK_FUNCTION(0, "GPIO44"),
554
+
MTK_FUNCTION(1, "KPCOL0")
555
+
),
556
+
557
+
MTK_PIN(
558
+
45, "GPIO45",
559
+
MTK_EINT_FUNCTION(0, 45),
560
+
DRV_GRP4,
561
+
MTK_FUNCTION(0, "GPIO45"),
562
+
MTK_FUNCTION(1, "KPCOL1"),
563
+
MTK_FUNCTION(2, "TP_GPIO0_AO"),
564
+
MTK_FUNCTION(3, "SRCLKENAI1"),
565
+
MTK_FUNCTION(7, "DBG_MON_A31")
566
+
),
567
+
568
+
MTK_PIN(
569
+
46, "GPIO46",
570
+
MTK_EINT_FUNCTION(0, 46),
571
+
DRV_GRP4,
572
+
MTK_FUNCTION(0, "GPIO46"),
573
+
MTK_FUNCTION(1, "KPROW0"),
574
+
MTK_FUNCTION(2, "TP_GPIO1_AO")
575
+
),
576
+
577
+
MTK_PIN(
578
+
47, "GPIO47",
579
+
MTK_EINT_FUNCTION(0, 47),
580
+
DRV_GRP4,
581
+
MTK_FUNCTION(0, "GPIO47"),
582
+
MTK_FUNCTION(1, "KPROW1"),
583
+
MTK_FUNCTION(2, "TP_GPIO2_AO"),
584
+
MTK_FUNCTION(3, "SRCLKENAI0"),
585
+
MTK_FUNCTION(7, "DBG_MON_A32")
586
+
),
587
+
588
+
MTK_PIN(
589
+
48, "GPIO48",
590
+
MTK_EINT_FUNCTION(0, 48),
591
+
DRV_GRP4,
592
+
MTK_FUNCTION(0, "GPIO48"),
593
+
MTK_FUNCTION(1, "WAKEN"),
594
+
MTK_FUNCTION(2, "TP_GPIO3_AO"),
595
+
MTK_FUNCTION(3, "SPMI_P_TRIG_FLAG")
596
+
),
597
+
598
+
MTK_PIN(
599
+
49, "GPIO49",
600
+
MTK_EINT_FUNCTION(0, 49),
601
+
DRV_GRP4,
602
+
MTK_FUNCTION(0, "GPIO49"),
603
+
MTK_FUNCTION(1, "PERSTN"),
604
+
MTK_FUNCTION(2, "MD32_0_GPIO0"),
605
+
MTK_FUNCTION(3, "UFS_MPHY_SCL"),
606
+
MTK_FUNCTION(7, "ANT_SEL3")
607
+
),
608
+
609
+
MTK_PIN(
610
+
50, "GPIO50",
611
+
MTK_EINT_FUNCTION(0, 50),
612
+
DRV_GRP4,
613
+
MTK_FUNCTION(0, "GPIO50"),
614
+
MTK_FUNCTION(1, "CLKREQN"),
615
+
MTK_FUNCTION(2, "MD32_1_GPIO0"),
616
+
MTK_FUNCTION(3, "UFS_MPHY_SDA"),
617
+
MTK_FUNCTION(7, "ANT_SEL4")
618
+
),
619
+
620
+
MTK_PIN(
621
+
51, "GPIO51",
622
+
MTK_EINT_FUNCTION(0, 51),
623
+
DRV_GRP4,
624
+
MTK_FUNCTION(0, "GPIO51"),
625
+
MTK_FUNCTION(1, "SCP_SCL0"),
626
+
MTK_FUNCTION(2, "SCL0")
627
+
),
628
+
629
+
MTK_PIN(
630
+
52, "GPIO52",
631
+
MTK_EINT_FUNCTION(0, 52),
632
+
DRV_GRP4,
633
+
MTK_FUNCTION(0, "GPIO52"),
634
+
MTK_FUNCTION(1, "SCP_SDA0"),
635
+
MTK_FUNCTION(2, "SDA0")
636
+
),
637
+
638
+
MTK_PIN(
639
+
53, "GPIO53",
640
+
MTK_EINT_FUNCTION(0, 53),
641
+
DRV_GRP4,
642
+
MTK_FUNCTION(0, "GPIO53"),
643
+
MTK_FUNCTION(1, "SCP_SCL1"),
644
+
MTK_FUNCTION(2, "SCL1")
645
+
),
646
+
647
+
MTK_PIN(
648
+
54, "GPIO54",
649
+
MTK_EINT_FUNCTION(0, 54),
650
+
DRV_GRP4,
651
+
MTK_FUNCTION(0, "GPIO54"),
652
+
MTK_FUNCTION(1, "SCP_SDA1"),
653
+
MTK_FUNCTION(2, "SDA1")
654
+
),
655
+
656
+
MTK_PIN(
657
+
55, "GPIO55",
658
+
MTK_EINT_FUNCTION(0, 55),
659
+
DRV_GRP4,
660
+
MTK_FUNCTION(0, "GPIO55"),
661
+
MTK_FUNCTION(1, "SCL2"),
662
+
MTK_FUNCTION(2, "UFS_MPHY_SCL"),
663
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SCL")
664
+
),
665
+
666
+
MTK_PIN(
667
+
56, "GPIO56",
668
+
MTK_EINT_FUNCTION(0, 56),
669
+
DRV_GRP4,
670
+
MTK_FUNCTION(0, "GPIO56"),
671
+
MTK_FUNCTION(1, "SDA2"),
672
+
MTK_FUNCTION(2, "UFS_MPHY_SDA"),
673
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SDA")
674
+
),
675
+
676
+
MTK_PIN(
677
+
57, "GPIO57",
678
+
MTK_EINT_FUNCTION(0, 57),
679
+
DRV_GRP4,
680
+
MTK_FUNCTION(0, "GPIO57"),
681
+
MTK_FUNCTION(1, "SCL3"),
682
+
MTK_FUNCTION(2, "PCIE_PHY_I2C_SCL"),
683
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SCL_1P")
684
+
),
685
+
686
+
MTK_PIN(
687
+
58, "GPIO58",
688
+
MTK_EINT_FUNCTION(0, 58),
689
+
DRV_GRP4,
690
+
MTK_FUNCTION(0, "GPIO58"),
691
+
MTK_FUNCTION(1, "SDA3"),
692
+
MTK_FUNCTION(2, "PCIE_PHY_I2C_SDA"),
693
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SDA_1P")
694
+
),
695
+
696
+
MTK_PIN(
697
+
59, "GPIO59",
698
+
MTK_EINT_FUNCTION(0, 59),
699
+
DRV_GRP4,
700
+
MTK_FUNCTION(0, "GPIO59"),
701
+
MTK_FUNCTION(1, "SCL4"),
702
+
MTK_FUNCTION(2, "SSUSB_U3PHY_I2C_SCL")
703
+
),
704
+
705
+
MTK_PIN(
706
+
60, "GPIO60",
707
+
MTK_EINT_FUNCTION(0, 60),
708
+
DRV_GRP4,
709
+
MTK_FUNCTION(0, "GPIO60"),
710
+
MTK_FUNCTION(1, "SDA4"),
711
+
MTK_FUNCTION(2, "SSUSB_U3PHY_I2C_SDA")
712
+
),
713
+
714
+
MTK_PIN(
715
+
61, "GPIO61",
716
+
MTK_EINT_FUNCTION(0, 61),
717
+
DRV_GRP4,
718
+
MTK_FUNCTION(0, "GPIO61"),
719
+
MTK_FUNCTION(1, "SCL5"),
720
+
MTK_FUNCTION(2, "SSPXTP_U3PHY_I2C_SCL")
721
+
),
722
+
723
+
MTK_PIN(
724
+
62, "GPIO62",
725
+
MTK_EINT_FUNCTION(0, 62),
726
+
DRV_GRP4,
727
+
MTK_FUNCTION(0, "GPIO62"),
728
+
MTK_FUNCTION(1, "SDA5"),
729
+
MTK_FUNCTION(2, "SSPXTP_U3PHY_I2C_SDA")
730
+
),
731
+
732
+
MTK_PIN(
733
+
63, "GPIO63",
734
+
MTK_EINT_FUNCTION(0, 63),
735
+
DRV_GRP4,
736
+
MTK_FUNCTION(0, "GPIO63"),
737
+
MTK_FUNCTION(1, "SCL6")
738
+
),
739
+
740
+
MTK_PIN(
741
+
64, "GPIO64",
742
+
MTK_EINT_FUNCTION(0, 64),
743
+
DRV_GRP4,
744
+
MTK_FUNCTION(0, "GPIO64"),
745
+
MTK_FUNCTION(1, "SDA6")
746
+
),
747
+
748
+
MTK_PIN(
749
+
65, "GPIO65",
750
+
MTK_EINT_FUNCTION(0, 65),
751
+
DRV_GRP4,
752
+
MTK_FUNCTION(0, "GPIO65"),
753
+
MTK_FUNCTION(1, "SCL7")
754
+
),
755
+
756
+
MTK_PIN(
757
+
66, "GPIO66",
758
+
MTK_EINT_FUNCTION(0, 66),
759
+
DRV_GRP4,
760
+
MTK_FUNCTION(0, "GPIO66"),
761
+
MTK_FUNCTION(1, "SDA7")
762
+
),
763
+
764
+
MTK_PIN(
765
+
67, "GPIO67",
766
+
MTK_EINT_FUNCTION(0, 67),
767
+
DRV_GRP4,
768
+
MTK_FUNCTION(0, "GPIO67"),
769
+
MTK_FUNCTION(1, "SCL8")
770
+
),
771
+
772
+
MTK_PIN(
773
+
68, "GPIO68",
774
+
MTK_EINT_FUNCTION(0, 68),
775
+
DRV_GRP4,
776
+
MTK_FUNCTION(0, "GPIO68"),
777
+
MTK_FUNCTION(1, "SDA8")
778
+
),
779
+
780
+
MTK_PIN(
781
+
69, "GPIO69",
782
+
MTK_EINT_FUNCTION(0, 69),
783
+
DRV_GRP4,
784
+
MTK_FUNCTION(0, "GPIO69"),
785
+
MTK_FUNCTION(1, "SPIM0_CSB"),
786
+
MTK_FUNCTION(2, "SCP_SPI0_CS"),
787
+
MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"),
788
+
MTK_FUNCTION(4, "VADSP_JTAG0_TMS"),
789
+
MTK_FUNCTION(5, "SPM_JTAG_TMS"),
790
+
MTK_FUNCTION(6, "SSPM_JTAG_TMS_VLP"),
791
+
MTK_FUNCTION(7, "SCP_JTAG0_TMS_VLP")
792
+
),
793
+
794
+
MTK_PIN(
795
+
70, "GPIO70",
796
+
MTK_EINT_FUNCTION(0, 70),
797
+
DRV_GRP4,
798
+
MTK_FUNCTION(0, "GPIO70"),
799
+
MTK_FUNCTION(1, "SPIM0_CLK"),
800
+
MTK_FUNCTION(2, "SCP_SPI0_CK"),
801
+
MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"),
802
+
MTK_FUNCTION(4, "VADSP_JTAG0_TCK"),
803
+
MTK_FUNCTION(5, "SPM_JTAG_TCK"),
804
+
MTK_FUNCTION(6, "SSPM_JTAG_TCK_VLP"),
805
+
MTK_FUNCTION(7, "SCP_JTAG0_TCK_VLP")
806
+
),
807
+
808
+
MTK_PIN(
809
+
71, "GPIO71",
810
+
MTK_EINT_FUNCTION(0, 71),
811
+
DRV_GRP4,
812
+
MTK_FUNCTION(0, "GPIO71"),
813
+
MTK_FUNCTION(1, "SPIM0_MO"),
814
+
MTK_FUNCTION(2, "SCP_SPI0_MO"),
815
+
MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"),
816
+
MTK_FUNCTION(4, "VADSP_JTAG0_TDI"),
817
+
MTK_FUNCTION(5, "SPM_JTAG_TDI"),
818
+
MTK_FUNCTION(6, "SSPM_JTAG_TDI_VLP"),
819
+
MTK_FUNCTION(7, "SCP_JTAG0_TDI_VLP")
820
+
),
821
+
822
+
MTK_PIN(
823
+
72, "GPIO72",
824
+
MTK_EINT_FUNCTION(0, 72),
825
+
DRV_GRP4,
826
+
MTK_FUNCTION(0, "GPIO72"),
827
+
MTK_FUNCTION(1, "SPIM0_MI"),
828
+
MTK_FUNCTION(2, "SCP_SPI0_MI"),
829
+
MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"),
830
+
MTK_FUNCTION(4, "VADSP_JTAG0_TDO"),
831
+
MTK_FUNCTION(5, "SPM_JTAG_TDO"),
832
+
MTK_FUNCTION(6, "SSPM_JTAG_TDO_VLP"),
833
+
MTK_FUNCTION(7, "SCP_JTAG0_TDO_VLP")
834
+
),
835
+
836
+
MTK_PIN(
837
+
73, "GPIO73",
838
+
MTK_EINT_FUNCTION(0, 73),
839
+
DRV_GRP4,
840
+
MTK_FUNCTION(0, "GPIO73"),
841
+
MTK_FUNCTION(1, "SPIM1_CSB"),
842
+
MTK_FUNCTION(2, "SCP_SPI1_CS"),
843
+
MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"),
844
+
MTK_FUNCTION(4, "VADSP_JTAG0_TRSTN"),
845
+
MTK_FUNCTION(5, "SPM_JTAG_TRSTN"),
846
+
MTK_FUNCTION(6, "SSPM_JTAG_TRSTN_VLP"),
847
+
MTK_FUNCTION(7, "SCP_JTAG0_TRSTN_VLP")
848
+
),
849
+
850
+
MTK_PIN(
851
+
74, "GPIO74",
852
+
MTK_EINT_FUNCTION(0, 74),
853
+
DRV_GRP4,
854
+
MTK_FUNCTION(0, "GPIO74"),
855
+
MTK_FUNCTION(1, "SPIM1_CLK"),
856
+
MTK_FUNCTION(2, "SCP_SPI1_CK")
857
+
),
858
+
859
+
MTK_PIN(
860
+
75, "GPIO75",
861
+
MTK_EINT_FUNCTION(0, 75),
862
+
DRV_GRP4,
863
+
MTK_FUNCTION(0, "GPIO75"),
864
+
MTK_FUNCTION(1, "SPIM1_MO"),
865
+
MTK_FUNCTION(2, "SCP_SPI1_MO")
866
+
),
867
+
868
+
MTK_PIN(
869
+
76, "GPIO76",
870
+
MTK_EINT_FUNCTION(0, 76),
871
+
DRV_GRP4,
872
+
MTK_FUNCTION(0, "GPIO76"),
873
+
MTK_FUNCTION(1, "SPIM1_MI"),
874
+
MTK_FUNCTION(2, "SCP_SPI1_MI")
875
+
),
876
+
877
+
MTK_PIN(
878
+
77, "GPIO77",
879
+
MTK_EINT_FUNCTION(0, 77),
880
+
DRV_GRP4,
881
+
MTK_FUNCTION(0, "GPIO77"),
882
+
MTK_FUNCTION(1, "SPIM2_CSB"),
883
+
MTK_FUNCTION(2, "PCM0_SYNC"),
884
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SCL"),
885
+
MTK_FUNCTION(7, "DBG_MON_A27")
886
+
),
887
+
888
+
MTK_PIN(
889
+
78, "GPIO78",
890
+
MTK_EINT_FUNCTION(0, 78),
891
+
DRV_GRP4,
892
+
MTK_FUNCTION(0, "GPIO78"),
893
+
MTK_FUNCTION(1, "SPIM2_CLK"),
894
+
MTK_FUNCTION(2, "PCM0_CLK"),
895
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SDA"),
896
+
MTK_FUNCTION(7, "DBG_MON_A28")
897
+
),
898
+
899
+
MTK_PIN(
900
+
79, "GPIO79",
901
+
MTK_EINT_FUNCTION(0, 79),
902
+
DRV_GRP4,
903
+
MTK_FUNCTION(0, "GPIO79"),
904
+
MTK_FUNCTION(1, "SPIM2_MO"),
905
+
MTK_FUNCTION(2, "PCM0_DO"),
906
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SCL_1P"),
907
+
MTK_FUNCTION(7, "DBG_MON_A29")
908
+
),
909
+
910
+
MTK_PIN(
911
+
80, "GPIO80",
912
+
MTK_EINT_FUNCTION(0, 80),
913
+
DRV_GRP4,
914
+
MTK_FUNCTION(0, "GPIO80"),
915
+
MTK_FUNCTION(1, "SPIM2_MI"),
916
+
MTK_FUNCTION(2, "PCM0_DI"),
917
+
MTK_FUNCTION(3, "SSUSB_U2SIF_SDA_1P"),
918
+
MTK_FUNCTION(7, "DBG_MON_A30")
919
+
),
920
+
921
+
MTK_PIN(
922
+
81, "GPIO81",
923
+
MTK_EINT_FUNCTION(0, 81),
924
+
DRV_GRP4,
925
+
MTK_FUNCTION(0, "GPIO81"),
926
+
MTK_FUNCTION(1, "IDDIG"),
927
+
MTK_FUNCTION(7, "DBG_MON_B32")
928
+
),
929
+
930
+
MTK_PIN(
931
+
82, "GPIO82",
932
+
MTK_EINT_FUNCTION(0, 82),
933
+
DRV_GRP4,
934
+
MTK_FUNCTION(0, "GPIO82"),
935
+
MTK_FUNCTION(1, "USB_DRVVBUS")
936
+
),
937
+
938
+
MTK_PIN(
939
+
83, "GPIO83",
940
+
MTK_EINT_FUNCTION(0, 83),
941
+
DRV_GRP4,
942
+
MTK_FUNCTION(0, "GPIO83"),
943
+
MTK_FUNCTION(1, "VBUSVALID")
944
+
),
945
+
946
+
MTK_PIN(
947
+
84, "GPIO84",
948
+
MTK_EINT_FUNCTION(0, 84),
949
+
DRV_GRP4,
950
+
MTK_FUNCTION(0, "GPIO84"),
951
+
MTK_FUNCTION(1, "USB_DRVVBUS_1P"),
952
+
MTK_FUNCTION(7, "DBG_MON_A16")
953
+
),
954
+
955
+
MTK_PIN(
956
+
85, "GPIO85",
957
+
MTK_EINT_FUNCTION(0, 85),
958
+
DRV_GRP4,
959
+
MTK_FUNCTION(0, "GPIO85"),
960
+
MTK_FUNCTION(1, "USB_DRVVBUS_2P"),
961
+
MTK_FUNCTION(7, "DBG_MON_A17")
962
+
),
963
+
964
+
MTK_PIN(
965
+
86, "GPIO86",
966
+
MTK_EINT_FUNCTION(0, 86),
967
+
DRV_GRP4,
968
+
MTK_FUNCTION(0, "GPIO86"),
969
+
MTK_FUNCTION(1, "USB_DRVVBUS_3P"),
970
+
MTK_FUNCTION(7, "DBG_MON_A18")
971
+
),
972
+
973
+
MTK_PIN(
974
+
87, "GPIO87",
975
+
MTK_EINT_FUNCTION(0, 87),
976
+
DRV_GRP4,
977
+
MTK_FUNCTION(0, "GPIO87"),
978
+
MTK_FUNCTION(1, "USB_DRVVBUS_4P"),
979
+
MTK_FUNCTION(6, "CMVREF4"),
980
+
MTK_FUNCTION(7, "DBG_MON_A19")
981
+
),
982
+
983
+
MTK_PIN(
984
+
88, "GPIO88",
985
+
MTK_EINT_FUNCTION(0, 88),
986
+
DRV_GRP4,
987
+
MTK_FUNCTION(0, "GPIO88"),
988
+
MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
989
+
),
990
+
991
+
MTK_PIN(
992
+
89, "GPIO89",
993
+
MTK_EINT_FUNCTION(0, 89),
994
+
DRV_GRP4,
995
+
MTK_FUNCTION(0, "GPIO89"),
996
+
MTK_FUNCTION(1, "PWRAP_SPI0_CK")
997
+
),
998
+
999
+
MTK_PIN(
1000
+
90, "GPIO90",
1001
+
MTK_EINT_FUNCTION(0, 90),
1002
+
DRV_GRP4,
1003
+
MTK_FUNCTION(0, "GPIO90"),
1004
+
MTK_FUNCTION(1, "PWRAP_SPI0_MO")
1005
+
),
1006
+
1007
+
MTK_PIN(
1008
+
91, "GPIO91",
1009
+
MTK_EINT_FUNCTION(0, 91),
1010
+
DRV_GRP4,
1011
+
MTK_FUNCTION(0, "GPIO91"),
1012
+
MTK_FUNCTION(1, "PWRAP_SPI0_MI")
1013
+
),
1014
+
1015
+
MTK_PIN(
1016
+
92, "GPIO92",
1017
+
MTK_EINT_FUNCTION(0, 92),
1018
+
DRV_GRP4,
1019
+
MTK_FUNCTION(0, "GPIO92"),
1020
+
MTK_FUNCTION(1, "SRCLKENA0")
1021
+
),
1022
+
1023
+
MTK_PIN(
1024
+
93, "GPIO93",
1025
+
MTK_EINT_FUNCTION(0, 93),
1026
+
DRV_GRP4,
1027
+
MTK_FUNCTION(0, "GPIO93"),
1028
+
MTK_FUNCTION(1, "SRCLKENA1")
1029
+
),
1030
+
1031
+
MTK_PIN(
1032
+
94, "GPIO94",
1033
+
MTK_EINT_FUNCTION(0, 94),
1034
+
DRV_GRP4,
1035
+
MTK_FUNCTION(0, "GPIO94"),
1036
+
MTK_FUNCTION(1, "SCP_VREQ_VAO")
1037
+
),
1038
+
1039
+
MTK_PIN(
1040
+
95, "GPIO95",
1041
+
MTK_EINT_FUNCTION(0, 95),
1042
+
DRV_GRP4,
1043
+
MTK_FUNCTION(0, "GPIO95"),
1044
+
MTK_FUNCTION(1, "RTC32K_CK")
1045
+
),
1046
+
1047
+
MTK_PIN(
1048
+
96, "GPIO96",
1049
+
MTK_EINT_FUNCTION(0, 96),
1050
+
DRV_GRP4,
1051
+
MTK_FUNCTION(0, "GPIO96"),
1052
+
MTK_FUNCTION(1, "WATCHDOG")
1053
+
),
1054
+
1055
+
MTK_PIN(
1056
+
97, "GPIO97",
1057
+
MTK_EINT_FUNCTION(0, 97),
1058
+
DRV_GRP4,
1059
+
MTK_FUNCTION(0, "GPIO97"),
1060
+
MTK_FUNCTION(1, "AUD_CLK_MOSI")
1061
+
),
1062
+
1063
+
MTK_PIN(
1064
+
98, "GPIO98",
1065
+
MTK_EINT_FUNCTION(0, 98),
1066
+
DRV_GRP4,
1067
+
MTK_FUNCTION(0, "GPIO98"),
1068
+
MTK_FUNCTION(1, "AUD_SYNC_MOSI")
1069
+
),
1070
+
1071
+
MTK_PIN(
1072
+
99, "GPIO99",
1073
+
MTK_EINT_FUNCTION(0, 99),
1074
+
DRV_GRP4,
1075
+
MTK_FUNCTION(0, "GPIO99"),
1076
+
MTK_FUNCTION(1, "AUD_DAT_MOSI0")
1077
+
),
1078
+
1079
+
MTK_PIN(
1080
+
100, "GPIO100",
1081
+
MTK_EINT_FUNCTION(0, 100),
1082
+
DRV_GRP4,
1083
+
MTK_FUNCTION(0, "GPIO100"),
1084
+
MTK_FUNCTION(1, "AUD_DAT_MOSI1")
1085
+
),
1086
+
1087
+
MTK_PIN(
1088
+
101, "GPIO101",
1089
+
MTK_EINT_FUNCTION(0, 101),
1090
+
DRV_GRP4,
1091
+
MTK_FUNCTION(0, "GPIO101"),
1092
+
MTK_FUNCTION(1, "AUD_DAT_MISO0")
1093
+
),
1094
+
1095
+
MTK_PIN(
1096
+
102, "GPIO102",
1097
+
MTK_EINT_FUNCTION(0, 102),
1098
+
DRV_GRP4,
1099
+
MTK_FUNCTION(0, "GPIO102"),
1100
+
MTK_FUNCTION(1, "AUD_DAT_MISO1")
1101
+
),
1102
+
1103
+
MTK_PIN(
1104
+
103, "GPIO103",
1105
+
MTK_EINT_FUNCTION(0, 103),
1106
+
DRV_GRP4,
1107
+
MTK_FUNCTION(0, "GPIO103"),
1108
+
MTK_FUNCTION(1, "I2SIN0_MCK"),
1109
+
MTK_FUNCTION(2, "SPIM3_B_CSB"),
1110
+
MTK_FUNCTION(3, "APU_JTAG_TMS"),
1111
+
MTK_FUNCTION(4, "SCP_JTAG0_TMS_VCORE"),
1112
+
MTK_FUNCTION(5, "CONN_WF_MCU_TMS"),
1113
+
MTK_FUNCTION(6, "SSPM_JTAG_TMS_VCORE"),
1114
+
MTK_FUNCTION(7, "IPU_JTAG_TMS")
1115
+
),
1116
+
1117
+
MTK_PIN(
1118
+
104, "GPIO104",
1119
+
MTK_EINT_FUNCTION(0, 104),
1120
+
DRV_GRP4,
1121
+
MTK_FUNCTION(0, "GPIO104"),
1122
+
MTK_FUNCTION(1, "I2SIN0_BCK"),
1123
+
MTK_FUNCTION(2, "SPIM3_B_CLK"),
1124
+
MTK_FUNCTION(3, "APU_JTAG_TCK"),
1125
+
MTK_FUNCTION(4, "SCP_JTAG0_TCK_VCORE"),
1126
+
MTK_FUNCTION(5, "CONN_WF_MCU_TCK"),
1127
+
MTK_FUNCTION(6, "SSPM_JTAG_TCK_VCORE"),
1128
+
MTK_FUNCTION(7, "IPU_JTAG_TCK")
1129
+
),
1130
+
1131
+
MTK_PIN(
1132
+
105, "GPIO105",
1133
+
MTK_EINT_FUNCTION(0, 105),
1134
+
DRV_GRP4,
1135
+
MTK_FUNCTION(0, "GPIO105"),
1136
+
MTK_FUNCTION(1, "I2SIN0_LRCK"),
1137
+
MTK_FUNCTION(2, "SPIM3_B_MO"),
1138
+
MTK_FUNCTION(3, "APU_JTAG_TDI"),
1139
+
MTK_FUNCTION(4, "SCP_JTAG0_TDI_VCORE"),
1140
+
MTK_FUNCTION(5, "CONN_WF_MCU_TDI"),
1141
+
MTK_FUNCTION(6, "SSPM_JTAG_TDI_VCORE"),
1142
+
MTK_FUNCTION(7, "IPU_JTAG_TDI")
1143
+
),
1144
+
1145
+
MTK_PIN(
1146
+
106, "GPIO106",
1147
+
MTK_EINT_FUNCTION(0, 106),
1148
+
DRV_GRP4,
1149
+
MTK_FUNCTION(0, "GPIO106"),
1150
+
MTK_FUNCTION(1, "I2SIN0_DI"),
1151
+
MTK_FUNCTION(2, "SPIM3_B_MI"),
1152
+
MTK_FUNCTION(3, "APU_JTAG_TDO"),
1153
+
MTK_FUNCTION(4, "SCP_JTAG0_TDO_VCORE"),
1154
+
MTK_FUNCTION(5, "CONN_WF_MCU_TDO"),
1155
+
MTK_FUNCTION(6, "SSPM_JTAG_TDO_VCORE"),
1156
+
MTK_FUNCTION(7, "IPU_JTAG_TDO")
1157
+
),
1158
+
1159
+
MTK_PIN(
1160
+
107, "GPIO107",
1161
+
MTK_EINT_FUNCTION(0, 107),
1162
+
DRV_GRP4,
1163
+
MTK_FUNCTION(0, "GPIO107"),
1164
+
MTK_FUNCTION(1, "I2SOUT0_MCK"),
1165
+
MTK_FUNCTION(2, "SPIM4_B_CSB"),
1166
+
MTK_FUNCTION(3, "APU_JTAG_TRST"),
1167
+
MTK_FUNCTION(4, "SCP_JTAG0_TRSTN_VCORE"),
1168
+
MTK_FUNCTION(5, "CONN_WF_MCU_TRST_B"),
1169
+
MTK_FUNCTION(6, "SSPM_JTAG_TRSTN_VCORE"),
1170
+
MTK_FUNCTION(7, "IPU_JTAG_TRST")
1171
+
),
1172
+
1173
+
MTK_PIN(
1174
+
108, "GPIO108",
1175
+
MTK_EINT_FUNCTION(0, 108),
1176
+
DRV_GRP4,
1177
+
MTK_FUNCTION(0, "GPIO108"),
1178
+
MTK_FUNCTION(1, "I2SOUT0_BCK"),
1179
+
MTK_FUNCTION(2, "SPIM4_B_CLK"),
1180
+
MTK_FUNCTION(3, "EXTIF0_ACT"),
1181
+
MTK_FUNCTION(4, "SPM_JTAG_TMS_VCORE"),
1182
+
MTK_FUNCTION(6, "CLKM2"),
1183
+
MTK_FUNCTION(7, "DBG_MON_A20")
1184
+
),
1185
+
1186
+
MTK_PIN(
1187
+
109, "GPIO109",
1188
+
MTK_EINT_FUNCTION(0, 109),
1189
+
DRV_GRP4,
1190
+
MTK_FUNCTION(0, "GPIO109"),
1191
+
MTK_FUNCTION(1, "I2SOUT0_LRCK"),
1192
+
MTK_FUNCTION(2, "SPIM4_B_MO"),
1193
+
MTK_FUNCTION(3, "EXTIF0_PRI"),
1194
+
MTK_FUNCTION(4, "SPM_JTAG_TCK_VCORE"),
1195
+
MTK_FUNCTION(6, "CLKM3"),
1196
+
MTK_FUNCTION(7, "DBG_MON_A21")
1197
+
),
1198
+
1199
+
MTK_PIN(
1200
+
110, "GPIO110",
1201
+
MTK_EINT_FUNCTION(0, 110),
1202
+
DRV_GRP4,
1203
+
MTK_FUNCTION(0, "GPIO110"),
1204
+
MTK_FUNCTION(1, "I2SOUT0_DO"),
1205
+
MTK_FUNCTION(2, "SPIM4_B_MI"),
1206
+
MTK_FUNCTION(3, "EXTIF0_GNT_B"),
1207
+
MTK_FUNCTION(4, "SPM_JTAG_TDI_VCORE"),
1208
+
MTK_FUNCTION(7, "DBG_MON_A22")
1209
+
),
1210
+
1211
+
MTK_PIN(
1212
+
111, "GPIO111",
1213
+
MTK_EINT_FUNCTION(0, 111),
1214
+
DRV_GRP4,
1215
+
MTK_FUNCTION(0, "GPIO111"),
1216
+
MTK_FUNCTION(1, "DMIC0_CLK"),
1217
+
MTK_FUNCTION(2, "I2SIN1_MCK"),
1218
+
MTK_FUNCTION(3, "I2SOUT1_MCK"),
1219
+
MTK_FUNCTION(4, "SPM_JTAG_TDO_VCORE"),
1220
+
MTK_FUNCTION(6, "CONN_MIPI0_SDATA"),
1221
+
MTK_FUNCTION(7, "DBG_MON_A23")
1222
+
),
1223
+
1224
+
MTK_PIN(
1225
+
112, "GPIO112",
1226
+
MTK_EINT_FUNCTION(0, 112),
1227
+
DRV_GRP4,
1228
+
MTK_FUNCTION(0, "GPIO112"),
1229
+
MTK_FUNCTION(1, "DMIC0_DAT0"),
1230
+
MTK_FUNCTION(2, "I2SIN1_BCK"),
1231
+
MTK_FUNCTION(3, "I2SOUT1_BCK"),
1232
+
MTK_FUNCTION(4, "SPM_JTAG_TRSTN_VCORE"),
1233
+
MTK_FUNCTION(6, "CONN_MIPI0_SCLK"),
1234
+
MTK_FUNCTION(7, "DBG_MON_A24")
1235
+
),
1236
+
1237
+
MTK_PIN(
1238
+
113, "GPIO113",
1239
+
MTK_EINT_FUNCTION(0, 113),
1240
+
DRV_GRP4,
1241
+
MTK_FUNCTION(0, "GPIO113"),
1242
+
MTK_FUNCTION(1, "DMIC1_CLK"),
1243
+
MTK_FUNCTION(2, "I2SIN1_LRCK"),
1244
+
MTK_FUNCTION(3, "I2SOUT1_LRCK"),
1245
+
MTK_FUNCTION(4, "PMSR_SMAP"),
1246
+
MTK_FUNCTION(6, "CONN_MIPI1_SDATA"),
1247
+
MTK_FUNCTION(7, "DBG_MON_A25")
1248
+
),
1249
+
1250
+
MTK_PIN(
1251
+
114, "GPIO114",
1252
+
MTK_EINT_FUNCTION(0, 114),
1253
+
DRV_GRP4,
1254
+
MTK_FUNCTION(0, "GPIO114"),
1255
+
MTK_FUNCTION(1, "DMIC1_DAT0"),
1256
+
MTK_FUNCTION(2, "I2SIN1_DI"),
1257
+
MTK_FUNCTION(3, "I2SOUT1_DO"),
1258
+
MTK_FUNCTION(6, "CONN_MIPI1_SCLK"),
1259
+
MTK_FUNCTION(7, "DBG_MON_A26")
1260
+
),
1261
+
1262
+
MTK_PIN(
1263
+
115, "GPIO115",
1264
+
MTK_EINT_FUNCTION(0, 115),
1265
+
DRV_GRP4,
1266
+
MTK_FUNCTION(0, "GPIO115"),
1267
+
MTK_FUNCTION(1, "PCM0_CLK"),
1268
+
MTK_FUNCTION(2, "USB_DRVVBUS_1P"),
1269
+
MTK_FUNCTION(3, "PCIE_PHY_I2C_SCL"),
1270
+
MTK_FUNCTION(4, "SSUSB_U3PHY_I2C_SCL"),
1271
+
MTK_FUNCTION(6, "CMFLASH0"),
1272
+
MTK_FUNCTION(7, "EXTIF0_ACT")
1273
+
),
1274
+
1275
+
MTK_PIN(
1276
+
116, "GPIO116",
1277
+
MTK_EINT_FUNCTION(0, 116),
1278
+
DRV_GRP4,
1279
+
MTK_FUNCTION(0, "GPIO116"),
1280
+
MTK_FUNCTION(1, "PCM0_SYNC"),
1281
+
MTK_FUNCTION(2, "USB_DRVVBUS_2P"),
1282
+
MTK_FUNCTION(3, "PCIE_PHY_I2C_SDA"),
1283
+
MTK_FUNCTION(4, "SSUSB_U3PHY_I2C_SDA"),
1284
+
MTK_FUNCTION(6, "CMFLASH1"),
1285
+
MTK_FUNCTION(7, "EXTIF0_PRI")
1286
+
),
1287
+
1288
+
MTK_PIN(
1289
+
117, "GPIO117",
1290
+
MTK_EINT_FUNCTION(0, 117),
1291
+
DRV_GRP4,
1292
+
MTK_FUNCTION(0, "GPIO117"),
1293
+
MTK_FUNCTION(1, "PCM0_DI"),
1294
+
MTK_FUNCTION(2, "USB_DRVVBUS_3P"),
1295
+
MTK_FUNCTION(3, "DP_TX_HPD"),
1296
+
MTK_FUNCTION(4, "SSPXTP_U3PHY_I2C_SCL"),
1297
+
MTK_FUNCTION(6, "CMVREF0"),
1298
+
MTK_FUNCTION(7, "EXTIF0_GNT_B")
1299
+
),
1300
+
1301
+
MTK_PIN(
1302
+
118, "GPIO118",
1303
+
MTK_EINT_FUNCTION(0, 118),
1304
+
DRV_GRP4,
1305
+
MTK_FUNCTION(0, "GPIO118"),
1306
+
MTK_FUNCTION(1, "PCM0_DO"),
1307
+
MTK_FUNCTION(2, "USB_DRVVBUS_4P"),
1308
+
MTK_FUNCTION(3, "EDP_TX_HPD"),
1309
+
MTK_FUNCTION(4, "SSPXTP_U3PHY_I2C_SDA"),
1310
+
MTK_FUNCTION(6, "CMVREF1")
1311
+
),
1312
+
1313
+
MTK_PIN(
1314
+
119, "GPIO119",
1315
+
MTK_EINT_FUNCTION(0, 119),
1316
+
DRV_GRP4,
1317
+
MTK_FUNCTION(0, "GPIO119"),
1318
+
MTK_FUNCTION(1, "GBE_TXD3"),
1319
+
MTK_FUNCTION(2, "DMIC0_CLK"),
1320
+
MTK_FUNCTION(3, "LVTS_FOUT"),
1321
+
MTK_FUNCTION(4, "CONN_BGF_MCU_TMS"),
1322
+
MTK_FUNCTION(5, "UDI_TMS"),
1323
+
MTK_FUNCTION(6, "ANT_SEL5"),
1324
+
MTK_FUNCTION(7, "DBG_MON_B0")
1325
+
),
1326
+
1327
+
MTK_PIN(
1328
+
120, "GPIO120",
1329
+
MTK_EINT_FUNCTION(0, 120),
1330
+
DRV_GRP4,
1331
+
MTK_FUNCTION(0, "GPIO120"),
1332
+
MTK_FUNCTION(1, "GBE_TXD2"),
1333
+
MTK_FUNCTION(2, "DMIC0_DAT0"),
1334
+
MTK_FUNCTION(3, "LVTS_SDO"),
1335
+
MTK_FUNCTION(4, "CONN_BGF_MCU_TCK"),
1336
+
MTK_FUNCTION(5, "UDI_TCK"),
1337
+
MTK_FUNCTION(6, "ANT_SEL6"),
1338
+
MTK_FUNCTION(7, "DBG_MON_B1")
1339
+
),
1340
+
1341
+
MTK_PIN(
1342
+
121, "GPIO121",
1343
+
MTK_EINT_FUNCTION(0, 121),
1344
+
DRV_GRP4,
1345
+
MTK_FUNCTION(0, "GPIO121"),
1346
+
MTK_FUNCTION(1, "GBE_TXD1"),
1347
+
MTK_FUNCTION(2, "DMIC0_DAT1"),
1348
+
MTK_FUNCTION(3, "LVTS_26M"),
1349
+
MTK_FUNCTION(4, "CONN_BGF_MCU_TDI"),
1350
+
MTK_FUNCTION(5, "UDI_TDI"),
1351
+
MTK_FUNCTION(6, "ANT_SEL7"),
1352
+
MTK_FUNCTION(7, "DBG_MON_B2")
1353
+
),
1354
+
1355
+
MTK_PIN(
1356
+
122, "GPIO122",
1357
+
MTK_EINT_FUNCTION(0, 122),
1358
+
DRV_GRP4,
1359
+
MTK_FUNCTION(0, "GPIO122"),
1360
+
MTK_FUNCTION(1, "GBE_TXD0"),
1361
+
MTK_FUNCTION(2, "DMIC1_CLK"),
1362
+
MTK_FUNCTION(3, "LVTS_SCF"),
1363
+
MTK_FUNCTION(4, "CONN_BGF_MCU_TDO"),
1364
+
MTK_FUNCTION(5, "UDI_TDO"),
1365
+
MTK_FUNCTION(6, "ANT_SEL8"),
1366
+
MTK_FUNCTION(7, "DBG_MON_B3")
1367
+
),
1368
+
1369
+
MTK_PIN(
1370
+
123, "GPIO123",
1371
+
MTK_EINT_FUNCTION(0, 123),
1372
+
DRV_GRP4,
1373
+
MTK_FUNCTION(0, "GPIO123"),
1374
+
MTK_FUNCTION(1, "GBE_RXD3"),
1375
+
MTK_FUNCTION(2, "DMIC1_DAT0"),
1376
+
MTK_FUNCTION(3, "LVTS_SCK"),
1377
+
MTK_FUNCTION(4, "CONN_BGF_MCU_TRST_B"),
1378
+
MTK_FUNCTION(5, "UDI_NTRST"),
1379
+
MTK_FUNCTION(6, "ANT_SEL9"),
1380
+
MTK_FUNCTION(7, "DBG_MON_B4")
1381
+
),
1382
+
1383
+
MTK_PIN(
1384
+
124, "GPIO124",
1385
+
MTK_EINT_FUNCTION(0, 124),
1386
+
DRV_GRP4,
1387
+
MTK_FUNCTION(0, "GPIO124"),
1388
+
MTK_FUNCTION(1, "GBE_RXD2"),
1389
+
MTK_FUNCTION(2, "DMIC1_DAT1"),
1390
+
MTK_FUNCTION(3, "LVTS_SDI"),
1391
+
MTK_FUNCTION(4, "CONN_WF_MCU_TMS"),
1392
+
MTK_FUNCTION(5, "SCP_JTAG0_TMS_VCORE"),
1393
+
MTK_FUNCTION(6, "ANT_SEL10"),
1394
+
MTK_FUNCTION(7, "DBG_MON_B5")
1395
+
),
1396
+
1397
+
MTK_PIN(
1398
+
125, "GPIO125",
1399
+
MTK_EINT_FUNCTION(0, 125),
1400
+
DRV_GRP4,
1401
+
MTK_FUNCTION(0, "GPIO125"),
1402
+
MTK_FUNCTION(1, "GBE_RXD1"),
1403
+
MTK_FUNCTION(2, "CLKM2"),
1404
+
MTK_FUNCTION(4, "CONN_WF_MCU_TCK"),
1405
+
MTK_FUNCTION(5, "SCP_JTAG0_TCK_VCORE"),
1406
+
MTK_FUNCTION(6, "ANT_SEL11"),
1407
+
MTK_FUNCTION(7, "DBG_MON_B6")
1408
+
),
1409
+
1410
+
MTK_PIN(
1411
+
126, "GPIO126",
1412
+
MTK_EINT_FUNCTION(0, 126),
1413
+
DRV_GRP4,
1414
+
MTK_FUNCTION(0, "GPIO126"),
1415
+
MTK_FUNCTION(1, "GBE_RXD0"),
1416
+
MTK_FUNCTION(2, "CLKM3"),
1417
+
MTK_FUNCTION(4, "CONN_WF_MCU_TDI"),
1418
+
MTK_FUNCTION(5, "SCP_JTAG0_TDI_VCORE"),
1419
+
MTK_FUNCTION(6, "ANT_SEL12"),
1420
+
MTK_FUNCTION(7, "DBG_MON_B7")
1421
+
),
1422
+
1423
+
MTK_PIN(
1424
+
127, "GPIO127",
1425
+
MTK_EINT_FUNCTION(0, 127),
1426
+
DRV_GRP4,
1427
+
MTK_FUNCTION(0, "GPIO127"),
1428
+
MTK_FUNCTION(1, "GBE_TXC"),
1429
+
MTK_FUNCTION(2, "I2SIN1_MCK"),
1430
+
MTK_FUNCTION(4, "CONN_WF_MCU_TDO"),
1431
+
MTK_FUNCTION(5, "SCP_JTAG0_TDO_VCORE"),
1432
+
MTK_FUNCTION(6, "ANT_SEL13"),
1433
+
MTK_FUNCTION(7, "DBG_MON_B8")
1434
+
),
1435
+
1436
+
MTK_PIN(
1437
+
128, "GPIO128",
1438
+
MTK_EINT_FUNCTION(0, 128),
1439
+
DRV_GRP4,
1440
+
MTK_FUNCTION(0, "GPIO128"),
1441
+
MTK_FUNCTION(1, "GBE_RXC"),
1442
+
MTK_FUNCTION(2, "I2SIN1_BCK"),
1443
+
MTK_FUNCTION(4, "CONN_WF_MCU_TRST_B"),
1444
+
MTK_FUNCTION(5, "SCP_JTAG0_TRSTN_VCORE"),
1445
+
MTK_FUNCTION(6, "ANT_SEL14"),
1446
+
MTK_FUNCTION(7, "DBG_MON_B9")
1447
+
),
1448
+
1449
+
MTK_PIN(
1450
+
129, "GPIO129",
1451
+
MTK_EINT_FUNCTION(0, 129),
1452
+
DRV_GRP4,
1453
+
MTK_FUNCTION(0, "GPIO129"),
1454
+
MTK_FUNCTION(1, "GBE_RXDV"),
1455
+
MTK_FUNCTION(2, "I2SIN1_LRCK"),
1456
+
MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"),
1457
+
MTK_FUNCTION(5, "IPU_JTAG_TMS"),
1458
+
MTK_FUNCTION(6, "ANT_SEL15"),
1459
+
MTK_FUNCTION(7, "DBG_MON_B10")
1460
+
),
1461
+
1462
+
MTK_PIN(
1463
+
130, "GPIO130",
1464
+
MTK_EINT_FUNCTION(0, 130),
1465
+
DRV_GRP4,
1466
+
MTK_FUNCTION(0, "GPIO130"),
1467
+
MTK_FUNCTION(1, "GBE_TXEN"),
1468
+
MTK_FUNCTION(2, "I2SIN1_DI"),
1469
+
MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"),
1470
+
MTK_FUNCTION(5, "IPU_JTAG_TCK"),
1471
+
MTK_FUNCTION(6, "ANT_SEL16"),
1472
+
MTK_FUNCTION(7, "DBG_MON_B11")
1473
+
),
1474
+
1475
+
MTK_PIN(
1476
+
131, "GPIO131",
1477
+
MTK_EINT_FUNCTION(0, 131),
1478
+
DRV_GRP4,
1479
+
MTK_FUNCTION(0, "GPIO131"),
1480
+
MTK_FUNCTION(1, "GBE_MDC"),
1481
+
MTK_FUNCTION(2, "CLKM0"),
1482
+
MTK_FUNCTION(3, "mbistreaden_trigger"),
1483
+
MTK_FUNCTION(4, "CONN_BGF_UART0_TXD"),
1484
+
MTK_FUNCTION(5, "IPU_JTAG_TDI"),
1485
+
MTK_FUNCTION(6, "ANT_SEL17"),
1486
+
MTK_FUNCTION(7, "DBG_MON_B12")
1487
+
),
1488
+
1489
+
MTK_PIN(
1490
+
132, "GPIO132",
1491
+
MTK_EINT_FUNCTION(0, 132),
1492
+
DRV_GRP4,
1493
+
MTK_FUNCTION(0, "GPIO132"),
1494
+
MTK_FUNCTION(1, "GBE_MDIO"),
1495
+
MTK_FUNCTION(2, "CLKM1"),
1496
+
MTK_FUNCTION(3, "mbistwriteen_trigger"),
1497
+
MTK_FUNCTION(4, "CONN_BGF_UART0_RXD"),
1498
+
MTK_FUNCTION(5, "IPU_JTAG_TDO"),
1499
+
MTK_FUNCTION(6, "ANT_SEL18"),
1500
+
MTK_FUNCTION(7, "DBG_MON_B13")
1501
+
),
1502
+
1503
+
MTK_PIN(
1504
+
133, "GPIO133",
1505
+
MTK_EINT_FUNCTION(0, 133),
1506
+
DRV_GRP4,
1507
+
MTK_FUNCTION(0, "GPIO133"),
1508
+
MTK_FUNCTION(1, "GBE_TXER"),
1509
+
MTK_FUNCTION(2, "GBE_AUX_PPS2"),
1510
+
MTK_FUNCTION(4, "CONN_BT_TXD"),
1511
+
MTK_FUNCTION(5, "IPU_JTAG_TRST"),
1512
+
MTK_FUNCTION(6, "ANT_SEL19"),
1513
+
MTK_FUNCTION(7, "DBG_MON_B14")
1514
+
),
1515
+
1516
+
MTK_PIN(
1517
+
134, "GPIO134",
1518
+
MTK_EINT_FUNCTION(0, 134),
1519
+
DRV_GRP4,
1520
+
MTK_FUNCTION(0, "GPIO134"),
1521
+
MTK_FUNCTION(1, "GBE_RXER"),
1522
+
MTK_FUNCTION(2, "GBE_AUX_PPS3"),
1523
+
MTK_FUNCTION(3, "MCUPM_JTAG_TMS"),
1524
+
MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TMSC"),
1525
+
MTK_FUNCTION(5, "APU_JTAG_TMS"),
1526
+
MTK_FUNCTION(6, "ANT_SEL20"),
1527
+
MTK_FUNCTION(7, "DBG_MON_B15")
1528
+
),
1529
+
1530
+
MTK_PIN(
1531
+
135, "GPIO135",
1532
+
MTK_EINT_FUNCTION(0, 135),
1533
+
DRV_GRP4,
1534
+
MTK_FUNCTION(0, "GPIO135"),
1535
+
MTK_FUNCTION(1, "GBE_COL"),
1536
+
MTK_FUNCTION(2, "I2SOUT1_MCK"),
1537
+
MTK_FUNCTION(3, "MCUPM_JTAG_TCK"),
1538
+
MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TCKC"),
1539
+
MTK_FUNCTION(5, "APU_JTAG_TCK"),
1540
+
MTK_FUNCTION(6, "ANT_SEL21"),
1541
+
MTK_FUNCTION(7, "DBG_MON_B16")
1542
+
),
1543
+
1544
+
MTK_PIN(
1545
+
136, "GPIO136",
1546
+
MTK_EINT_FUNCTION(0, 136),
1547
+
DRV_GRP4,
1548
+
MTK_FUNCTION(0, "GPIO136"),
1549
+
MTK_FUNCTION(1, "GBE_INTR"),
1550
+
MTK_FUNCTION(2, "I2SOUT1_BCK"),
1551
+
MTK_FUNCTION(3, "MCUPM_JTAG_TDI"),
1552
+
MTK_FUNCTION(4, "CONN_WIFI_TXD"),
1553
+
MTK_FUNCTION(5, "APU_JTAG_TDI"),
1554
+
MTK_FUNCTION(6, "PWM_0"),
1555
+
MTK_FUNCTION(7, "DBG_MON_B17")
1556
+
),
1557
+
1558
+
MTK_PIN(
1559
+
137, "GPIO137",
1560
+
MTK_EINT_FUNCTION(0, 137),
1561
+
DRV_GRP4,
1562
+
MTK_FUNCTION(0, "GPIO137"),
1563
+
MTK_FUNCTION(1, "GBE_AUX_PPS0"),
1564
+
MTK_FUNCTION(2, "I2SOUT1_LRCK"),
1565
+
MTK_FUNCTION(3, "MCUPM_JTAG_TDO"),
1566
+
MTK_FUNCTION(4, "DP_TX_HPD"),
1567
+
MTK_FUNCTION(5, "APU_JTAG_TDO"),
1568
+
MTK_FUNCTION(6, "PWM_1"),
1569
+
MTK_FUNCTION(7, "DBG_MON_B18")
1570
+
),
1571
+
1572
+
MTK_PIN(
1573
+
138, "GPIO138",
1574
+
MTK_EINT_FUNCTION(0, 138),
1575
+
DRV_GRP4,
1576
+
MTK_FUNCTION(0, "GPIO138"),
1577
+
MTK_FUNCTION(1, "GBE_AUX_PPS1"),
1578
+
MTK_FUNCTION(2, "I2SOUT1_DO"),
1579
+
MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"),
1580
+
MTK_FUNCTION(4, "EDP_TX_HPD"),
1581
+
MTK_FUNCTION(5, "APU_JTAG_TRST"),
1582
+
MTK_FUNCTION(6, "PWM_2"),
1583
+
MTK_FUNCTION(7, "DBG_MON_B19")
1584
+
),
1585
+
1586
+
MTK_PIN(
1587
+
139, "GPIO139",
1588
+
MTK_EINT_FUNCTION(0, 139),
1589
+
DRV_GRP4,
1590
+
MTK_FUNCTION(0, "GPIO139"),
1591
+
MTK_FUNCTION(1, "CONN_TOP_CLK")
1592
+
),
1593
+
1594
+
MTK_PIN(
1595
+
140, "GPIO140",
1596
+
MTK_EINT_FUNCTION(0, 140),
1597
+
DRV_GRP4,
1598
+
MTK_FUNCTION(0, "GPIO140"),
1599
+
MTK_FUNCTION(1, "CONN_TOP_DATA")
1600
+
),
1601
+
1602
+
MTK_PIN(
1603
+
141, "GPIO141",
1604
+
MTK_EINT_FUNCTION(0, 141),
1605
+
DRV_GRP4,
1606
+
MTK_FUNCTION(0, "GPIO141"),
1607
+
MTK_FUNCTION(1, "CONN_BT_CLK")
1608
+
),
1609
+
1610
+
MTK_PIN(
1611
+
142, "GPIO142",
1612
+
MTK_EINT_FUNCTION(0, 142),
1613
+
DRV_GRP4,
1614
+
MTK_FUNCTION(0, "GPIO142"),
1615
+
MTK_FUNCTION(1, "CONN_BT_DATA")
1616
+
),
1617
+
1618
+
MTK_PIN(
1619
+
143, "GPIO143",
1620
+
MTK_EINT_FUNCTION(0, 143),
1621
+
DRV_GRP4,
1622
+
MTK_FUNCTION(0, "GPIO143"),
1623
+
MTK_FUNCTION(1, "CONN_HRST_B")
1624
+
),
1625
+
1626
+
MTK_PIN(
1627
+
144, "GPIO144",
1628
+
MTK_EINT_FUNCTION(0, 144),
1629
+
DRV_GRP4,
1630
+
MTK_FUNCTION(0, "GPIO144"),
1631
+
MTK_FUNCTION(1, "CONN_WB_PTA")
1632
+
),
1633
+
1634
+
MTK_PIN(
1635
+
145, "GPIO145",
1636
+
MTK_EINT_FUNCTION(0, 145),
1637
+
DRV_GRP4,
1638
+
MTK_FUNCTION(0, "GPIO145"),
1639
+
MTK_FUNCTION(1, "CONN_WF_CTRL0")
1640
+
),
1641
+
1642
+
MTK_PIN(
1643
+
146, "GPIO146",
1644
+
MTK_EINT_FUNCTION(0, 146),
1645
+
DRV_GRP4,
1646
+
MTK_FUNCTION(0, "GPIO146"),
1647
+
MTK_FUNCTION(1, "CONN_WF_CTRL1")
1648
+
),
1649
+
1650
+
MTK_PIN(
1651
+
147, "GPIO147",
1652
+
MTK_EINT_FUNCTION(0, 147),
1653
+
DRV_GRP4,
1654
+
MTK_FUNCTION(0, "GPIO147"),
1655
+
MTK_FUNCTION(1, "CONN_WF_CTRL2")
1656
+
),
1657
+
1658
+
MTK_PIN(
1659
+
148, "GPIO148",
1660
+
MTK_EINT_FUNCTION(0, 148),
1661
+
DRV_GRP4,
1662
+
MTK_FUNCTION(0, "GPIO148"),
1663
+
MTK_FUNCTION(1, "CONN_WF_CTRL3")
1664
+
),
1665
+
1666
+
MTK_PIN(
1667
+
149, "GPIO149",
1668
+
MTK_EINT_FUNCTION(0, 149),
1669
+
DRV_GRP4,
1670
+
MTK_FUNCTION(0, "GPIO149"),
1671
+
MTK_FUNCTION(1, "CONN_WF_CTRL4")
1672
+
),
1673
+
1674
+
MTK_PIN(
1675
+
150, "GPIO150",
1676
+
MTK_EINT_FUNCTION(0, 150),
1677
+
DRV_GRP4,
1678
+
MTK_FUNCTION(0, "GPIO150"),
1679
+
MTK_FUNCTION(1, "SPINOR_CK"),
1680
+
MTK_FUNCTION(2, "DMIC0_CLK"),
1681
+
MTK_FUNCTION(3, "DP_TX_HPD"),
1682
+
MTK_FUNCTION(4, "PWM_0"),
1683
+
MTK_FUNCTION(5, "CONN_BPI_BUS17_ANT0"),
1684
+
MTK_FUNCTION(6, "LVTS_FOUT"),
1685
+
MTK_FUNCTION(7, "DBG_MON_B26")
1686
+
),
1687
+
1688
+
MTK_PIN(
1689
+
151, "GPIO151",
1690
+
MTK_EINT_FUNCTION(0, 151),
1691
+
DRV_GRP4,
1692
+
MTK_FUNCTION(0, "GPIO151"),
1693
+
MTK_FUNCTION(1, "SPINOR_CS"),
1694
+
MTK_FUNCTION(2, "DMIC0_DAT0"),
1695
+
MTK_FUNCTION(3, "EDP_TX_HPD"),
1696
+
MTK_FUNCTION(4, "PWM_1"),
1697
+
MTK_FUNCTION(5, "CONN_BPI_BUS18_ANT1"),
1698
+
MTK_FUNCTION(6, "LVTS_SDO"),
1699
+
MTK_FUNCTION(7, "DBG_MON_B27")
1700
+
),
1701
+
1702
+
MTK_PIN(
1703
+
152, "GPIO152",
1704
+
MTK_EINT_FUNCTION(0, 152),
1705
+
DRV_GRP4,
1706
+
MTK_FUNCTION(0, "GPIO152"),
1707
+
MTK_FUNCTION(1, "SPINOR_IO0"),
1708
+
MTK_FUNCTION(2, "DMIC0_DAT1"),
1709
+
MTK_FUNCTION(3, "UTXD2"),
1710
+
MTK_FUNCTION(4, "USB_DRVVBUS_1P"),
1711
+
MTK_FUNCTION(5, "CONN_BPI_BUS19_ANT2"),
1712
+
MTK_FUNCTION(6, "LVTS_26M"),
1713
+
MTK_FUNCTION(7, "DBG_MON_B28")
1714
+
),
1715
+
1716
+
MTK_PIN(
1717
+
153, "GPIO153",
1718
+
MTK_EINT_FUNCTION(0, 153),
1719
+
DRV_GRP4,
1720
+
MTK_FUNCTION(0, "GPIO153"),
1721
+
MTK_FUNCTION(1, "SPINOR_IO1"),
1722
+
MTK_FUNCTION(2, "DMIC1_CLK"),
1723
+
MTK_FUNCTION(3, "UCTS2"),
1724
+
MTK_FUNCTION(4, "USB_DRVVBUS_2P"),
1725
+
MTK_FUNCTION(5, "CONN_BPI_BUS20_ANT3"),
1726
+
MTK_FUNCTION(6, "LVTS_SCF"),
1727
+
MTK_FUNCTION(7, "DBG_MON_B29")
1728
+
),
1729
+
1730
+
MTK_PIN(
1731
+
154, "GPIO154",
1732
+
MTK_EINT_FUNCTION(0, 154),
1733
+
DRV_GRP4,
1734
+
MTK_FUNCTION(0, "GPIO154"),
1735
+
MTK_FUNCTION(1, "SPINOR_IO2"),
1736
+
MTK_FUNCTION(2, "DMIC1_DAT0"),
1737
+
MTK_FUNCTION(3, "URTS2"),
1738
+
MTK_FUNCTION(4, "USB_DRVVBUS_3P"),
1739
+
MTK_FUNCTION(5, "CONN_BPI_BUS21_ANT4"),
1740
+
MTK_FUNCTION(6, "LVTS_SCK"),
1741
+
MTK_FUNCTION(7, "DBG_MON_B30")
1742
+
),
1743
+
1744
+
MTK_PIN(
1745
+
155, "GPIO155",
1746
+
MTK_EINT_FUNCTION(0, 155),
1747
+
DRV_GRP4,
1748
+
MTK_FUNCTION(0, "GPIO155"),
1749
+
MTK_FUNCTION(1, "SPINOR_IO3"),
1750
+
MTK_FUNCTION(2, "DMIC1_DAT1"),
1751
+
MTK_FUNCTION(3, "URXD2"),
1752
+
MTK_FUNCTION(4, "USB_DRVVBUS_4P"),
1753
+
MTK_FUNCTION(5, "DISP_PWM1"),
1754
+
MTK_FUNCTION(6, "LVTS_SDI"),
1755
+
MTK_FUNCTION(7, "DBG_MON_B31")
1756
+
),
1757
+
1758
+
MTK_PIN(
1759
+
156, "GPIO156",
1760
+
MTK_EINT_FUNCTION(0, 156),
1761
+
DRV_GRP4,
1762
+
MTK_FUNCTION(0, "GPIO156"),
1763
+
MTK_FUNCTION(1, "MSDC0_DAT7")
1764
+
),
1765
+
1766
+
MTK_PIN(
1767
+
157, "GPIO157",
1768
+
MTK_EINT_FUNCTION(0, 157),
1769
+
DRV_GRP4,
1770
+
MTK_FUNCTION(0, "GPIO157"),
1771
+
MTK_FUNCTION(1, "MSDC0_DAT6")
1772
+
),
1773
+
1774
+
MTK_PIN(
1775
+
158, "GPIO158",
1776
+
MTK_EINT_FUNCTION(0, 158),
1777
+
DRV_GRP4,
1778
+
MTK_FUNCTION(0, "GPIO158"),
1779
+
MTK_FUNCTION(1, "MSDC0_DAT5")
1780
+
),
1781
+
1782
+
MTK_PIN(
1783
+
159, "GPIO159",
1784
+
MTK_EINT_FUNCTION(0, 159),
1785
+
DRV_GRP4,
1786
+
MTK_FUNCTION(0, "GPIO159"),
1787
+
MTK_FUNCTION(1, "MSDC0_DAT4")
1788
+
),
1789
+
1790
+
MTK_PIN(
1791
+
160, "GPIO160",
1792
+
MTK_EINT_FUNCTION(0, 160),
1793
+
DRV_GRP4,
1794
+
MTK_FUNCTION(0, "GPIO160"),
1795
+
MTK_FUNCTION(1, "MSDC0_RSTB")
1796
+
),
1797
+
1798
+
MTK_PIN(
1799
+
161, "GPIO161",
1800
+
MTK_EINT_FUNCTION(0, 161),
1801
+
DRV_GRP4,
1802
+
MTK_FUNCTION(0, "GPIO161"),
1803
+
MTK_FUNCTION(1, "MSDC0_CMD")
1804
+
),
1805
+
1806
+
MTK_PIN(
1807
+
162, "GPIO162",
1808
+
MTK_EINT_FUNCTION(0, 162),
1809
+
DRV_GRP4,
1810
+
MTK_FUNCTION(0, "GPIO162"),
1811
+
MTK_FUNCTION(1, "MSDC0_CLK")
1812
+
),
1813
+
1814
+
MTK_PIN(
1815
+
163, "GPIO163",
1816
+
MTK_EINT_FUNCTION(0, 163),
1817
+
DRV_GRP4,
1818
+
MTK_FUNCTION(0, "GPIO163"),
1819
+
MTK_FUNCTION(1, "MSDC0_DAT3")
1820
+
),
1821
+
1822
+
MTK_PIN(
1823
+
164, "GPIO164",
1824
+
MTK_EINT_FUNCTION(0, 164),
1825
+
DRV_GRP4,
1826
+
MTK_FUNCTION(0, "GPIO164"),
1827
+
MTK_FUNCTION(1, "MSDC0_DAT2")
1828
+
),
1829
+
1830
+
MTK_PIN(
1831
+
165, "GPIO165",
1832
+
MTK_EINT_FUNCTION(0, 165),
1833
+
DRV_GRP4,
1834
+
MTK_FUNCTION(0, "GPIO165"),
1835
+
MTK_FUNCTION(1, "MSDC0_DAT1")
1836
+
),
1837
+
1838
+
MTK_PIN(
1839
+
166, "GPIO166",
1840
+
MTK_EINT_FUNCTION(0, 166),
1841
+
DRV_GRP4,
1842
+
MTK_FUNCTION(0, "GPIO166"),
1843
+
MTK_FUNCTION(1, "MSDC0_DAT0")
1844
+
),
1845
+
1846
+
MTK_PIN(
1847
+
167, "GPIO167",
1848
+
MTK_EINT_FUNCTION(0, 167),
1849
+
DRV_GRP4,
1850
+
MTK_FUNCTION(0, "GPIO167"),
1851
+
MTK_FUNCTION(1, "MSDC0_DSL")
1852
+
),
1853
+
1854
+
MTK_PIN(
1855
+
168, "GPIO168",
1856
+
MTK_EINT_FUNCTION(0, 168),
1857
+
DRV_GRP4,
1858
+
MTK_FUNCTION(0, "GPIO168"),
1859
+
MTK_FUNCTION(1, "MSDC1_CMD"),
1860
+
MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TMSC"),
1861
+
MTK_FUNCTION(3, "UCTS1"),
1862
+
MTK_FUNCTION(4, "UDI_TMS"),
1863
+
MTK_FUNCTION(5, "SSPM_JTAG_TMS_VCORE"),
1864
+
MTK_FUNCTION(6, "MCUPM_JTAG_TMS"),
1865
+
MTK_FUNCTION(7, "CONN_BGF_MCU_TMS")
1866
+
),
1867
+
1868
+
MTK_PIN(
1869
+
169, "GPIO169",
1870
+
MTK_EINT_FUNCTION(0, 169),
1871
+
DRV_GRP4,
1872
+
MTK_FUNCTION(0, "GPIO169"),
1873
+
MTK_FUNCTION(1, "MSDC1_CLK"),
1874
+
MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TCKC"),
1875
+
MTK_FUNCTION(3, "URTS1"),
1876
+
MTK_FUNCTION(4, "UDI_TCK"),
1877
+
MTK_FUNCTION(5, "SSPM_JTAG_TCK_VCORE"),
1878
+
MTK_FUNCTION(6, "MCUPM_JTAG_TCK"),
1879
+
MTK_FUNCTION(7, "CONN_BGF_MCU_TCK")
1880
+
),
1881
+
1882
+
MTK_PIN(
1883
+
170, "GPIO170",
1884
+
MTK_EINT_FUNCTION(0, 170),
1885
+
DRV_GRP4,
1886
+
MTK_FUNCTION(0, "GPIO170"),
1887
+
MTK_FUNCTION(1, "MSDC1_DAT0"),
1888
+
MTK_FUNCTION(2, "SPIM5_B_CSB"),
1889
+
MTK_FUNCTION(3, "UCTS2"),
1890
+
MTK_FUNCTION(4, "UDI_TDI"),
1891
+
MTK_FUNCTION(5, "SSPM_JTAG_TDI_VCORE"),
1892
+
MTK_FUNCTION(6, "MCUPM_JTAG_TDI"),
1893
+
MTK_FUNCTION(7, "CONN_BGF_MCU_TDI")
1894
+
),
1895
+
1896
+
MTK_PIN(
1897
+
171, "GPIO171",
1898
+
MTK_EINT_FUNCTION(0, 171),
1899
+
DRV_GRP4,
1900
+
MTK_FUNCTION(0, "GPIO171"),
1901
+
MTK_FUNCTION(1, "MSDC1_DAT1"),
1902
+
MTK_FUNCTION(2, "SPIM5_B_CLK"),
1903
+
MTK_FUNCTION(3, "URTS2"),
1904
+
MTK_FUNCTION(4, "UDI_TDO"),
1905
+
MTK_FUNCTION(5, "SSPM_JTAG_TDO_VCORE"),
1906
+
MTK_FUNCTION(6, "MCUPM_JTAG_TDO"),
1907
+
MTK_FUNCTION(7, "CONN_BGF_MCU_TDO")
1908
+
),
1909
+
1910
+
MTK_PIN(
1911
+
172, "GPIO172",
1912
+
MTK_EINT_FUNCTION(0, 172),
1913
+
DRV_GRP4,
1914
+
MTK_FUNCTION(0, "GPIO172"),
1915
+
MTK_FUNCTION(1, "MSDC1_DAT2"),
1916
+
MTK_FUNCTION(2, "SPIM5_B_MO"),
1917
+
MTK_FUNCTION(3, "UCTS3"),
1918
+
MTK_FUNCTION(4, "UDI_NTRST"),
1919
+
MTK_FUNCTION(5, "SSPM_JTAG_TRSTN_VCORE"),
1920
+
MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN"),
1921
+
MTK_FUNCTION(7, "CONN_BGF_MCU_TRST_B")
1922
+
),
1923
+
1924
+
MTK_PIN(
1925
+
173, "GPIO173",
1926
+
MTK_EINT_FUNCTION(0, 173),
1927
+
DRV_GRP4,
1928
+
MTK_FUNCTION(0, "GPIO173"),
1929
+
MTK_FUNCTION(1, "MSDC1_DAT3"),
1930
+
MTK_FUNCTION(2, "SPIM5_B_MI"),
1931
+
MTK_FUNCTION(3, "URTS3"),
1932
+
MTK_FUNCTION(4, "CLKM0"),
1933
+
MTK_FUNCTION(5, "PWM_2")
1934
+
),
1935
+
1936
+
MTK_PIN(
1937
+
174, "GPIO174",
1938
+
MTK_EINT_FUNCTION(0, 174),
1939
+
DRV_GRP4,
1940
+
MTK_FUNCTION(0, "GPIO174"),
1941
+
MTK_FUNCTION(1, "MSDC2_CMD"),
1942
+
MTK_FUNCTION(2, "CONN_BGF_MCU_AICE_TMSC"),
1943
+
MTK_FUNCTION(3, "UTXD1"),
1944
+
MTK_FUNCTION(4, "VADSP_JTAG0_TMS"),
1945
+
MTK_FUNCTION(5, "SSPM_JTAG_TMS_VLP"),
1946
+
MTK_FUNCTION(6, "SPM_JTAG_TMS"),
1947
+
MTK_FUNCTION(7, "SCP_JTAG0_TMS_VLP")
1948
+
),
1949
+
1950
+
MTK_PIN(
1951
+
175, "GPIO175",
1952
+
MTK_EINT_FUNCTION(0, 175),
1953
+
DRV_GRP4,
1954
+
MTK_FUNCTION(0, "GPIO175"),
1955
+
MTK_FUNCTION(1, "MSDC2_CLK"),
1956
+
MTK_FUNCTION(2, "CONN_BGF_MCU_AICE_TCKC"),
1957
+
MTK_FUNCTION(3, "URXD1"),
1958
+
MTK_FUNCTION(4, "VADSP_JTAG0_TCK"),
1959
+
MTK_FUNCTION(5, "SSPM_JTAG_TCK_VLP"),
1960
+
MTK_FUNCTION(6, "SPM_JTAG_TCK"),
1961
+
MTK_FUNCTION(7, "SCP_JTAG0_TCK_VLP")
1962
+
),
1963
+
1964
+
MTK_PIN(
1965
+
176, "GPIO176",
1966
+
MTK_EINT_FUNCTION(0, 176),
1967
+
DRV_GRP4,
1968
+
MTK_FUNCTION(0, "GPIO176"),
1969
+
MTK_FUNCTION(1, "MSDC2_DAT0"),
1970
+
MTK_FUNCTION(2, "SRCLKENAI0"),
1971
+
MTK_FUNCTION(3, "UTXD2"),
1972
+
MTK_FUNCTION(4, "VADSP_JTAG0_TDI"),
1973
+
MTK_FUNCTION(5, "SSPM_JTAG_TDI_VLP"),
1974
+
MTK_FUNCTION(6, "SPM_JTAG_TDI"),
1975
+
MTK_FUNCTION(7, "SCP_JTAG0_TDI_VLP")
1976
+
),
1977
+
1978
+
MTK_PIN(
1979
+
177, "GPIO177",
1980
+
MTK_EINT_FUNCTION(0, 177),
1981
+
DRV_GRP4,
1982
+
MTK_FUNCTION(0, "GPIO177"),
1983
+
MTK_FUNCTION(1, "MSDC2_DAT1"),
1984
+
MTK_FUNCTION(2, "SRCLKENAI1"),
1985
+
MTK_FUNCTION(3, "URXD2"),
1986
+
MTK_FUNCTION(4, "VADSP_JTAG0_TDO"),
1987
+
MTK_FUNCTION(5, "SSPM_JTAG_TDO_VLP"),
1988
+
MTK_FUNCTION(6, "SPM_JTAG_TDO"),
1989
+
MTK_FUNCTION(7, "SCP_JTAG0_TDO_VLP")
1990
+
),
1991
+
1992
+
MTK_PIN(
1993
+
178, "GPIO178",
1994
+
MTK_EINT_FUNCTION(0, 178),
1995
+
DRV_GRP4,
1996
+
MTK_FUNCTION(0, "GPIO178"),
1997
+
MTK_FUNCTION(1, "MSDC2_DAT2"),
1998
+
MTK_FUNCTION(3, "UTXD3"),
1999
+
MTK_FUNCTION(4, "VADSP_JTAG0_TRSTN"),
2000
+
MTK_FUNCTION(5, "SSPM_JTAG_TRSTN_VLP"),
2001
+
MTK_FUNCTION(6, "SPM_JTAG_TRSTN"),
2002
+
MTK_FUNCTION(7, "SCP_JTAG0_TRSTN_VLP")
2003
+
),
2004
+
2005
+
MTK_PIN(
2006
+
179, "GPIO179",
2007
+
MTK_EINT_FUNCTION(0, 179),
2008
+
DRV_GRP4,
2009
+
MTK_FUNCTION(0, "GPIO179"),
2010
+
MTK_FUNCTION(1, "MSDC2_DAT3"),
2011
+
MTK_FUNCTION(3, "URXD3"),
2012
+
MTK_FUNCTION(4, "CLKM1"),
2013
+
MTK_FUNCTION(5, "PWM_vlp"),
2014
+
MTK_FUNCTION(7, "TP_GPIO7_AO")
2015
+
),
2016
+
2017
+
MTK_PIN(
2018
+
180, "GPIO180",
2019
+
MTK_EINT_FUNCTION(0, 180),
2020
+
DRV_GRP4,
2021
+
MTK_FUNCTION(0, "GPIO180"),
2022
+
MTK_FUNCTION(1, "SPMI_P_SCL")
2023
+
),
2024
+
2025
+
MTK_PIN(
2026
+
181, "GPIO181",
2027
+
MTK_EINT_FUNCTION(0, 181),
2028
+
DRV_GRP4,
2029
+
MTK_FUNCTION(0, "GPIO181"),
2030
+
MTK_FUNCTION(1, "SPMI_P_SDA")
2031
+
),
2032
+
2033
+
MTK_PIN(
2034
+
182, "GPIO182",
2035
+
MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
2036
+
DRV_GRP4,
2037
+
MTK_FUNCTION(0, "GPIO182"),
2038
+
MTK_FUNCTION(1, "DDR_PAD_RRESETB")
2039
+
),
2040
+
2041
+
MTK_PIN(
2042
+
183, "GPIO183",
2043
+
MTK_EINT_FUNCTION(0, 182),
2044
+
DRV_FIXED,
2045
+
MTK_FUNCTION(0, NULL)
2046
+
),
2047
+
2048
+
MTK_PIN(
2049
+
184, "GPIO184",
2050
+
MTK_EINT_FUNCTION(0, 183),
2051
+
DRV_FIXED,
2052
+
MTK_FUNCTION(0, NULL)
2053
+
),
2054
+
2055
+
MTK_PIN(
2056
+
185, "GPIO185",
2057
+
MTK_EINT_FUNCTION(0, 184),
2058
+
DRV_FIXED,
2059
+
MTK_FUNCTION(0, NULL)
2060
+
),
2061
+
2062
+
MTK_PIN(
2063
+
186, "GPIO186",
2064
+
MTK_EINT_FUNCTION(0, 185),
2065
+
DRV_FIXED,
2066
+
MTK_FUNCTION(0, NULL)
2067
+
),
2068
+
2069
+
MTK_PIN(
2070
+
187, "GPIO187",
2071
+
MTK_EINT_FUNCTION(0, 186),
2072
+
DRV_FIXED,
2073
+
MTK_FUNCTION(0, NULL)
2074
+
),
2075
+
2076
+
MTK_PIN(
2077
+
188, "GPIO188",
2078
+
MTK_EINT_FUNCTION(0, 187),
2079
+
DRV_FIXED,
2080
+
MTK_FUNCTION(0, NULL)
2081
+
),
2082
+
2083
+
MTK_PIN(
2084
+
189, "GPIO189",
2085
+
MTK_EINT_FUNCTION(0, 188),
2086
+
DRV_FIXED,
2087
+
MTK_FUNCTION(0, NULL)
2088
+
),
2089
+
2090
+
MTK_PIN(
2091
+
190, "GPIO190",
2092
+
MTK_EINT_FUNCTION(0, 189),
2093
+
DRV_FIXED,
2094
+
MTK_FUNCTION(0, NULL)
2095
+
),
2096
+
2097
+
MTK_PIN(
2098
+
191, "GPIO191",
2099
+
MTK_EINT_FUNCTION(0, 190),
2100
+
DRV_FIXED,
2101
+
MTK_FUNCTION(0, NULL)
2102
+
),
2103
+
2104
+
MTK_PIN(
2105
+
192, "GPIO192",
2106
+
MTK_EINT_FUNCTION(0, 191),
2107
+
DRV_FIXED,
2108
+
MTK_FUNCTION(0, NULL)
2109
+
),
2110
+
2111
+
MTK_PIN(
2112
+
193, "GPIO193",
2113
+
MTK_EINT_FUNCTION(0, 192),
2114
+
DRV_FIXED,
2115
+
MTK_FUNCTION(0, NULL)
2116
+
),
2117
+
2118
+
MTK_PIN(
2119
+
194, "GPIO194",
2120
+
MTK_EINT_FUNCTION(0, 193),
2121
+
DRV_FIXED,
2122
+
MTK_FUNCTION(0, NULL)
2123
+
),
2124
+
2125
+
MTK_PIN(
2126
+
195, "GPIO195",
2127
+
MTK_EINT_FUNCTION(0, 194),
2128
+
DRV_FIXED,
2129
+
MTK_FUNCTION(0, NULL)
2130
+
),
2131
+
2132
+
MTK_PIN(
2133
+
196, "GPIO196",
2134
+
MTK_EINT_FUNCTION(0, 195),
2135
+
DRV_FIXED,
2136
+
MTK_FUNCTION(0, NULL)
2137
+
),
2138
+
2139
+
MTK_PIN(
2140
+
197, "GPIO197",
2141
+
MTK_EINT_FUNCTION(0, 196),
2142
+
DRV_FIXED,
2143
+
MTK_FUNCTION(0, NULL)
2144
+
),
2145
+
2146
+
MTK_PIN(
2147
+
198, "GPIO198",
2148
+
MTK_EINT_FUNCTION(0, 197),
2149
+
DRV_FIXED,
2150
+
MTK_FUNCTION(0, NULL)
2151
+
),
2152
+
2153
+
MTK_PIN(
2154
+
199, "GPIO199",
2155
+
MTK_EINT_FUNCTION(0, 198),
2156
+
DRV_FIXED,
2157
+
MTK_FUNCTION(0, NULL)
2158
+
),
2159
+
2160
+
MTK_PIN(
2161
+
200, "GPIO200",
2162
+
MTK_EINT_FUNCTION(0, 199),
2163
+
DRV_FIXED,
2164
+
MTK_FUNCTION(0, NULL)
2165
+
),
2166
+
2167
+
MTK_PIN(
2168
+
201, "GPIO201",
2169
+
MTK_EINT_FUNCTION(0, 200),
2170
+
DRV_FIXED,
2171
+
MTK_FUNCTION(0, NULL)
2172
+
),
2173
+
2174
+
MTK_PIN(
2175
+
202, "GPIO202",
2176
+
MTK_EINT_FUNCTION(0, 201),
2177
+
DRV_FIXED,
2178
+
MTK_FUNCTION(0, NULL)
2179
+
),
2180
+
2181
+
MTK_PIN(
2182
+
203, "GPIO203",
2183
+
MTK_EINT_FUNCTION(0, 202),
2184
+
DRV_FIXED,
2185
+
MTK_FUNCTION(0, NULL)
2186
+
),
2187
+
2188
+
MTK_PIN(
2189
+
204, "GPIO204",
2190
+
MTK_EINT_FUNCTION(0, 203),
2191
+
DRV_FIXED,
2192
+
MTK_FUNCTION(0, NULL)
2193
+
),
2194
+
2195
+
MTK_PIN(
2196
+
205, "GPIO205",
2197
+
MTK_EINT_FUNCTION(0, 204),
2198
+
DRV_FIXED,
2199
+
MTK_FUNCTION(0, NULL)
2200
+
),
2201
+
2202
+
MTK_PIN(
2203
+
206, "GPIO206",
2204
+
MTK_EINT_FUNCTION(0, 205),
2205
+
DRV_FIXED,
2206
+
MTK_FUNCTION(0, NULL)
2207
+
),
2208
+
2209
+
MTK_PIN(
2210
+
207, "GPIO207",
2211
+
MTK_EINT_FUNCTION(0, 206),
2212
+
DRV_FIXED,
2213
+
MTK_FUNCTION(0, NULL)
2214
+
),
2215
+
2216
+
MTK_PIN(
2217
+
208, "GPIO208",
2218
+
MTK_EINT_FUNCTION(0, 207),
2219
+
DRV_FIXED,
2220
+
MTK_FUNCTION(0, NULL)
2221
+
),
2222
+
2223
+
MTK_PIN(
2224
+
209, "GPIO209",
2225
+
MTK_EINT_FUNCTION(0, 208),
2226
+
DRV_FIXED,
2227
+
MTK_FUNCTION(0, NULL)
2228
+
),
2229
+
2230
+
MTK_PIN(
2231
+
210, "GPIO210",
2232
+
MTK_EINT_FUNCTION(0, 209),
2233
+
DRV_FIXED,
2234
+
MTK_FUNCTION(0, NULL)
2235
+
),
2236
+
2237
+
};
2238
+
2239
+
static struct mtk_eint_pin eint_pins_mt8189[] = {
2240
+
MTK_EINT_PIN(0, 0, 0, 1),
2241
+
MTK_EINT_PIN(1, 0, 1, 1),
2242
+
MTK_EINT_PIN(2, 0, 2, 1),
2243
+
MTK_EINT_PIN(3, 0, 3, 1),
2244
+
MTK_EINT_PIN(4, 0, 4, 1),
2245
+
MTK_EINT_PIN(5, 0, 5, 1),
2246
+
MTK_EINT_PIN(6, 0, 6, 1),
2247
+
MTK_EINT_PIN(7, 0, 7, 1),
2248
+
MTK_EINT_PIN(8, 0, 8, 1),
2249
+
MTK_EINT_PIN(9, 0, 9, 1),
2250
+
MTK_EINT_PIN(10, 0, 10, 1),
2251
+
MTK_EINT_PIN(11, 0, 11, 1),
2252
+
MTK_EINT_PIN(12, 1, 0, 1),
2253
+
MTK_EINT_PIN(13, 1, 1, 1),
2254
+
MTK_EINT_PIN(14, 1, 2, 1),
2255
+
MTK_EINT_PIN(15, 1, 3, 1),
2256
+
MTK_EINT_PIN(16, 1, 4, 1),
2257
+
MTK_EINT_PIN(17, 1, 5, 1),
2258
+
MTK_EINT_PIN(18, 0, 12, 1),
2259
+
MTK_EINT_PIN(19, 0, 13, 1),
2260
+
MTK_EINT_PIN(20, 0, 14, 1),
2261
+
MTK_EINT_PIN(21, 0, 15, 1),
2262
+
MTK_EINT_PIN(22, 0, 16, 1),
2263
+
MTK_EINT_PIN(23, 0, 17, 1),
2264
+
MTK_EINT_PIN(24, 0, 18, 1),
2265
+
MTK_EINT_PIN(25, 2, 0, 1),
2266
+
MTK_EINT_PIN(26, 2, 1, 1),
2267
+
MTK_EINT_PIN(27, 1, 6, 1),
2268
+
MTK_EINT_PIN(28, 1, 7, 1),
2269
+
MTK_EINT_PIN(29, 2, 2, 1),
2270
+
MTK_EINT_PIN(30, 1, 8, 1),
2271
+
MTK_EINT_PIN(31, 1, 9, 1),
2272
+
MTK_EINT_PIN(32, 1, 10, 1),
2273
+
MTK_EINT_PIN(33, 1, 11, 1),
2274
+
MTK_EINT_PIN(34, 1, 12, 1),
2275
+
MTK_EINT_PIN(35, 1, 13, 1),
2276
+
MTK_EINT_PIN(36, 1, 14, 1),
2277
+
MTK_EINT_PIN(37, 1, 15, 1),
2278
+
MTK_EINT_PIN(38, 1, 16, 1),
2279
+
MTK_EINT_PIN(39, 1, 17, 1),
2280
+
MTK_EINT_PIN(40, 1, 18, 1),
2281
+
MTK_EINT_PIN(41, 1, 19, 1),
2282
+
MTK_EINT_PIN(42, 1, 20, 1),
2283
+
MTK_EINT_PIN(43, 1, 21, 1),
2284
+
MTK_EINT_PIN(44, 0, 19, 1),
2285
+
MTK_EINT_PIN(45, 0, 20, 1),
2286
+
MTK_EINT_PIN(46, 0, 21, 1),
2287
+
MTK_EINT_PIN(47, 0, 22, 1),
2288
+
MTK_EINT_PIN(48, 2, 3, 1),
2289
+
MTK_EINT_PIN(49, 2, 4, 1),
2290
+
MTK_EINT_PIN(50, 2, 5, 1),
2291
+
MTK_EINT_PIN(51, 0, 23, 1),
2292
+
MTK_EINT_PIN(52, 0, 24, 1),
2293
+
MTK_EINT_PIN(53, 0, 25, 1),
2294
+
MTK_EINT_PIN(54, 0, 26, 1),
2295
+
MTK_EINT_PIN(55, 2, 6, 1),
2296
+
MTK_EINT_PIN(56, 2, 7, 1),
2297
+
MTK_EINT_PIN(57, 1, 22, 1),
2298
+
MTK_EINT_PIN(58, 1, 23, 1),
2299
+
MTK_EINT_PIN(59, 1, 24, 1),
2300
+
MTK_EINT_PIN(60, 1, 25, 1),
2301
+
MTK_EINT_PIN(61, 1, 26, 1),
2302
+
MTK_EINT_PIN(62, 1, 27, 1),
2303
+
MTK_EINT_PIN(63, 1, 28, 1),
2304
+
MTK_EINT_PIN(64, 1, 29, 1),
2305
+
MTK_EINT_PIN(65, 0, 27, 1),
2306
+
MTK_EINT_PIN(66, 0, 28, 1),
2307
+
MTK_EINT_PIN(67, 0, 29, 1),
2308
+
MTK_EINT_PIN(68, 0, 30, 1),
2309
+
MTK_EINT_PIN(69, 1, 30, 1),
2310
+
MTK_EINT_PIN(70, 1, 31, 1),
2311
+
MTK_EINT_PIN(71, 1, 32, 1),
2312
+
MTK_EINT_PIN(72, 1, 33, 1),
2313
+
MTK_EINT_PIN(73, 1, 34, 1),
2314
+
MTK_EINT_PIN(74, 1, 35, 1),
2315
+
MTK_EINT_PIN(75, 1, 36, 1),
2316
+
MTK_EINT_PIN(76, 1, 37, 1),
2317
+
MTK_EINT_PIN(77, 0, 31, 1),
2318
+
MTK_EINT_PIN(78, 0, 32, 1),
2319
+
MTK_EINT_PIN(79, 0, 33, 1),
2320
+
MTK_EINT_PIN(80, 0, 34, 1),
2321
+
MTK_EINT_PIN(81, 1, 38, 1),
2322
+
MTK_EINT_PIN(82, 1, 39, 1),
2323
+
MTK_EINT_PIN(83, 1, 40, 1),
2324
+
MTK_EINT_PIN(84, 0, 35, 1),
2325
+
MTK_EINT_PIN(85, 0, 36, 1),
2326
+
MTK_EINT_PIN(86, 0, 37, 1),
2327
+
MTK_EINT_PIN(87, 0, 38, 1),
2328
+
MTK_EINT_PIN(88, 2, 8, 1),
2329
+
MTK_EINT_PIN(89, 2, 9, 1),
2330
+
MTK_EINT_PIN(90, 2, 10, 1),
2331
+
MTK_EINT_PIN(91, 2, 11, 1),
2332
+
MTK_EINT_PIN(92, 2, 12, 1),
2333
+
MTK_EINT_PIN(93, 2, 13, 1),
2334
+
MTK_EINT_PIN(94, 2, 14, 1),
2335
+
MTK_EINT_PIN(95, 2, 15, 1),
2336
+
MTK_EINT_PIN(96, 2, 16, 1),
2337
+
MTK_EINT_PIN(97, 2, 17, 1),
2338
+
MTK_EINT_PIN(98, 2, 18, 1),
2339
+
MTK_EINT_PIN(99, 2, 19, 1),
2340
+
MTK_EINT_PIN(100, 2, 20, 1),
2341
+
MTK_EINT_PIN(101, 2, 21, 1),
2342
+
MTK_EINT_PIN(102, 2, 22, 1),
2343
+
MTK_EINT_PIN(103, 0, 39, 1),
2344
+
MTK_EINT_PIN(104, 0, 40, 1),
2345
+
MTK_EINT_PIN(105, 0, 41, 1),
2346
+
MTK_EINT_PIN(106, 0, 42, 1),
2347
+
MTK_EINT_PIN(107, 0, 43, 1),
2348
+
MTK_EINT_PIN(108, 0, 44, 1),
2349
+
MTK_EINT_PIN(109, 0, 45, 1),
2350
+
MTK_EINT_PIN(110, 0, 46, 1),
2351
+
MTK_EINT_PIN(111, 0, 47, 1),
2352
+
MTK_EINT_PIN(112, 0, 48, 0),
2353
+
MTK_EINT_PIN(113, 0, 49, 1),
2354
+
MTK_EINT_PIN(114, 0, 50, 0),
2355
+
MTK_EINT_PIN(115, 1, 41, 1),
2356
+
MTK_EINT_PIN(116, 1, 42, 1),
2357
+
MTK_EINT_PIN(117, 1, 43, 1),
2358
+
MTK_EINT_PIN(118, 1, 44, 1),
2359
+
MTK_EINT_PIN(119, 1, 45, 1),
2360
+
MTK_EINT_PIN(120, 1, 46, 1),
2361
+
MTK_EINT_PIN(121, 1, 47, 1),
2362
+
MTK_EINT_PIN(122, 1, 48, 1),
2363
+
MTK_EINT_PIN(123, 1, 49, 1),
2364
+
MTK_EINT_PIN(124, 1, 50, 1),
2365
+
MTK_EINT_PIN(125, 1, 51, 1),
2366
+
MTK_EINT_PIN(126, 1, 52, 1),
2367
+
MTK_EINT_PIN(127, 1, 53, 1),
2368
+
MTK_EINT_PIN(128, 1, 54, 1),
2369
+
MTK_EINT_PIN(129, 1, 55, 1),
2370
+
MTK_EINT_PIN(130, 1, 56, 1),
2371
+
MTK_EINT_PIN(131, 1, 57, 1),
2372
+
MTK_EINT_PIN(132, 1, 58, 1),
2373
+
MTK_EINT_PIN(133, 1, 59, 1),
2374
+
MTK_EINT_PIN(134, 1, 60, 1),
2375
+
MTK_EINT_PIN(135, 1, 61, 1),
2376
+
MTK_EINT_PIN(136, 1, 62, 1),
2377
+
MTK_EINT_PIN(137, 1, 63, 1),
2378
+
MTK_EINT_PIN(138, 1, 64, 1),
2379
+
MTK_EINT_PIN(139, 1, 65, 1),
2380
+
MTK_EINT_PIN(140, 1, 66, 1),
2381
+
MTK_EINT_PIN(141, 1, 67, 1),
2382
+
MTK_EINT_PIN(142, 1, 68, 1),
2383
+
MTK_EINT_PIN(143, 1, 69, 1),
2384
+
MTK_EINT_PIN(144, 1, 70, 1),
2385
+
MTK_EINT_PIN(145, 1, 71, 1),
2386
+
MTK_EINT_PIN(146, 1, 72, 1),
2387
+
MTK_EINT_PIN(147, 1, 73, 1),
2388
+
MTK_EINT_PIN(148, 1, 74, 1),
2389
+
MTK_EINT_PIN(149, 1, 75, 1),
2390
+
MTK_EINT_PIN(150, 1, 76, 1),
2391
+
MTK_EINT_PIN(151, 1, 77, 1),
2392
+
MTK_EINT_PIN(152, 1, 78, 1),
2393
+
MTK_EINT_PIN(153, 1, 79, 1),
2394
+
MTK_EINT_PIN(154, 1, 80, 1),
2395
+
MTK_EINT_PIN(155, 1, 81, 1),
2396
+
MTK_EINT_PIN(156, 2, 23, 1),
2397
+
MTK_EINT_PIN(157, 2, 24, 1),
2398
+
MTK_EINT_PIN(158, 2, 25, 1),
2399
+
MTK_EINT_PIN(159, 4, 0, 1),
2400
+
MTK_EINT_PIN(160, 2, 26, 1),
2401
+
MTK_EINT_PIN(161, 2, 27, 1),
2402
+
MTK_EINT_PIN(162, 2, 28, 1),
2403
+
MTK_EINT_PIN(163, 4, 1, 1),
2404
+
MTK_EINT_PIN(164, 2, 29, 1),
2405
+
MTK_EINT_PIN(165, 2, 30, 1),
2406
+
MTK_EINT_PIN(166, 4, 2, 1),
2407
+
MTK_EINT_PIN(167, 2, 31, 0),
2408
+
MTK_EINT_PIN(168, 1, 82, 1),
2409
+
MTK_EINT_PIN(169, 1, 83, 1),
2410
+
MTK_EINT_PIN(170, 1, 84, 1),
2411
+
MTK_EINT_PIN(171, 1, 85, 0),
2412
+
MTK_EINT_PIN(172, 1, 86, 1),
2413
+
MTK_EINT_PIN(173, 1, 87, 0),
2414
+
MTK_EINT_PIN(174, 4, 3, 1),
2415
+
MTK_EINT_PIN(175, 4, 4, 1),
2416
+
MTK_EINT_PIN(176, 4, 5, 1),
2417
+
MTK_EINT_PIN(177, 4, 6, 1),
2418
+
MTK_EINT_PIN(178, 4, 7, 1),
2419
+
MTK_EINT_PIN(179, 4, 8, 1),
2420
+
MTK_EINT_PIN(180, 2, 32, 1),
2421
+
MTK_EINT_PIN(181, 2, 33, 0),
2422
+
MTK_EINT_PIN(182, 3, 0, 1),
2423
+
MTK_EINT_PIN(183, 3, 1, 1),
2424
+
MTK_EINT_PIN(184, 3, 2, 1),
2425
+
MTK_EINT_PIN(185, 3, 3, 1),
2426
+
MTK_EINT_PIN(186, 3, 4, 1),
2427
+
MTK_EINT_PIN(187, 3, 5, 1),
2428
+
MTK_EINT_PIN(188, 3, 6, 1),
2429
+
MTK_EINT_PIN(189, 3, 7, 1),
2430
+
MTK_EINT_PIN(190, 3, 8, 1),
2431
+
MTK_EINT_PIN(191, 3, 9, 1),
2432
+
MTK_EINT_PIN(192, 3, 10, 1),
2433
+
MTK_EINT_PIN(193, 3, 11, 1),
2434
+
MTK_EINT_PIN(194, 3, 12, 1),
2435
+
MTK_EINT_PIN(195, 3, 13, 1),
2436
+
MTK_EINT_PIN(196, 3, 14, 1),
2437
+
MTK_EINT_PIN(197, 3, 15, 1),
2438
+
MTK_EINT_PIN(198, 3, 16, 1),
2439
+
MTK_EINT_PIN(199, 3, 17, 1),
2440
+
MTK_EINT_PIN(200, 3, 18, 1),
2441
+
MTK_EINT_PIN(201, 3, 19, 1),
2442
+
MTK_EINT_PIN(202, 3, 20, 1),
2443
+
MTK_EINT_PIN(203, 3, 21, 1),
2444
+
MTK_EINT_PIN(204, 3, 22, 1),
2445
+
MTK_EINT_PIN(205, 3, 23, 1),
2446
+
MTK_EINT_PIN(206, 3, 24, 1),
2447
+
MTK_EINT_PIN(207, 3, 25, 1),
2448
+
MTK_EINT_PIN(208, 3, 26, 1),
2449
+
MTK_EINT_PIN(209, 3, 27, 1)
2450
+
};
2451
+
2452
+
#endif /* __PINCTRL_MTK_MT8189_H */
+94
-24
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
+94
-24
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
···
50
50
u32 bit_offset[AML_NUM_REG];
51
51
};
52
52
53
-
struct aml_reg_bit {
54
-
u32 bank_id;
55
-
u32 reg_offs[AML_NUM_REG];
56
-
u32 bit_offs[AML_NUM_REG];
53
+
/*
54
+
* partial bank(subordinate) pins mux config use other bank(main) mux registgers
55
+
* m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0
56
+
* m_bit_offs: bit offset the main bank mux register
57
+
* sid: start pin_id of subordinate bank
58
+
* eid: end pin_id of subordinate bank
59
+
*/
60
+
struct multi_mux {
61
+
unsigned int m_bank_id;
62
+
unsigned int m_bit_offs;
63
+
unsigned int sid;
64
+
unsigned int eid;
57
65
};
58
66
59
67
struct aml_pctl_data {
60
68
unsigned int number;
61
-
struct aml_reg_bit rb_offs[];
69
+
const struct multi_mux *p_mux;
62
70
};
63
71
64
72
struct aml_pmx_func {
···
86
78
struct gpio_chip gpio_chip;
87
79
struct aml_pio_control pc;
88
80
u32 bank_id;
81
+
u32 mux_bit_offs;
89
82
unsigned int pin_base;
90
83
struct regmap *reg_mux;
91
84
struct regmap *reg_gpio;
92
85
struct regmap *reg_ds;
86
+
const struct multi_mux *p_mux;
93
87
};
94
88
95
89
struct aml_pinctrl {
···
123
113
"GPIOCC", "TEST_N", "ANALOG"
124
114
};
125
115
116
+
static const struct multi_mux multi_mux_s7[] = {
117
+
{
118
+
.m_bank_id = AMLOGIC_GPIO_CC,
119
+
.m_bit_offs = 24,
120
+
.sid = (AMLOGIC_GPIO_X << 8) + 16,
121
+
.eid = (AMLOGIC_GPIO_X << 8) + 19,
122
+
},
123
+
};
124
+
125
+
static const struct aml_pctl_data s7_priv_data = {
126
+
.number = ARRAY_SIZE(multi_mux_s7),
127
+
.p_mux = multi_mux_s7,
128
+
};
129
+
130
+
static const struct multi_mux multi_mux_s6[] = {
131
+
{
132
+
.m_bank_id = AMLOGIC_GPIO_CC,
133
+
.m_bit_offs = 24,
134
+
.sid = (AMLOGIC_GPIO_X << 8) + 16,
135
+
.eid = (AMLOGIC_GPIO_X << 8) + 19,
136
+
}, {
137
+
.m_bank_id = AMLOGIC_GPIO_F,
138
+
.m_bit_offs = 4,
139
+
.sid = (AMLOGIC_GPIO_D << 8) + 6,
140
+
.eid = (AMLOGIC_GPIO_D << 8) + 6,
141
+
},
142
+
};
143
+
144
+
static const struct aml_pctl_data s6_priv_data = {
145
+
.number = ARRAY_SIZE(multi_mux_s6),
146
+
.p_mux = multi_mux_s6,
147
+
};
148
+
126
149
static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range,
127
150
unsigned int pin, unsigned int *reg,
128
151
unsigned int *offset)
129
152
{
130
153
unsigned int shift;
131
154
132
-
shift = (pin - range->pin_base) << 2;
155
+
shift = ((pin - range->pin_base) << 2) + *offset;
133
156
*reg = (shift / 32) * 4;
134
157
*offset = shift % 32;
135
158
···
174
131
int pin_id, int func)
175
132
{
176
133
struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
134
+
unsigned int shift;
177
135
int reg;
178
-
int offset;
136
+
int i;
137
+
unsigned int offset = bank->mux_bit_offs;
138
+
const struct multi_mux *p_mux;
179
139
140
+
/* peculiar mux reg set */
141
+
if (bank->p_mux) {
142
+
p_mux = bank->p_mux;
143
+
if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) {
144
+
bank = NULL;
145
+
for (i = 0; i < info->nbanks; i++) {
146
+
if (info->banks[i].bank_id == p_mux->m_bank_id) {
147
+
bank = &info->banks[i];
148
+
break;
149
+
}
150
+
}
151
+
152
+
if (!bank || !bank->reg_mux)
153
+
return -EINVAL;
154
+
155
+
shift = (pin_id - p_mux->sid) << 2;
156
+
reg = (shift / 32) * 4;
157
+
offset = shift % 32;
158
+
return regmap_update_bits(bank->reg_mux, reg,
159
+
0xf << offset, (func & 0xf) << offset);
160
+
}
161
+
}
162
+
163
+
/* normal mux reg set */
180
164
if (!bank->reg_mux)
181
165
return 0;
182
166
···
900
830
struct aml_gpio_bank *bank)
901
831
{
902
832
const struct aml_pctl_data *data = info->data;
903
-
const struct aml_reg_bit *aml_rb;
904
-
bool def_offs = true;
833
+
const struct multi_mux *p_mux;
905
834
int i;
835
+
836
+
for (i = 0; i < AML_NUM_REG; i++) {
837
+
bank->pc.reg_offset[i] = aml_def_regoffs[i];
838
+
bank->pc.bit_offset[i] = 0;
839
+
}
840
+
841
+
bank->mux_bit_offs = 0;
906
842
907
843
if (data) {
908
844
for (i = 0; i < data->number; i++) {
909
-
aml_rb = &data->rb_offs[i];
910
-
if (bank->bank_id == aml_rb->bank_id) {
911
-
def_offs = false;
845
+
p_mux = &data->p_mux[i];
846
+
if (bank->bank_id == p_mux->m_bank_id) {
847
+
bank->mux_bit_offs = p_mux->m_bit_offs;
912
848
break;
913
849
}
914
-
}
915
-
}
916
-
917
-
if (def_offs) {
918
-
for (i = 0; i < AML_NUM_REG; i++) {
919
-
bank->pc.reg_offset[i] = aml_def_regoffs[i];
920
-
bank->pc.bit_offset[i] = 0;
921
-
}
922
-
} else {
923
-
for (i = 0; i < AML_NUM_REG; i++) {
924
-
bank->pc.reg_offset[i] = aml_rb->reg_offs[i];
925
-
bank->pc.bit_offset[i] = aml_rb->bit_offs[i];
850
+
if (p_mux->sid >> 8 == bank->bank_id) {
851
+
bank->p_mux = p_mux;
852
+
break;
853
+
}
926
854
}
927
855
}
928
856
}
···
1089
1021
1090
1022
static const struct of_device_id aml_pctl_of_match[] = {
1091
1023
{ .compatible = "amlogic,pinctrl-a4", },
1024
+
{ .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, },
1025
+
{ .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, },
1092
1026
{ /* sentinel */ }
1093
1027
};
1094
1028
MODULE_DEVICE_TABLE(of, aml_pctl_dt_match);
+19
-3
drivers/pinctrl/meson/pinctrl-meson-g12a.c
+19
-3
drivers/pinctrl/meson/pinctrl-meson-g12a.c
···
270
270
/* pwm_b */
271
271
static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 };
272
272
static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 };
273
+
static const unsigned int pwm_b_z0_pins[] = { GPIOZ_0 };
274
+
static const unsigned int pwm_b_z13_pins[] = { GPIOZ_13 };
275
+
static const unsigned int pwm_b_h_pins[] = { GPIOH_7 };
273
276
274
277
/* pwm_c */
275
278
static const unsigned int pwm_c_c_pins[] = { GPIOC_4 };
276
279
static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 };
277
280
static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 };
281
+
static const unsigned int pwm_c_z_pins[] = { GPIOZ_1 };
278
282
279
283
/* pwm_d */
280
284
static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 };
281
285
static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 };
286
+
static const unsigned int pwm_d_z_pins[] = { GPIOZ_2 };
287
+
static const unsigned int pwm_d_a_pins[] = { GPIOA_4 };
282
288
283
289
/* pwm_e */
284
290
static const unsigned int pwm_e_pins[] = { GPIOX_16 };
···
655
649
GROUP(pwm_a, 1),
656
650
GROUP(pwm_b_x7, 4),
657
651
GROUP(pwm_b_x19, 1),
652
+
GROUP(pwm_b_z0, 5),
653
+
GROUP(pwm_b_z13, 5),
654
+
GROUP(pwm_b_h, 5),
658
655
GROUP(pwm_c_x5, 4),
659
656
GROUP(pwm_c_x8, 5),
657
+
GROUP(pwm_c_c, 5),
658
+
GROUP(pwm_c_z, 5),
659
+
GROUP(pwm_d_z, 4),
660
+
GROUP(pwm_d_a, 3),
660
661
GROUP(pwm_d_x3, 4),
661
662
GROUP(pwm_d_x6, 4),
662
663
GROUP(pwm_e, 1),
664
+
GROUP(pwm_f_a, 3),
665
+
GROUP(pwm_f_h, 4),
663
666
GROUP(pwm_f_x, 1),
667
+
GROUP(pwm_f_z, 5),
664
668
GROUP(tsin_a_valid, 3),
665
669
GROUP(tsin_a_sop, 3),
666
670
GROUP(tsin_a_din0, 3),
···
1074
1058
};
1075
1059
1076
1060
static const char * const pwm_b_groups[] = {
1077
-
"pwm_b_x7", "pwm_b_x19",
1061
+
"pwm_b_h", "pwm_b_x7", "pwm_b_x19", "pwm_b_z0", "pwm_b_z13"
1078
1062
};
1079
1063
1080
1064
static const char * const pwm_c_groups[] = {
1081
-
"pwm_c_c", "pwm_c_x5", "pwm_c_x8",
1065
+
"pwm_c_c", "pwm_c_x5", "pwm_c_x8", "pwm_c_z",
1082
1066
};
1083
1067
1084
1068
static const char * const pwm_d_groups[] = {
1085
-
"pwm_d_x3", "pwm_d_x6",
1069
+
"pwm_d_a", "pwm_d_x3", "pwm_d_x6", "pwm_d_z",
1086
1070
};
1087
1071
1088
1072
static const char * const pwm_e_groups[] = {
+4
-2
drivers/pinctrl/nuvoton/pinctrl-ma35.c
+4
-2
drivers/pinctrl/nuvoton/pinctrl-ma35.c
···
361
361
return !!(readl(reg_pin) & BIT(gpio));
362
362
}
363
363
364
-
static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
364
+
static int ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
365
365
{
366
366
struct ma35_pin_bank *bank = gpiochip_get_data(gc);
367
367
void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
···
373
373
regval = readl(reg_dout) & ~BIT(gpio);
374
374
375
375
writel(regval, reg_dout);
376
+
377
+
return 0;
376
378
}
377
379
378
380
static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
···
526
524
bank->chip.direction_input = ma35_gpio_core_direction_in;
527
525
bank->chip.direction_output = ma35_gpio_core_direction_out;
528
526
bank->chip.get = ma35_gpio_core_get;
529
-
bank->chip.set = ma35_gpio_core_set;
527
+
bank->chip.set_rv = ma35_gpio_core_set;
530
528
bank->chip.base = -1;
531
529
bank->chip.ngpio = bank->nr_pins;
532
530
bank->chip.can_sleep = false;
+1
-1
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+4
-4
drivers/pinctrl/pinctrl-amd.c
+4
-4
drivers/pinctrl/pinctrl-amd.c
···
872
872
873
873
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
874
874
{
875
-
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
875
+
const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
876
876
unsigned long flags;
877
877
u32 pin_reg, mask;
878
878
int i;
···
901
901
static void amd_gpio_check_pending(void)
902
902
{
903
903
struct amd_gpio *gpio_dev = pinctrl_dev;
904
-
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
904
+
const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
905
905
int i;
906
906
907
907
if (!pm_debug_messages_on)
···
957
957
static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend)
958
958
{
959
959
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
960
-
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
960
+
const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
961
961
unsigned long flags;
962
962
int i;
963
963
u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE;
···
1012
1012
static int amd_gpio_resume(struct device *dev)
1013
1013
{
1014
1014
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
1015
-
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
1015
+
const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
1016
1016
unsigned long flags;
1017
1017
int i;
1018
1018
+4
-2
drivers/pinctrl/pinctrl-amdisp.c
+4
-2
drivers/pinctrl/pinctrl-amdisp.c
···
117
117
return !!(pin_reg & BIT(GPIO_CONTROL_PIN));
118
118
}
119
119
120
-
static void amdisp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
120
+
static int amdisp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
121
121
{
122
122
unsigned long flags;
123
123
u32 pin_reg;
···
131
131
pin_reg &= ~BIT(GPIO_CONTROL_PIN);
132
132
writel(pin_reg, pctrl->gpiobase + gpio_offset[gpio]);
133
133
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
134
+
135
+
return 0;
134
136
}
135
137
136
138
static int amdisp_gpiochip_add(struct platform_device *pdev,
···
151
149
gc->direction_input = amdisp_gpio_direction_input;
152
150
gc->direction_output = amdisp_gpio_direction_output;
153
151
gc->get = amdisp_gpio_get;
154
-
gc->set = amdisp_gpio_set;
152
+
gc->set_rv = amdisp_gpio_set;
155
153
gc->base = -1;
156
154
gc->ngpio = ARRAY_SIZE(amdisp_range_pins);
157
155
+4
-2
drivers/pinctrl/pinctrl-apple-gpio.c
+4
-2
drivers/pinctrl/pinctrl-apple-gpio.c
···
217
217
return !!(reg & REG_GPIOx_DATA);
218
218
}
219
219
220
-
static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
220
+
static int apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
221
221
{
222
222
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
223
223
224
224
apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
225
+
226
+
return 0;
225
227
}
226
228
227
229
static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
···
378
376
pctl->gpio_chip.direction_input = apple_gpio_direction_input;
379
377
pctl->gpio_chip.direction_output = apple_gpio_direction_output;
380
378
pctl->gpio_chip.get = apple_gpio_get;
381
-
pctl->gpio_chip.set = apple_gpio_set;
379
+
pctl->gpio_chip.set_rv = apple_gpio_set;
382
380
pctl->gpio_chip.base = -1;
383
381
pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
384
382
pctl->gpio_chip.parent = pctl->dev;
+1
-1
drivers/pinctrl/pinctrl-artpec6.c
+1
-1
drivers/pinctrl/pinctrl-artpec6.c
+15
-8
drivers/pinctrl/pinctrl-as3722.c
+15
-8
drivers/pinctrl/pinctrl-as3722.c
···
422
422
.pmxops = &as3722_pinmux_ops,
423
423
.confops = &as3722_pinconf_ops,
424
424
.owner = THIS_MODULE,
425
+
.pins = as3722_pins_desc,
426
+
.npins = ARRAY_SIZE(as3722_pins_desc),
425
427
};
426
428
427
429
static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
···
473
471
return (invert_enable) ? !val : val;
474
472
}
475
473
476
-
static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
477
-
int value)
474
+
static int as3722_gpio_set(struct gpio_chip *chip, unsigned int offset,
475
+
int value)
478
476
{
479
477
struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
480
478
struct as3722 *as3722 = as_pci->as3722;
···
486
484
if (ret < 0) {
487
485
dev_err(as_pci->dev,
488
486
"GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
489
-
return;
487
+
return ret;
490
488
}
491
489
en_invert = !!(val & AS3722_GPIO_INV);
492
490
···
500
498
if (ret < 0)
501
499
dev_err(as_pci->dev,
502
500
"GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
501
+
502
+
return ret;
503
503
}
504
504
505
505
static int as3722_gpio_direction_output(struct gpio_chip *chip,
506
-
unsigned offset, int value)
506
+
unsigned int offset, int value)
507
507
{
508
-
as3722_gpio_set(chip, offset, value);
508
+
int ret;
509
+
510
+
ret = as3722_gpio_set(chip, offset, value);
511
+
if (ret)
512
+
return ret;
513
+
509
514
return pinctrl_gpio_direction_output(chip, offset);
510
515
}
511
516
···
529
520
.request = gpiochip_generic_request,
530
521
.free = gpiochip_generic_free,
531
522
.get = as3722_gpio_get,
532
-
.set = as3722_gpio_set,
523
+
.set_rv = as3722_gpio_set,
533
524
.direction_input = pinctrl_gpio_direction_input,
534
525
.direction_output = as3722_gpio_direction_output,
535
526
.to_irq = as3722_gpio_to_irq,
···
559
550
as_pci->pin_groups = as3722_pingroups;
560
551
as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
561
552
as3722_pinctrl_desc.name = dev_name(&pdev->dev);
562
-
as3722_pinctrl_desc.pins = as3722_pins_desc;
563
-
as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
564
553
as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc,
565
554
as_pci);
566
555
if (IS_ERR(as_pci->pctl)) {
+3
-3
drivers/pinctrl/pinctrl-at91-pio4.c
+3
-3
drivers/pinctrl/pinctrl-at91-pio4.c
···
1212
1212
dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
1213
1213
}
1214
1214
1215
-
atmel_pioctrl->irq_domain = irq_domain_create_linear(of_fwnode_handle(dev->of_node),
1216
-
atmel_pioctrl->gpio_chip->ngpio,
1217
-
&irq_domain_simple_ops, NULL);
1215
+
atmel_pioctrl->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
1216
+
atmel_pioctrl->gpio_chip->ngpio,
1217
+
&irq_domain_simple_ops, NULL);
1218
1218
if (!atmel_pioctrl->irq_domain)
1219
1219
return dev_err_probe(dev, -ENODEV, "can't add the irq domain\n");
1220
1220
+16
-10
drivers/pinctrl/pinctrl-aw9523.c
+16
-10
drivers/pinctrl/pinctrl-aw9523.c
···
625
625
return ret;
626
626
}
627
627
628
-
static void aw9523_gpio_set_multiple(struct gpio_chip *chip,
628
+
static int aw9523_gpio_set_multiple(struct gpio_chip *chip,
629
629
unsigned long *mask,
630
630
unsigned long *bits)
631
631
{
632
632
struct aw9523 *awi = gpiochip_get_data(chip);
633
633
u8 mask_lo, mask_hi, bits_lo, bits_hi;
634
634
unsigned int reg;
635
-
int ret;
635
+
int ret = 0;
636
636
637
637
mask_lo = *mask;
638
638
mask_hi = *mask >> 8;
···
644
644
reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT);
645
645
ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);
646
646
if (ret)
647
-
dev_warn(awi->dev, "Cannot write port1 out level\n");
647
+
goto out;
648
648
}
649
649
if (mask_lo) {
650
650
reg = AW9523_REG_OUT_STATE(0);
651
651
ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo);
652
652
if (ret)
653
-
dev_warn(awi->dev, "Cannot write port0 out level\n");
653
+
goto out;
654
654
}
655
+
656
+
out:
655
657
mutex_unlock(&awi->i2c_lock);
658
+
return ret;
656
659
}
657
660
658
-
static void aw9523_gpio_set(struct gpio_chip *chip,
659
-
unsigned int offset, int value)
661
+
static int aw9523_gpio_set(struct gpio_chip *chip, unsigned int offset,
662
+
int value)
660
663
{
661
664
struct aw9523 *awi = gpiochip_get_data(chip);
662
665
u8 regbit = offset % AW9523_PINS_PER_PORT;
666
+
int ret;
663
667
664
668
mutex_lock(&awi->i2c_lock);
665
-
regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
666
-
BIT(regbit), value ? BIT(regbit) : 0);
669
+
ret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
670
+
BIT(regbit), value ? BIT(regbit) : 0);
667
671
mutex_unlock(&awi->i2c_lock);
672
+
673
+
return ret;
668
674
}
669
675
670
676
···
785
779
gc->direction_output = aw9523_direction_output;
786
780
gc->get = aw9523_gpio_get;
787
781
gc->get_multiple = aw9523_gpio_get_multiple;
788
-
gc->set = aw9523_gpio_set;
789
-
gc->set_multiple = aw9523_gpio_set_multiple;
782
+
gc->set_rv = aw9523_gpio_set;
783
+
gc->set_multiple_rv = aw9523_gpio_set_multiple;
790
784
gc->set_config = gpiochip_generic_config;
791
785
gc->parent = dev;
792
786
gc->owner = THIS_MODULE;
+1
-1
drivers/pinctrl/pinctrl-bm1880.c
+1
-1
drivers/pinctrl/pinctrl-bm1880.c
+6
-8
drivers/pinctrl/pinctrl-da9062.c
+6
-8
drivers/pinctrl/pinctrl-da9062.c
···
102
102
return !!(val & BIT(offset));
103
103
}
104
104
105
-
static void da9062_gpio_set(struct gpio_chip *gc, unsigned int offset,
106
-
int value)
105
+
static int da9062_gpio_set(struct gpio_chip *gc, unsigned int offset,
106
+
int value)
107
107
{
108
108
struct da9062_pctl *pctl = gpiochip_get_data(gc);
109
109
struct regmap *regmap = pctl->da9062->regmap;
110
110
111
-
regmap_update_bits(regmap, DA9062AA_GPIO_MODE0_4, BIT(offset),
112
-
value << offset);
111
+
return regmap_update_bits(regmap, DA9062AA_GPIO_MODE0_4, BIT(offset),
112
+
value << offset);
113
113
}
114
114
115
115
static int da9062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
···
172
172
if (ret)
173
173
return ret;
174
174
175
-
da9062_gpio_set(gc, offset, value);
176
-
177
-
return 0;
175
+
return da9062_gpio_set(gc, offset, value);
178
176
}
179
177
180
178
static int da9062_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
···
233
235
static const struct gpio_chip reference_gc = {
234
236
.owner = THIS_MODULE,
235
237
.get = da9062_gpio_get,
236
-
.set = da9062_gpio_set,
238
+
.set_rv = da9062_gpio_set,
237
239
.get_direction = da9062_gpio_get_direction,
238
240
.direction_input = da9062_gpio_direction_input,
239
241
.direction_output = da9062_gpio_direction_output,
+5
-3
drivers/pinctrl/pinctrl-digicolor.c
+5
-3
drivers/pinctrl/pinctrl-digicolor.c
···
182
182
return 0;
183
183
}
184
184
185
-
static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value);
185
+
static int dc_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value);
186
186
187
187
static int dc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
188
188
int value)
···
216
216
return !!(input & BIT(bit_off));
217
217
}
218
218
219
-
static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
219
+
static int dc_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
220
220
{
221
221
struct dc_pinmap *pmap = gpiochip_get_data(chip);
222
222
int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION);
···
232
232
output &= ~BIT(bit_off);
233
233
writeb_relaxed(output, pmap->regs + reg_off);
234
234
spin_unlock_irqrestore(&pmap->lock, flags);
235
+
236
+
return 0;
235
237
}
236
238
237
239
static int dc_gpiochip_add(struct dc_pinmap *pmap)
···
248
246
chip->direction_input = dc_gpio_direction_input;
249
247
chip->direction_output = dc_gpio_direction_output;
250
248
chip->get = dc_gpio_get;
251
-
chip->set = dc_gpio_set;
249
+
chip->set_rv = dc_gpio_set;
252
250
chip->base = -1;
253
251
chip->ngpio = PINS_COUNT;
254
252
+704
drivers/pinctrl/pinctrl-eic7700.c
+704
drivers/pinctrl/pinctrl-eic7700.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* ESWIN Pinctrl Controller Platform Device Driver
4
+
*
5
+
* Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
6
+
*
7
+
* Authors: Samuel Holland <samuel.holland@sifive.com>
8
+
* Yulin Lu <luyulin@eswincomputing.com>
9
+
*/
10
+
11
+
#include <linux/bitfield.h>
12
+
#include <linux/device.h>
13
+
#include <linux/io.h>
14
+
#include <linux/mod_devicetable.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/seq_file.h>
19
+
#include <linux/regulator/consumer.h>
20
+
21
+
#include <linux/pinctrl/pinconf.h>
22
+
#include <linux/pinctrl/pinconf-generic.h>
23
+
#include <linux/pinctrl/pinctrl.h>
24
+
#include <linux/pinctrl/pinmux.h>
25
+
26
+
#include "core.h"
27
+
#include "pinmux.h"
28
+
#include "pinconf.h"
29
+
30
+
#define EIC7700_PIN_REG(i) (4 * (i))
31
+
#define EIC7700_IE BIT(0)
32
+
#define EIC7700_PU BIT(1)
33
+
#define EIC7700_PD BIT(2)
34
+
#define EIC7700_DS GENMASK(6, 3)
35
+
#define EIC7700_ST BIT(7)
36
+
#define EIC7700_FUNC_SEL GENMASK(18, 16)
37
+
38
+
#define EIC7700_BIAS (EIC7700_PD | EIC7700_PU)
39
+
#define EIC7700_PINCONF GENMASK(7, 0)
40
+
41
+
#define EIC7700_RGMII0_SEL_MODE (0x310 - 0x80)
42
+
#define EIC7700_RGMII1_SEL_MODE (0x314 - 0x80)
43
+
#define EIC7700_MS GENMASK(1, 0)
44
+
#define EIC7700_MS_3V3 0x0
45
+
#define EIC7700_MS_1V8 0x3
46
+
47
+
#define EIC7700_FUNCTIONS_PER_PIN 8
48
+
49
+
struct eic7700_pin {
50
+
u8 functions[EIC7700_FUNCTIONS_PER_PIN];
51
+
};
52
+
53
+
struct eic7700_pinctrl {
54
+
void __iomem *base;
55
+
struct pinctrl_desc desc;
56
+
unsigned int functions_count;
57
+
struct pinfunction functions[] __counted_by(functions_count);
58
+
};
59
+
60
+
enum {
61
+
F_DISABLED,
62
+
F_BOOT_SEL,
63
+
F_CHIP_MODE,
64
+
F_EMMC,
65
+
F_FAN_TACH,
66
+
F_GPIO,
67
+
F_HDMI,
68
+
F_I2C,
69
+
F_I2S,
70
+
F_JTAG,
71
+
F_DDR_REF_CLK_SEL,
72
+
F_LPDDR_REF_CLK,
73
+
F_MIPI_CSI,
74
+
F_OSC,
75
+
F_PCIE,
76
+
F_PWM,
77
+
F_RGMII,
78
+
F_RESET,
79
+
F_SATA,
80
+
F_SDIO,
81
+
F_SPI,
82
+
F_S_MODE,
83
+
F_UART,
84
+
F_USB,
85
+
EIC7700_FUNCTIONS_COUNT
86
+
};
87
+
88
+
static const char *const eic7700_functions[EIC7700_FUNCTIONS_COUNT] = {
89
+
[F_DISABLED] = "disabled",
90
+
[F_BOOT_SEL] = "boot_sel",
91
+
[F_CHIP_MODE] = "chip_mode",
92
+
[F_EMMC] = "emmc",
93
+
[F_FAN_TACH] = "fan_tach",
94
+
[F_GPIO] = "gpio",
95
+
[F_HDMI] = "hdmi",
96
+
[F_I2C] = "i2c",
97
+
[F_I2S] = "i2s",
98
+
[F_JTAG] = "jtag",
99
+
[F_DDR_REF_CLK_SEL] = "ddr_ref_clk_sel",
100
+
[F_LPDDR_REF_CLK] = "lpddr_ref_clk",
101
+
[F_MIPI_CSI] = "mipi_csi",
102
+
[F_OSC] = "osc",
103
+
[F_PCIE] = "pcie",
104
+
[F_PWM] = "pwm",
105
+
[F_RGMII] = "rgmii",
106
+
[F_RESET] = "reset",
107
+
[F_SATA] = "sata",
108
+
[F_SDIO] = "sdio",
109
+
[F_SPI] = "spi",
110
+
[F_S_MODE] = "s_mode",
111
+
[F_UART] = "uart",
112
+
[F_USB] = "usb",
113
+
};
114
+
115
+
#define EIC7700_PIN(_number, _name, ...) \
116
+
{ \
117
+
.number = _number, \
118
+
.name = _name, \
119
+
.drv_data = (void *)&(struct eic7700_pin) { { __VA_ARGS__ } } \
120
+
}
121
+
122
+
static const struct pinctrl_pin_desc eic7700_pins[] = {
123
+
EIC7700_PIN(0, "chip_mode", [0] = F_CHIP_MODE),
124
+
EIC7700_PIN(1, "mode_set0", [0] = F_SDIO, [2] = F_GPIO),
125
+
EIC7700_PIN(2, "mode_set1", [0] = F_SDIO, [2] = F_GPIO),
126
+
EIC7700_PIN(3, "mode_set2", [0] = F_SDIO, [2] = F_GPIO),
127
+
EIC7700_PIN(4, "mode_set3", [0] = F_SDIO, [2] = F_GPIO),
128
+
EIC7700_PIN(5, "xin", [0] = F_OSC),
129
+
EIC7700_PIN(6, "rtc_xin", [0] = F_DISABLED),
130
+
EIC7700_PIN(7, "rst_out_n", [0] = F_RESET),
131
+
EIC7700_PIN(8, "key_reset_n", [0] = F_RESET),
132
+
EIC7700_PIN(9, "rst_in_n", [0] = F_DISABLED),
133
+
EIC7700_PIN(10, "por_in_n", [0] = F_DISABLED),
134
+
EIC7700_PIN(11, "por_out_n", [0] = F_DISABLED),
135
+
EIC7700_PIN(12, "gpio0", [0] = F_GPIO),
136
+
EIC7700_PIN(13, "por_sel", [0] = F_RESET),
137
+
EIC7700_PIN(14, "jtag0_tck", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
138
+
EIC7700_PIN(15, "jtag0_tms", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
139
+
EIC7700_PIN(16, "jtag0_tdi", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
140
+
EIC7700_PIN(17, "jtag0_tdo", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
141
+
EIC7700_PIN(18, "gpio5", [0] = F_GPIO, [1] = F_SPI),
142
+
EIC7700_PIN(19, "spi2_cs0_n", [0] = F_SPI, [2] = F_GPIO),
143
+
EIC7700_PIN(20, "jtag1_tck", [0] = F_JTAG, [2] = F_GPIO),
144
+
EIC7700_PIN(21, "jtag1_tms", [0] = F_JTAG, [2] = F_GPIO),
145
+
EIC7700_PIN(22, "jtag1_tdi", [0] = F_JTAG, [2] = F_GPIO),
146
+
EIC7700_PIN(23, "jtag1_tdo", [0] = F_JTAG, [2] = F_GPIO),
147
+
EIC7700_PIN(24, "gpio11", [0] = F_GPIO),
148
+
EIC7700_PIN(25, "spi2_cs1_n", [0] = F_SPI, [2] = F_GPIO),
149
+
EIC7700_PIN(26, "pcie_clkreq_n", [0] = F_PCIE),
150
+
EIC7700_PIN(27, "pcie_wake_n", [0] = F_PCIE),
151
+
EIC7700_PIN(28, "pcie_perst_n", [0] = F_PCIE),
152
+
EIC7700_PIN(29, "hdmi_scl", [0] = F_HDMI),
153
+
EIC7700_PIN(30, "hdmi_sda", [0] = F_HDMI),
154
+
EIC7700_PIN(31, "hdmi_cec", [0] = F_HDMI),
155
+
EIC7700_PIN(32, "jtag2_trst", [0] = F_JTAG, [2] = F_GPIO),
156
+
EIC7700_PIN(33, "rgmii0_clk_125", [0] = F_RGMII),
157
+
EIC7700_PIN(34, "rgmii0_txen", [0] = F_RGMII),
158
+
EIC7700_PIN(35, "rgmii0_txclk", [0] = F_RGMII),
159
+
EIC7700_PIN(36, "rgmii0_txd0", [0] = F_RGMII),
160
+
EIC7700_PIN(37, "rgmii0_txd1", [0] = F_RGMII),
161
+
EIC7700_PIN(38, "rgmii0_txd2", [0] = F_RGMII),
162
+
EIC7700_PIN(39, "rgmii0_txd3", [0] = F_RGMII),
163
+
EIC7700_PIN(40, "i2s0_bclk", [0] = F_I2S, [2] = F_GPIO),
164
+
EIC7700_PIN(41, "i2s0_wclk", [0] = F_I2S, [2] = F_GPIO),
165
+
EIC7700_PIN(42, "i2s0_sdi", [0] = F_I2S, [2] = F_GPIO),
166
+
EIC7700_PIN(43, "i2s0_sdo", [0] = F_I2S, [2] = F_GPIO),
167
+
EIC7700_PIN(44, "i2s_mclk", [0] = F_I2S, [2] = F_GPIO),
168
+
EIC7700_PIN(45, "rgmii0_rxclk", [0] = F_RGMII),
169
+
EIC7700_PIN(46, "rgmii0_rxdv", [0] = F_RGMII),
170
+
EIC7700_PIN(47, "rgmii0_rxd0", [0] = F_RGMII),
171
+
EIC7700_PIN(48, "rgmii0_rxd1", [0] = F_RGMII),
172
+
EIC7700_PIN(49, "rgmii0_rxd2", [0] = F_RGMII),
173
+
EIC7700_PIN(50, "rgmii0_rxd3", [0] = F_RGMII),
174
+
EIC7700_PIN(51, "i2s2_bclk", [0] = F_I2S, [2] = F_GPIO),
175
+
EIC7700_PIN(52, "i2s2_wclk", [0] = F_I2S, [2] = F_GPIO),
176
+
EIC7700_PIN(53, "i2s2_sdi", [0] = F_I2S, [2] = F_GPIO),
177
+
EIC7700_PIN(54, "i2s2_sdo", [0] = F_I2S, [2] = F_GPIO),
178
+
EIC7700_PIN(55, "gpio27", [0] = F_GPIO, [1] = F_SATA),
179
+
EIC7700_PIN(56, "gpio28", [0] = F_GPIO),
180
+
EIC7700_PIN(57, "gpio29", [0] = F_RESET, [1] = F_EMMC, [2] = F_GPIO),
181
+
EIC7700_PIN(58, "rgmii0_mdc", [0] = F_RGMII),
182
+
EIC7700_PIN(59, "rgmii0_mdio", [0] = F_RGMII),
183
+
EIC7700_PIN(60, "rgmii0_intb", [0] = F_RGMII),
184
+
EIC7700_PIN(61, "rgmii1_clk_125", [0] = F_RGMII),
185
+
EIC7700_PIN(62, "rgmii1_txen", [0] = F_RGMII),
186
+
EIC7700_PIN(63, "rgmii1_txclk", [0] = F_RGMII),
187
+
EIC7700_PIN(64, "rgmii1_txd0", [0] = F_RGMII),
188
+
EIC7700_PIN(65, "rgmii1_txd1", [0] = F_RGMII),
189
+
EIC7700_PIN(66, "rgmii1_txd2", [0] = F_RGMII),
190
+
EIC7700_PIN(67, "rgmii1_txd3", [0] = F_RGMII),
191
+
EIC7700_PIN(68, "i2s1_bclk", [0] = F_I2S, [2] = F_GPIO),
192
+
EIC7700_PIN(69, "i2s1_wclk", [0] = F_I2S, [2] = F_GPIO),
193
+
EIC7700_PIN(70, "i2s1_sdi", [0] = F_I2S, [2] = F_GPIO),
194
+
EIC7700_PIN(71, "i2s1_sdo", [0] = F_I2S, [2] = F_GPIO),
195
+
EIC7700_PIN(72, "gpio34", [0] = F_RESET, [1] = F_SDIO, [2] = F_GPIO),
196
+
EIC7700_PIN(73, "rgmii1_rxclk", [0] = F_RGMII),
197
+
EIC7700_PIN(74, "rgmii1_rxdv", [0] = F_RGMII),
198
+
EIC7700_PIN(75, "rgmii1_rxd0", [0] = F_RGMII),
199
+
EIC7700_PIN(76, "rgmii1_rxd1", [0] = F_RGMII),
200
+
EIC7700_PIN(77, "rgmii1_rxd2", [0] = F_RGMII),
201
+
EIC7700_PIN(78, "rgmii1_rxd3", [0] = F_RGMII),
202
+
EIC7700_PIN(79, "spi1_cs0_n", [0] = F_SPI, [2] = F_GPIO),
203
+
EIC7700_PIN(80, "spi1_clk", [0] = F_SPI, [2] = F_GPIO),
204
+
EIC7700_PIN(81, "spi1_d0", [0] = F_SPI, [1] = F_I2C, [2] = F_GPIO, [3] = F_UART),
205
+
EIC7700_PIN(82, "spi1_d1", [0] = F_SPI, [1] = F_I2C, [2] = F_GPIO, [3] = F_UART),
206
+
EIC7700_PIN(83, "spi1_d2", [0] = F_SPI, [1] = F_SDIO, [2] = F_GPIO),
207
+
EIC7700_PIN(84, "spi1_d3", [0] = F_SPI, [1] = F_PWM, [2] = F_GPIO),
208
+
EIC7700_PIN(85, "spi1_cs1_n", [0] = F_SPI, [1] = F_PWM, [2] = F_GPIO),
209
+
EIC7700_PIN(86, "rgmii1_mdc", [0] = F_RGMII),
210
+
EIC7700_PIN(87, "rgmii1_mdio", [0] = F_RGMII),
211
+
EIC7700_PIN(88, "rgmii1_intb", [0] = F_RGMII),
212
+
EIC7700_PIN(89, "usb0_pwren", [0] = F_USB, [2] = F_GPIO),
213
+
EIC7700_PIN(90, "usb1_pwren", [0] = F_USB, [2] = F_GPIO),
214
+
EIC7700_PIN(91, "i2c0_scl", [0] = F_I2C, [2] = F_GPIO),
215
+
EIC7700_PIN(92, "i2c0_sda", [0] = F_I2C, [2] = F_GPIO),
216
+
EIC7700_PIN(93, "i2c1_scl", [0] = F_I2C, [2] = F_GPIO),
217
+
EIC7700_PIN(94, "i2c1_sda", [0] = F_I2C, [2] = F_GPIO),
218
+
EIC7700_PIN(95, "i2c2_scl", [0] = F_I2C, [2] = F_GPIO),
219
+
EIC7700_PIN(96, "i2c2_sda", [0] = F_I2C, [2] = F_GPIO),
220
+
EIC7700_PIN(97, "i2c3_scl", [0] = F_I2C, [2] = F_GPIO),
221
+
EIC7700_PIN(98, "i2c3_sda", [0] = F_I2C, [2] = F_GPIO),
222
+
EIC7700_PIN(99, "i2c4_scl", [0] = F_I2C, [2] = F_GPIO),
223
+
EIC7700_PIN(100, "i2c4_sda", [0] = F_I2C, [2] = F_GPIO),
224
+
EIC7700_PIN(101, "i2c5_scl", [0] = F_I2C, [2] = F_GPIO),
225
+
EIC7700_PIN(102, "i2c5_sda", [0] = F_I2C, [2] = F_GPIO),
226
+
EIC7700_PIN(103, "uart0_tx", [0] = F_UART, [2] = F_GPIO),
227
+
EIC7700_PIN(104, "uart0_rx", [0] = F_UART, [2] = F_GPIO),
228
+
EIC7700_PIN(105, "uart1_tx", [0] = F_UART, [2] = F_GPIO),
229
+
EIC7700_PIN(106, "uart1_rx", [0] = F_UART, [2] = F_GPIO),
230
+
EIC7700_PIN(107, "uart1_cts", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
231
+
EIC7700_PIN(108, "uart1_rts", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
232
+
EIC7700_PIN(109, "uart2_tx", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
233
+
EIC7700_PIN(110, "uart2_rx", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
234
+
EIC7700_PIN(111, "jtag2_tck", [0] = F_JTAG, [2] = F_GPIO),
235
+
EIC7700_PIN(112, "jtag2_tms", [0] = F_JTAG, [2] = F_GPIO),
236
+
EIC7700_PIN(113, "jtag2_tdi", [0] = F_JTAG, [2] = F_GPIO),
237
+
EIC7700_PIN(114, "jtag2_tdo", [0] = F_JTAG, [2] = F_GPIO),
238
+
EIC7700_PIN(115, "fan_pwm", [0] = F_PWM, [2] = F_GPIO),
239
+
EIC7700_PIN(116, "fan_tach", [0] = F_FAN_TACH, [2] = F_GPIO),
240
+
EIC7700_PIN(117, "mipi_csi0_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
241
+
EIC7700_PIN(118, "mipi_csi0_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
242
+
EIC7700_PIN(119, "mipi_csi0_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
243
+
EIC7700_PIN(120, "mipi_csi1_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
244
+
EIC7700_PIN(121, "mipi_csi1_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
245
+
EIC7700_PIN(122, "mipi_csi1_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
246
+
EIC7700_PIN(123, "mipi_csi2_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
247
+
EIC7700_PIN(124, "mipi_csi2_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
248
+
EIC7700_PIN(125, "mipi_csi2_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
249
+
EIC7700_PIN(126, "mipi_csi3_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
250
+
EIC7700_PIN(127, "mipi_csi3_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
251
+
EIC7700_PIN(128, "mipi_csi3_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
252
+
EIC7700_PIN(129, "mipi_csi4_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
253
+
EIC7700_PIN(130, "mipi_csi4_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
254
+
EIC7700_PIN(131, "mipi_csi4_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
255
+
EIC7700_PIN(132, "mipi_csi5_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
256
+
EIC7700_PIN(133, "mipi_csi5_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
257
+
EIC7700_PIN(134, "mipi_csi5_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
258
+
EIC7700_PIN(135, "spi3_cs_n", [0] = F_SPI, [2] = F_GPIO),
259
+
EIC7700_PIN(136, "spi3_clk", [0] = F_SPI, [2] = F_GPIO),
260
+
EIC7700_PIN(137, "spi3_di", [0] = F_SPI, [2] = F_GPIO),
261
+
EIC7700_PIN(138, "spi3_do", [0] = F_SPI, [2] = F_GPIO),
262
+
EIC7700_PIN(139, "gpio92", [0] = F_I2C, [1] = F_MIPI_CSI, [2] = F_GPIO, [3] = F_UART),
263
+
EIC7700_PIN(140, "gpio93", [0] = F_I2C, [1] = F_MIPI_CSI, [2] = F_GPIO, [3] = F_UART),
264
+
EIC7700_PIN(141, "s_mode", [0] = F_S_MODE, [2] = F_GPIO),
265
+
EIC7700_PIN(142, "gpio95", [0] = F_DDR_REF_CLK_SEL, [2] = F_GPIO),
266
+
EIC7700_PIN(143, "spi0_cs_n", [0] = F_SPI, [2] = F_GPIO),
267
+
EIC7700_PIN(144, "spi0_clk", [0] = F_SPI, [2] = F_GPIO),
268
+
EIC7700_PIN(145, "spi0_d0", [0] = F_SPI, [2] = F_GPIO),
269
+
EIC7700_PIN(146, "spi0_d1", [0] = F_SPI, [2] = F_GPIO),
270
+
EIC7700_PIN(147, "spi0_d2", [0] = F_SPI, [2] = F_GPIO),
271
+
EIC7700_PIN(148, "spi0_d3", [0] = F_SPI, [2] = F_GPIO),
272
+
EIC7700_PIN(149, "i2c10_scl", [0] = F_I2C, [2] = F_GPIO),
273
+
EIC7700_PIN(150, "i2c10_sda", [0] = F_I2C, [2] = F_GPIO),
274
+
EIC7700_PIN(151, "i2c11_scl", [0] = F_I2C, [2] = F_GPIO),
275
+
EIC7700_PIN(152, "i2c11_sda", [0] = F_I2C, [2] = F_GPIO),
276
+
EIC7700_PIN(153, "gpio106", [0] = F_GPIO),
277
+
EIC7700_PIN(154, "boot_sel0", [0] = F_BOOT_SEL, [2] = F_GPIO),
278
+
EIC7700_PIN(155, "boot_sel1", [0] = F_BOOT_SEL, [2] = F_GPIO),
279
+
EIC7700_PIN(156, "boot_sel2", [0] = F_BOOT_SEL, [2] = F_GPIO),
280
+
EIC7700_PIN(157, "boot_sel3", [0] = F_BOOT_SEL, [2] = F_GPIO),
281
+
EIC7700_PIN(158, "gpio111", [0] = F_GPIO),
282
+
EIC7700_PIN(159, "reserved0", [0] = F_DISABLED),
283
+
EIC7700_PIN(160, "reserved1", [0] = F_DISABLED),
284
+
EIC7700_PIN(161, "reserved2", [0] = F_DISABLED),
285
+
EIC7700_PIN(162, "reserved3", [0] = F_DISABLED),
286
+
EIC7700_PIN(163, "lpddr_ref_clk", [0] = F_LPDDR_REF_CLK),
287
+
};
288
+
289
+
static int eic7700_get_groups_count(struct pinctrl_dev *pctldev)
290
+
{
291
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
292
+
293
+
return pc->desc.npins;
294
+
}
295
+
296
+
static const char *eic7700_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
297
+
{
298
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
299
+
300
+
return pc->desc.pins[selector].name;
301
+
}
302
+
303
+
static int eic7700_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
304
+
const unsigned int **pins, unsigned int *npins)
305
+
{
306
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
307
+
308
+
*pins = &pc->desc.pins[selector].number;
309
+
*npins = 1;
310
+
311
+
return 0;
312
+
}
313
+
314
+
static const struct pinctrl_ops eic7700_pinctrl_ops = {
315
+
.get_groups_count = eic7700_get_groups_count,
316
+
.get_group_name = eic7700_get_group_name,
317
+
.get_group_pins = eic7700_get_group_pins,
318
+
#ifdef CONFIG_OF
319
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
320
+
.dt_free_map = pinconf_generic_dt_free_map,
321
+
#endif
322
+
};
323
+
324
+
static int eic7700_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
325
+
unsigned long *config)
326
+
{
327
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
328
+
const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data;
329
+
u32 arg, value;
330
+
int param;
331
+
332
+
if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED)
333
+
return -EOPNOTSUPP;
334
+
335
+
value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin));
336
+
337
+
param = pinconf_to_config_param(*config);
338
+
switch (param) {
339
+
case PIN_CONFIG_BIAS_DISABLE:
340
+
arg = (value & EIC7700_BIAS) == 0;
341
+
break;
342
+
case PIN_CONFIG_BIAS_PULL_DOWN:
343
+
arg = (value & EIC7700_BIAS) == EIC7700_PD;
344
+
break;
345
+
case PIN_CONFIG_BIAS_PULL_UP:
346
+
arg = (value & EIC7700_BIAS) == EIC7700_PU;
347
+
break;
348
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
349
+
if (pin_data->functions[0] == F_RGMII ||
350
+
pin_data->functions[0] == F_LPDDR_REF_CLK)
351
+
arg = FIELD_GET(EIC7700_DS, value) * 3000 + 3000;
352
+
else
353
+
arg = FIELD_GET(EIC7700_DS, value) * 3000 + 6000;
354
+
break;
355
+
case PIN_CONFIG_INPUT_ENABLE:
356
+
arg = value & EIC7700_IE;
357
+
break;
358
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
359
+
arg = value & EIC7700_ST;
360
+
break;
361
+
default:
362
+
return -EOPNOTSUPP;
363
+
}
364
+
365
+
*config = pinconf_to_config_packed(param, arg);
366
+
return arg ? 0 : -EINVAL;
367
+
}
368
+
369
+
static int eic7700_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
370
+
unsigned long *configs, unsigned int num_configs)
371
+
{
372
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
373
+
const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data;
374
+
u32 value;
375
+
376
+
if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED)
377
+
return -EOPNOTSUPP;
378
+
379
+
value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin));
380
+
381
+
for (unsigned int i = 0; i < num_configs; i++) {
382
+
int param = pinconf_to_config_param(configs[i]);
383
+
u32 arg = pinconf_to_config_argument(configs[i]);
384
+
385
+
switch (param) {
386
+
case PIN_CONFIG_BIAS_DISABLE:
387
+
value &= ~EIC7700_BIAS;
388
+
break;
389
+
case PIN_CONFIG_BIAS_PULL_DOWN:
390
+
if (arg == 0)
391
+
return -EOPNOTSUPP;
392
+
value &= ~EIC7700_BIAS;
393
+
value |= EIC7700_PD;
394
+
break;
395
+
case PIN_CONFIG_BIAS_PULL_UP:
396
+
if (arg == 0)
397
+
return -EOPNOTSUPP;
398
+
value &= ~EIC7700_BIAS;
399
+
value |= EIC7700_PU;
400
+
break;
401
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
402
+
value &= ~EIC7700_DS;
403
+
if (pin_data->functions[0] == F_RGMII ||
404
+
pin_data->functions[0] == F_LPDDR_REF_CLK) {
405
+
if (arg < 3000 || arg > 24000)
406
+
return -EOPNOTSUPP;
407
+
value |= FIELD_PREP(EIC7700_DS, (arg - 3000) / 3000);
408
+
} else {
409
+
if (arg < 6000 || arg > 27000)
410
+
return -EOPNOTSUPP;
411
+
value |= FIELD_PREP(EIC7700_DS, (arg - 6000) / 3000);
412
+
}
413
+
break;
414
+
case PIN_CONFIG_INPUT_ENABLE:
415
+
if (arg)
416
+
value |= EIC7700_IE;
417
+
else
418
+
value &= ~EIC7700_IE;
419
+
break;
420
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
421
+
if (arg)
422
+
value |= EIC7700_ST;
423
+
else
424
+
value &= ~EIC7700_ST;
425
+
break;
426
+
default:
427
+
return -EOPNOTSUPP;
428
+
}
429
+
}
430
+
431
+
writel_relaxed(value, pc->base + EIC7700_PIN_REG(pin));
432
+
433
+
return 0;
434
+
}
435
+
436
+
#ifdef CONFIG_DEBUG_FS
437
+
static void eic7700_pin_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
438
+
unsigned int pin)
439
+
{
440
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
441
+
u32 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin)) & EIC7700_PINCONF;
442
+
443
+
seq_printf(s, " [0x%02x]", value);
444
+
}
445
+
#else
446
+
#define eic7700_pin_config_dbg_show NULL
447
+
#endif
448
+
449
+
static const struct pinconf_ops eic7700_pinconf_ops = {
450
+
.is_generic = true,
451
+
.pin_config_get = eic7700_pin_config_get,
452
+
.pin_config_set = eic7700_pin_config_set,
453
+
.pin_config_group_get = eic7700_pin_config_get,
454
+
.pin_config_group_set = eic7700_pin_config_set,
455
+
.pin_config_dbg_show = eic7700_pin_config_dbg_show,
456
+
.pin_config_group_dbg_show = eic7700_pin_config_dbg_show,
457
+
};
458
+
459
+
static int eic7700_get_functions_count(struct pinctrl_dev *pctldev)
460
+
{
461
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
462
+
463
+
return pc->functions_count;
464
+
}
465
+
466
+
static const char *eic7700_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
467
+
{
468
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
469
+
470
+
return pc->functions[selector].name;
471
+
}
472
+
473
+
static int eic7700_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
474
+
const char *const **groups, unsigned int *num_groups)
475
+
{
476
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
477
+
478
+
*groups = pc->functions[selector].groups;
479
+
*num_groups = pc->functions[selector].ngroups;
480
+
481
+
return 0;
482
+
}
483
+
484
+
static int eic7700_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
485
+
unsigned int group_selector)
486
+
{
487
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
488
+
const struct eic7700_pin *pin_data = pc->desc.pins[group_selector].drv_data;
489
+
u32 fs, value;
490
+
491
+
if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED)
492
+
return -EOPNOTSUPP;
493
+
494
+
for (fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++)
495
+
if (pin_data->functions[fs] == func_selector)
496
+
break;
497
+
498
+
if (fs == EIC7700_FUNCTIONS_PER_PIN) {
499
+
dev_err(pctldev->dev, "invalid mux %s for pin %s\n",
500
+
pc->functions[func_selector].name,
501
+
pc->desc.pins[group_selector].name);
502
+
return -EINVAL;
503
+
}
504
+
505
+
value = readl_relaxed(pc->base + EIC7700_PIN_REG(group_selector));
506
+
value &= ~EIC7700_FUNC_SEL;
507
+
value |= FIELD_PREP(EIC7700_FUNC_SEL, fs);
508
+
writel_relaxed(value, pc->base + EIC7700_PIN_REG(group_selector));
509
+
510
+
return 0;
511
+
}
512
+
513
+
static int eic7700_gpio_request_enable(struct pinctrl_dev *pctldev,
514
+
struct pinctrl_gpio_range *range, unsigned int offset)
515
+
{
516
+
return eic7700_set_mux(pctldev, F_GPIO, offset);
517
+
}
518
+
519
+
static void eic7700_gpio_disable_free(struct pinctrl_dev *pctldev,
520
+
struct pinctrl_gpio_range *range, unsigned int offset)
521
+
{
522
+
eic7700_set_mux(pctldev, F_DISABLED, offset);
523
+
}
524
+
525
+
static int eic7700_gpio_set_direction(struct pinctrl_dev *pctldev,
526
+
struct pinctrl_gpio_range *range, unsigned int offset,
527
+
bool input)
528
+
{
529
+
struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
530
+
u32 value;
531
+
532
+
value = readl_relaxed(pc->base + EIC7700_PIN_REG(offset));
533
+
if (input)
534
+
value |= EIC7700_IE;
535
+
else
536
+
value &= ~EIC7700_IE;
537
+
writel_relaxed(value, pc->base + EIC7700_PIN_REG(offset));
538
+
539
+
return 0;
540
+
}
541
+
542
+
static const struct pinmux_ops eic7700_pinmux_ops = {
543
+
.get_functions_count = eic7700_get_functions_count,
544
+
.get_function_name = eic7700_get_function_name,
545
+
.get_function_groups = eic7700_get_function_groups,
546
+
.set_mux = eic7700_set_mux,
547
+
.gpio_request_enable = eic7700_gpio_request_enable,
548
+
.gpio_disable_free = eic7700_gpio_disable_free,
549
+
.gpio_set_direction = eic7700_gpio_set_direction,
550
+
.strict = true,
551
+
};
552
+
553
+
static int eic7700_pinctrl_init_function_groups(struct device *dev, struct eic7700_pinctrl *pc,
554
+
const char *const *function_names)
555
+
{
556
+
unsigned int ngroups = 0;
557
+
const char **groups;
558
+
559
+
/* Count the number of groups for each function */
560
+
for (unsigned int pin = 0; pin < pc->desc.npins; pin++) {
561
+
const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data;
562
+
bool found_disabled = false;
563
+
564
+
for (unsigned int fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) {
565
+
unsigned int selector = pin_data->functions[fs];
566
+
struct pinfunction *function = &pc->functions[selector];
567
+
568
+
/* Only count F_DISABLED once per pin */
569
+
if (selector == F_DISABLED) {
570
+
if (found_disabled)
571
+
continue;
572
+
found_disabled = true;
573
+
}
574
+
575
+
function->ngroups++;
576
+
ngroups++;
577
+
}
578
+
}
579
+
580
+
groups = devm_kcalloc(dev, ngroups, sizeof(*groups), GFP_KERNEL);
581
+
if (!groups)
582
+
return -ENOMEM;
583
+
584
+
for (unsigned int selector = 0; selector < pc->functions_count; selector++) {
585
+
struct pinfunction *function = &pc->functions[selector];
586
+
587
+
function->name = function_names[selector];
588
+
function->groups = groups;
589
+
groups += function->ngroups;
590
+
591
+
/* Reset per-function ngroups for use as iterator below */
592
+
function->ngroups = 0;
593
+
}
594
+
595
+
/* Fill in the group pointers for each function */
596
+
for (unsigned int pin = 0; pin < pc->desc.npins; pin++) {
597
+
const struct pinctrl_pin_desc *desc = &pc->desc.pins[pin];
598
+
const struct eic7700_pin *pin_data = desc->drv_data;
599
+
bool found_disabled = false;
600
+
601
+
for (unsigned int fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) {
602
+
unsigned int selector = pin_data->functions[fs];
603
+
struct pinfunction *function = &pc->functions[selector];
604
+
605
+
/* Only count F_DISABLED once per pin */
606
+
if (selector == F_DISABLED) {
607
+
if (found_disabled)
608
+
continue;
609
+
found_disabled = true;
610
+
}
611
+
612
+
((const char **)function->groups)[function->ngroups++] = desc->name;
613
+
}
614
+
}
615
+
616
+
return 0;
617
+
}
618
+
619
+
static int eic7700_pinctrl_probe(struct platform_device *pdev)
620
+
{
621
+
struct device *dev = &pdev->dev;
622
+
struct pinctrl_dev *pctldev;
623
+
struct eic7700_pinctrl *pc;
624
+
struct regulator *regulator;
625
+
u32 rgmii0_mode, rgmii1_mode;
626
+
int ret, voltage;
627
+
628
+
pc = devm_kzalloc(dev, struct_size(pc, functions, EIC7700_FUNCTIONS_COUNT), GFP_KERNEL);
629
+
if (!pc)
630
+
return -ENOMEM;
631
+
632
+
pc->base = devm_platform_ioremap_resource(pdev, 0);
633
+
if (IS_ERR(pc->base))
634
+
return PTR_ERR(pc->base);
635
+
636
+
regulator = devm_regulator_get(dev, "vrgmii");
637
+
if (IS_ERR_OR_NULL(regulator)) {
638
+
return dev_err_probe(dev, PTR_ERR(regulator),
639
+
"failed to get vrgmii regulator\n");
640
+
}
641
+
642
+
voltage = regulator_get_voltage(regulator);
643
+
if (voltage < 0) {
644
+
return dev_err_probe(&pdev->dev, voltage,
645
+
"Failed to get voltage from regulator\n");
646
+
}
647
+
648
+
rgmii0_mode = readl_relaxed(pc->base + EIC7700_RGMII0_SEL_MODE);
649
+
rgmii1_mode = readl_relaxed(pc->base + EIC7700_RGMII1_SEL_MODE);
650
+
rgmii0_mode &= ~EIC7700_MS;
651
+
rgmii1_mode &= ~EIC7700_MS;
652
+
if (voltage == 1800000) {
653
+
rgmii0_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8);
654
+
rgmii1_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8);
655
+
} else if (voltage == 3300000) {
656
+
rgmii0_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3);
657
+
rgmii1_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3);
658
+
} else {
659
+
return dev_err_probe(&pdev->dev, -EINVAL,
660
+
"Invalid voltage configuration, should be either 1.8V or 3.3V\n");
661
+
}
662
+
663
+
writel_relaxed(rgmii0_mode, pc->base + EIC7700_RGMII0_SEL_MODE);
664
+
writel_relaxed(rgmii1_mode, pc->base + EIC7700_RGMII1_SEL_MODE);
665
+
666
+
pc->desc.name = dev_name(dev);
667
+
pc->desc.pins = eic7700_pins;
668
+
pc->desc.npins = ARRAY_SIZE(eic7700_pins);
669
+
pc->desc.pctlops = &eic7700_pinctrl_ops;
670
+
pc->desc.pmxops = &eic7700_pinmux_ops;
671
+
pc->desc.confops = &eic7700_pinconf_ops;
672
+
pc->desc.owner = THIS_MODULE;
673
+
674
+
pc->functions_count = EIC7700_FUNCTIONS_COUNT;
675
+
ret = eic7700_pinctrl_init_function_groups(dev, pc, eic7700_functions);
676
+
if (ret)
677
+
return ret;
678
+
679
+
ret = devm_pinctrl_register_and_init(dev, &pc->desc, pc, &pctldev);
680
+
if (ret)
681
+
return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
682
+
683
+
return pinctrl_enable(pctldev);
684
+
}
685
+
686
+
static const struct of_device_id eic7700_pinctrl_of_match[] = {
687
+
{ .compatible = "eswin,eic7700-pinctrl" },
688
+
{ /* sentinel */ }
689
+
};
690
+
MODULE_DEVICE_TABLE(of, eic7700_pinctrl_of_match);
691
+
692
+
static struct platform_driver eic7700_pinctrl_driver = {
693
+
.probe = eic7700_pinctrl_probe,
694
+
.driver = {
695
+
.name = "pinctrl-eic7700",
696
+
.of_match_table = eic7700_pinctrl_of_match,
697
+
},
698
+
};
699
+
module_platform_driver(eic7700_pinctrl_driver);
700
+
701
+
MODULE_DESCRIPTION("Pinctrl driver for the ESWIN EIC7700 SoC");
702
+
MODULE_AUTHOR("Samuel Holland <samuel.holland@sifive.com>");
703
+
MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
704
+
MODULE_LICENSE("GPL");
+4
-5
drivers/pinctrl/pinctrl-equilibrium.c
+4
-5
drivers/pinctrl/pinctrl-equilibrium.c
···
182
182
gc = &gctrl->chip;
183
183
gc->label = gctrl->name;
184
184
gc->fwnode = gctrl->fwnode;
185
+
gc->request = gpiochip_generic_request;
186
+
gc->free = gpiochip_generic_free;
185
187
186
188
if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) {
187
189
dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
···
687
685
if (funcs[i].name == NULL)
688
686
continue;
689
687
690
-
ret = pinmux_generic_add_function(drvdata->pctl_dev,
691
-
funcs[i].name,
692
-
funcs[i].groups,
693
-
funcs[i].ngroups,
694
-
drvdata);
688
+
ret = pinmux_generic_add_pinfunction(drvdata->pctl_dev,
689
+
&funcs[i], drvdata);
695
690
if (ret < 0) {
696
691
dev_err(dev, "Failed to register function %s\n",
697
692
funcs[i].name);
+1
-1
drivers/pinctrl/pinctrl-falcon.c
+1
-1
drivers/pinctrl/pinctrl-falcon.c
+2
-3
drivers/pinctrl/pinctrl-ingenic.c
+2
-3
drivers/pinctrl/pinctrl-ingenic.c
···
4574
4574
const struct function_desc *function = &chip_info->functions[i];
4575
4575
const struct pinfunction *func = &function->func;
4576
4576
4577
-
err = pinmux_generic_add_function(jzpc->pctl, func->name,
4578
-
func->groups, func->ngroups,
4579
-
function->data);
4577
+
err = pinmux_generic_add_pinfunction(jzpc->pctl, func,
4578
+
function->data);
4580
4579
if (err < 0) {
4581
4580
dev_err(dev, "Failed to register function %s\n", func->name);
4582
4581
return err;
+1
-1
drivers/pinctrl/pinctrl-k210.c
+1
-1
drivers/pinctrl/pinctrl-k210.c
+10
-3
drivers/pinctrl/pinctrl-k230.c
+10
-3
drivers/pinctrl/pinctrl-k230.c
···
477
477
grp->name = np->name;
478
478
479
479
list = of_get_property(np, "pinmux", &size);
480
+
if (!list) {
481
+
dev_err(dev, "failed to get pinmux property\n");
482
+
return -EINVAL;
483
+
}
480
484
size /= sizeof(*list);
481
485
482
486
grp->num_pins = size;
···
590
586
struct device *dev = &pdev->dev;
591
587
struct k230_pinctrl *info;
592
588
struct pinctrl_desc *pctl;
589
+
int ret;
593
590
594
591
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
595
592
if (!info)
···
616
611
return dev_err_probe(dev, PTR_ERR(info->regmap_base),
617
612
"failed to init regmap\n");
618
613
614
+
ret = k230_pinctrl_parse_dt(pdev, info);
615
+
if (ret)
616
+
return ret;
617
+
619
618
info->pctl_dev = devm_pinctrl_register(dev, pctl, info);
620
619
if (IS_ERR(info->pctl_dev))
621
620
return dev_err_probe(dev, PTR_ERR(info->pctl_dev),
622
621
"devm_pinctrl_register failed\n");
623
-
624
-
k230_pinctrl_parse_dt(pdev, info);
625
622
626
623
return 0;
627
624
}
628
625
629
626
static const struct of_device_id k230_dt_ids[] = {
630
627
{ .compatible = "canaan,k230-pinctrl", },
631
-
{ /* sintenel */ }
628
+
{ /* sentinel */ }
632
629
};
633
630
MODULE_DEVICE_TABLE(of, k230_dt_ids);
634
631
+8
-11
drivers/pinctrl/pinctrl-keembay.c
+8
-11
drivers/pinctrl/pinctrl-keembay.c
···
1188
1188
return keembay_read_pin(kpc->base0 + offset, pin);
1189
1189
}
1190
1190
1191
-
static void keembay_gpio_set(struct gpio_chip *gc, unsigned int pin, int val)
1191
+
static int keembay_gpio_set(struct gpio_chip *gc, unsigned int pin, int val)
1192
1192
{
1193
1193
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1194
1194
unsigned int reg_val;
···
1200
1200
else
1201
1201
keembay_write_gpio_reg(~reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),
1202
1202
kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin);
1203
+
1204
+
return 0;
1203
1205
}
1204
1206
1205
1207
static int keembay_gpio_get_direction(struct gpio_chip *gc, unsigned int pin)
···
1233
1231
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1234
1232
val &= ~KEEMBAY_GPIO_MODE_DIR;
1235
1233
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1236
-
keembay_gpio_set(gc, pin, value);
1237
1234
1238
-
return 0;
1235
+
return keembay_gpio_set(gc, pin, value);
1239
1236
}
1240
1237
1241
1238
static void keembay_gpio_irq_handler(struct irq_desc *desc)
···
1481
1480
gc->direction_input = keembay_gpio_set_direction_in;
1482
1481
gc->direction_output = keembay_gpio_set_direction_out;
1483
1482
gc->get = keembay_gpio_get;
1484
-
gc->set = keembay_gpio_set;
1483
+
gc->set_rv = keembay_gpio_set;
1485
1484
gc->set_config = gpiochip_generic_config;
1486
1485
gc->base = -1;
1487
1486
gc->ngpio = kpc->npins;
···
1586
1585
}
1587
1586
1588
1587
/* Add all functions */
1589
-
for (i = 0; i < kpc->nfuncs; i++) {
1590
-
pinmux_generic_add_function(kpc->pctrl,
1591
-
functions[i].func.name,
1592
-
functions[i].func.groups,
1593
-
functions[i].func.ngroups,
1594
-
functions[i].data);
1595
-
}
1588
+
for (i = 0; i < kpc->nfuncs; i++)
1589
+
pinmux_generic_add_pinfunction(kpc->pctrl, &functions[i].func,
1590
+
functions[i].data);
1596
1591
1597
1592
return 0;
1598
1593
}
+1
-1
drivers/pinctrl/pinctrl-lpc18xx.c
+1
-1
drivers/pinctrl/pinctrl-lpc18xx.c
···
1257
1257
.dt_free_map = pinctrl_utils_free_map,
1258
1258
};
1259
1259
1260
-
static struct pinctrl_desc lpc18xx_scu_desc = {
1260
+
static const struct pinctrl_desc lpc18xx_scu_desc = {
1261
1261
.name = "lpc18xx/43xx-scu",
1262
1262
.pins = lpc18xx_pins,
1263
1263
.npins = ARRAY_SIZE(lpc18xx_pins),
+4
-5
drivers/pinctrl/pinctrl-max77620.c
+4
-5
drivers/pinctrl/pinctrl-max77620.c
···
543
543
.pctlops = &max77620_pinctrl_ops,
544
544
.pmxops = &max77620_pinmux_ops,
545
545
.confops = &max77620_pinconf_ops,
546
+
.pins = max77620_pins_desc,
547
+
.npins = ARRAY_SIZE(max77620_pins_desc),
548
+
.num_custom_params = ARRAY_SIZE(max77620_cfg_params),
549
+
.custom_params = max77620_cfg_params,
546
550
};
547
551
548
552
static int max77620_pinctrl_probe(struct platform_device *pdev)
···
573
569
platform_set_drvdata(pdev, mpci);
574
570
575
571
max77620_pinctrl_desc.name = dev_name(&pdev->dev);
576
-
max77620_pinctrl_desc.pins = max77620_pins_desc;
577
-
max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
578
-
max77620_pinctrl_desc.num_custom_params =
579
-
ARRAY_SIZE(max77620_cfg_params);
580
-
max77620_pinctrl_desc.custom_params = max77620_cfg_params;
581
572
582
573
for (i = 0; i < MAX77620_PIN_NUM; ++i) {
583
574
mpci->fps_config[i].active_fps_src = -1;
+13
-7
drivers/pinctrl/pinctrl-mcp23s08.c
+13
-7
drivers/pinctrl/pinctrl-mcp23s08.c
···
341
341
return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
342
342
}
343
343
344
-
static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
344
+
static int mcp23s08_set(struct gpio_chip *chip, unsigned int offset, int value)
345
345
{
346
346
struct mcp23s08 *mcp = gpiochip_get_data(chip);
347
347
unsigned mask = BIT(offset);
348
+
int ret;
348
349
349
350
mutex_lock(&mcp->lock);
350
-
__mcp23s08_set(mcp, mask, !!value);
351
+
ret = __mcp23s08_set(mcp, mask, !!value);
351
352
mutex_unlock(&mcp->lock);
353
+
354
+
return ret;
352
355
}
353
356
354
-
static void mcp23s08_set_multiple(struct gpio_chip *chip,
355
-
unsigned long *mask, unsigned long *bits)
357
+
static int mcp23s08_set_multiple(struct gpio_chip *chip,
358
+
unsigned long *mask, unsigned long *bits)
356
359
{
357
360
struct mcp23s08 *mcp = gpiochip_get_data(chip);
361
+
int ret;
358
362
359
363
mutex_lock(&mcp->lock);
360
-
mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
364
+
ret = mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
361
365
mutex_unlock(&mcp->lock);
366
+
367
+
return ret;
362
368
}
363
369
364
370
static int
···
632
626
mcp->chip.get = mcp23s08_get;
633
627
mcp->chip.get_multiple = mcp23s08_get_multiple;
634
628
mcp->chip.direction_output = mcp23s08_direction_output;
635
-
mcp->chip.set = mcp23s08_set;
636
-
mcp->chip.set_multiple = mcp23s08_set_multiple;
629
+
mcp->chip.set_rv = mcp23s08_set;
630
+
mcp->chip.set_multiple_rv = mcp23s08_set_multiple;
637
631
638
632
mcp->chip.base = base;
639
633
mcp->chip.can_sleep = true;
+1
-1
drivers/pinctrl/pinctrl-mlxbf3.c
+1
-1
drivers/pinctrl/pinctrl-mlxbf3.c
+2
-2
drivers/pinctrl/pinctrl-palmas.c
+2
-2
drivers/pinctrl/pinctrl-palmas.c
···
956
956
.pmxops = &palmas_pinmux_ops,
957
957
.confops = &palmas_pinconf_ops,
958
958
.owner = THIS_MODULE,
959
+
.pins = palmas_pins_desc,
960
+
.npins = ARRAY_SIZE(palmas_pins_desc),
959
961
};
960
962
961
963
struct palmas_pinctrl_data {
···
1025
1023
}
1026
1024
1027
1025
palmas_pinctrl_desc.name = dev_name(&pdev->dev);
1028
-
palmas_pinctrl_desc.pins = palmas_pins_desc;
1029
-
palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
1030
1026
pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
1031
1027
pci);
1032
1028
if (IS_ERR(pci->pctl)) {
+5
-3
drivers/pinctrl/pinctrl-pic32.c
+5
-3
drivers/pinctrl/pinctrl-pic32.c
···
1828
1828
return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));
1829
1829
}
1830
1830
1831
-
static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset,
1832
-
int value)
1831
+
static int pic32_gpio_set(struct gpio_chip *chip, unsigned int offset,
1832
+
int value)
1833
1833
{
1834
1834
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
1835
1835
u32 mask = BIT(offset);
···
1838
1838
writel(mask, bank->reg_base + PIC32_SET(PORT_REG));
1839
1839
else
1840
1840
writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));
1841
+
1842
+
return 0;
1841
1843
}
1842
1844
1843
1845
static int pic32_gpio_direction_output(struct gpio_chip *chip,
···
2120
2118
.direction_input = pic32_gpio_direction_input, \
2121
2119
.direction_output = pic32_gpio_direction_output, \
2122
2120
.get = pic32_gpio_get, \
2123
-
.set = pic32_gpio_set, \
2121
+
.set_rv = pic32_gpio_set, \
2124
2122
.ngpio = _npins, \
2125
2123
.base = GPIO_BANK_START(_bank), \
2126
2124
.owner = THIS_MODULE, \
+4
-4
drivers/pinctrl/pinctrl-pistachio.c
+4
-4
drivers/pinctrl/pinctrl-pistachio.c
···
1156
1156
.is_generic = true,
1157
1157
};
1158
1158
1159
-
static struct pinctrl_desc pistachio_pinctrl_desc = {
1159
+
static const struct pinctrl_desc pistachio_pinctrl_desc = {
1160
1160
.name = "pistachio-pinctrl",
1161
1161
.pctlops = &pistachio_pinctrl_ops,
1162
1162
.pmxops = &pistachio_pinmux_ops,
1163
1163
.confops = &pistachio_pinconf_ops,
1164
+
.pins = pistachio_pins,
1165
+
.npins = ARRAY_SIZE(pistachio_pins),
1166
+
1164
1167
};
1165
1168
1166
1169
static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
···
1476
1473
pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1477
1474
pctl->gpio_banks = pistachio_gpio_banks;
1478
1475
pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1479
-
1480
-
pistachio_pinctrl_desc.pins = pctl->pins;
1481
-
pistachio_pinctrl_desc.npins = pctl->npins;
1482
1476
1483
1477
pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
1484
1478
pctl);
+4
-2
drivers/pinctrl/pinctrl-st.c
+4
-2
drivers/pinctrl/pinctrl-st.c
···
706
706
return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
707
707
}
708
708
709
-
static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
709
+
static int st_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
710
710
{
711
711
struct st_gpio_bank *bank = gpiochip_get_data(chip);
712
712
__st_gpio_set(bank, offset, value);
713
+
714
+
return 0;
713
715
}
714
716
715
717
static int st_gpio_direction_output(struct gpio_chip *chip,
···
1467
1465
.request = gpiochip_generic_request,
1468
1466
.free = gpiochip_generic_free,
1469
1467
.get = st_gpio_get,
1470
-
.set = st_gpio_set,
1468
+
.set_rv = st_gpio_set,
1471
1469
.direction_input = pinctrl_gpio_direction_input,
1472
1470
.direction_output = st_gpio_direction_output,
1473
1471
.get_direction = st_gpio_get_direction,
+1
-1
drivers/pinctrl/pinctrl-tb10x.c
+1
-1
drivers/pinctrl/pinctrl-tb10x.c
+9
-9
drivers/pinctrl/pinctrl-xway.c
+9
-9
drivers/pinctrl/pinctrl-xway.c
···
1228
1228
return 0;
1229
1229
}
1230
1230
1231
-
int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
1232
-
unsigned selector,
1233
-
unsigned long *configs,
1234
-
unsigned num_configs)
1231
+
static int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
1232
+
unsigned int selector,
1233
+
unsigned long *configs,
1234
+
unsigned int num_configs)
1235
1235
{
1236
1236
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1237
1237
int i, ret = 0;
···
1293
1293
};
1294
1294
1295
1295
/* --------- gpio_chip related code --------- */
1296
-
static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
1296
+
static int xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
1297
1297
{
1298
1298
struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1299
1299
···
1301
1301
gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1302
1302
else
1303
1303
gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1304
+
1305
+
return 0;
1304
1306
}
1305
1307
1306
1308
static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
···
1330
1328
else
1331
1329
gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
1332
1330
gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1333
-
xway_gpio_set(chip, pin, val);
1334
-
1335
-
return 0;
1331
+
return xway_gpio_set(chip, pin, val);
1336
1332
}
1337
1333
1338
1334
/*
···
1354
1354
.direction_input = xway_gpio_dir_in,
1355
1355
.direction_output = xway_gpio_dir_out,
1356
1356
.get = xway_gpio_get,
1357
-
.set = xway_gpio_set,
1357
+
.set_rv = xway_gpio_set,
1358
1358
.request = gpiochip_generic_request,
1359
1359
.free = gpiochip_generic_free,
1360
1360
.to_irq = xway_gpio_to_irq,
+1
-1
drivers/pinctrl/pinctrl-zynq.c
+1
-1
drivers/pinctrl/pinctrl-zynq.c
+28
-17
drivers/pinctrl/pinmux.c
+28
-17
drivers/pinctrl/pinmux.c
···
236
236
if (desc->mux_usecount)
237
237
return NULL;
238
238
}
239
+
240
+
if (gpio_range) {
241
+
owner = desc->gpio_owner;
242
+
desc->gpio_owner = NULL;
243
+
} else {
244
+
owner = desc->mux_owner;
245
+
desc->mux_owner = NULL;
246
+
desc->mux_setting = NULL;
247
+
}
239
248
}
240
249
241
250
/*
···
255
246
ops->gpio_disable_free(pctldev, gpio_range, pin);
256
247
else if (ops->free)
257
248
ops->free(pctldev, pin);
258
-
259
-
scoped_guard(mutex, &desc->mux_lock) {
260
-
if (gpio_range) {
261
-
owner = desc->gpio_owner;
262
-
desc->gpio_owner = NULL;
263
-
} else {
264
-
owner = desc->mux_owner;
265
-
desc->mux_owner = NULL;
266
-
desc->mux_setting = NULL;
267
-
}
268
-
}
269
249
270
250
module_put(pctldev->owner);
271
251
···
875
877
const unsigned int ngroups,
876
878
void *data)
877
879
{
880
+
struct pinfunction func = PINCTRL_PINFUNCTION(name, groups, ngroups);
881
+
882
+
return pinmux_generic_add_pinfunction(pctldev, &func, data);
883
+
}
884
+
EXPORT_SYMBOL_GPL(pinmux_generic_add_function);
885
+
886
+
/**
887
+
* pinmux_generic_add_pinfunction() - adds a function group
888
+
* @pctldev: pin controller device
889
+
* @func: pinfunction structure describing the function group
890
+
* @data: pin controller driver specific data
891
+
*/
892
+
int pinmux_generic_add_pinfunction(struct pinctrl_dev *pctldev,
893
+
const struct pinfunction *func, void *data)
894
+
{
878
895
struct function_desc *function;
879
896
int selector, error;
880
897
881
-
if (!name)
882
-
return -EINVAL;
883
-
884
-
selector = pinmux_func_name_to_selector(pctldev, name);
898
+
selector = pinmux_func_name_to_selector(pctldev, func->name);
885
899
if (selector >= 0)
886
900
return selector;
887
901
···
903
893
if (!function)
904
894
return -ENOMEM;
905
895
906
-
*function = PINCTRL_FUNCTION_DESC(name, groups, ngroups, data);
896
+
function->func = *func;
897
+
function->data = data;
907
898
908
899
error = radix_tree_insert(&pctldev->pin_function_tree, selector, function);
909
900
if (error)
···
914
903
915
904
return selector;
916
905
}
917
-
EXPORT_SYMBOL_GPL(pinmux_generic_add_function);
906
+
EXPORT_SYMBOL_GPL(pinmux_generic_add_pinfunction);
918
907
919
908
/**
920
909
* pinmux_generic_remove_function() - removes a numbered function
+3
-7
drivers/pinctrl/pinmux.h
+3
-7
drivers/pinctrl/pinmux.h
···
141
141
void *data;
142
142
};
143
143
144
-
/* Convenient macro to define a generic pin function descriptor */
145
-
#define PINCTRL_FUNCTION_DESC(_name, _grps, _num_grps, _data) \
146
-
(struct function_desc) { \
147
-
.func = PINCTRL_PINFUNCTION(_name, _grps, _num_grps), \
148
-
.data = _data, \
149
-
}
150
-
151
144
int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev);
152
145
153
146
const char *
···
160
167
const char * const *groups,
161
168
unsigned int const ngroups,
162
169
void *data);
170
+
171
+
int pinmux_generic_add_pinfunction(struct pinctrl_dev *pctldev,
172
+
const struct pinfunction *func, void *data);
163
173
164
174
int pinmux_generic_remove_function(struct pinctrl_dev *pctldev,
165
175
unsigned int selector);
+8
drivers/pinctrl/qcom/Kconfig.msm
+8
drivers/pinctrl/qcom/Kconfig.msm
···
371
371
Qualcomm Technologies Inc TLMM block found on the Qualcomm
372
372
Technologies Inc SM7150 platform.
373
373
374
+
config PINCTRL_MILOS
375
+
tristate "Qualcomm Technologies Inc Milos pin controller driver"
376
+
depends on ARM64 || COMPILE_TEST
377
+
help
378
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
379
+
Qualcomm Technologies Inc TLMM block found on the Qualcomm
380
+
Technologies Inc Milos platform.
381
+
374
382
config PINCTRL_SM8150
375
383
tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
376
384
depends on ARM64 || COMPILE_TEST
+1
drivers/pinctrl/qcom/Makefile
+1
drivers/pinctrl/qcom/Makefile
···
30
30
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
31
31
obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
32
32
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
33
+
obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o
33
34
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
34
35
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
35
36
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
+1339
drivers/pinctrl/qcom/pinctrl-milos.c
+1339
drivers/pinctrl/qcom/pinctrl-milos.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
5
+
*/
6
+
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <linux/platform_device.h>
10
+
11
+
#include "pinctrl-msm.h"
12
+
13
+
#define REG_SIZE 0x1000
14
+
15
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
16
+
{ \
17
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
18
+
gpio##id##_pins, \
19
+
ARRAY_SIZE(gpio##id##_pins)), \
20
+
.funcs = (int[]){ \
21
+
msm_mux_gpio, /* gpio mode */ \
22
+
msm_mux_##f1, \
23
+
msm_mux_##f2, \
24
+
msm_mux_##f3, \
25
+
msm_mux_##f4, \
26
+
msm_mux_##f5, \
27
+
msm_mux_##f6, \
28
+
msm_mux_##f7, \
29
+
msm_mux_##f8, \
30
+
msm_mux_##f9, \
31
+
msm_mux_##f10, \
32
+
msm_mux_##f11 /* egpio mode */ \
33
+
}, \
34
+
.nfuncs = 12, \
35
+
.ctl_reg = REG_SIZE * id, \
36
+
.io_reg = 0x4 + REG_SIZE * id, \
37
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
38
+
.intr_status_reg = 0xc + REG_SIZE * id, \
39
+
.intr_target_reg = 0x8 + REG_SIZE * id, \
40
+
.mux_bit = 2, \
41
+
.pull_bit = 0, \
42
+
.drv_bit = 6, \
43
+
.i2c_pull_bit = 13, \
44
+
.egpio_enable = 12, \
45
+
.egpio_present = 11, \
46
+
.oe_bit = 9, \
47
+
.in_bit = 0, \
48
+
.out_bit = 1, \
49
+
.intr_enable_bit = 0, \
50
+
.intr_status_bit = 0, \
51
+
.intr_target_bit = 8, \
52
+
.intr_wakeup_enable_bit = 7, \
53
+
.intr_wakeup_present_bit = 6, \
54
+
.intr_target_kpss_val = 3, \
55
+
.intr_raw_status_bit = 4, \
56
+
.intr_polarity_bit = 1, \
57
+
.intr_detection_bit = 2, \
58
+
.intr_detection_width = 2, \
59
+
}
60
+
61
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
62
+
{ \
63
+
.grp = PINCTRL_PINGROUP(#pg_name, \
64
+
pg_name##_pins, \
65
+
ARRAY_SIZE(pg_name##_pins)), \
66
+
.ctl_reg = ctl, \
67
+
.io_reg = 0, \
68
+
.intr_cfg_reg = 0, \
69
+
.intr_status_reg = 0, \
70
+
.intr_target_reg = 0, \
71
+
.mux_bit = -1, \
72
+
.pull_bit = pull, \
73
+
.drv_bit = drv, \
74
+
.oe_bit = -1, \
75
+
.in_bit = -1, \
76
+
.out_bit = -1, \
77
+
.intr_enable_bit = -1, \
78
+
.intr_status_bit = -1, \
79
+
.intr_target_bit = -1, \
80
+
.intr_raw_status_bit = -1, \
81
+
.intr_polarity_bit = -1, \
82
+
.intr_detection_bit = -1, \
83
+
.intr_detection_width = -1, \
84
+
}
85
+
86
+
#define UFS_RESET(pg_name, ctl, io) \
87
+
{ \
88
+
.grp = PINCTRL_PINGROUP(#pg_name, \
89
+
pg_name##_pins, \
90
+
ARRAY_SIZE(pg_name##_pins)), \
91
+
.ctl_reg = ctl, \
92
+
.io_reg = io, \
93
+
.intr_cfg_reg = 0, \
94
+
.intr_status_reg = 0, \
95
+
.intr_target_reg = 0, \
96
+
.mux_bit = -1, \
97
+
.pull_bit = 3, \
98
+
.drv_bit = 0, \
99
+
.oe_bit = -1, \
100
+
.in_bit = -1, \
101
+
.out_bit = 0, \
102
+
.intr_enable_bit = -1, \
103
+
.intr_status_bit = -1, \
104
+
.intr_target_bit = -1, \
105
+
.intr_raw_status_bit = -1, \
106
+
.intr_polarity_bit = -1, \
107
+
.intr_detection_bit = -1, \
108
+
.intr_detection_width = -1, \
109
+
}
110
+
111
+
static const struct pinctrl_pin_desc milos_pins[] = {
112
+
PINCTRL_PIN(0, "GPIO_0"),
113
+
PINCTRL_PIN(1, "GPIO_1"),
114
+
PINCTRL_PIN(2, "GPIO_2"),
115
+
PINCTRL_PIN(3, "GPIO_3"),
116
+
PINCTRL_PIN(4, "GPIO_4"),
117
+
PINCTRL_PIN(5, "GPIO_5"),
118
+
PINCTRL_PIN(6, "GPIO_6"),
119
+
PINCTRL_PIN(7, "GPIO_7"),
120
+
PINCTRL_PIN(8, "GPIO_8"),
121
+
PINCTRL_PIN(9, "GPIO_9"),
122
+
PINCTRL_PIN(10, "GPIO_10"),
123
+
PINCTRL_PIN(11, "GPIO_11"),
124
+
PINCTRL_PIN(12, "GPIO_12"),
125
+
PINCTRL_PIN(13, "GPIO_13"),
126
+
PINCTRL_PIN(14, "GPIO_14"),
127
+
PINCTRL_PIN(15, "GPIO_15"),
128
+
PINCTRL_PIN(16, "GPIO_16"),
129
+
PINCTRL_PIN(17, "GPIO_17"),
130
+
PINCTRL_PIN(18, "GPIO_18"),
131
+
PINCTRL_PIN(19, "GPIO_19"),
132
+
PINCTRL_PIN(20, "GPIO_20"),
133
+
PINCTRL_PIN(21, "GPIO_21"),
134
+
PINCTRL_PIN(22, "GPIO_22"),
135
+
PINCTRL_PIN(23, "GPIO_23"),
136
+
PINCTRL_PIN(24, "GPIO_24"),
137
+
PINCTRL_PIN(25, "GPIO_25"),
138
+
PINCTRL_PIN(26, "GPIO_26"),
139
+
PINCTRL_PIN(27, "GPIO_27"),
140
+
PINCTRL_PIN(28, "GPIO_28"),
141
+
PINCTRL_PIN(29, "GPIO_29"),
142
+
PINCTRL_PIN(30, "GPIO_30"),
143
+
PINCTRL_PIN(31, "GPIO_31"),
144
+
PINCTRL_PIN(32, "GPIO_32"),
145
+
PINCTRL_PIN(33, "GPIO_33"),
146
+
PINCTRL_PIN(34, "GPIO_34"),
147
+
PINCTRL_PIN(35, "GPIO_35"),
148
+
PINCTRL_PIN(36, "GPIO_36"),
149
+
PINCTRL_PIN(37, "GPIO_37"),
150
+
PINCTRL_PIN(38, "GPIO_38"),
151
+
PINCTRL_PIN(39, "GPIO_39"),
152
+
PINCTRL_PIN(40, "GPIO_40"),
153
+
PINCTRL_PIN(41, "GPIO_41"),
154
+
PINCTRL_PIN(42, "GPIO_42"),
155
+
PINCTRL_PIN(43, "GPIO_43"),
156
+
PINCTRL_PIN(44, "GPIO_44"),
157
+
PINCTRL_PIN(45, "GPIO_45"),
158
+
PINCTRL_PIN(46, "GPIO_46"),
159
+
PINCTRL_PIN(47, "GPIO_47"),
160
+
PINCTRL_PIN(48, "GPIO_48"),
161
+
PINCTRL_PIN(49, "GPIO_49"),
162
+
PINCTRL_PIN(50, "GPIO_50"),
163
+
PINCTRL_PIN(51, "GPIO_51"),
164
+
PINCTRL_PIN(52, "GPIO_52"),
165
+
PINCTRL_PIN(53, "GPIO_53"),
166
+
PINCTRL_PIN(54, "GPIO_54"),
167
+
PINCTRL_PIN(55, "GPIO_55"),
168
+
PINCTRL_PIN(56, "GPIO_56"),
169
+
PINCTRL_PIN(57, "GPIO_57"),
170
+
PINCTRL_PIN(58, "GPIO_58"),
171
+
PINCTRL_PIN(59, "GPIO_59"),
172
+
PINCTRL_PIN(60, "GPIO_60"),
173
+
PINCTRL_PIN(61, "GPIO_61"),
174
+
PINCTRL_PIN(62, "GPIO_62"),
175
+
PINCTRL_PIN(63, "GPIO_63"),
176
+
PINCTRL_PIN(64, "GPIO_64"),
177
+
PINCTRL_PIN(65, "GPIO_65"),
178
+
PINCTRL_PIN(66, "GPIO_66"),
179
+
PINCTRL_PIN(67, "GPIO_67"),
180
+
PINCTRL_PIN(68, "GPIO_68"),
181
+
PINCTRL_PIN(69, "GPIO_69"),
182
+
PINCTRL_PIN(70, "GPIO_70"),
183
+
PINCTRL_PIN(71, "GPIO_71"),
184
+
PINCTRL_PIN(72, "GPIO_72"),
185
+
PINCTRL_PIN(73, "GPIO_73"),
186
+
PINCTRL_PIN(74, "GPIO_74"),
187
+
PINCTRL_PIN(75, "GPIO_75"),
188
+
PINCTRL_PIN(76, "GPIO_76"),
189
+
PINCTRL_PIN(77, "GPIO_77"),
190
+
PINCTRL_PIN(78, "GPIO_78"),
191
+
PINCTRL_PIN(79, "GPIO_79"),
192
+
PINCTRL_PIN(80, "GPIO_80"),
193
+
PINCTRL_PIN(81, "GPIO_81"),
194
+
PINCTRL_PIN(82, "GPIO_82"),
195
+
PINCTRL_PIN(83, "GPIO_83"),
196
+
PINCTRL_PIN(84, "GPIO_84"),
197
+
PINCTRL_PIN(85, "GPIO_85"),
198
+
PINCTRL_PIN(86, "GPIO_86"),
199
+
PINCTRL_PIN(87, "GPIO_87"),
200
+
PINCTRL_PIN(88, "GPIO_88"),
201
+
PINCTRL_PIN(89, "GPIO_89"),
202
+
PINCTRL_PIN(90, "GPIO_90"),
203
+
PINCTRL_PIN(91, "GPIO_91"),
204
+
PINCTRL_PIN(92, "GPIO_92"),
205
+
PINCTRL_PIN(93, "GPIO_93"),
206
+
PINCTRL_PIN(94, "GPIO_94"),
207
+
PINCTRL_PIN(95, "GPIO_95"),
208
+
PINCTRL_PIN(96, "GPIO_96"),
209
+
PINCTRL_PIN(97, "GPIO_97"),
210
+
PINCTRL_PIN(98, "GPIO_98"),
211
+
PINCTRL_PIN(99, "GPIO_99"),
212
+
PINCTRL_PIN(100, "GPIO_100"),
213
+
PINCTRL_PIN(101, "GPIO_101"),
214
+
PINCTRL_PIN(102, "GPIO_102"),
215
+
PINCTRL_PIN(103, "GPIO_103"),
216
+
PINCTRL_PIN(104, "GPIO_104"),
217
+
PINCTRL_PIN(105, "GPIO_105"),
218
+
PINCTRL_PIN(106, "GPIO_106"),
219
+
PINCTRL_PIN(107, "GPIO_107"),
220
+
PINCTRL_PIN(108, "GPIO_108"),
221
+
PINCTRL_PIN(109, "GPIO_109"),
222
+
PINCTRL_PIN(110, "GPIO_110"),
223
+
PINCTRL_PIN(111, "GPIO_111"),
224
+
PINCTRL_PIN(112, "GPIO_112"),
225
+
PINCTRL_PIN(113, "GPIO_113"),
226
+
PINCTRL_PIN(114, "GPIO_114"),
227
+
PINCTRL_PIN(115, "GPIO_115"),
228
+
PINCTRL_PIN(116, "GPIO_116"),
229
+
PINCTRL_PIN(117, "GPIO_117"),
230
+
PINCTRL_PIN(118, "GPIO_118"),
231
+
PINCTRL_PIN(119, "GPIO_119"),
232
+
PINCTRL_PIN(120, "GPIO_120"),
233
+
PINCTRL_PIN(121, "GPIO_121"),
234
+
PINCTRL_PIN(122, "GPIO_122"),
235
+
PINCTRL_PIN(123, "GPIO_123"),
236
+
PINCTRL_PIN(124, "GPIO_124"),
237
+
PINCTRL_PIN(125, "GPIO_125"),
238
+
PINCTRL_PIN(126, "GPIO_126"),
239
+
PINCTRL_PIN(127, "GPIO_127"),
240
+
PINCTRL_PIN(128, "GPIO_128"),
241
+
PINCTRL_PIN(129, "GPIO_129"),
242
+
PINCTRL_PIN(130, "GPIO_130"),
243
+
PINCTRL_PIN(131, "GPIO_131"),
244
+
PINCTRL_PIN(132, "GPIO_132"),
245
+
PINCTRL_PIN(133, "GPIO_133"),
246
+
PINCTRL_PIN(134, "GPIO_134"),
247
+
PINCTRL_PIN(135, "GPIO_135"),
248
+
PINCTRL_PIN(136, "GPIO_136"),
249
+
PINCTRL_PIN(137, "GPIO_137"),
250
+
PINCTRL_PIN(138, "GPIO_138"),
251
+
PINCTRL_PIN(139, "GPIO_139"),
252
+
PINCTRL_PIN(140, "GPIO_140"),
253
+
PINCTRL_PIN(141, "GPIO_141"),
254
+
PINCTRL_PIN(142, "GPIO_142"),
255
+
PINCTRL_PIN(143, "GPIO_143"),
256
+
PINCTRL_PIN(144, "GPIO_144"),
257
+
PINCTRL_PIN(145, "GPIO_145"),
258
+
PINCTRL_PIN(146, "GPIO_146"),
259
+
PINCTRL_PIN(147, "GPIO_147"),
260
+
PINCTRL_PIN(148, "GPIO_148"),
261
+
PINCTRL_PIN(149, "GPIO_149"),
262
+
PINCTRL_PIN(150, "GPIO_150"),
263
+
PINCTRL_PIN(151, "GPIO_151"),
264
+
PINCTRL_PIN(152, "GPIO_152"),
265
+
PINCTRL_PIN(153, "GPIO_153"),
266
+
PINCTRL_PIN(154, "GPIO_154"),
267
+
PINCTRL_PIN(155, "GPIO_155"),
268
+
PINCTRL_PIN(156, "GPIO_156"),
269
+
PINCTRL_PIN(157, "GPIO_157"),
270
+
PINCTRL_PIN(158, "GPIO_158"),
271
+
PINCTRL_PIN(159, "GPIO_159"),
272
+
PINCTRL_PIN(160, "GPIO_160"),
273
+
PINCTRL_PIN(161, "GPIO_161"),
274
+
PINCTRL_PIN(162, "GPIO_162"),
275
+
PINCTRL_PIN(163, "GPIO_163"),
276
+
PINCTRL_PIN(164, "GPIO_164"),
277
+
PINCTRL_PIN(165, "GPIO_165"),
278
+
PINCTRL_PIN(166, "GPIO_166"),
279
+
PINCTRL_PIN(167, "UFS_RESET"),
280
+
PINCTRL_PIN(168, "SDC2_CLK"),
281
+
PINCTRL_PIN(169, "SDC2_CMD"),
282
+
PINCTRL_PIN(170, "SDC2_DATA"),
283
+
};
284
+
285
+
#define DECLARE_MSM_GPIO_PINS(pin) \
286
+
static const unsigned int gpio##pin##_pins[] = { pin }
287
+
DECLARE_MSM_GPIO_PINS(0);
288
+
DECLARE_MSM_GPIO_PINS(1);
289
+
DECLARE_MSM_GPIO_PINS(2);
290
+
DECLARE_MSM_GPIO_PINS(3);
291
+
DECLARE_MSM_GPIO_PINS(4);
292
+
DECLARE_MSM_GPIO_PINS(5);
293
+
DECLARE_MSM_GPIO_PINS(6);
294
+
DECLARE_MSM_GPIO_PINS(7);
295
+
DECLARE_MSM_GPIO_PINS(8);
296
+
DECLARE_MSM_GPIO_PINS(9);
297
+
DECLARE_MSM_GPIO_PINS(10);
298
+
DECLARE_MSM_GPIO_PINS(11);
299
+
DECLARE_MSM_GPIO_PINS(12);
300
+
DECLARE_MSM_GPIO_PINS(13);
301
+
DECLARE_MSM_GPIO_PINS(14);
302
+
DECLARE_MSM_GPIO_PINS(15);
303
+
DECLARE_MSM_GPIO_PINS(16);
304
+
DECLARE_MSM_GPIO_PINS(17);
305
+
DECLARE_MSM_GPIO_PINS(18);
306
+
DECLARE_MSM_GPIO_PINS(19);
307
+
DECLARE_MSM_GPIO_PINS(20);
308
+
DECLARE_MSM_GPIO_PINS(21);
309
+
DECLARE_MSM_GPIO_PINS(22);
310
+
DECLARE_MSM_GPIO_PINS(23);
311
+
DECLARE_MSM_GPIO_PINS(24);
312
+
DECLARE_MSM_GPIO_PINS(25);
313
+
DECLARE_MSM_GPIO_PINS(26);
314
+
DECLARE_MSM_GPIO_PINS(27);
315
+
DECLARE_MSM_GPIO_PINS(28);
316
+
DECLARE_MSM_GPIO_PINS(29);
317
+
DECLARE_MSM_GPIO_PINS(30);
318
+
DECLARE_MSM_GPIO_PINS(31);
319
+
DECLARE_MSM_GPIO_PINS(32);
320
+
DECLARE_MSM_GPIO_PINS(33);
321
+
DECLARE_MSM_GPIO_PINS(34);
322
+
DECLARE_MSM_GPIO_PINS(35);
323
+
DECLARE_MSM_GPIO_PINS(36);
324
+
DECLARE_MSM_GPIO_PINS(37);
325
+
DECLARE_MSM_GPIO_PINS(38);
326
+
DECLARE_MSM_GPIO_PINS(39);
327
+
DECLARE_MSM_GPIO_PINS(40);
328
+
DECLARE_MSM_GPIO_PINS(41);
329
+
DECLARE_MSM_GPIO_PINS(42);
330
+
DECLARE_MSM_GPIO_PINS(43);
331
+
DECLARE_MSM_GPIO_PINS(44);
332
+
DECLARE_MSM_GPIO_PINS(45);
333
+
DECLARE_MSM_GPIO_PINS(46);
334
+
DECLARE_MSM_GPIO_PINS(47);
335
+
DECLARE_MSM_GPIO_PINS(48);
336
+
DECLARE_MSM_GPIO_PINS(49);
337
+
DECLARE_MSM_GPIO_PINS(50);
338
+
DECLARE_MSM_GPIO_PINS(51);
339
+
DECLARE_MSM_GPIO_PINS(52);
340
+
DECLARE_MSM_GPIO_PINS(53);
341
+
DECLARE_MSM_GPIO_PINS(54);
342
+
DECLARE_MSM_GPIO_PINS(55);
343
+
DECLARE_MSM_GPIO_PINS(56);
344
+
DECLARE_MSM_GPIO_PINS(57);
345
+
DECLARE_MSM_GPIO_PINS(58);
346
+
DECLARE_MSM_GPIO_PINS(59);
347
+
DECLARE_MSM_GPIO_PINS(60);
348
+
DECLARE_MSM_GPIO_PINS(61);
349
+
DECLARE_MSM_GPIO_PINS(62);
350
+
DECLARE_MSM_GPIO_PINS(63);
351
+
DECLARE_MSM_GPIO_PINS(64);
352
+
DECLARE_MSM_GPIO_PINS(65);
353
+
DECLARE_MSM_GPIO_PINS(66);
354
+
DECLARE_MSM_GPIO_PINS(67);
355
+
DECLARE_MSM_GPIO_PINS(68);
356
+
DECLARE_MSM_GPIO_PINS(69);
357
+
DECLARE_MSM_GPIO_PINS(70);
358
+
DECLARE_MSM_GPIO_PINS(71);
359
+
DECLARE_MSM_GPIO_PINS(72);
360
+
DECLARE_MSM_GPIO_PINS(73);
361
+
DECLARE_MSM_GPIO_PINS(74);
362
+
DECLARE_MSM_GPIO_PINS(75);
363
+
DECLARE_MSM_GPIO_PINS(76);
364
+
DECLARE_MSM_GPIO_PINS(77);
365
+
DECLARE_MSM_GPIO_PINS(78);
366
+
DECLARE_MSM_GPIO_PINS(79);
367
+
DECLARE_MSM_GPIO_PINS(80);
368
+
DECLARE_MSM_GPIO_PINS(81);
369
+
DECLARE_MSM_GPIO_PINS(82);
370
+
DECLARE_MSM_GPIO_PINS(83);
371
+
DECLARE_MSM_GPIO_PINS(84);
372
+
DECLARE_MSM_GPIO_PINS(85);
373
+
DECLARE_MSM_GPIO_PINS(86);
374
+
DECLARE_MSM_GPIO_PINS(87);
375
+
DECLARE_MSM_GPIO_PINS(88);
376
+
DECLARE_MSM_GPIO_PINS(89);
377
+
DECLARE_MSM_GPIO_PINS(90);
378
+
DECLARE_MSM_GPIO_PINS(91);
379
+
DECLARE_MSM_GPIO_PINS(92);
380
+
DECLARE_MSM_GPIO_PINS(93);
381
+
DECLARE_MSM_GPIO_PINS(94);
382
+
DECLARE_MSM_GPIO_PINS(95);
383
+
DECLARE_MSM_GPIO_PINS(96);
384
+
DECLARE_MSM_GPIO_PINS(97);
385
+
DECLARE_MSM_GPIO_PINS(98);
386
+
DECLARE_MSM_GPIO_PINS(99);
387
+
DECLARE_MSM_GPIO_PINS(100);
388
+
DECLARE_MSM_GPIO_PINS(101);
389
+
DECLARE_MSM_GPIO_PINS(102);
390
+
DECLARE_MSM_GPIO_PINS(103);
391
+
DECLARE_MSM_GPIO_PINS(104);
392
+
DECLARE_MSM_GPIO_PINS(105);
393
+
DECLARE_MSM_GPIO_PINS(106);
394
+
DECLARE_MSM_GPIO_PINS(107);
395
+
DECLARE_MSM_GPIO_PINS(108);
396
+
DECLARE_MSM_GPIO_PINS(109);
397
+
DECLARE_MSM_GPIO_PINS(110);
398
+
DECLARE_MSM_GPIO_PINS(111);
399
+
DECLARE_MSM_GPIO_PINS(112);
400
+
DECLARE_MSM_GPIO_PINS(113);
401
+
DECLARE_MSM_GPIO_PINS(114);
402
+
DECLARE_MSM_GPIO_PINS(115);
403
+
DECLARE_MSM_GPIO_PINS(116);
404
+
DECLARE_MSM_GPIO_PINS(117);
405
+
DECLARE_MSM_GPIO_PINS(118);
406
+
DECLARE_MSM_GPIO_PINS(119);
407
+
DECLARE_MSM_GPIO_PINS(120);
408
+
DECLARE_MSM_GPIO_PINS(121);
409
+
DECLARE_MSM_GPIO_PINS(122);
410
+
DECLARE_MSM_GPIO_PINS(123);
411
+
DECLARE_MSM_GPIO_PINS(124);
412
+
DECLARE_MSM_GPIO_PINS(125);
413
+
DECLARE_MSM_GPIO_PINS(126);
414
+
DECLARE_MSM_GPIO_PINS(127);
415
+
DECLARE_MSM_GPIO_PINS(128);
416
+
DECLARE_MSM_GPIO_PINS(129);
417
+
DECLARE_MSM_GPIO_PINS(130);
418
+
DECLARE_MSM_GPIO_PINS(131);
419
+
DECLARE_MSM_GPIO_PINS(132);
420
+
DECLARE_MSM_GPIO_PINS(133);
421
+
DECLARE_MSM_GPIO_PINS(134);
422
+
DECLARE_MSM_GPIO_PINS(135);
423
+
DECLARE_MSM_GPIO_PINS(136);
424
+
DECLARE_MSM_GPIO_PINS(137);
425
+
DECLARE_MSM_GPIO_PINS(138);
426
+
DECLARE_MSM_GPIO_PINS(139);
427
+
DECLARE_MSM_GPIO_PINS(140);
428
+
DECLARE_MSM_GPIO_PINS(141);
429
+
DECLARE_MSM_GPIO_PINS(142);
430
+
DECLARE_MSM_GPIO_PINS(143);
431
+
DECLARE_MSM_GPIO_PINS(144);
432
+
DECLARE_MSM_GPIO_PINS(145);
433
+
DECLARE_MSM_GPIO_PINS(146);
434
+
DECLARE_MSM_GPIO_PINS(147);
435
+
DECLARE_MSM_GPIO_PINS(148);
436
+
DECLARE_MSM_GPIO_PINS(149);
437
+
DECLARE_MSM_GPIO_PINS(150);
438
+
DECLARE_MSM_GPIO_PINS(151);
439
+
DECLARE_MSM_GPIO_PINS(152);
440
+
DECLARE_MSM_GPIO_PINS(153);
441
+
DECLARE_MSM_GPIO_PINS(154);
442
+
DECLARE_MSM_GPIO_PINS(155);
443
+
DECLARE_MSM_GPIO_PINS(156);
444
+
DECLARE_MSM_GPIO_PINS(157);
445
+
DECLARE_MSM_GPIO_PINS(158);
446
+
DECLARE_MSM_GPIO_PINS(159);
447
+
DECLARE_MSM_GPIO_PINS(160);
448
+
DECLARE_MSM_GPIO_PINS(161);
449
+
DECLARE_MSM_GPIO_PINS(162);
450
+
DECLARE_MSM_GPIO_PINS(163);
451
+
DECLARE_MSM_GPIO_PINS(164);
452
+
DECLARE_MSM_GPIO_PINS(165);
453
+
DECLARE_MSM_GPIO_PINS(166);
454
+
455
+
static const unsigned int ufs_reset_pins[] = { 167 };
456
+
static const unsigned int sdc2_clk_pins[] = { 168 };
457
+
static const unsigned int sdc2_cmd_pins[] = { 169 };
458
+
static const unsigned int sdc2_data_pins[] = { 170 };
459
+
460
+
enum milos_functions {
461
+
msm_mux_gpio,
462
+
msm_mux_aoss_cti,
463
+
msm_mux_atest_char,
464
+
msm_mux_atest_usb,
465
+
msm_mux_audio_ext_mclk0,
466
+
msm_mux_audio_ext_mclk1,
467
+
msm_mux_audio_ref_clk,
468
+
msm_mux_cam_mclk,
469
+
msm_mux_cci_async_in0,
470
+
msm_mux_cci_i2c_scl,
471
+
msm_mux_cci_i2c_sda,
472
+
msm_mux_cci_timer,
473
+
msm_mux_coex_uart1_rx,
474
+
msm_mux_coex_uart1_tx,
475
+
msm_mux_dbg_out_clk,
476
+
msm_mux_ddr_bist_complete,
477
+
msm_mux_ddr_bist_fail,
478
+
msm_mux_ddr_bist_start,
479
+
msm_mux_ddr_bist_stop,
480
+
msm_mux_ddr_pxi0,
481
+
msm_mux_ddr_pxi1,
482
+
msm_mux_dp0_hot,
483
+
msm_mux_egpio,
484
+
msm_mux_gcc_gp1,
485
+
msm_mux_gcc_gp2,
486
+
msm_mux_gcc_gp3,
487
+
msm_mux_host2wlan_sol,
488
+
msm_mux_i2s0_data0,
489
+
msm_mux_i2s0_data1,
490
+
msm_mux_i2s0_sck,
491
+
msm_mux_i2s0_ws,
492
+
msm_mux_ibi_i3c,
493
+
msm_mux_jitter_bist,
494
+
msm_mux_mdp_vsync,
495
+
msm_mux_mdp_vsync0_out,
496
+
msm_mux_mdp_vsync1_out,
497
+
msm_mux_mdp_vsync2_out,
498
+
msm_mux_mdp_vsync3_out,
499
+
msm_mux_mdp_vsync_e,
500
+
msm_mux_nav_gpio0,
501
+
msm_mux_nav_gpio1,
502
+
msm_mux_nav_gpio2,
503
+
msm_mux_pcie0_clk_req_n,
504
+
msm_mux_pcie1_clk_req_n,
505
+
msm_mux_phase_flag,
506
+
msm_mux_pll_bist_sync,
507
+
msm_mux_pll_clk_aux,
508
+
msm_mux_prng_rosc0,
509
+
msm_mux_prng_rosc1,
510
+
msm_mux_prng_rosc2,
511
+
msm_mux_prng_rosc3,
512
+
msm_mux_qdss_cti,
513
+
msm_mux_qdss_gpio,
514
+
msm_mux_qlink0_enable,
515
+
msm_mux_qlink0_request,
516
+
msm_mux_qlink0_wmss,
517
+
msm_mux_qlink1_enable,
518
+
msm_mux_qlink1_request,
519
+
msm_mux_qlink1_wmss,
520
+
msm_mux_qspi0,
521
+
msm_mux_qup0_se0,
522
+
msm_mux_qup0_se1,
523
+
msm_mux_qup0_se2,
524
+
msm_mux_qup0_se3,
525
+
msm_mux_qup0_se4,
526
+
msm_mux_qup0_se5,
527
+
msm_mux_qup0_se6,
528
+
msm_mux_qup1_se0,
529
+
msm_mux_qup1_se1,
530
+
msm_mux_qup1_se2,
531
+
msm_mux_qup1_se3,
532
+
msm_mux_qup1_se4,
533
+
msm_mux_qup1_se5,
534
+
msm_mux_qup1_se6,
535
+
msm_mux_resout_gpio_n,
536
+
msm_mux_sd_write_protect,
537
+
msm_mux_sdc1_clk,
538
+
msm_mux_sdc1_cmd,
539
+
msm_mux_sdc1_data,
540
+
msm_mux_sdc1_rclk,
541
+
msm_mux_sdc2_clk,
542
+
msm_mux_sdc2_cmd,
543
+
msm_mux_sdc2_data,
544
+
msm_mux_sdc2_fb_clk,
545
+
msm_mux_tb_trig_sdc1,
546
+
msm_mux_tb_trig_sdc2,
547
+
msm_mux_tgu_ch0_trigout,
548
+
msm_mux_tgu_ch1_trigout,
549
+
msm_mux_tmess_prng0,
550
+
msm_mux_tmess_prng1,
551
+
msm_mux_tmess_prng2,
552
+
msm_mux_tmess_prng3,
553
+
msm_mux_tsense_pwm1,
554
+
msm_mux_tsense_pwm2,
555
+
msm_mux_uim0_clk,
556
+
msm_mux_uim0_data,
557
+
msm_mux_uim0_present,
558
+
msm_mux_uim0_reset,
559
+
msm_mux_uim1_clk_mira,
560
+
msm_mux_uim1_clk_mirb,
561
+
msm_mux_uim1_data_mira,
562
+
msm_mux_uim1_data_mirb,
563
+
msm_mux_uim1_present_mira,
564
+
msm_mux_uim1_present_mirb,
565
+
msm_mux_uim1_reset_mira,
566
+
msm_mux_uim1_reset_mirb,
567
+
msm_mux_usb0_hs,
568
+
msm_mux_usb0_phy_ps,
569
+
msm_mux_vfr_0,
570
+
msm_mux_vfr_1,
571
+
msm_mux_vsense_trigger_mirnat,
572
+
msm_mux_wcn_sw,
573
+
msm_mux_wcn_sw_ctrl,
574
+
msm_mux__,
575
+
};
576
+
577
+
static const char *const gpio_groups[] = {
578
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
579
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
580
+
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
581
+
"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
582
+
"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
583
+
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
584
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
585
+
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
586
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
587
+
"gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
588
+
"gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
589
+
"gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
590
+
"gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
591
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
592
+
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
593
+
"gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
594
+
"gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
595
+
"gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
596
+
"gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
597
+
"gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
598
+
"gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
599
+
"gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
600
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
601
+
"gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
602
+
"gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
603
+
"gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
604
+
"gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
605
+
"gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
606
+
};
607
+
static const char *const resout_gpio_n_groups[] = {
608
+
"gpio39",
609
+
};
610
+
static const char *const sdc1_clk_groups[] = {
611
+
"gpio77",
612
+
};
613
+
static const char *const sdc1_cmd_groups[] = {
614
+
"gpio78",
615
+
};
616
+
static const char *const sdc1_data_groups[] = {
617
+
"gpio73", "gpio74", "gpio75", "gpio76", "gpio79", "gpio80",
618
+
"gpio81", "gpio82",
619
+
};
620
+
static const char *const sdc1_rclk_groups[] = {
621
+
"gpio72",
622
+
};
623
+
static const char *const aoss_cti_groups[] = {
624
+
"gpio0",
625
+
"gpio1",
626
+
"gpio4",
627
+
"gpio5",
628
+
};
629
+
static const char *const atest_char_groups[] = {
630
+
"gpio44", "gpio45", "gpio46", "gpio47", "gpio63",
631
+
};
632
+
static const char *const atest_usb_groups[] = {
633
+
"gpio23", "gpio24", "gpio60",
634
+
};
635
+
static const char *const audio_ext_mclk0_groups[] = {
636
+
"gpio23",
637
+
};
638
+
static const char *const audio_ext_mclk1_groups[] = {
639
+
"gpio24",
640
+
};
641
+
static const char *const audio_ref_clk_groups[] = {
642
+
"gpio24",
643
+
};
644
+
static const char *const cam_mclk_groups[] = {
645
+
"gpio83", "gpio84", "gpio85", "gpio86", "gpio87",
646
+
};
647
+
static const char *const cci_async_in0_groups[] = {
648
+
"gpio86",
649
+
};
650
+
static const char *const cci_i2c_scl_groups[] = {
651
+
"gpio89", "gpio91", "gpio93", "gpio95",
652
+
};
653
+
static const char *const cci_i2c_sda_groups[] = {
654
+
"gpio88", "gpio90", "gpio92", "gpio94",
655
+
};
656
+
static const char *const cci_timer_groups[] = {
657
+
"gpio77", "gpio83", "gpio84", "gpio85",
658
+
};
659
+
static const char *const coex_uart1_rx_groups[] = {
660
+
"gpio64",
661
+
};
662
+
static const char *const coex_uart1_tx_groups[] = {
663
+
"gpio63",
664
+
};
665
+
static const char *const dbg_out_clk_groups[] = {
666
+
"gpio24",
667
+
};
668
+
static const char *const ddr_bist_complete_groups[] = {
669
+
"gpio137",
670
+
};
671
+
static const char *const ddr_bist_fail_groups[] = {
672
+
"gpio56",
673
+
};
674
+
static const char *const ddr_bist_start_groups[] = {
675
+
"gpio133",
676
+
};
677
+
static const char *const ddr_bist_stop_groups[] = {
678
+
"gpio47",
679
+
};
680
+
static const char *const ddr_pxi0_groups[] = {
681
+
"gpio23",
682
+
"gpio24",
683
+
};
684
+
static const char *const ddr_pxi1_groups[] = {
685
+
"gpio50",
686
+
"gpio51",
687
+
};
688
+
static const char *const dp0_hot_groups[] = {
689
+
"gpio75",
690
+
};
691
+
static const char *const egpio_groups[] = {
692
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
693
+
"gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
694
+
"gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
695
+
"gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
696
+
"gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
697
+
"gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
698
+
};
699
+
static const char *const gcc_gp1_groups[] = {
700
+
"gpio29",
701
+
"gpio32",
702
+
};
703
+
static const char *const gcc_gp2_groups[] = {
704
+
"gpio28",
705
+
"gpio30",
706
+
};
707
+
static const char *const gcc_gp3_groups[] = {
708
+
"gpio31",
709
+
"gpio33",
710
+
};
711
+
static const char *const host2wlan_sol_groups[] = {
712
+
"gpio46",
713
+
};
714
+
static const char *const i2s0_data0_groups[] = {
715
+
"gpio16",
716
+
};
717
+
static const char *const i2s0_data1_groups[] = {
718
+
"gpio17",
719
+
};
720
+
static const char *const i2s0_sck_groups[] = {
721
+
"gpio15",
722
+
};
723
+
static const char *const i2s0_ws_groups[] = {
724
+
"gpio18",
725
+
};
726
+
static const char *const ibi_i3c_groups[] = {
727
+
"gpio0", "gpio1", "gpio4", "gpio5",
728
+
"gpio32", "gpio33", "gpio36", "gpio37",
729
+
};
730
+
static const char *const jitter_bist_groups[] = {
731
+
"gpio141",
732
+
};
733
+
static const char *const mdp_vsync_groups[] = {
734
+
"gpio19",
735
+
"gpio37",
736
+
"gpio72",
737
+
"gpio129",
738
+
};
739
+
static const char *const mdp_vsync0_out_groups[] = {
740
+
"gpio12",
741
+
};
742
+
static const char *const mdp_vsync1_out_groups[] = {
743
+
"gpio12",
744
+
};
745
+
static const char *const mdp_vsync2_out_groups[] = {
746
+
"gpio40",
747
+
};
748
+
static const char *const mdp_vsync3_out_groups[] = {
749
+
"gpio40",
750
+
};
751
+
static const char *const mdp_vsync_e_groups[] = {
752
+
"gpio45",
753
+
};
754
+
static const char *const nav_gpio0_groups[] = {
755
+
"gpio124",
756
+
};
757
+
static const char *const nav_gpio1_groups[] = {
758
+
"gpio125",
759
+
};
760
+
static const char *const nav_gpio2_groups[] = {
761
+
"gpio126",
762
+
};
763
+
static const char *const pcie0_clk_req_n_groups[] = {
764
+
"gpio67",
765
+
};
766
+
static const char *const pcie1_clk_req_n_groups[] = {
767
+
"gpio70",
768
+
};
769
+
static const char *const phase_flag_groups[] = {
770
+
"gpio8", "gpio9", "gpio11", "gpio12", "gpio13", "gpio14",
771
+
"gpio15", "gpio16", "gpio18", "gpio26", "gpio38", "gpio39",
772
+
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
773
+
"gpio46", "gpio47", "gpio48", "gpio49", "gpio63", "gpio64",
774
+
"gpio127", "gpio138", "gpio139", "gpio140", "gpio142", "gpio143",
775
+
"gpio144", "gpio147",
776
+
};
777
+
static const char *const pll_bist_sync_groups[] = {
778
+
"gpio26",
779
+
};
780
+
static const char *const pll_clk_aux_groups[] = {
781
+
"gpio36",
782
+
};
783
+
static const char *const prng_rosc0_groups[] = {
784
+
"gpio66",
785
+
};
786
+
static const char *const prng_rosc1_groups[] = {
787
+
"gpio67",
788
+
};
789
+
static const char *const prng_rosc2_groups[] = {
790
+
"gpio68",
791
+
};
792
+
static const char *const prng_rosc3_groups[] = {
793
+
"gpio69",
794
+
};
795
+
static const char *const qdss_cti_groups[] = {
796
+
"gpio4", "gpio5", "gpio6", "gpio7",
797
+
"gpio44", "gpio45", "gpio54", "gpio87",
798
+
};
799
+
static const char *const qdss_gpio_groups[] = {
800
+
"gpio40", "gpio41", "gpio42", "gpio43", "gpio46", "gpio47",
801
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
802
+
"gpio83", "gpio84", "gpio85", "gpio86", "gpio88", "gpio89",
803
+
"gpio138", "gpio139", "gpio140", "gpio141", "gpio149", "gpio150",
804
+
"gpio155", "gpio156", "gpio157", "gpio158", "gpio159", "gpio160",
805
+
"gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
806
+
};
807
+
static const char *const qlink0_enable_groups[] = {
808
+
"gpio105",
809
+
};
810
+
static const char *const qlink0_request_groups[] = {
811
+
"gpio104",
812
+
};
813
+
static const char *const qlink0_wmss_groups[] = {
814
+
"gpio106",
815
+
};
816
+
static const char *const qlink1_enable_groups[] = {
817
+
"gpio108",
818
+
};
819
+
static const char *const qlink1_request_groups[] = {
820
+
"gpio107",
821
+
};
822
+
static const char *const qlink1_wmss_groups[] = {
823
+
"gpio109",
824
+
};
825
+
static const char *const qspi0_groups[] = {
826
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
827
+
};
828
+
static const char *const qup0_se0_groups[] = {
829
+
"gpio0", "gpio1", "gpio2", "gpio3",
830
+
};
831
+
static const char *const qup0_se1_groups[] = {
832
+
"gpio4", "gpio5", "gpio6", "gpio7",
833
+
};
834
+
static const char *const qup0_se2_groups[] = {
835
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
836
+
};
837
+
static const char *const qup0_se3_groups[] = {
838
+
"gpio15", "gpio16", "gpio17", "gpio18", "gpio23", "gpio24", "gpio26",
839
+
};
840
+
static const char *const qup0_se4_groups[] = {
841
+
"gpio19", "gpio20", "gpio21", "gpio22",
842
+
};
843
+
static const char *const qup0_se5_groups[] = {
844
+
"gpio23", "gpio24", "gpio25", "gpio26",
845
+
};
846
+
static const char *const qup0_se6_groups[] = {
847
+
"gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
848
+
};
849
+
static const char *const qup1_se0_groups[] = {
850
+
"gpio32", "gpio33", "gpio94", "gpio95",
851
+
};
852
+
static const char *const qup1_se1_groups[] = {
853
+
"gpio36", "gpio37", "gpio38", "gpio39",
854
+
};
855
+
static const char *const qup1_se2_groups[] = {
856
+
"gpio36", "gpio37", "gpio38", "gpio40", "gpio41", "gpio42", "gpio43",
857
+
};
858
+
static const char *const qup1_se3_groups[] = {
859
+
"gpio92", "gpio93", "gpio94", "gpio95",
860
+
};
861
+
static const char *const qup1_se4_groups[] = {
862
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54",
863
+
};
864
+
static const char *const qup1_se5_groups[] = {
865
+
"gpio55", "gpio56", "gpio59", "gpio60",
866
+
};
867
+
static const char *const qup1_se6_groups[] = {
868
+
"gpio55", "gpio56", "gpio59", "gpio60", "gpio90", "gpio91",
869
+
};
870
+
static const char *const sd_write_protect_groups[] = {
871
+
"gpio4",
872
+
};
873
+
static const char *const sdc2_data_groups[] = {
874
+
"gpio34",
875
+
"gpio35",
876
+
"gpio57",
877
+
"gpio58",
878
+
};
879
+
static const char *const sdc2_clk_groups[] = {
880
+
"gpio62",
881
+
};
882
+
static const char *const sdc2_cmd_groups[] = {
883
+
"gpio61",
884
+
};
885
+
static const char *const sdc2_fb_clk_groups[] = {
886
+
"gpio128",
887
+
};
888
+
static const char *const tb_trig_sdc1_groups[] = {
889
+
"gpio87",
890
+
};
891
+
static const char *const tb_trig_sdc2_groups[] = {
892
+
"gpio78",
893
+
};
894
+
static const char *const tgu_ch0_trigout_groups[] = {
895
+
"gpio87",
896
+
};
897
+
static const char *const tgu_ch1_trigout_groups[] = {
898
+
"gpio88",
899
+
};
900
+
static const char *const tmess_prng0_groups[] = {
901
+
"gpio86",
902
+
};
903
+
static const char *const tmess_prng1_groups[] = {
904
+
"gpio83",
905
+
};
906
+
static const char *const tmess_prng2_groups[] = {
907
+
"gpio84",
908
+
};
909
+
static const char *const tmess_prng3_groups[] = {
910
+
"gpio85",
911
+
};
912
+
static const char *const tsense_pwm1_groups[] = {
913
+
"gpio17",
914
+
};
915
+
static const char *const tsense_pwm2_groups[] = {
916
+
"gpio17",
917
+
};
918
+
static const char *const uim0_clk_groups[] = {
919
+
"gpio97",
920
+
};
921
+
static const char *const uim0_data_groups[] = {
922
+
"gpio96",
923
+
};
924
+
static const char *const uim0_present_groups[] = {
925
+
"gpio99",
926
+
};
927
+
static const char *const uim0_reset_groups[] = {
928
+
"gpio98",
929
+
};
930
+
static const char *const uim1_clk_mira_groups[] = {
931
+
"gpio111",
932
+
};
933
+
static const char *const uim1_clk_mirb_groups[] = {
934
+
"gpio101",
935
+
};
936
+
static const char *const uim1_data_mira_groups[] = {
937
+
"gpio110",
938
+
};
939
+
static const char *const uim1_data_mirb_groups[] = {
940
+
"gpio100",
941
+
};
942
+
static const char *const uim1_present_mira_groups[] = {
943
+
"gpio113",
944
+
};
945
+
static const char *const uim1_present_mirb_groups[] = {
946
+
"gpio103",
947
+
};
948
+
static const char *const uim1_reset_mira_groups[] = {
949
+
"gpio112",
950
+
};
951
+
static const char *const uim1_reset_mirb_groups[] = {
952
+
"gpio102",
953
+
};
954
+
static const char *const usb0_hs_groups[] = {
955
+
"gpio125",
956
+
};
957
+
static const char *const usb0_phy_ps_groups[] = {
958
+
"gpio131",
959
+
};
960
+
static const char *const vfr_0_groups[] = {
961
+
"gpio56",
962
+
};
963
+
static const char *const vfr_1_groups[] = {
964
+
"gpio126",
965
+
};
966
+
static const char *const vsense_trigger_mirnat_groups[] = {
967
+
"gpio94",
968
+
};
969
+
static const char *const wcn_sw_groups[] = {
970
+
"gpio52",
971
+
};
972
+
static const char *const wcn_sw_ctrl_groups[] = {
973
+
"gpio45",
974
+
};
975
+
976
+
static const struct pinfunction milos_functions[] = {
977
+
MSM_PIN_FUNCTION(gpio),
978
+
MSM_PIN_FUNCTION(aoss_cti),
979
+
MSM_PIN_FUNCTION(atest_char),
980
+
MSM_PIN_FUNCTION(atest_usb),
981
+
MSM_PIN_FUNCTION(audio_ext_mclk0),
982
+
MSM_PIN_FUNCTION(audio_ext_mclk1),
983
+
MSM_PIN_FUNCTION(audio_ref_clk),
984
+
MSM_PIN_FUNCTION(cam_mclk),
985
+
MSM_PIN_FUNCTION(cci_async_in0),
986
+
MSM_PIN_FUNCTION(cci_i2c_scl),
987
+
MSM_PIN_FUNCTION(cci_i2c_sda),
988
+
MSM_PIN_FUNCTION(cci_timer),
989
+
MSM_PIN_FUNCTION(coex_uart1_rx),
990
+
MSM_PIN_FUNCTION(coex_uart1_tx),
991
+
MSM_PIN_FUNCTION(dbg_out_clk),
992
+
MSM_PIN_FUNCTION(ddr_bist_complete),
993
+
MSM_PIN_FUNCTION(ddr_bist_fail),
994
+
MSM_PIN_FUNCTION(ddr_bist_start),
995
+
MSM_PIN_FUNCTION(ddr_bist_stop),
996
+
MSM_PIN_FUNCTION(ddr_pxi0),
997
+
MSM_PIN_FUNCTION(ddr_pxi1),
998
+
MSM_PIN_FUNCTION(dp0_hot),
999
+
MSM_PIN_FUNCTION(egpio),
1000
+
MSM_PIN_FUNCTION(gcc_gp1),
1001
+
MSM_PIN_FUNCTION(gcc_gp2),
1002
+
MSM_PIN_FUNCTION(gcc_gp3),
1003
+
MSM_PIN_FUNCTION(host2wlan_sol),
1004
+
MSM_PIN_FUNCTION(i2s0_data0),
1005
+
MSM_PIN_FUNCTION(i2s0_data1),
1006
+
MSM_PIN_FUNCTION(i2s0_sck),
1007
+
MSM_PIN_FUNCTION(i2s0_ws),
1008
+
MSM_PIN_FUNCTION(ibi_i3c),
1009
+
MSM_PIN_FUNCTION(jitter_bist),
1010
+
MSM_PIN_FUNCTION(mdp_vsync),
1011
+
MSM_PIN_FUNCTION(mdp_vsync0_out),
1012
+
MSM_PIN_FUNCTION(mdp_vsync1_out),
1013
+
MSM_PIN_FUNCTION(mdp_vsync2_out),
1014
+
MSM_PIN_FUNCTION(mdp_vsync3_out),
1015
+
MSM_PIN_FUNCTION(mdp_vsync_e),
1016
+
MSM_PIN_FUNCTION(nav_gpio0),
1017
+
MSM_PIN_FUNCTION(nav_gpio1),
1018
+
MSM_PIN_FUNCTION(nav_gpio2),
1019
+
MSM_PIN_FUNCTION(pcie0_clk_req_n),
1020
+
MSM_PIN_FUNCTION(pcie1_clk_req_n),
1021
+
MSM_PIN_FUNCTION(phase_flag),
1022
+
MSM_PIN_FUNCTION(pll_bist_sync),
1023
+
MSM_PIN_FUNCTION(pll_clk_aux),
1024
+
MSM_PIN_FUNCTION(prng_rosc0),
1025
+
MSM_PIN_FUNCTION(prng_rosc1),
1026
+
MSM_PIN_FUNCTION(prng_rosc2),
1027
+
MSM_PIN_FUNCTION(prng_rosc3),
1028
+
MSM_PIN_FUNCTION(qdss_cti),
1029
+
MSM_PIN_FUNCTION(qdss_gpio),
1030
+
MSM_PIN_FUNCTION(qlink0_enable),
1031
+
MSM_PIN_FUNCTION(qlink0_request),
1032
+
MSM_PIN_FUNCTION(qlink0_wmss),
1033
+
MSM_PIN_FUNCTION(qlink1_enable),
1034
+
MSM_PIN_FUNCTION(qlink1_request),
1035
+
MSM_PIN_FUNCTION(qlink1_wmss),
1036
+
MSM_PIN_FUNCTION(qspi0),
1037
+
MSM_PIN_FUNCTION(qup0_se0),
1038
+
MSM_PIN_FUNCTION(qup0_se1),
1039
+
MSM_PIN_FUNCTION(qup0_se2),
1040
+
MSM_PIN_FUNCTION(qup0_se3),
1041
+
MSM_PIN_FUNCTION(qup0_se4),
1042
+
MSM_PIN_FUNCTION(qup0_se5),
1043
+
MSM_PIN_FUNCTION(qup0_se6),
1044
+
MSM_PIN_FUNCTION(qup1_se0),
1045
+
MSM_PIN_FUNCTION(qup1_se1),
1046
+
MSM_PIN_FUNCTION(qup1_se2),
1047
+
MSM_PIN_FUNCTION(qup1_se3),
1048
+
MSM_PIN_FUNCTION(qup1_se4),
1049
+
MSM_PIN_FUNCTION(qup1_se5),
1050
+
MSM_PIN_FUNCTION(qup1_se6),
1051
+
MSM_PIN_FUNCTION(resout_gpio_n),
1052
+
MSM_PIN_FUNCTION(sd_write_protect),
1053
+
MSM_PIN_FUNCTION(sdc1_clk),
1054
+
MSM_PIN_FUNCTION(sdc1_cmd),
1055
+
MSM_PIN_FUNCTION(sdc1_data),
1056
+
MSM_PIN_FUNCTION(sdc1_rclk),
1057
+
MSM_PIN_FUNCTION(sdc2_clk),
1058
+
MSM_PIN_FUNCTION(sdc2_cmd),
1059
+
MSM_PIN_FUNCTION(sdc2_data),
1060
+
MSM_PIN_FUNCTION(sdc2_fb_clk),
1061
+
MSM_PIN_FUNCTION(tb_trig_sdc1),
1062
+
MSM_PIN_FUNCTION(tb_trig_sdc2),
1063
+
MSM_PIN_FUNCTION(tgu_ch0_trigout),
1064
+
MSM_PIN_FUNCTION(tgu_ch1_trigout),
1065
+
MSM_PIN_FUNCTION(tmess_prng0),
1066
+
MSM_PIN_FUNCTION(tmess_prng1),
1067
+
MSM_PIN_FUNCTION(tmess_prng2),
1068
+
MSM_PIN_FUNCTION(tmess_prng3),
1069
+
MSM_PIN_FUNCTION(tsense_pwm1),
1070
+
MSM_PIN_FUNCTION(tsense_pwm2),
1071
+
MSM_PIN_FUNCTION(uim0_clk),
1072
+
MSM_PIN_FUNCTION(uim0_data),
1073
+
MSM_PIN_FUNCTION(uim0_present),
1074
+
MSM_PIN_FUNCTION(uim0_reset),
1075
+
MSM_PIN_FUNCTION(uim1_clk_mira),
1076
+
MSM_PIN_FUNCTION(uim1_clk_mirb),
1077
+
MSM_PIN_FUNCTION(uim1_data_mira),
1078
+
MSM_PIN_FUNCTION(uim1_data_mirb),
1079
+
MSM_PIN_FUNCTION(uim1_present_mira),
1080
+
MSM_PIN_FUNCTION(uim1_present_mirb),
1081
+
MSM_PIN_FUNCTION(uim1_reset_mira),
1082
+
MSM_PIN_FUNCTION(uim1_reset_mirb),
1083
+
MSM_PIN_FUNCTION(usb0_hs),
1084
+
MSM_PIN_FUNCTION(usb0_phy_ps),
1085
+
MSM_PIN_FUNCTION(vfr_0),
1086
+
MSM_PIN_FUNCTION(vfr_1),
1087
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1088
+
MSM_PIN_FUNCTION(wcn_sw),
1089
+
MSM_PIN_FUNCTION(wcn_sw_ctrl),
1090
+
};
1091
+
1092
+
/*
1093
+
* Every pin is maintained as a single group, and missing or non-existing pin
1094
+
* would be maintained as dummy group to synchronize pin group index with
1095
+
* pin descriptor registered with pinctrl core.
1096
+
* Clients would not be able to request these dummy pin groups.
1097
+
*/
1098
+
static const struct msm_pingroup milos_groups[] = {
1099
+
[0] = PINGROUP(0, qup0_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _),
1100
+
[1] = PINGROUP(1, qup0_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _),
1101
+
[2] = PINGROUP(2, qup0_se0, _, _, _, _, _, _, _, _, _, _),
1102
+
[3] = PINGROUP(3, qup0_se0, _, _, _, _, _, _, _, _, _, _),
1103
+
[4] = PINGROUP(4, qup0_se1, ibi_i3c, aoss_cti, sd_write_protect, qdss_cti, _, _, _, _, _, _),
1104
+
[5] = PINGROUP(5, qup0_se1, ibi_i3c, aoss_cti, qdss_cti, _, _, _, _, _, _, _),
1105
+
[6] = PINGROUP(6, qup0_se1, qdss_cti, _, _, _, _, _, _, _, _, _),
1106
+
[7] = PINGROUP(7, qup0_se1, qdss_cti, _, _, _, _, _, _, _, _, _),
1107
+
[8] = PINGROUP(8, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _),
1108
+
[9] = PINGROUP(9, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _),
1109
+
[10] = PINGROUP(10, qup0_se2, qspi0, _, _, _, _, _, _, _, _, _),
1110
+
[11] = PINGROUP(11, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _),
1111
+
[12] = PINGROUP(12, qup0_se2, qspi0, mdp_vsync0_out, mdp_vsync1_out, _, phase_flag, _, _, _, _, _),
1112
+
[13] = PINGROUP(13, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _),
1113
+
[14] = PINGROUP(14, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _),
1114
+
[15] = PINGROUP(15, qup0_se3, i2s0_sck, _, phase_flag, _, _, _, _, _, _, _),
1115
+
[16] = PINGROUP(16, qup0_se3, i2s0_data0, _, phase_flag, _, _, _, _, _, _, _),
1116
+
[17] = PINGROUP(17, qup0_se3, i2s0_data1, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _, _),
1117
+
[18] = PINGROUP(18, qup0_se3, i2s0_ws, _, phase_flag, _, _, _, _, _, _, _),
1118
+
[19] = PINGROUP(19, qup0_se4, mdp_vsync, _, _, _, _, _, _, _, _, _),
1119
+
[20] = PINGROUP(20, qup0_se4, _, _, _, _, _, _, _, _, _, _),
1120
+
[21] = PINGROUP(21, qup0_se4, _, _, _, _, _, _, _, _, _, _),
1121
+
[22] = PINGROUP(22, qup0_se4, _, _, _, _, _, _, _, _, _, _),
1122
+
[23] = PINGROUP(23, qup0_se5, qup0_se3, audio_ext_mclk0, _, atest_usb, ddr_pxi0, _, _, _, _, _),
1123
+
[24] = PINGROUP(24, qup0_se5, qup0_se3, audio_ext_mclk1, audio_ref_clk, dbg_out_clk, _, atest_usb, ddr_pxi0, _, _, _),
1124
+
[25] = PINGROUP(25, qup0_se5, _, _, _, _, _, _, _, _, _, _),
1125
+
[26] = PINGROUP(26, qup0_se5, qup0_se3, pll_bist_sync, _, phase_flag, _, _, _, _, _, _),
1126
+
[27] = PINGROUP(27, qup0_se6, _, _, _, _, _, _, _, _, _, _),
1127
+
[28] = PINGROUP(28, qup0_se6, gcc_gp2, _, _, _, _, _, _, _, _, _),
1128
+
[29] = PINGROUP(29, qup0_se6, gcc_gp1, _, _, _, _, _, _, _, _, _),
1129
+
[30] = PINGROUP(30, qup0_se6, gcc_gp2, _, _, _, _, _, _, _, _, _),
1130
+
[31] = PINGROUP(31, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _),
1131
+
[32] = PINGROUP(32, qup1_se0, ibi_i3c, gcc_gp1, _, _, _, _, _, _, _, _),
1132
+
[33] = PINGROUP(33, qup1_se0, ibi_i3c, gcc_gp3, _, _, _, _, _, _, _, _),
1133
+
[34] = PINGROUP(34, sdc2_data, _, _, _, _, _, _, _, _, _, _),
1134
+
[35] = PINGROUP(35, sdc2_data, _, _, _, _, _, _, _, _, _, _),
1135
+
[36] = PINGROUP(36, qup1_se1, qup1_se2, ibi_i3c, pll_clk_aux, _, _, _, _, _, _, _),
1136
+
[37] = PINGROUP(37, qup1_se1, qup1_se2, ibi_i3c, mdp_vsync, _, _, _, _, _, _, _),
1137
+
[38] = PINGROUP(38, qup1_se1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _),
1138
+
[39] = PINGROUP(39, qup1_se1, resout_gpio_n, _, phase_flag, _, _, _, _, _, _, _),
1139
+
[40] = PINGROUP(40, qup1_se2, mdp_vsync2_out, mdp_vsync3_out, _, phase_flag, qdss_gpio, _, _, _, _, _),
1140
+
[41] = PINGROUP(41, qup1_se2, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _),
1141
+
[42] = PINGROUP(42, qup1_se2, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _),
1142
+
[43] = PINGROUP(43, qup1_se2, _, _, phase_flag, qdss_gpio, _, _, _, _, _, _),
1143
+
[44] = PINGROUP(44, _, _, phase_flag, qdss_cti, atest_char, _, _, _, _, _, _),
1144
+
[45] = PINGROUP(45, wcn_sw_ctrl, mdp_vsync_e, _, _, phase_flag, qdss_cti, atest_char, _, _, _, _),
1145
+
[46] = PINGROUP(46, host2wlan_sol, _, phase_flag, qdss_gpio, atest_char, _, _, _, _, _, _),
1146
+
[47] = PINGROUP(47, ddr_bist_stop, _, phase_flag, qdss_gpio, atest_char, _, _, _, _, _, _),
1147
+
[48] = PINGROUP(48, qup1_se4, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _),
1148
+
[49] = PINGROUP(49, qup1_se4, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _),
1149
+
[50] = PINGROUP(50, qup1_se4, qdss_gpio, ddr_pxi1, _, _, _, _, _, _, _, _),
1150
+
[51] = PINGROUP(51, qup1_se4, qdss_gpio, ddr_pxi1, _, _, _, _, _, _, _, _),
1151
+
[52] = PINGROUP(52, qup1_se4, wcn_sw, qdss_gpio, _, _, _, _, _, _, _, _),
1152
+
[53] = PINGROUP(53, qup1_se4, qdss_gpio, _, _, _, _, _, _, _, _, _),
1153
+
[54] = PINGROUP(54, qup1_se4, qdss_cti, _, _, _, _, _, _, _, _, _),
1154
+
[55] = PINGROUP(55, qup1_se5, qup1_se6, _, _, _, _, _, _, _, _, _),
1155
+
[56] = PINGROUP(56, qup1_se5, qup1_se6, vfr_0, ddr_bist_fail, _, _, _, _, _, _, _),
1156
+
[57] = PINGROUP(57, sdc2_data, _, _, _, _, _, _, _, _, _, _),
1157
+
[58] = PINGROUP(58, sdc2_data, _, _, _, _, _, _, _, _, _, _),
1158
+
[59] = PINGROUP(59, qup1_se6, _, qup1_se5, _, _, _, _, _, _, _, _),
1159
+
[60] = PINGROUP(60, qup1_se6, _, qup1_se5, atest_usb, _, _, _, _, _, _, _),
1160
+
[61] = PINGROUP(61, sdc2_cmd, _, _, _, _, _, _, _, _, _, _),
1161
+
[62] = PINGROUP(62, sdc2_clk, _, _, _, _, _, _, _, _, _, _),
1162
+
[63] = PINGROUP(63, coex_uart1_tx, _, phase_flag, atest_char, _, _, _, _, _, _, _),
1163
+
[64] = PINGROUP(64, coex_uart1_rx, _, phase_flag, _, _, _, _, _, _, _, _),
1164
+
[65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _),
1165
+
[66] = PINGROUP(66, prng_rosc0, _, _, _, _, _, _, _, _, _, _),
1166
+
[67] = PINGROUP(67, pcie0_clk_req_n, prng_rosc1, _, _, _, _, _, _, _, _, _),
1167
+
[68] = PINGROUP(68, prng_rosc2, _, _, _, _, _, _, _, _, _, _),
1168
+
[69] = PINGROUP(69, prng_rosc3, _, _, _, _, _, _, _, _, _, _),
1169
+
[70] = PINGROUP(70, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1170
+
[71] = PINGROUP(71, _, _, _, _, _, _, _, _, _, _, _),
1171
+
[72] = PINGROUP(72, sdc1_rclk, mdp_vsync, _, _, _, _, _, _, _, _, _),
1172
+
[73] = PINGROUP(73, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1173
+
[74] = PINGROUP(74, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1174
+
[75] = PINGROUP(75, sdc1_data, dp0_hot, _, _, _, _, _, _, _, _, _),
1175
+
[76] = PINGROUP(76, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1176
+
[77] = PINGROUP(77, sdc1_clk, cci_timer, _, _, _, _, _, _, _, _, _),
1177
+
[78] = PINGROUP(78, sdc1_cmd, tb_trig_sdc2, _, _, _, _, _, _, _, _, _),
1178
+
[79] = PINGROUP(79, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1179
+
[80] = PINGROUP(80, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1180
+
[81] = PINGROUP(81, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1181
+
[82] = PINGROUP(82, sdc1_data, _, _, _, _, _, _, _, _, _, _),
1182
+
[83] = PINGROUP(83, cam_mclk, cci_timer, tmess_prng1, qdss_gpio, _, _, _, _, _, _, _),
1183
+
[84] = PINGROUP(84, cam_mclk, cci_timer, tmess_prng2, qdss_gpio, _, _, _, _, _, _, _),
1184
+
[85] = PINGROUP(85, cam_mclk, cci_timer, tmess_prng3, qdss_gpio, _, _, _, _, _, _, _),
1185
+
[86] = PINGROUP(86, cam_mclk, cci_async_in0, tmess_prng0, qdss_gpio, _, _, _, _, _, _, _),
1186
+
[87] = PINGROUP(87, cam_mclk, tb_trig_sdc1, tgu_ch0_trigout, qdss_cti, _, _, _, _, _, _, _),
1187
+
[88] = PINGROUP(88, cci_i2c_sda, tgu_ch1_trigout, _, qdss_gpio, _, _, _, _, _, _, _),
1188
+
[89] = PINGROUP(89, cci_i2c_scl, _, qdss_gpio, _, _, _, _, _, _, _, _),
1189
+
[90] = PINGROUP(90, cci_i2c_sda, qup1_se6, _, _, _, _, _, _, _, _, _),
1190
+
[91] = PINGROUP(91, cci_i2c_scl, qup1_se6, _, _, _, _, _, _, _, _, _),
1191
+
[92] = PINGROUP(92, cci_i2c_sda, qup1_se3, _, _, _, _, _, _, _, _, _),
1192
+
[93] = PINGROUP(93, cci_i2c_scl, qup1_se3, _, _, _, _, _, _, _, _, _),
1193
+
[94] = PINGROUP(94, cci_i2c_sda, qup1_se3, qup1_se0, _, vsense_trigger_mirnat, _, _, _, _, _, _),
1194
+
[95] = PINGROUP(95, cci_i2c_scl, qup1_se3, qup1_se0, _, _, _, _, _, _, _, _),
1195
+
[96] = PINGROUP(96, uim0_data, _, _, _, _, _, _, _, _, _, _),
1196
+
[97] = PINGROUP(97, uim0_clk, _, _, _, _, _, _, _, _, _, _),
1197
+
[98] = PINGROUP(98, uim0_reset, _, _, _, _, _, _, _, _, _, _),
1198
+
[99] = PINGROUP(99, uim0_present, _, _, _, _, _, _, _, _, _, _),
1199
+
[100] = PINGROUP(100, uim1_data_mirb, _, _, _, _, _, _, _, _, _, _),
1200
+
[101] = PINGROUP(101, uim1_clk_mirb, _, _, _, _, _, _, _, _, _, _),
1201
+
[102] = PINGROUP(102, uim1_reset_mirb, _, _, _, _, _, _, _, _, _, _),
1202
+
[103] = PINGROUP(103, uim1_present_mirb, _, _, _, _, _, _, _, _, _, _),
1203
+
[104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _, _, _),
1204
+
[105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _, _, _),
1205
+
[106] = PINGROUP(106, qlink0_wmss, _, _, _, _, _, _, _, _, _, _),
1206
+
[107] = PINGROUP(107, qlink1_request, _, _, _, _, _, _, _, _, _, _),
1207
+
[108] = PINGROUP(108, qlink1_enable, _, _, _, _, _, _, _, _, _, _),
1208
+
[109] = PINGROUP(109, qlink1_wmss, _, _, _, _, _, _, _, _, _, _),
1209
+
[110] = PINGROUP(110, uim1_data_mira, _, _, _, _, _, _, _, _, _, _),
1210
+
[111] = PINGROUP(111, uim1_clk_mira, _, _, _, _, _, _, _, _, _, _),
1211
+
[112] = PINGROUP(112, uim1_reset_mira, _, _, _, _, _, _, _, _, _, _),
1212
+
[113] = PINGROUP(113, uim1_present_mira, _, _, _, _, _, _, _, _, _, _),
1213
+
[114] = PINGROUP(114, _, _, _, _, _, _, _, _, _, _, _),
1214
+
[115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, _),
1215
+
[116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _),
1216
+
[117] = PINGROUP(117, _, _, _, _, _, _, _, _, _, _, _),
1217
+
[118] = PINGROUP(118, _, _, _, _, _, _, _, _, _, _, _),
1218
+
[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _),
1219
+
[120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _, _),
1220
+
[121] = PINGROUP(121, _, _, _, _, _, _, _, _, _, _, _),
1221
+
[122] = PINGROUP(122, _, _, _, _, _, _, _, _, _, _, _),
1222
+
[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, _),
1223
+
[124] = PINGROUP(124, nav_gpio0, _, _, _, _, _, _, _, _, _, _),
1224
+
[125] = PINGROUP(125, nav_gpio1, usb0_hs, _, _, _, _, _, _, _, _, _),
1225
+
[126] = PINGROUP(126, _, nav_gpio2, vfr_1, _, _, _, _, _, _, _, _),
1226
+
[127] = PINGROUP(127, _, _, phase_flag, _, _, _, _, _, _, _, _),
1227
+
[128] = PINGROUP(128, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),
1228
+
[129] = PINGROUP(129, mdp_vsync, _, _, _, _, _, _, _, _, _, _),
1229
+
[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, _),
1230
+
[131] = PINGROUP(131, usb0_phy_ps, _, _, _, _, _, _, _, _, _, _),
1231
+
[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio),
1232
+
[133] = PINGROUP(133, ddr_bist_start, _, _, _, _, _, _, _, _, _, egpio),
1233
+
[134] = PINGROUP(134, _, _, _, _, _, _, _, _, _, _, egpio),
1234
+
[135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, egpio),
1235
+
[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, egpio),
1236
+
[137] = PINGROUP(137, ddr_bist_complete, _, _, _, _, _, _, _, _, _, egpio),
1237
+
[138] = PINGROUP(138, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio),
1238
+
[139] = PINGROUP(139, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio),
1239
+
[140] = PINGROUP(140, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio),
1240
+
[141] = PINGROUP(141, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1241
+
[142] = PINGROUP(142, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1242
+
[143] = PINGROUP(143, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1243
+
[144] = PINGROUP(144, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1244
+
[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _, _, egpio),
1245
+
[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _, _, egpio),
1246
+
[147] = PINGROUP(147, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1247
+
[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio),
1248
+
[149] = PINGROUP(149, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1249
+
[150] = PINGROUP(150, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1250
+
[151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio),
1251
+
[152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio),
1252
+
[153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio),
1253
+
[154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, egpio),
1254
+
[155] = PINGROUP(155, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1255
+
[156] = PINGROUP(156, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1256
+
[157] = PINGROUP(157, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1257
+
[158] = PINGROUP(158, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1258
+
[159] = PINGROUP(159, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1259
+
[160] = PINGROUP(160, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1260
+
[161] = PINGROUP(161, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1261
+
[162] = PINGROUP(162, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1262
+
[163] = PINGROUP(163, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1263
+
[164] = PINGROUP(164, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1264
+
[165] = PINGROUP(165, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1265
+
[166] = PINGROUP(166, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1266
+
[167] = UFS_RESET(ufs_reset, 0xb4004, 0xb5000),
1267
+
[168] = SDC_QDSD_PINGROUP(sdc2_clk, 0xab000, 0, 6),
1268
+
[169] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xab000, 12, 3),
1269
+
[170] = SDC_QDSD_PINGROUP(sdc2_data, 0xab000, 9, 0),
1270
+
};
1271
+
1272
+
static const struct msm_gpio_wakeirq_map milos_pdc_map[] = {
1273
+
{ 0, 122 }, { 3, 95 }, { 4, 100 }, { 6, 52 }, { 7, 119 },
1274
+
{ 8, 92 }, { 11, 54 }, { 12, 56 }, { 13, 64 }, { 14, 75 },
1275
+
{ 15, 82 }, { 18, 89 }, { 19, 90 }, { 22, 93 }, { 23, 94 },
1276
+
{ 26, 91 }, { 27, 57 }, { 30, 138 }, { 31, 96 }, { 32, 67 },
1277
+
{ 34, 128 }, { 35, 98 }, { 36, 99 }, { 38, 101 }, { 39, 102 },
1278
+
{ 40, 69 }, { 43, 103 }, { 44, 104 }, { 45, 126 }, { 47, 59 },
1279
+
{ 48, 106 }, { 51, 107 }, { 52, 108 }, { 54, 110 }, { 55, 140 },
1280
+
{ 56, 58 }, { 57, 129 }, { 58, 111 }, { 59, 112 }, { 60, 115 },
1281
+
{ 61, 113 }, { 62, 114 }, { 64, 105 }, { 65, 55 }, { 67, 116 },
1282
+
{ 68, 117 }, { 70, 120 }, { 71, 121 }, { 72, 97 }, { 73, 109 },
1283
+
{ 74, 118 }, { 75, 132 }, { 76, 144 }, { 77, 127 }, { 78, 133 },
1284
+
{ 79, 134 }, { 80, 135 }, { 81, 124 }, { 82, 136 }, { 87, 60 },
1285
+
{ 91, 123 }, { 92, 125 }, { 95, 139 }, { 99, 53 }, { 103, 61 },
1286
+
{ 104, 71 }, { 107, 137 }, { 113, 51 }, { 124, 72 }, { 125, 62 },
1287
+
{ 126, 73 }, { 128, 63 }, { 129, 130 }, { 130, 65 }, { 131, 66 },
1288
+
{ 133, 68 }, { 136, 70 }, { 143, 78 }, { 144, 79 }, { 145, 142 },
1289
+
{ 148, 81 }, { 149, 76 }, { 150, 83 }, { 151, 84 }, { 153, 74 },
1290
+
{ 155, 131 }, { 158, 85 }, { 159, 77 }, { 161, 80 }, { 162, 143 },
1291
+
{ 163, 86 }, { 164, 87 }, { 166, 88 },
1292
+
};
1293
+
1294
+
static const struct msm_pinctrl_soc_data milos_tlmm = {
1295
+
.pins = milos_pins,
1296
+
.npins = ARRAY_SIZE(milos_pins),
1297
+
.functions = milos_functions,
1298
+
.nfunctions = ARRAY_SIZE(milos_functions),
1299
+
.groups = milos_groups,
1300
+
.ngroups = ARRAY_SIZE(milos_groups),
1301
+
.ngpios = 168,
1302
+
.wakeirq_map = milos_pdc_map,
1303
+
.nwakeirq_map = ARRAY_SIZE(milos_pdc_map),
1304
+
.egpio_func = 11,
1305
+
};
1306
+
1307
+
static int milos_tlmm_probe(struct platform_device *pdev)
1308
+
{
1309
+
return msm_pinctrl_probe(pdev, &milos_tlmm);
1310
+
}
1311
+
1312
+
static const struct of_device_id milos_tlmm_of_match[] = {
1313
+
{ .compatible = "qcom,milos-tlmm" },
1314
+
{ /* sentinel */ }
1315
+
};
1316
+
1317
+
static struct platform_driver milos_tlmm_driver = {
1318
+
.driver = {
1319
+
.name = "milos-tlmm",
1320
+
.of_match_table = milos_tlmm_of_match,
1321
+
},
1322
+
.probe = milos_tlmm_probe,
1323
+
};
1324
+
1325
+
static int __init milos_tlmm_init(void)
1326
+
{
1327
+
return platform_driver_register(&milos_tlmm_driver);
1328
+
}
1329
+
arch_initcall(milos_tlmm_init);
1330
+
1331
+
static void __exit milos_tlmm_exit(void)
1332
+
{
1333
+
platform_driver_unregister(&milos_tlmm_driver);
1334
+
}
1335
+
module_exit(milos_tlmm_exit);
1336
+
1337
+
MODULE_DESCRIPTION("QTI Milos TLMM driver");
1338
+
MODULE_LICENSE("GPL");
1339
+
MODULE_DEVICE_TABLE(of, milos_tlmm_of_match);
+2
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+2
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
···
1206
1206
{ .compatible = "qcom,pm6450-gpio", .data = (void *) 9 },
1207
1207
{ .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
1208
1208
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1209
+
{ .compatible = "qcom,pm7550-gpio", .data = (void *) 12 },
1209
1210
{ .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8},
1210
1211
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1211
1212
{ .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
···
1245
1244
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1246
1245
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1247
1246
{ .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 },
1247
+
{ .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 },
1248
1248
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1249
1249
{ .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 },
1250
1250
{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
+46
-1
drivers/pinctrl/qcom/tlmm-test.c
+46
-1
drivers/pinctrl/qcom/tlmm-test.c
···
16
16
#include <linux/of_irq.h>
17
17
#include <linux/pinctrl/consumer.h>
18
18
#include <linux/platform_device.h>
19
+
#include <linux/slab.h>
19
20
20
21
/*
21
22
* This TLMM test module serves the purpose of validating that the TLMM driver
···
39
38
#define TLMM_REG_SIZE 0x1000
40
39
41
40
static int tlmm_test_gpio = -1;
41
+
static char *tlmm_reg_name = "default_region";
42
+
42
43
module_param_named(gpio, tlmm_test_gpio, int, 0600);
44
+
module_param_named(name, tlmm_reg_name, charp, 0600);
43
45
44
46
static struct {
45
47
void __iomem *base;
···
574
570
{}
575
571
};
576
572
573
+
static int tlmm_reg_base(struct device_node *tlmm, struct resource *res)
574
+
{
575
+
const char **reg_names;
576
+
int count;
577
+
int ret;
578
+
int i;
579
+
580
+
count = of_property_count_strings(tlmm, "reg-names");
581
+
if (count <= 0) {
582
+
pr_err("failed to find tlmm reg name\n");
583
+
return count;
584
+
}
585
+
586
+
reg_names = kcalloc(count, sizeof(char *), GFP_KERNEL);
587
+
if (!reg_names)
588
+
return -ENOMEM;
589
+
590
+
ret = of_property_read_string_array(tlmm, "reg-names", reg_names, count);
591
+
if (ret != count) {
592
+
kfree(reg_names);
593
+
return -EINVAL;
594
+
}
595
+
596
+
if (!strcmp(tlmm_reg_name, "default_region")) {
597
+
ret = of_address_to_resource(tlmm, 0, res);
598
+
} else {
599
+
for (i = 0; i < count; i++) {
600
+
if (!strcmp(reg_names[i], tlmm_reg_name)) {
601
+
ret = of_address_to_resource(tlmm, i, res);
602
+
break;
603
+
}
604
+
}
605
+
if (i == count)
606
+
ret = -EINVAL;
607
+
}
608
+
609
+
kfree(reg_names);
610
+
611
+
return ret;
612
+
}
613
+
577
614
static int tlmm_test_init_suite(struct kunit_suite *suite)
578
615
{
579
616
struct of_phandle_args args = {};
···
633
588
return -EINVAL;
634
589
}
635
590
636
-
ret = of_address_to_resource(tlmm, 0, &res);
591
+
ret = tlmm_reg_base(tlmm, &res);
637
592
if (ret < 0)
638
593
return ret;
639
594
+134
-135
drivers/pinctrl/renesas/Kconfig
+134
-135
drivers/pinctrl/renesas/Kconfig
···
86
86
bool "pin control support for Emma Mobile EV2" if COMPILE_TEST
87
87
select PINCTRL_SH_PFC
88
88
89
-
config PINCTRL_PFC_R8A77995
90
-
bool "pin control support for R-Car D3" if COMPILE_TEST
89
+
config PINCTRL_PFC_R8A73A4
90
+
bool "pin control support for R8A73A4 (R-Mobile APE6)" if COMPILE_TEST
91
+
select PINCTRL_SH_PFC_GPIO
92
+
93
+
config PINCTRL_PFC_R8A7740
94
+
bool "pin control support for R8A7740 (R-Mobile A1)" if COMPILE_TEST
95
+
select PINCTRL_SH_PFC_GPIO
96
+
97
+
config PINCTRL_PFC_R8A7742
98
+
bool "pin control support for R8A7742 (RZ/G1H)" if COMPILE_TEST
91
99
select PINCTRL_SH_PFC
92
100
93
-
config PINCTRL_PFC_R8A7794
94
-
bool "pin control support for R-Car E2" if COMPILE_TEST
101
+
config PINCTRL_PFC_R8A7743
102
+
bool "pin control support for R8A7743 (RZ/G1M)" if COMPILE_TEST
95
103
select PINCTRL_SH_PFC
96
104
97
-
config PINCTRL_PFC_R8A77990
98
-
bool "pin control support for R-Car E3" if COMPILE_TEST
105
+
config PINCTRL_PFC_R8A7744
106
+
bool "pin control support for R8A7744 (RZ/G1N)" if COMPILE_TEST
99
107
select PINCTRL_SH_PFC
100
108
101
-
config PINCTRL_PFC_R8A7779
102
-
bool "pin control support for R-Car H1" if COMPILE_TEST
109
+
config PINCTRL_PFC_R8A7745
110
+
bool "pin control support for R8A7745 (RZ/G1E)" if COMPILE_TEST
103
111
select PINCTRL_SH_PFC
104
112
105
-
config PINCTRL_PFC_R8A7790
106
-
bool "pin control support for R-Car H2" if COMPILE_TEST
113
+
config PINCTRL_PFC_R8A77470
114
+
bool "pin control support for R8A77470 (RZ/G1C)" if COMPILE_TEST
107
115
select PINCTRL_SH_PFC
108
116
109
-
config PINCTRL_PFC_R8A77951
110
-
bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST
117
+
config PINCTRL_PFC_R8A774A1
118
+
bool "pin control support for R8A774A1 (RZ/G2M)" if COMPILE_TEST
119
+
select PINCTRL_SH_PFC
120
+
121
+
config PINCTRL_PFC_R8A774B1
122
+
bool "pin control support for R8A774B1 (RZ/G2N)" if COMPILE_TEST
123
+
select PINCTRL_SH_PFC
124
+
125
+
config PINCTRL_PFC_R8A774C0
126
+
bool "pin control support for R8A774C0 (RZ/G2E)" if COMPILE_TEST
127
+
select PINCTRL_SH_PFC
128
+
129
+
config PINCTRL_PFC_R8A774E1
130
+
bool "pin control support for R8A774E1 (RZ/G2H)" if COMPILE_TEST
111
131
select PINCTRL_SH_PFC
112
132
113
133
config PINCTRL_PFC_R8A7778
114
-
bool "pin control support for R-Car M1A" if COMPILE_TEST
134
+
bool "pin control support for R8A7778 (R-Car M1A)" if COMPILE_TEST
115
135
select PINCTRL_SH_PFC
116
136
117
-
config PINCTRL_PFC_R8A7793
118
-
bool "pin control support for R-Car M2-N" if COMPILE_TEST
137
+
config PINCTRL_PFC_R8A7779
138
+
bool "pin control support for R8A7779 (R-Car H1)" if COMPILE_TEST
139
+
select PINCTRL_SH_PFC
140
+
141
+
config PINCTRL_PFC_R8A7790
142
+
bool "pin control support for R8A7790 (R-Car H2)" if COMPILE_TEST
119
143
select PINCTRL_SH_PFC
120
144
121
145
config PINCTRL_PFC_R8A7791
122
-
bool "pin control support for R-Car M2-W" if COMPILE_TEST
123
-
select PINCTRL_SH_PFC
124
-
125
-
config PINCTRL_PFC_R8A77965
126
-
bool "pin control support for R-Car M3-N" if COMPILE_TEST
127
-
select PINCTRL_SH_PFC
128
-
129
-
config PINCTRL_PFC_R8A77960
130
-
bool "pin control support for R-Car M3-W" if COMPILE_TEST
131
-
select PINCTRL_SH_PFC
132
-
133
-
config PINCTRL_PFC_R8A77961
134
-
bool "pin control support for R-Car M3-W+" if COMPILE_TEST
135
-
select PINCTRL_SH_PFC
136
-
137
-
config PINCTRL_PFC_R8A779F0
138
-
bool "pin control support for R-Car S4-8" if COMPILE_TEST
146
+
bool "pin control support for R8A7791 (R-Car M2-W)" if COMPILE_TEST
139
147
select PINCTRL_SH_PFC
140
148
141
149
config PINCTRL_PFC_R8A7792
142
-
bool "pin control support for R-Car V2H" if COMPILE_TEST
150
+
bool "pin control support for R8A7792 (R-Car V2H)" if COMPILE_TEST
143
151
select PINCTRL_SH_PFC
144
152
145
-
config PINCTRL_PFC_R8A77980
146
-
bool "pin control support for R-Car V3H" if COMPILE_TEST
153
+
config PINCTRL_PFC_R8A7793
154
+
bool "pin control support for R8A7793 (R-Car M2-N)" if COMPILE_TEST
155
+
select PINCTRL_SH_PFC
156
+
157
+
config PINCTRL_PFC_R8A7794
158
+
bool "pin control support for R8A7794 (R-Car E2)" if COMPILE_TEST
159
+
select PINCTRL_SH_PFC
160
+
161
+
config PINCTRL_PFC_R8A77951
162
+
bool "pin control support for R8A77951 (R-Car H3 ES2.0+)" if COMPILE_TEST
163
+
select PINCTRL_SH_PFC
164
+
165
+
config PINCTRL_PFC_R8A77960
166
+
bool "pin control support for R8A77960 (R-Car M3-W)" if COMPILE_TEST
167
+
select PINCTRL_SH_PFC
168
+
169
+
config PINCTRL_PFC_R8A77961
170
+
bool "pin control support for R8A77961 (R-Car M3-W+)" if COMPILE_TEST
171
+
select PINCTRL_SH_PFC
172
+
173
+
config PINCTRL_PFC_R8A77965
174
+
bool "pin control support for R8A77965 (R-Car M3-N)" if COMPILE_TEST
147
175
select PINCTRL_SH_PFC
148
176
149
177
config PINCTRL_PFC_R8A77970
150
-
bool "pin control support for R-Car V3M" if COMPILE_TEST
178
+
bool "pin control support for R8A77970 (R-Car V3M)" if COMPILE_TEST
179
+
select PINCTRL_SH_PFC
180
+
181
+
config PINCTRL_PFC_R8A77980
182
+
bool "pin control support for R8A77980 (R-Car V3H)" if COMPILE_TEST
183
+
select PINCTRL_SH_PFC
184
+
185
+
config PINCTRL_PFC_R8A77990
186
+
bool "pin control support for R8A77990 (R-Car E3)" if COMPILE_TEST
187
+
select PINCTRL_SH_PFC
188
+
189
+
config PINCTRL_PFC_R8A77995
190
+
bool "pin control support for R8A77995 (R-Car D3)" if COMPILE_TEST
151
191
select PINCTRL_SH_PFC
152
192
153
193
config PINCTRL_PFC_R8A779A0
154
-
bool "pin control support for R-Car V3U" if COMPILE_TEST
194
+
bool "pin control support for R8A779A0 (R-Car V3U)" if COMPILE_TEST
195
+
select PINCTRL_SH_PFC
196
+
197
+
config PINCTRL_PFC_R8A779F0
198
+
bool "pin control support for R8A779F0 (R-Car S4-8)" if COMPILE_TEST
155
199
select PINCTRL_SH_PFC
156
200
157
201
config PINCTRL_PFC_R8A779G0
158
-
bool "pin control support for R-Car V4H" if COMPILE_TEST
202
+
bool "pin control support for R8A779G0 (R-Car V4H)" if COMPILE_TEST
159
203
select PINCTRL_SH_PFC
160
204
161
205
config PINCTRL_PFC_R8A779H0
162
-
bool "pin control support for R-Car V4M" if COMPILE_TEST
206
+
bool "pin control support for R8A779H0 (R-Car V4M)" if COMPILE_TEST
163
207
select PINCTRL_SH_PFC
164
208
165
-
config PINCTRL_PFC_R8A7740
166
-
bool "pin control support for R-Mobile A1" if COMPILE_TEST
167
-
select PINCTRL_SH_PFC_GPIO
209
+
config PINCTRL_PFC_SH7203
210
+
bool "pin control support for SH7203" if COMPILE_TEST
211
+
select PINCTRL_SH_FUNC_GPIO
168
212
169
-
config PINCTRL_PFC_R8A73A4
170
-
bool "pin control support for R-Mobile APE6" if COMPILE_TEST
213
+
config PINCTRL_PFC_SH7264
214
+
bool "pin control support for SH7264" if COMPILE_TEST
215
+
select PINCTRL_SH_FUNC_GPIO
216
+
217
+
config PINCTRL_PFC_SH7269
218
+
bool "pin control support for SH7269" if COMPILE_TEST
219
+
select PINCTRL_SH_FUNC_GPIO
220
+
221
+
config PINCTRL_PFC_SH73A0
222
+
bool "pin control support for SH73A0 (SH-Mobile AG5)" if COMPILE_TEST
171
223
select PINCTRL_SH_PFC_GPIO
224
+
select REGULATOR
225
+
226
+
config PINCTRL_PFC_SH7720
227
+
bool "pin control support for SH7720" if COMPILE_TEST
228
+
select PINCTRL_SH_FUNC_GPIO
229
+
230
+
config PINCTRL_PFC_SH7722
231
+
bool "pin control support for SH7722" if COMPILE_TEST
232
+
select PINCTRL_SH_FUNC_GPIO
233
+
234
+
config PINCTRL_PFC_SH7723
235
+
bool "pin control support for SH7723 (SH-Mobile R2)" if COMPILE_TEST
236
+
select PINCTRL_SH_FUNC_GPIO
237
+
238
+
config PINCTRL_PFC_SH7724
239
+
bool "pin control support for SH7724 (SH-Mobile R2R)" if COMPILE_TEST
240
+
select PINCTRL_SH_FUNC_GPIO
241
+
242
+
config PINCTRL_PFC_SH7734
243
+
bool "pin control support for SH7734" if COMPILE_TEST
244
+
select PINCTRL_SH_FUNC_GPIO
245
+
246
+
config PINCTRL_PFC_SH7757
247
+
bool "pin control support for SH7757" if COMPILE_TEST
248
+
select PINCTRL_SH_FUNC_GPIO
249
+
250
+
config PINCTRL_PFC_SH7785
251
+
bool "pin control support for SH7785" if COMPILE_TEST
252
+
select PINCTRL_SH_FUNC_GPIO
253
+
254
+
config PINCTRL_PFC_SH7786
255
+
bool "pin control support for SH7786" if COMPILE_TEST
256
+
select PINCTRL_SH_FUNC_GPIO
257
+
258
+
config PINCTRL_PFC_SHX3
259
+
bool "pin control support for SH-X3" if COMPILE_TEST
260
+
select PINCTRL_SH_FUNC_GPIO
172
261
173
262
config PINCTRL_RZA1
174
263
bool "pin control support for RZ/A1"
···
293
204
This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L}
294
205
platforms.
295
206
296
-
config PINCTRL_PFC_R8A77470
297
-
bool "pin control support for RZ/G1C" if COMPILE_TEST
298
-
select PINCTRL_SH_PFC
299
-
300
-
config PINCTRL_PFC_R8A7745
301
-
bool "pin control support for RZ/G1E" if COMPILE_TEST
302
-
select PINCTRL_SH_PFC
303
-
304
-
config PINCTRL_PFC_R8A7742
305
-
bool "pin control support for RZ/G1H" if COMPILE_TEST
306
-
select PINCTRL_SH_PFC
307
-
308
-
config PINCTRL_PFC_R8A7743
309
-
bool "pin control support for RZ/G1M" if COMPILE_TEST
310
-
select PINCTRL_SH_PFC
311
-
312
-
config PINCTRL_PFC_R8A7744
313
-
bool "pin control support for RZ/G1N" if COMPILE_TEST
314
-
select PINCTRL_SH_PFC
315
-
316
-
config PINCTRL_PFC_R8A774C0
317
-
bool "pin control support for RZ/G2E" if COMPILE_TEST
318
-
select PINCTRL_SH_PFC
319
-
320
-
config PINCTRL_PFC_R8A774E1
321
-
bool "pin control support for RZ/G2H" if COMPILE_TEST
322
-
select PINCTRL_SH_PFC
323
-
324
-
config PINCTRL_PFC_R8A774A1
325
-
bool "pin control support for RZ/G2M" if COMPILE_TEST
326
-
select PINCTRL_SH_PFC
327
-
328
-
config PINCTRL_PFC_R8A774B1
329
-
bool "pin control support for RZ/G2N" if COMPILE_TEST
330
-
select PINCTRL_SH_PFC
331
-
332
207
config PINCTRL_RZN1
333
208
bool "pin control support for RZ/N1"
334
209
depends on OF
···
303
250
This selects pinctrl driver for Renesas RZ/N1 devices.
304
251
305
252
config PINCTRL_RZV2M
306
-
bool "pin control support for RZ/V2M"
253
+
bool "pin control support for RZ/V2M" if COMPILE_TEST
307
254
depends on OF
308
-
depends on ARCH_R9A09G011 || COMPILE_TEST
309
255
select GPIOLIB
310
256
select GENERIC_PINCTRL_GROUPS
311
257
select GENERIC_PINMUX_FUNCTIONS
···
312
260
help
313
261
This selects GPIO and pinctrl driver for Renesas RZ/V2M
314
262
platforms.
315
-
316
-
config PINCTRL_PFC_SH7203
317
-
bool "pin control support for SH7203" if COMPILE_TEST
318
-
select PINCTRL_SH_FUNC_GPIO
319
-
320
-
config PINCTRL_PFC_SH7264
321
-
bool "pin control support for SH7264" if COMPILE_TEST
322
-
select PINCTRL_SH_FUNC_GPIO
323
-
324
-
config PINCTRL_PFC_SH7269
325
-
bool "pin control support for SH7269" if COMPILE_TEST
326
-
select PINCTRL_SH_FUNC_GPIO
327
-
328
-
config PINCTRL_PFC_SH7720
329
-
bool "pin control support for SH7720" if COMPILE_TEST
330
-
select PINCTRL_SH_FUNC_GPIO
331
-
332
-
config PINCTRL_PFC_SH7722
333
-
bool "pin control support for SH7722" if COMPILE_TEST
334
-
select PINCTRL_SH_FUNC_GPIO
335
-
336
-
config PINCTRL_PFC_SH7734
337
-
bool "pin control support for SH7734" if COMPILE_TEST
338
-
select PINCTRL_SH_FUNC_GPIO
339
-
340
-
config PINCTRL_PFC_SH7757
341
-
bool "pin control support for SH7757" if COMPILE_TEST
342
-
select PINCTRL_SH_FUNC_GPIO
343
-
344
-
config PINCTRL_PFC_SH7785
345
-
bool "pin control support for SH7785" if COMPILE_TEST
346
-
select PINCTRL_SH_FUNC_GPIO
347
-
348
-
config PINCTRL_PFC_SH7786
349
-
bool "pin control support for SH7786" if COMPILE_TEST
350
-
select PINCTRL_SH_FUNC_GPIO
351
-
352
-
config PINCTRL_PFC_SH73A0
353
-
bool "pin control support for SH-Mobile AG5" if COMPILE_TEST
354
-
select PINCTRL_SH_PFC_GPIO
355
-
select REGULATOR
356
-
357
-
config PINCTRL_PFC_SH7723
358
-
bool "pin control support for SH-Mobile R2" if COMPILE_TEST
359
-
select PINCTRL_SH_FUNC_GPIO
360
-
361
-
config PINCTRL_PFC_SH7724
362
-
bool "pin control support for SH-Mobile R2R" if COMPILE_TEST
363
-
select PINCTRL_SH_FUNC_GPIO
364
-
365
-
config PINCTRL_PFC_SHX3
366
-
bool "pin control support for SH-X3" if COMPILE_TEST
367
-
select PINCTRL_SH_FUNC_GPIO
368
263
369
264
endmenu
+4
-2
drivers/pinctrl/renesas/gpio.c
+4
-2
drivers/pinctrl/renesas/gpio.c
···
189
189
return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
190
190
}
191
191
192
-
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
192
+
static int gpio_pin_set(struct gpio_chip *gc, unsigned int offset, int value)
193
193
{
194
194
gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
195
+
196
+
return 0;
195
197
}
196
198
197
199
static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
···
234
232
gc->direction_input = gpio_pin_direction_input;
235
233
gc->get = gpio_pin_get;
236
234
gc->direction_output = gpio_pin_direction_output;
237
-
gc->set = gpio_pin_set;
235
+
gc->set_rv = gpio_pin_set;
238
236
gc->to_irq = gpio_pin_to_irq;
239
237
240
238
gc->label = pfc->info->name;
+4
-3
drivers/pinctrl/renesas/pinctrl-rza1.c
+4
-3
drivers/pinctrl/renesas/pinctrl-rza1.c
···
830
830
return rza1_pin_get(port, gpio);
831
831
}
832
832
833
-
static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
834
-
int value)
833
+
static int rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
835
834
{
836
835
struct rza1_port *port = gpiochip_get_data(chip);
837
836
838
837
rza1_pin_set(port, gpio, value);
838
+
839
+
return 0;
839
840
}
840
841
841
842
static const struct gpio_chip rza1_gpiochip_template = {
···
846
845
.direction_input = rza1_gpio_direction_input,
847
846
.direction_output = rza1_gpio_direction_output,
848
847
.get = rza1_gpio_get,
849
-
.set = rza1_gpio_set,
848
+
.set_rv = rza1_gpio_set,
850
849
};
851
850
/* ----------------------------------------------------------------------------
852
851
* pinctrl operations
+4
-3
drivers/pinctrl/renesas/pinctrl-rza2.c
+4
-3
drivers/pinctrl/renesas/pinctrl-rza2.c
···
172
172
return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
173
173
}
174
174
175
-
static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
176
-
int value)
175
+
static int rza2_chip_set(struct gpio_chip *chip, unsigned int offset, int value)
177
176
{
178
177
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
179
178
u8 port = RZA2_PIN_ID_TO_PORT(offset);
···
187
188
new_value &= ~BIT(pin);
188
189
189
190
writeb(new_value, priv->base + RZA2_PODR(port));
191
+
192
+
return 0;
190
193
}
191
194
192
195
static int rza2_chip_direction_output(struct gpio_chip *chip,
···
237
236
.direction_input = rza2_chip_direction_input,
238
237
.direction_output = rza2_chip_direction_output,
239
238
.get = rza2_chip_get,
240
-
.set = rza2_chip_set,
239
+
.set_rv = rza2_chip_set,
241
240
};
242
241
243
242
static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
+30
-23
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+30
-23
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
493
493
writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
494
494
}
495
495
496
+
static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,
497
+
u64 cfg, u32 port, u8 bit)
498
+
{
499
+
u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
500
+
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
501
+
u64 data;
502
+
503
+
if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
504
+
return -EINVAL;
505
+
506
+
data = pctrl->data->port_pin_configs[port];
507
+
if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
508
+
return -EINVAL;
509
+
510
+
return 0;
511
+
}
512
+
496
513
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
497
514
u8 pin, u8 off, u8 func)
498
515
{
···
553
536
unsigned int i, *psel_val;
554
537
struct group_desc *group;
555
538
const unsigned int *pins;
539
+
int ret;
556
540
557
541
func = pinmux_generic_get_function(pctldev, func_selector);
558
542
if (!func)
···
569
551
u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
570
552
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
571
553
u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
554
+
555
+
ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin);
556
+
if (ret)
557
+
return ret;
572
558
573
559
dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
574
560
RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
···
826
804
rzg2l_dt_free_map(pctldev, *map, *num_maps);
827
805
828
806
return ret;
829
-
}
830
-
831
-
static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
832
-
u64 cfg, u32 port, u8 bit)
833
-
{
834
-
u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
835
-
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
836
-
u64 data;
837
-
838
-
if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
839
-
return -EINVAL;
840
-
841
-
data = pctrl->data->port_pin_configs[port];
842
-
if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
843
-
return -EINVAL;
844
-
845
-
return 0;
846
807
}
847
808
848
809
static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
···
1292
1287
} else {
1293
1288
bit = RZG2L_PIN_ID_TO_PIN(_pin);
1294
1289
1295
-
if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1290
+
if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1296
1291
return -EINVAL;
1297
1292
}
1298
1293
···
1452
1447
} else {
1453
1448
bit = RZG2L_PIN_ID_TO_PIN(_pin);
1454
1449
1455
-
if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1450
+
if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1456
1451
return -EINVAL;
1457
1452
}
1458
1453
···
1692
1687
u8 reg8;
1693
1688
int ret;
1694
1689
1695
-
ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
1690
+
ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit);
1696
1691
if (ret)
1697
1692
return ret;
1698
1693
···
1763
1758
return 0;
1764
1759
}
1765
1760
1766
-
static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1767
-
int value)
1761
+
static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1762
+
int value)
1768
1763
{
1769
1764
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1770
1765
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
···
1784
1779
writeb(reg8 & ~BIT(bit), pctrl->base + P(off));
1785
1780
1786
1781
spin_unlock_irqrestore(&pctrl->lock, flags);
1782
+
1783
+
return 0;
1787
1784
}
1788
1785
1789
1786
static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
···
2795
2788
chip->direction_input = rzg2l_gpio_direction_input;
2796
2789
chip->direction_output = rzg2l_gpio_direction_output;
2797
2790
chip->get = rzg2l_gpio_get;
2798
-
chip->set = rzg2l_gpio_set;
2791
+
chip->set_rv = rzg2l_gpio_set;
2799
2792
chip->label = name;
2800
2793
chip->parent = pctrl->dev;
2801
2794
chip->owner = THIS_MODULE;
+2
-2
drivers/pinctrl/renesas/pinctrl-rzn1.c
+2
-2
drivers/pinctrl/renesas/pinctrl-rzn1.c
···
680
680
.pmxops = &rzn1_pmx_ops,
681
681
.confops = &rzn1_pinconf_ops,
682
682
.owner = THIS_MODULE,
683
+
.pins = rzn1_pins,
684
+
.npins = ARRAY_SIZE(rzn1_pins),
683
685
};
684
686
685
687
static int rzn1_pinctrl_parse_groups(struct device_node *np,
···
880
878
881
879
ipctl->dev = &pdev->dev;
882
880
rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
883
-
rzn1_pinctrl_desc.pins = rzn1_pins;
884
-
rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
885
881
886
882
ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
887
883
if (ret) {
+5
-3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+5
-3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
···
790
790
return 0;
791
791
}
792
792
793
-
static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
794
-
int value)
793
+
static int rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
794
+
int value)
795
795
{
796
796
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
797
797
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
798
798
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
799
799
800
800
rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
801
+
802
+
return 0;
801
803
}
802
804
803
805
static int rzv2m_gpio_direction_output(struct gpio_chip *chip,
···
957
955
chip->direction_input = rzv2m_gpio_direction_input;
958
956
chip->direction_output = rzv2m_gpio_direction_output;
959
957
chip->get = rzv2m_gpio_get;
960
-
chip->set = rzv2m_gpio_set;
958
+
chip->set_rv = rzv2m_gpio_set;
961
959
chip->label = name;
962
960
chip->parent = pctrl->dev;
963
961
chip->owner = THIS_MODULE;
+4
-2
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+4
-2
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
···
1405
1405
EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28),
1406
1406
};
1407
1407
1408
-
static const struct samsung_retention_data exynosautov920_retention_data __initconst = {
1408
+
static const struct samsung_retention_data no_retention_data __initconst = {
1409
1409
.regs = NULL,
1410
1410
.nr_regs = 0,
1411
1411
.value = 0,
···
1421
1421
.eint_wkup_init = exynos_eint_wkup_init,
1422
1422
.suspend = exynosautov920_pinctrl_suspend,
1423
1423
.resume = exynosautov920_pinctrl_resume,
1424
-
.retention_data = &exynosautov920_retention_data,
1424
+
.retention_data = &no_retention_data,
1425
1425
}, {
1426
1426
/* pin-controller instance 1 AUD data */
1427
1427
.pin_banks = exynosautov920_pin_banks1,
···
1764
1764
.eint_wkup_init = exynos_eint_wkup_init,
1765
1765
.suspend = gs101_pinctrl_suspend,
1766
1766
.resume = gs101_pinctrl_resume,
1767
+
.retention_data = &no_retention_data,
1767
1768
}, {
1768
1769
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
1769
1770
.pin_banks = gs101_pin_far_alive,
···
1772
1771
.eint_wkup_init = exynos_eint_wkup_init,
1773
1772
.suspend = gs101_pinctrl_suspend,
1774
1773
.resume = gs101_pinctrl_resume,
1774
+
.retention_data = &no_retention_data,
1775
1775
}, {
1776
1776
/* pin banks of gs101 pin-controller (GSACORE) */
1777
1777
.pin_banks = gs101_pin_gsacore,
+89
-14
drivers/pinctrl/samsung/pinctrl-exynos.c
+89
-14
drivers/pinctrl/samsung/pinctrl-exynos.c
···
32
32
#include "pinctrl-samsung.h"
33
33
#include "pinctrl-exynos.h"
34
34
35
+
#define MAX_WAKEUP_REG 3
36
+
35
37
struct exynos_irq_chip {
36
38
struct irq_chip chip;
37
39
38
40
u32 eint_con;
39
41
u32 eint_mask;
40
42
u32 eint_pend;
41
-
u32 *eint_wake_mask_value;
43
+
u32 eint_num_wakeup_reg;
42
44
u32 eint_wake_mask_reg;
43
45
void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata,
44
46
struct exynos_irq_chip *irq_chip);
45
47
};
48
+
49
+
static u32 eint_wake_mask_values[MAX_WAKEUP_REG] = { EXYNOS_EINT_WAKEUP_MASK_DISABLED,
50
+
EXYNOS_EINT_WAKEUP_MASK_DISABLED,
51
+
EXYNOS_EINT_WAKEUP_MASK_DISABLED};
46
52
47
53
static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
48
54
{
···
313
307
.eint_con = EXYNOS_GPIO_ECON_OFFSET,
314
308
.eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
315
309
.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
316
-
/* eint_wake_mask_value not used */
310
+
/* eint_wake_mask_values not used */
317
311
};
318
312
319
313
static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
···
473
467
return ret;
474
468
}
475
469
470
+
#define BITS_PER_U32 32
471
+
static int gs101_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
472
+
{
473
+
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
474
+
struct samsung_pinctrl_drv_data *d = bank->drvdata;
475
+
u32 bit, wakeup_reg, shift;
476
+
477
+
bit = bank->eint_num + irqd->hwirq;
478
+
wakeup_reg = bit / BITS_PER_U32;
479
+
shift = bit - (wakeup_reg * BITS_PER_U32);
480
+
481
+
if (!on)
482
+
eint_wake_mask_values[wakeup_reg] |= BIT_U32(shift);
483
+
else
484
+
eint_wake_mask_values[wakeup_reg] &= ~BIT_U32(shift);
485
+
486
+
dev_info(d->dev, "wake %s for irq %d\n", str_enabled_disabled(on),
487
+
irqd->irq);
488
+
489
+
return 0;
490
+
}
491
+
492
+
static void
493
+
gs101_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
494
+
struct exynos_irq_chip *irq_chip)
495
+
{
496
+
struct regmap *pmu_regs;
497
+
498
+
if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
499
+
dev_warn(drvdata->dev,
500
+
"No PMU syscon available. Wake-up mask will not be set.\n");
501
+
return;
502
+
}
503
+
504
+
pmu_regs = drvdata->retention_ctrl->priv;
505
+
506
+
dev_dbg(drvdata->dev, "Setting external wakeup interrupt mask:\n");
507
+
508
+
for (int i = 0; i < irq_chip->eint_num_wakeup_reg; i++) {
509
+
dev_dbg(drvdata->dev, "\tWAKEUP_MASK%d[0x%X] value[0x%X]\n",
510
+
i, irq_chip->eint_wake_mask_reg + i * 4,
511
+
eint_wake_mask_values[i]);
512
+
regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg + i * 4,
513
+
eint_wake_mask_values[i]);
514
+
}
515
+
}
516
+
476
517
static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
477
518
{
478
-
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
479
-
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
480
519
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
481
520
unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
482
521
···
529
478
irqd->irq, bank->name, irqd->hwirq);
530
479
531
480
if (!on)
532
-
*our_chip->eint_wake_mask_value |= bit;
481
+
eint_wake_mask_values[0] |= bit;
533
482
else
534
-
*our_chip->eint_wake_mask_value &= ~bit;
483
+
eint_wake_mask_values[0] &= ~bit;
535
484
536
485
return 0;
537
486
}
···
551
500
pmu_regs = drvdata->retention_ctrl->priv;
552
501
dev_info(drvdata->dev,
553
502
"Setting external wakeup interrupt mask: 0x%x\n",
554
-
*irq_chip->eint_wake_mask_value);
503
+
eint_wake_mask_values[0]);
555
504
556
505
regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
557
-
*irq_chip->eint_wake_mask_value);
506
+
eint_wake_mask_values[0]);
558
507
}
559
508
560
509
static void
···
573
522
574
523
clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
575
524
576
-
__raw_writel(*irq_chip->eint_wake_mask_value,
525
+
__raw_writel(eint_wake_mask_values[0],
577
526
clk_base + irq_chip->eint_wake_mask_reg);
578
527
}
579
528
580
-
static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED;
581
529
/*
582
530
* irq_chip for wakeup interrupts
583
531
*/
···
594
544
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
595
545
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
596
546
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
597
-
.eint_wake_mask_value = &eint_wake_mask_value,
547
+
.eint_num_wakeup_reg = 1,
598
548
/* Only differences with exynos4210_wkup_irq_chip: */
599
549
.eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
600
550
.set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask,
···
614
564
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
615
565
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
616
566
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
617
-
.eint_wake_mask_value = &eint_wake_mask_value,
567
+
.eint_num_wakeup_reg = 1,
618
568
.eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
619
569
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
620
570
};
···
633
583
.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
634
584
.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
635
585
.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
636
-
.eint_wake_mask_value = &eint_wake_mask_value,
586
+
.eint_num_wakeup_reg = 1,
637
587
.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
638
588
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
639
589
};
···
649
599
.irq_request_resources = exynos_irq_request_resources,
650
600
.irq_release_resources = exynos_irq_release_resources,
651
601
},
652
-
.eint_wake_mask_value = &eint_wake_mask_value,
602
+
.eint_num_wakeup_reg = 1,
653
603
.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
654
604
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
655
605
};
656
606
607
+
static const struct exynos_irq_chip gs101_wkup_irq_chip __initconst = {
608
+
.chip = {
609
+
.name = "gs101_wkup_irq_chip",
610
+
.irq_unmask = exynos_irq_unmask,
611
+
.irq_mask = exynos_irq_mask,
612
+
.irq_ack = exynos_irq_ack,
613
+
.irq_set_type = exynos_irq_set_type,
614
+
.irq_set_wake = gs101_wkup_irq_set_wake,
615
+
.irq_request_resources = exynos_irq_request_resources,
616
+
.irq_release_resources = exynos_irq_release_resources,
617
+
},
618
+
.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
619
+
.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
620
+
.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
621
+
.eint_num_wakeup_reg = 3,
622
+
.eint_wake_mask_reg = GS101_EINT_WAKEUP_MASK,
623
+
.set_eint_wakeup_mask = gs101_pinctrl_set_eint_wakeup_mask,
624
+
};
625
+
657
626
/* list of external wakeup controllers supported */
658
627
static const struct of_device_id exynos_wkup_irq_ids[] = {
628
+
{ .compatible = "google,gs101-wakeup-eint",
629
+
.data = &gs101_wkup_irq_chip },
659
630
{ .compatible = "samsung,s5pv210-wakeup-eint",
660
631
.data = &s5pv210_wkup_irq_chip },
661
632
{ .compatible = "samsung,exynos4210-wakeup-eint",
···
759
688
chained_irq_exit(chip, desc);
760
689
}
761
690
691
+
static int eint_num;
762
692
/*
763
693
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
764
694
* @d: driver data of samsung pinctrl driver.
···
807
735
dev_err(dev, "wkup irq domain add failed\n");
808
736
return -ENXIO;
809
737
}
738
+
739
+
bank->eint_num = eint_num;
740
+
eint_num = eint_num + bank->nr_pins;
810
741
811
742
if (!fwnode_property_present(bank->fwnode, "interrupts")) {
812
743
bank->eint_type = EINT_TYPE_WKUP_MUX;
+4
drivers/pinctrl/samsung/pinctrl-samsung.h
+4
drivers/pinctrl/samsung/pinctrl-samsung.h
···
141
141
* @eint_type: type of the external interrupt supported by the bank.
142
142
* @eint_mask: bit mask of pins which support EINT function.
143
143
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
144
+
* @eint_num: total number of eint pins.
144
145
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
145
146
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
146
147
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
···
157
156
enum eint_type eint_type;
158
157
u32 eint_mask;
159
158
u32 eint_offset;
159
+
u32 eint_num;
160
160
u32 eint_con_offset;
161
161
u32 eint_mask_offset;
162
162
u32 eint_pend_offset;
···
176
174
* @eint_type: type of the external interrupt supported by the bank.
177
175
* @eint_mask: bit mask of pins which support EINT function.
178
176
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
177
+
* @eint_num: total number of eint pins.
179
178
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
180
179
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
181
180
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
···
204
201
enum eint_type eint_type;
205
202
u32 eint_mask;
206
203
u32 eint_offset;
204
+
u32 eint_num;
207
205
u32 eint_con_offset;
208
206
u32 eint_mask_offset;
209
207
u32 eint_pend_offset;
+7
-4
drivers/pinctrl/spear/pinctrl-plgpio.c
+7
-4
drivers/pinctrl/spear/pinctrl-plgpio.c
···
181
181
return is_plgpio_set(plgpio->regmap, offset, plgpio->regs.rdata);
182
182
}
183
183
184
-
static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
184
+
static int plgpio_set_value(struct gpio_chip *chip, unsigned int offset,
185
+
int value)
185
186
{
186
187
struct plgpio *plgpio = gpiochip_get_data(chip);
187
188
188
189
if (offset >= chip->ngpio)
189
-
return;
190
+
return -EINVAL;
190
191
191
192
/* get correct offset for "offset" pin */
192
193
if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
193
194
offset = plgpio->p2o(offset);
194
195
if (offset == -1)
195
-
return;
196
+
return -EINVAL;
196
197
}
197
198
198
199
if (value)
199
200
plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.wdata);
200
201
else
201
202
plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.wdata);
203
+
204
+
return 0;
202
205
}
203
206
204
207
static int plgpio_request(struct gpio_chip *chip, unsigned offset)
···
582
579
plgpio->chip.direction_input = plgpio_direction_input;
583
580
plgpio->chip.direction_output = plgpio_direction_output;
584
581
plgpio->chip.get = plgpio_get_value;
585
-
plgpio->chip.set = plgpio_set_value;
582
+
plgpio->chip.set_rv = plgpio_set_value;
586
583
plgpio->chip.label = dev_name(&pdev->dev);
587
584
plgpio->chip.parent = &pdev->dev;
588
585
plgpio->chip.owner = THIS_MODULE;
+6
-4
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+6
-4
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
···
898
898
.is_generic = true,
899
899
};
900
900
901
-
static struct pinctrl_desc starfive_desc = {
901
+
static const struct pinctrl_desc starfive_desc = {
902
902
.name = DRIVER_NAME,
903
903
.pins = starfive_pins,
904
904
.npins = ARRAY_SIZE(starfive_pins),
···
969
969
return !!(readl_relaxed(din) & BIT(gpio % 32));
970
970
}
971
971
972
-
static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
973
-
int value)
972
+
static int starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
973
+
int value)
974
974
{
975
975
struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
976
976
void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
···
979
979
raw_spin_lock_irqsave(&sfp->lock, flags);
980
980
writel_relaxed(value, dout);
981
981
raw_spin_unlock_irqrestore(&sfp->lock, flags);
982
+
983
+
return 0;
982
984
}
983
985
984
986
static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
···
1302
1300
sfp->gc.direction_input = starfive_gpio_direction_input;
1303
1301
sfp->gc.direction_output = starfive_gpio_direction_output;
1304
1302
sfp->gc.get = starfive_gpio_get;
1305
-
sfp->gc.set = starfive_gpio_set;
1303
+
sfp->gc.set_rv = starfive_gpio_set;
1306
1304
sfp->gc.set_config = starfive_gpio_set_config;
1307
1305
sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1308
1306
sfp->gc.base = -1;
+4
-3
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+4
-3
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
···
608
608
return !!(readl_relaxed(reg) & BIT(gpio % 32));
609
609
}
610
610
611
-
static void jh7110_gpio_set(struct gpio_chip *gc,
612
-
unsigned int gpio, int value)
611
+
static int jh7110_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
613
612
{
614
613
struct jh7110_pinctrl *sfp = container_of(gc,
615
614
struct jh7110_pinctrl, gc);
···
624
625
dout |= readl_relaxed(reg_dout) & ~mask;
625
626
writel_relaxed(dout, reg_dout);
626
627
raw_spin_unlock_irqrestore(&sfp->lock, flags);
628
+
629
+
return 0;
627
630
}
628
631
629
632
static int jh7110_gpio_set_config(struct gpio_chip *gc,
···
935
934
sfp->gc.direction_input = jh7110_gpio_direction_input;
936
935
sfp->gc.direction_output = jh7110_gpio_direction_output;
937
936
sfp->gc.get = jh7110_gpio_get;
938
-
sfp->gc.set = jh7110_gpio_set;
937
+
sfp->gc.set_rv = jh7110_gpio_set;
939
938
sfp->gc.set_config = jh7110_gpio_set_config;
940
939
sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
941
940
sfp->gc.base = info->gc_base;
+17
-3
drivers/pinctrl/stm32/Kconfig
+17
-3
drivers/pinctrl/stm32/Kconfig
···
2
2
if ARCH_STM32 || COMPILE_TEST
3
3
4
4
config PINCTRL_STM32
5
-
bool
5
+
tristate
6
6
depends on OF
7
7
select PINMUX
8
8
select GENERIC_PINCONF
···
53
53
select PINCTRL_STM32
54
54
55
55
config PINCTRL_STM32MP257
56
-
bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25
56
+
tristate "STMicroelectronics STM32MP257 pin control"
57
57
depends on OF && HAS_IOMEM
58
-
default MACH_STM32MP25
58
+
default MACH_STM32MP25 || (ARCH_STM32 && ARM64)
59
59
select PINCTRL_STM32
60
+
61
+
config PINCTRL_STM32_HDP
62
+
tristate "STMicroelectronics STM32 Hardware Debug Port (HDP) pin control"
63
+
depends on OF && HAS_IOMEM
64
+
default ARCH_STM32 && !ARM_SINGLE_ARMV7M
65
+
select PINMUX
66
+
select GENERIC_PINCONF
67
+
select GPIOLIB
68
+
help
69
+
The Hardware Debug Port allows the observation of internal signals.
70
+
It uses configurable multiplexer to route signals in a dedicated observation register.
71
+
This driver also permits the observation of signals on external SoC pins.
72
+
It permits the observation of up to 16 signals per HDP line.
73
+
60
74
endif
+1
drivers/pinctrl/stm32/Makefile
+1
drivers/pinctrl/stm32/Makefile
+720
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
+720
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4
+
* Author: Clément Le Goffic <clement.legoffic@foss.st.com> for STMicroelectronics.
5
+
*/
6
+
#include <linux/bits.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/gpio/driver.h>
9
+
#include <linux/io.h>
10
+
#include <linux/of.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/pinctrl/consumer.h>
13
+
#include <linux/pinctrl/pinconf-generic.h>
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/pinctrl/pinmux.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/pm.h>
18
+
19
+
#include "../core.h"
20
+
21
+
#define DRIVER_NAME "stm32_hdp"
22
+
#define HDP_CTRL_ENABLE 1
23
+
#define HDP_CTRL_DISABLE 0
24
+
25
+
#define HDP_CTRL 0x000
26
+
#define HDP_MUX 0x004
27
+
#define HDP_VAL 0x010
28
+
#define HDP_GPOSET 0x014
29
+
#define HDP_GPOCLR 0x018
30
+
#define HDP_GPOVAL 0x01c
31
+
#define HDP_VERR 0x3f4
32
+
#define HDP_IPIDR 0x3f8
33
+
#define HDP_SIDR 0x3fc
34
+
35
+
#define HDP_MUX_SHIFT(n) ((n) * 4)
36
+
#define HDP_MUX_MASK(n) (GENMASK(3, 0) << HDP_MUX_SHIFT(n))
37
+
#define HDP_MUX_GPOVAL(n) (0xf << HDP_MUX_SHIFT(n))
38
+
39
+
#define HDP_PIN 8
40
+
#define HDP_FUNC 16
41
+
#define HDP_FUNC_TOTAL (HDP_PIN * HDP_FUNC)
42
+
43
+
struct stm32_hdp {
44
+
struct device *dev;
45
+
void __iomem *base;
46
+
struct clk *clk;
47
+
struct pinctrl_dev *pctl_dev;
48
+
struct gpio_chip gpio_chip;
49
+
u32 mux_conf;
50
+
u32 gposet_conf;
51
+
const char * const *func_name;
52
+
};
53
+
54
+
static const struct pinctrl_pin_desc stm32_hdp_pins[] = {
55
+
PINCTRL_PIN(0, "HDP0"),
56
+
PINCTRL_PIN(1, "HDP1"),
57
+
PINCTRL_PIN(2, "HDP2"),
58
+
PINCTRL_PIN(3, "HDP3"),
59
+
PINCTRL_PIN(4, "HDP4"),
60
+
PINCTRL_PIN(5, "HDP5"),
61
+
PINCTRL_PIN(6, "HDP6"),
62
+
PINCTRL_PIN(7, "HDP7"),
63
+
};
64
+
65
+
static const char * const func_name_mp13[] = {
66
+
//HDP0 functions:
67
+
"pwr_pwrwake_sys",
68
+
"pwr_stop_forbidden",
69
+
"pwr_stdby_wakeup",
70
+
"pwr_encomp_vddcore",
71
+
"bsec_out_sec_niden",
72
+
"aiec_sys_wakeup",
73
+
"none",
74
+
"none",
75
+
"ddrctrl_lp_req",
76
+
"pwr_ddr_ret_enable_n",
77
+
"dts_clk_ptat",
78
+
"none",
79
+
"sram3ctrl_tamp_erase_act",
80
+
"none",
81
+
"none",
82
+
"gpoval0",
83
+
//HDP1 functions:
84
+
"pwr_sel_vth_vddcpu",
85
+
"pwr_mpu_ram_lowspeed",
86
+
"ca7_naxierrirq",
87
+
"pwr_okin_mr",
88
+
"bsec_out_sec_dbgen",
89
+
"aiec_c1_wakeup",
90
+
"rcc_pwrds_mpu",
91
+
"none",
92
+
"ddrctrl_dfi_ctrlupd_req",
93
+
"ddrctrl_cactive_ddrc_asr",
94
+
"none",
95
+
"none",
96
+
"sram3ctrl_hw_erase_act",
97
+
"nic400_s0_bready",
98
+
"none",
99
+
"gpoval1",
100
+
//HDP2 functions:
101
+
"pwr_pwrwake_mpu",
102
+
"pwr_mpu_clock_disable_ack",
103
+
"ca7_ndbgreset_i",
104
+
"none",
105
+
"bsec_in_rstcore_n",
106
+
"bsec_out_sec_bsc_dis",
107
+
"none",
108
+
"none",
109
+
"ddrctrl_dfi_init_complete",
110
+
"ddrctrl_perf_op_is_refresh",
111
+
"ddrctrl_gskp_dfi_lp_req",
112
+
"none",
113
+
"sram3ctrl_sw_erase_act",
114
+
"nic400_s0_bvalid",
115
+
"none",
116
+
"gpoval2",
117
+
//HDP3 functions:
118
+
"pwr_sel_vth_vddcore",
119
+
"pwr_mpu_clock_disable_req",
120
+
"ca7_npmuirq0",
121
+
"ca7_nfiqout0",
122
+
"bsec_out_sec_dftlock",
123
+
"bsec_out_sec_jtag_dis",
124
+
"rcc_pwrds_sys",
125
+
"sram3ctrl_tamp_erase_req",
126
+
"ddrctrl_stat_ddrc_reg_selfref_type0",
127
+
"none",
128
+
"dts_valobus1_0",
129
+
"dts_valobus2_0",
130
+
"tamp_potential_tamp_erfcfg",
131
+
"nic400_s0_wready",
132
+
"nic400_s0_rready",
133
+
"gpoval3",
134
+
//HDP4 functions:
135
+
"none",
136
+
"pwr_stop2_active",
137
+
"ca7_nl2reset_i",
138
+
"ca7_npreset_varm_i",
139
+
"bsec_out_sec_dften",
140
+
"bsec_out_sec_dbgswenable",
141
+
"eth1_out_pmt_intr_o",
142
+
"eth2_out_pmt_intr_o",
143
+
"ddrctrl_stat_ddrc_reg_selfref_type1",
144
+
"ddrctrl_cactive_0",
145
+
"dts_valobus1_1",
146
+
"dts_valobus2_1",
147
+
"tamp_nreset_sram_ercfg",
148
+
"nic400_s0_wlast",
149
+
"nic400_s0_rlast",
150
+
"gpoval4",
151
+
//HDP5 functions:
152
+
"ca7_standbywfil2",
153
+
"pwr_vth_vddcore_ack",
154
+
"ca7_ncorereset_i",
155
+
"ca7_nirqout0",
156
+
"bsec_in_pwrok",
157
+
"bsec_out_sec_deviceen",
158
+
"eth1_out_lpi_intr_o",
159
+
"eth2_out_lpi_intr_o",
160
+
"ddrctrl_cactive_ddrc",
161
+
"ddrctrl_wr_credit_cnt",
162
+
"dts_valobus1_2",
163
+
"dts_valobus2_2",
164
+
"pka_pka_itamp_out",
165
+
"nic400_s0_wvalid",
166
+
"nic400_s0_rvalid",
167
+
"gpoval5",
168
+
//HDP6 functions:
169
+
"ca7_standbywfe0",
170
+
"pwr_vth_vddcpu_ack",
171
+
"ca7_evento",
172
+
"none",
173
+
"bsec_in_tamper_det",
174
+
"bsec_out_sec_spniden",
175
+
"eth1_out_mac_speed_o1",
176
+
"eth2_out_mac_speed_o1",
177
+
"ddrctrl_csysack_ddrc",
178
+
"ddrctrl_lpr_credit_cnt",
179
+
"dts_valobus1_3",
180
+
"dts_valobus2_3",
181
+
"saes_tamper_out",
182
+
"nic400_s0_awready",
183
+
"nic400_s0_arready",
184
+
"gpoval6",
185
+
//HDP7 functions:
186
+
"ca7_standbywfi0",
187
+
"pwr_rcc_vcpu_rdy",
188
+
"ca7_eventi",
189
+
"ca7_dbgack0",
190
+
"bsec_out_fuse_ok",
191
+
"bsec_out_sec_spiden",
192
+
"eth1_out_mac_speed_o0",
193
+
"eth2_out_mac_speed_o0",
194
+
"ddrctrl_csysreq_ddrc",
195
+
"ddrctrl_hpr_credit_cnt",
196
+
"dts_valobus1_4",
197
+
"dts_valobus2_4",
198
+
"rng_tamper_out",
199
+
"nic400_s0_awavalid",
200
+
"nic400_s0_aravalid",
201
+
"gpoval7",
202
+
};
203
+
204
+
static const char * const func_name_mp15[] = {
205
+
//HDP0 functions:
206
+
"pwr_pwrwake_sys",
207
+
"cm4_sleepdeep",
208
+
"pwr_stdby_wkup",
209
+
"pwr_encomp_vddcore",
210
+
"bsec_out_sec_niden",
211
+
"none",
212
+
"rcc_cm4_sleepdeep",
213
+
"gpu_dbg7",
214
+
"ddrctrl_lp_req",
215
+
"pwr_ddr_ret_enable_n",
216
+
"dts_clk_ptat",
217
+
"none",
218
+
"none",
219
+
"none",
220
+
"none",
221
+
"gpoval0",
222
+
//HDP1 functions:
223
+
"pwr_pwrwake_mcu",
224
+
"cm4_halted",
225
+
"ca7_naxierrirq",
226
+
"pwr_okin_mr",
227
+
"bsec_out_sec_dbgen",
228
+
"exti_sys_wakeup",
229
+
"rcc_pwrds_mpu",
230
+
"gpu_dbg6",
231
+
"ddrctrl_dfi_ctrlupd_req",
232
+
"ddrctrl_cactive_ddrc_asr",
233
+
"none",
234
+
"none",
235
+
"none",
236
+
"none",
237
+
"none",
238
+
"gpoval1",
239
+
//HDP2 functions:
240
+
"pwr_pwrwake_mpu",
241
+
"cm4_rxev",
242
+
"ca7_npmuirq1",
243
+
"ca7_nfiqout1",
244
+
"bsec_in_rstcore_n",
245
+
"exti_c2_wakeup",
246
+
"rcc_pwrds_mcu",
247
+
"gpu_dbg5",
248
+
"ddrctrl_dfi_init_complete",
249
+
"ddrctrl_perf_op_is_refresh",
250
+
"ddrctrl_gskp_dfi_lp_req",
251
+
"none",
252
+
"none",
253
+
"none",
254
+
"none",
255
+
"gpoval2",
256
+
//HDP3 functions:
257
+
"pwr_sel_vth_vddcore",
258
+
"cm4_txev",
259
+
"ca7_npmuirq0",
260
+
"ca7_nfiqout0",
261
+
"bsec_out_sec_dftlock",
262
+
"exti_c1_wakeup",
263
+
"rcc_pwrds_sys",
264
+
"gpu_dbg4",
265
+
"ddrctrl_stat_ddrc_reg_selfref_type0",
266
+
"ddrctrl_cactive_1",
267
+
"dts_valobus1_0",
268
+
"dts_valobus2_0",
269
+
"none",
270
+
"none",
271
+
"none",
272
+
"gpoval3",
273
+
//HDP4 functions:
274
+
"pwr_mpu_pdds_not_cstbydis",
275
+
"cm4_sleeping",
276
+
"ca7_nreset1",
277
+
"ca7_nirqout1",
278
+
"bsec_out_sec_dften",
279
+
"bsec_out_sec_dbgswenable",
280
+
"eth_out_pmt_intr_o",
281
+
"gpu_dbg3",
282
+
"ddrctrl_stat_ddrc_reg_selfref_type1",
283
+
"ddrctrl_cactive_0",
284
+
"dts_valobus1_1",
285
+
"dts_valobus2_1",
286
+
"none",
287
+
"none",
288
+
"none",
289
+
"gpoval4",
290
+
//HDP5 functions:
291
+
"ca7_standbywfil2",
292
+
"pwr_vth_vddcore_ack",
293
+
"ca7_nreset0",
294
+
"ca7_nirqout0",
295
+
"bsec_in_pwrok",
296
+
"bsec_out_sec_deviceen",
297
+
"eth_out_lpi_intr_o",
298
+
"gpu_dbg2",
299
+
"ddrctrl_cactive_ddrc",
300
+
"ddrctrl_wr_credit_cnt",
301
+
"dts_valobus1_2",
302
+
"dts_valobus2_2",
303
+
"none",
304
+
"none",
305
+
"none",
306
+
"gpoval5",
307
+
//HDP6 functions:
308
+
"ca7_standbywfi1",
309
+
"ca7_standbywfe1",
310
+
"ca7_evento",
311
+
"ca7_dbgack1",
312
+
"none",
313
+
"bsec_out_sec_spniden",
314
+
"eth_out_mac_speed_o1",
315
+
"gpu_dbg1",
316
+
"ddrctrl_csysack_ddrc",
317
+
"ddrctrl_lpr_credit_cnt",
318
+
"dts_valobus1_3",
319
+
"dts_valobus2_3",
320
+
"none",
321
+
"none",
322
+
"none",
323
+
"gpoval6",
324
+
//HDP7 functions:
325
+
"ca7_standbywfi0",
326
+
"ca7_standbywfe0",
327
+
"none",
328
+
"ca7_dbgack0",
329
+
"bsec_out_fuse_ok",
330
+
"bsec_out_sec_spiden",
331
+
"eth_out_mac_speed_o0",
332
+
"gpu_dbg0",
333
+
"ddrctrl_csysreq_ddrc",
334
+
"ddrctrl_hpr_credit_cnt",
335
+
"dts_valobus1_4",
336
+
"dts_valobus2_4",
337
+
"none",
338
+
"none",
339
+
"none",
340
+
"gpoval7"
341
+
};
342
+
343
+
static const char * const func_name_mp25[] = {
344
+
//HDP0 functions:
345
+
"pwr_pwrwake_sys",
346
+
"cpu2_sleep_deep",
347
+
"bsec_out_tst_sdr_unlock_or_disable_scan",
348
+
"bsec_out_nidenm",
349
+
"bsec_out_nidena",
350
+
"cpu2_state_0",
351
+
"rcc_pwrds_sys",
352
+
"gpu_dbg7",
353
+
"ddrss_csysreq_ddrc",
354
+
"ddrss_dfi_phyupd_req",
355
+
"cpu3_sleep_deep",
356
+
"d2_gbl_per_clk_bus_req",
357
+
"pcie_usb_cxpl_debug_info_ei_0",
358
+
"pcie_usb_cxpl_debug_info_ei_8",
359
+
"d3_state_0",
360
+
"gpoval0",
361
+
//HDP1 functions:
362
+
"pwr_pwrwake_cpu2",
363
+
"cpu2_halted",
364
+
"cpu2_state_1",
365
+
"bsec_out_dbgenm",
366
+
"bsec_out_dbgena",
367
+
"exti1_sys_wakeup",
368
+
"rcc_pwrds_cpu2",
369
+
"gpu_dbg6",
370
+
"ddrss_csysack_ddrc",
371
+
"ddrss_dfi_phymstr_req",
372
+
"cpu3_halted",
373
+
"d2_gbl_per_dma_req",
374
+
"pcie_usb_cxpl_debug_info_ei_1",
375
+
"pcie_usb_cxpl_debug_info_ei_9",
376
+
"d3_state_1",
377
+
"gpoval1",
378
+
//HDP2 functions:
379
+
"pwr_pwrwake_cpu1",
380
+
"cpu2_rxev",
381
+
"cpu1_npumirq1",
382
+
"cpu1_nfiqout1",
383
+
"bsec_out_shdbgen",
384
+
"exti1_cpu2_wakeup",
385
+
"rcc_pwrds_cpu1",
386
+
"gpu_dbg5",
387
+
"ddrss_cactive_ddrc",
388
+
"ddrss_dfi_lp_req",
389
+
"cpu3_rxev",
390
+
"hpdma1_clk_bus_req",
391
+
"pcie_usb_cxpl_debug_info_ei_2",
392
+
"pcie_usb_cxpl_debug_info_ei_10",
393
+
"d3_state_2",
394
+
"gpoval2",
395
+
//HDP3 functions:
396
+
"pwr_sel_vth_vddcpu",
397
+
"cpu2_txev",
398
+
"cpu1_npumirq0",
399
+
"cpu1_nfiqout0",
400
+
"bsec_out_ddbgen",
401
+
"exti1_cpu1_wakeup",
402
+
"cpu3_state_0",
403
+
"gpu_dbg4",
404
+
"ddrss_mcdcg_en",
405
+
"ddrss_dfi_freq_0",
406
+
"cpu3_txev",
407
+
"hpdma2_clk_bus_req",
408
+
"pcie_usb_cxpl_debug_info_ei_3",
409
+
"pcie_usb_cxpl_debug_info_ei_11",
410
+
"d1_state_0",
411
+
"gpoval3",
412
+
//HDP4 functions:
413
+
"pwr_sel_vth_vddcore",
414
+
"cpu2_sleeping",
415
+
"cpu1_evento",
416
+
"cpu1_nirqout1",
417
+
"bsec_out_spnidena",
418
+
"exti2_d3_wakeup",
419
+
"eth1_out_pmt_intr_o",
420
+
"gpu_dbg3",
421
+
"ddrss_dphycg_en",
422
+
"ddrss_obsp0",
423
+
"cpu3_sleeping",
424
+
"hpdma3_clk_bus_req",
425
+
"pcie_usb_cxpl_debug_info_ei_4",
426
+
"pcie_usb_cxpl_debug_info_ei_12",
427
+
"d1_state_1",
428
+
"gpoval4",
429
+
//HDP5 functions:
430
+
"cpu1_standby_wfil2",
431
+
"none",
432
+
"none",
433
+
"cpu1_nirqout0",
434
+
"bsec_out_spidena",
435
+
"exti2_cpu3_wakeup",
436
+
"eth1_out_lpi_intr_o",
437
+
"gpu_dbg2",
438
+
"ddrctrl_dfi_init_start",
439
+
"ddrss_obsp1",
440
+
"cpu3_state_1",
441
+
"d3_gbl_per_clk_bus_req",
442
+
"pcie_usb_cxpl_debug_info_ei_5",
443
+
"pcie_usb_cxpl_debug_info_ei_13",
444
+
"d1_state_2",
445
+
"gpoval5",
446
+
//HDP6 functions:
447
+
"cpu1_standby_wfi1",
448
+
"cpu1_standby_wfe1",
449
+
"cpu1_halted1",
450
+
"cpu1_naxierrirq",
451
+
"bsec_out_spnidenm",
452
+
"exti2_cpu2_wakeup",
453
+
"eth2_out_pmt_intr_o",
454
+
"gpu_dbg1",
455
+
"ddrss_dfi_init_complete",
456
+
"ddrss_obsp2",
457
+
"d2_state_0",
458
+
"d3_gbl_per_dma_req",
459
+
"pcie_usb_cxpl_debug_info_ei_6",
460
+
"pcie_usb_cxpl_debug_info_ei_14",
461
+
"cpu1_state_0",
462
+
"gpoval6",
463
+
//HDP7 functions:
464
+
"cpu1_standby_wfi0",
465
+
"cpu1_standby_wfe0",
466
+
"cpu1_halted0",
467
+
"none",
468
+
"bsec_out_spidenm",
469
+
"exti2_cpu1__wakeup",
470
+
"eth2_out_lpi_intr_o",
471
+
"gpu_dbg0",
472
+
"ddrss_dfi_ctrlupd_req",
473
+
"ddrss_obsp3",
474
+
"d2_state_1",
475
+
"lpdma1_clk_bus_req",
476
+
"pcie_usb_cxpl_debug_info_ei_7",
477
+
"pcie_usb_cxpl_debug_info_ei_15",
478
+
"cpu1_state_1",
479
+
"gpoval7",
480
+
};
481
+
482
+
static const char * const stm32_hdp_pins_group[] = {
483
+
"HDP0",
484
+
"HDP1",
485
+
"HDP2",
486
+
"HDP3",
487
+
"HDP4",
488
+
"HDP5",
489
+
"HDP6",
490
+
"HDP7"
491
+
};
492
+
493
+
static int stm32_hdp_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
494
+
{
495
+
return GPIO_LINE_DIRECTION_OUT;
496
+
}
497
+
498
+
static int stm32_hdp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
499
+
{
500
+
return ARRAY_SIZE(stm32_hdp_pins);
501
+
}
502
+
503
+
static const char *stm32_hdp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
504
+
unsigned int selector)
505
+
{
506
+
return stm32_hdp_pins[selector].name;
507
+
}
508
+
509
+
static int stm32_hdp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
510
+
const unsigned int **pins, unsigned int *num_pins)
511
+
{
512
+
*pins = &stm32_hdp_pins[selector].number;
513
+
*num_pins = 1;
514
+
515
+
return 0;
516
+
}
517
+
518
+
static const struct pinctrl_ops stm32_hdp_pinctrl_ops = {
519
+
.get_groups_count = stm32_hdp_pinctrl_get_groups_count,
520
+
.get_group_name = stm32_hdp_pinctrl_get_group_name,
521
+
.get_group_pins = stm32_hdp_pinctrl_get_group_pins,
522
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
523
+
.dt_free_map = pinconf_generic_dt_free_map,
524
+
};
525
+
526
+
static int stm32_hdp_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
527
+
{
528
+
return HDP_FUNC_TOTAL;
529
+
}
530
+
531
+
static const char *stm32_hdp_pinmux_get_function_name(struct pinctrl_dev *pctldev,
532
+
unsigned int selector)
533
+
{
534
+
struct stm32_hdp *hdp = pinctrl_dev_get_drvdata(pctldev);
535
+
536
+
return hdp->func_name[selector];
537
+
}
538
+
539
+
static int stm32_hdp_pinmux_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
540
+
const char *const **groups,
541
+
unsigned int *num_groups)
542
+
{
543
+
u32 index = selector / HDP_FUNC;
544
+
545
+
*groups = &stm32_hdp_pins[index].name;
546
+
*num_groups = 1;
547
+
548
+
return 0;
549
+
}
550
+
551
+
static int stm32_hdp_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
552
+
unsigned int group_selector)
553
+
{
554
+
struct stm32_hdp *hdp = pinctrl_dev_get_drvdata(pctldev);
555
+
556
+
unsigned int pin = stm32_hdp_pins[group_selector].number;
557
+
u32 mux;
558
+
559
+
func_selector %= HDP_FUNC;
560
+
mux = readl_relaxed(hdp->base + HDP_MUX);
561
+
mux &= ~HDP_MUX_MASK(pin);
562
+
mux |= func_selector << HDP_MUX_SHIFT(pin);
563
+
564
+
writel_relaxed(mux, hdp->base + HDP_MUX);
565
+
hdp->mux_conf = mux;
566
+
567
+
return 0;
568
+
}
569
+
570
+
static const struct pinmux_ops stm32_hdp_pinmux_ops = {
571
+
.get_functions_count = stm32_hdp_pinmux_get_functions_count,
572
+
.get_function_name = stm32_hdp_pinmux_get_function_name,
573
+
.get_function_groups = stm32_hdp_pinmux_get_function_groups,
574
+
.set_mux = stm32_hdp_pinmux_set_mux,
575
+
.gpio_set_direction = NULL,
576
+
};
577
+
578
+
static struct pinctrl_desc stm32_hdp_pdesc = {
579
+
.name = DRIVER_NAME,
580
+
.pins = stm32_hdp_pins,
581
+
.npins = ARRAY_SIZE(stm32_hdp_pins),
582
+
.pctlops = &stm32_hdp_pinctrl_ops,
583
+
.pmxops = &stm32_hdp_pinmux_ops,
584
+
.owner = THIS_MODULE,
585
+
};
586
+
587
+
static const struct of_device_id stm32_hdp_of_match[] = {
588
+
{
589
+
.compatible = "st,stm32mp131-hdp",
590
+
.data = &func_name_mp13,
591
+
},
592
+
{
593
+
.compatible = "st,stm32mp151-hdp",
594
+
.data = &func_name_mp15,
595
+
},
596
+
{
597
+
.compatible = "st,stm32mp251-hdp",
598
+
.data = &func_name_mp25,
599
+
},
600
+
{}
601
+
};
602
+
MODULE_DEVICE_TABLE(of, stm32_hdp_of_match);
603
+
604
+
static int stm32_hdp_probe(struct platform_device *pdev)
605
+
{
606
+
struct device *dev = &pdev->dev;
607
+
struct stm32_hdp *hdp;
608
+
u8 version;
609
+
int err;
610
+
611
+
hdp = devm_kzalloc(dev, sizeof(*hdp), GFP_KERNEL);
612
+
if (!hdp)
613
+
return -ENOMEM;
614
+
hdp->dev = dev;
615
+
616
+
platform_set_drvdata(pdev, hdp);
617
+
618
+
hdp->base = devm_platform_ioremap_resource(pdev, 0);
619
+
if (IS_ERR(hdp->base))
620
+
return PTR_ERR(hdp->base);
621
+
622
+
hdp->func_name = of_device_get_match_data(dev);
623
+
if (!hdp->func_name)
624
+
return dev_err_probe(dev, -ENODEV, "No function name provided\n");
625
+
626
+
hdp->clk = devm_clk_get_enabled(dev, NULL);
627
+
if (IS_ERR(hdp->clk))
628
+
return dev_err_probe(dev, PTR_ERR(hdp->clk), "No HDP clock provided\n");
629
+
630
+
err = devm_pinctrl_register_and_init(dev, &stm32_hdp_pdesc, hdp, &hdp->pctl_dev);
631
+
if (err)
632
+
return dev_err_probe(dev, err, "Failed to register pinctrl\n");
633
+
634
+
err = pinctrl_enable(hdp->pctl_dev);
635
+
if (err)
636
+
return dev_err_probe(dev, err, "Failed to enable pinctrl\n");
637
+
638
+
hdp->gpio_chip.get_direction = stm32_hdp_gpio_get_direction;
639
+
hdp->gpio_chip.ngpio = ARRAY_SIZE(stm32_hdp_pins);
640
+
hdp->gpio_chip.can_sleep = true;
641
+
hdp->gpio_chip.names = stm32_hdp_pins_group;
642
+
643
+
err = bgpio_init(&hdp->gpio_chip, dev, 4,
644
+
hdp->base + HDP_GPOVAL,
645
+
hdp->base + HDP_GPOSET,
646
+
hdp->base + HDP_GPOCLR,
647
+
NULL, NULL, BGPIOF_NO_INPUT);
648
+
if (err)
649
+
return dev_err_probe(dev, err, "Failed to init bgpio\n");
650
+
651
+
652
+
err = devm_gpiochip_add_data(dev, &hdp->gpio_chip, hdp);
653
+
if (err)
654
+
return dev_err_probe(dev, err, "Failed to add gpiochip\n");
655
+
656
+
writel_relaxed(HDP_CTRL_ENABLE, hdp->base + HDP_CTRL);
657
+
658
+
version = readl_relaxed(hdp->base + HDP_VERR);
659
+
dev_dbg(dev, "STM32 HDP version %u.%u initialized\n", version >> 4, version & 0x0f);
660
+
661
+
return 0;
662
+
}
663
+
664
+
static void stm32_hdp_remove(struct platform_device *pdev)
665
+
{
666
+
struct stm32_hdp *hdp = platform_get_drvdata(pdev);
667
+
668
+
writel_relaxed(HDP_CTRL_DISABLE, hdp->base + HDP_CTRL);
669
+
}
670
+
671
+
static int stm32_hdp_suspend(struct device *dev)
672
+
{
673
+
struct stm32_hdp *hdp = dev_get_drvdata(dev);
674
+
675
+
hdp->gposet_conf = readl_relaxed(hdp->base + HDP_GPOSET);
676
+
677
+
pinctrl_pm_select_sleep_state(dev);
678
+
679
+
clk_disable_unprepare(hdp->clk);
680
+
681
+
return 0;
682
+
}
683
+
684
+
static int stm32_hdp_resume(struct device *dev)
685
+
{
686
+
struct stm32_hdp *hdp = dev_get_drvdata(dev);
687
+
int err;
688
+
689
+
err = clk_prepare_enable(hdp->clk);
690
+
if (err) {
691
+
dev_err(dev, "Failed to prepare_enable clk (%d)\n", err);
692
+
return err;
693
+
}
694
+
695
+
writel_relaxed(HDP_CTRL_ENABLE, hdp->base + HDP_CTRL);
696
+
writel_relaxed(hdp->gposet_conf, hdp->base + HDP_GPOSET);
697
+
writel_relaxed(hdp->mux_conf, hdp->base + HDP_MUX);
698
+
699
+
pinctrl_pm_select_default_state(dev);
700
+
701
+
return 0;
702
+
}
703
+
704
+
static DEFINE_SIMPLE_DEV_PM_OPS(stm32_hdp_pm_ops, stm32_hdp_suspend, stm32_hdp_resume);
705
+
706
+
static struct platform_driver stm32_hdp_driver = {
707
+
.probe = stm32_hdp_probe,
708
+
.remove = stm32_hdp_remove,
709
+
.driver = {
710
+
.name = DRIVER_NAME,
711
+
.pm = pm_sleep_ptr(&stm32_hdp_pm_ops),
712
+
.of_match_table = stm32_hdp_of_match,
713
+
}
714
+
};
715
+
716
+
module_platform_driver(stm32_hdp_driver);
717
+
718
+
MODULE_AUTHOR("Clément Le Goffic");
719
+
MODULE_DESCRIPTION("STMicroelectronics STM32 Hardware Debug Port driver");
720
+
MODULE_LICENSE("GPL");
+141
-3
drivers/pinctrl/stm32/pinctrl-stm32.c
+141
-3
drivers/pinctrl/stm32/pinctrl-stm32.c
···
6
6
*
7
7
* Heavily based on Mediatek's pinctrl driver
8
8
*/
9
+
#include <linux/bitfield.h>
9
10
#include <linux/clk.h>
11
+
#include <linux/export.h>
10
12
#include <linux/gpio/driver.h>
11
13
#include <linux/hwspinlock.h>
12
14
#include <linux/io.h>
···
38
36
#include "../pinctrl-utils.h"
39
37
#include "pinctrl-stm32.h"
40
38
39
+
#define STM32_GPIO_CID1 1
40
+
41
41
#define STM32_GPIO_MODER 0x00
42
42
#define STM32_GPIO_TYPER 0x04
43
43
#define STM32_GPIO_SPEEDR 0x08
···
51
47
#define STM32_GPIO_AFRL 0x20
52
48
#define STM32_GPIO_AFRH 0x24
53
49
#define STM32_GPIO_SECCFGR 0x30
50
+
#define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x)))
51
+
#define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x)))
54
52
55
53
/* custom bitfield to backup pin status */
56
54
#define STM32_GPIO_BKP_MODE_SHIFT 0
···
65
59
#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
66
60
#define STM32_GPIO_BKP_TYPE 10
67
61
#define STM32_GPIO_BKP_VAL 11
62
+
63
+
#define STM32_GPIO_CIDCFGR_CFEN BIT(0)
64
+
#define STM32_GPIO_CIDCFGR_SEMEN BIT(1)
65
+
#define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4)
66
+
#define STM32_GPIO_CIDCFGR_SEMWL_CID1 BIT(16 + STM32_GPIO_CID1)
67
+
68
+
#define STM32_GPIO_SEMCR_SEM_MUTEX BIT(0)
69
+
#define STM32_GPIO_SEMCR_SEMCID_MASK GENMASK(5, 4)
68
70
69
71
#define STM32_GPIO_PINS_PER_BANK 16
70
72
#define STM32_GPIO_IRQ_LINE 16
···
91
77
"af8", "af9", "af10",
92
78
"af11", "af12", "af13",
93
79
"af14", "af15", "analog",
80
+
"reserved",
94
81
};
95
82
96
83
struct stm32_pinctrl_group {
···
113
98
u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
114
99
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
115
100
bool secure_control;
101
+
bool rif_control;
116
102
};
117
103
118
104
struct stm32_pinctrl {
···
137
121
u16 irqmux_map;
138
122
spinlock_t irqmux_lock;
139
123
};
124
+
125
+
static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
140
126
141
127
static inline int stm32_gpio_pin(int gpio)
142
128
{
···
210
192
bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
211
193
}
212
194
195
+
/* RIF functions */
196
+
197
+
static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
198
+
{
199
+
u32 cid;
200
+
201
+
cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
202
+
203
+
if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
204
+
return true;
205
+
206
+
if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
207
+
if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
208
+
return true;
209
+
210
+
return false;
211
+
}
212
+
213
+
if (cid & STM32_GPIO_CIDCFGR_SEMWL_CID1)
214
+
return true;
215
+
216
+
return false;
217
+
}
218
+
219
+
static bool stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
220
+
{
221
+
u32 cid, sem;
222
+
223
+
cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
224
+
225
+
if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
226
+
return true;
227
+
228
+
if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
229
+
if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
230
+
return true;
231
+
232
+
return false;
233
+
}
234
+
235
+
if (!(cid & STM32_GPIO_CIDCFGR_SEMWL_CID1))
236
+
return false;
237
+
238
+
sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
239
+
if (sem & STM32_GPIO_SEMCR_SEM_MUTEX) {
240
+
if (FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
241
+
return true;
242
+
243
+
return false;
244
+
}
245
+
246
+
writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));
247
+
248
+
sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
249
+
if (sem & STM32_GPIO_SEMCR_SEM_MUTEX &&
250
+
FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
251
+
return true;
252
+
253
+
return false;
254
+
}
255
+
256
+
static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
257
+
{
258
+
u32 cid;
259
+
260
+
cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
261
+
262
+
if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
263
+
return;
264
+
265
+
if (cid & STM32_GPIO_CIDCFGR_SEMEN)
266
+
writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));
267
+
}
268
+
213
269
/* GPIO functions */
214
270
215
271
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
···
310
218
return -EINVAL;
311
219
}
312
220
221
+
if (bank->rif_control) {
222
+
if (!stm32_gpio_rif_acquire_semaphore(bank, offset)) {
223
+
dev_err(pctl->dev, "pin %d not available.\n", pin);
224
+
return -EINVAL;
225
+
}
226
+
}
227
+
313
228
return pinctrl_gpio_request(chip, offset);
229
+
}
230
+
231
+
static void stm32_gpio_free(struct gpio_chip *chip, unsigned int offset)
232
+
{
233
+
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
234
+
235
+
pinctrl_gpio_free(chip, offset);
236
+
237
+
if (bank->rif_control)
238
+
stm32_gpio_rif_release_semaphore(bank, offset);
314
239
}
315
240
316
241
static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
···
413
304
}
414
305
}
415
306
307
+
if (bank->rif_control) {
308
+
for (i = 0; i < ngpios; i++) {
309
+
if (!test_bit(i, valid_mask))
310
+
continue;
311
+
312
+
if (stm32_gpio_rif_valid(bank, i))
313
+
continue;
314
+
315
+
dev_dbg(pctl->dev, "RIF semaphore ownership conflict, GPIO %u", i);
316
+
clear_bit(i, valid_mask);
317
+
}
318
+
}
319
+
416
320
return 0;
417
321
}
418
322
419
323
static const struct gpio_chip stm32_gpio_template = {
420
324
.request = stm32_gpio_request,
421
-
.free = pinctrl_gpio_free,
325
+
.free = stm32_gpio_free,
422
326
.get = stm32_gpio_get,
423
327
.set_rv = stm32_gpio_set,
424
328
.direction_input = pinctrl_gpio_direction_input,
···
533
411
.irq_set_wake = irq_chip_set_wake_parent,
534
412
.irq_request_resources = stm32_gpio_irq_request_resources,
535
413
.irq_release_resources = stm32_gpio_irq_release_resources,
414
+
.irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
536
415
};
537
416
538
417
static int stm32_gpio_domain_translate(struct irq_domain *d,
···
663
540
664
541
if (pin->pin.number != pin_num)
665
542
continue;
543
+
544
+
if (fnum == STM32_PIN_RSVD)
545
+
return true;
666
546
667
547
for (k = 0; k < STM32_CONFIG_NUM; k++) {
668
548
if (func->num == fnum)
···
924
798
return err;
925
799
}
926
800
927
-
void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
928
-
u32 *alt)
801
+
static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt)
929
802
{
930
803
u32 val;
931
804
int alt_shift = (pin % 8) * 4;
···
964
839
if (!range) {
965
840
dev_err(pctl->dev, "No gpio range defined.\n");
966
841
return -EINVAL;
842
+
}
843
+
844
+
if (function == STM32_PIN_RSVD) {
845
+
dev_dbg(pctl->dev, "Reserved pins, skipping HW update.\n");
846
+
return 0;
967
847
}
968
848
969
849
bank = gpiochip_get_data(range->gc);
···
1478
1348
bank->bank_nr = bank_nr;
1479
1349
bank->bank_ioport_nr = bank_ioport_nr;
1480
1350
bank->secure_control = pctl->match_data->secure_control;
1351
+
bank->rif_control = pctl->match_data->rif_control;
1481
1352
spin_lock_init(&bank->lock);
1482
1353
1483
1354
if (pctl->domain) {
···
1795
1664
clk_bulk_disable_unprepare(banks, pctl->clks);
1796
1665
return ret;
1797
1666
}
1667
+
EXPORT_SYMBOL(stm32_pctl_probe);
1798
1668
1799
1669
static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1800
1670
struct stm32_pinctrl *pctl, u32 pin)
···
1868
1736
1869
1737
return 0;
1870
1738
}
1739
+
EXPORT_SYMBOL(stm32_pinctrl_suspend);
1871
1740
1872
1741
int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1873
1742
{
···
1885
1752
1886
1753
return 0;
1887
1754
}
1755
+
EXPORT_SYMBOL(stm32_pinctrl_resume);
1756
+
1757
+
MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@foss.st.com>");
1758
+
MODULE_DESCRIPTION("STM32 core pinctrl driver");
1759
+
MODULE_LICENSE("GPL");
+17
-5
drivers/pinctrl/stm32/pinctrl-stm32.h
+17
-5
drivers/pinctrl/stm32/pinctrl-stm32.h
···
17
17
#define STM32_PIN_GPIO 0
18
18
#define STM32_PIN_AF(x) ((x) + 1)
19
19
#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1)
20
-
#define STM32_CONFIG_NUM (STM32_PIN_ANALOG + 1)
20
+
#define STM32_PIN_RSVD (STM32_PIN_ANALOG + 1)
21
+
#define STM32_CONFIG_NUM (STM32_PIN_RSVD + 1)
21
22
22
23
/* package information */
23
24
#define STM32MP_PKG_AA BIT(0)
···
64
63
const struct stm32_desc_pin *pins;
65
64
const unsigned int npins;
66
65
bool secure_control;
66
+
bool rif_control;
67
67
};
68
68
69
-
struct stm32_gpio_bank;
70
-
69
+
/**
70
+
* stm32_pctl_probe() - Common probe for stm32 pinctrl drivers.
71
+
* @pdev: Pinctrl platform device.
72
+
*/
71
73
int stm32_pctl_probe(struct platform_device *pdev);
72
-
void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
73
-
int pin, u32 *mode, u32 *alt);
74
+
75
+
/**
76
+
* stm32_pinctrl_suspend() - Common suspend for stm32 pinctrl drivers.
77
+
* @dev: Pinctrl device.
78
+
*/
74
79
int stm32_pinctrl_suspend(struct device *dev);
80
+
81
+
/**
82
+
* stm32_pinctrl_resume() - Common resume for stm32 pinctrl drivers.
83
+
* @dev: Pinctrl device.
84
+
*/
75
85
int stm32_pinctrl_resume(struct device *dev);
76
86
77
87
#endif /* __PINCTRL_STM32_H */
+10
-5
drivers/pinctrl/stm32/pinctrl-stm32mp257.c
+10
-5
drivers/pinctrl/stm32/pinctrl-stm32mp257.c
···
4
4
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5
5
*/
6
6
#include <linux/init.h>
7
+
#include <linux/module.h>
7
8
#include <linux/of.h>
8
9
#include <linux/platform_device.h>
9
10
···
2543
2542
static struct stm32_pinctrl_match_data stm32mp257_match_data = {
2544
2543
.pins = stm32mp257_pins,
2545
2544
.npins = ARRAY_SIZE(stm32mp257_pins),
2545
+
.secure_control = true,
2546
+
.rif_control = true,
2546
2547
};
2547
2548
2548
2549
static struct stm32_pinctrl_match_data stm32mp257_z_match_data = {
2549
2550
.pins = stm32mp257_z_pins,
2550
2551
.npins = ARRAY_SIZE(stm32mp257_z_pins),
2552
+
.secure_control = true,
2553
+
.rif_control = true,
2551
2554
};
2552
2555
2553
2556
static const struct of_device_id stm32mp257_pctrl_match[] = {
···
2565
2560
},
2566
2561
{ }
2567
2562
};
2563
+
MODULE_DEVICE_TABLE(of, stm32mp257_pctrl_match);
2568
2564
2569
2565
static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
2570
2566
SET_LATE_SYSTEM_SLEEP_PM_OPS(stm32_pinctrl_suspend, stm32_pinctrl_resume)
···
2579
2573
.pm = &stm32_pinctrl_dev_pm_ops,
2580
2574
},
2581
2575
};
2576
+
module_platform_driver(stm32mp257_pinctrl_driver);
2582
2577
2583
-
static int __init stm32mp257_pinctrl_init(void)
2584
-
{
2585
-
return platform_driver_register(&stm32mp257_pinctrl_driver);
2586
-
}
2587
-
arch_initcall(stm32mp257_pinctrl_init);
2578
+
MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@foss.st.com>");
2579
+
MODULE_DESCRIPTION("STM32MP257 pinctrl driver");
2580
+
MODULE_LICENSE("GPL");
+4
-2
drivers/pinctrl/sunplus/sppctl.c
+4
-2
drivers/pinctrl/sunplus/sppctl.c
···
461
461
return (reg & BIT(bit_off)) ? 1 : 0;
462
462
}
463
463
464
-
static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
464
+
static int sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
465
465
{
466
466
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
467
467
u32 reg_off, reg;
468
468
469
469
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
470
470
sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
471
+
472
+
return 0;
471
473
}
472
474
473
475
static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
···
547
545
gchip->direction_input = sppctl_gpio_direction_input;
548
546
gchip->direction_output = sppctl_gpio_direction_output;
549
547
gchip->get = sppctl_gpio_get;
550
-
gchip->set = sppctl_gpio_set;
548
+
gchip->set_rv = sppctl_gpio_set;
551
549
gchip->set_config = sppctl_gpio_set_config;
552
550
gchip->dbg_show = IS_ENABLED(CONFIG_DEBUG_FS) ?
553
551
sppctl_gpio_dbg_show : NULL;
+1
-1
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+1
-1
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
···
45
45
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
46
46
SUNXI_FUNCTION(0x0, "gpio_in"),
47
47
SUNXI_FUNCTION(0x1, "gpio_out"),
48
-
SUNXI_FUNCTION(0x2, "uart2"), /* D1 */
48
+
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
49
49
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
50
50
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
51
51
SUNXI_FUNCTION(0x0, "gpio_in"),
+14
-7
drivers/pinctrl/sunxi/pinctrl-sunxi.c
+14
-7
drivers/pinctrl/sunxi/pinctrl-sunxi.c
···
408
408
const char *function, *pin_prop;
409
409
const char *group;
410
410
int ret, npins, nmaps, configlen = 0, i = 0;
411
+
struct pinctrl_map *new_map;
411
412
412
413
*map = NULL;
413
414
*num_maps = 0;
···
483
482
* We know have the number of maps we need, we can resize our
484
483
* map array
485
484
*/
486
-
*map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
487
-
if (!*map)
488
-
return -ENOMEM;
485
+
new_map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
486
+
if (!new_map) {
487
+
ret = -ENOMEM;
488
+
goto err_free_map;
489
+
}
490
+
491
+
*map = new_map;
489
492
490
493
return 0;
491
494
···
960
955
return val;
961
956
}
962
957
963
-
static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
964
-
unsigned offset, int value)
958
+
static int sunxi_pinctrl_gpio_set(struct gpio_chip *chip, unsigned int offset,
959
+
int value)
965
960
{
966
961
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
967
962
u32 reg, shift, mask, val;
···
981
976
writel(val, pctl->membase + reg);
982
977
983
978
raw_spin_unlock_irqrestore(&pctl->lock, flags);
979
+
980
+
return 0;
984
981
}
985
982
986
983
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
···
1604
1597
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1605
1598
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1606
1599
pctl->chip->get = sunxi_pinctrl_gpio_get;
1607
-
pctl->chip->set = sunxi_pinctrl_gpio_set;
1600
+
pctl->chip->set_rv = sunxi_pinctrl_gpio_set;
1608
1601
pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1609
1602
pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1610
1603
pctl->chip->of_gpio_n_cells = 3;
···
1653
1646
}
1654
1647
}
1655
1648
1656
-
pctl->domain = irq_domain_create_linear(of_fwnode_handle(node),
1649
+
pctl->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev),
1657
1650
pctl->desc->irq_banks * IRQ_PER_BANK,
1658
1651
&sunxi_pinctrl_irq_domain_ops, pctl);
1659
1652
if (!pctl->domain) {
+12
-5
drivers/pinctrl/vt8500/pinctrl-wmt.c
+12
-5
drivers/pinctrl/vt8500/pinctrl-wmt.c
···
507
507
return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit));
508
508
}
509
509
510
-
static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset,
511
-
int val)
510
+
static int wmt_gpio_set_value(struct gpio_chip *chip, unsigned int offset,
511
+
int val)
512
512
{
513
513
struct wmt_pinctrl_data *data = gpiochip_get_data(chip);
514
514
u32 bank = WMT_BANK_FROM_PIN(offset);
···
517
517
518
518
if (reg_data_out == NO_REG) {
519
519
dev_err(data->dev, "no data out register defined\n");
520
-
return;
520
+
return -EINVAL;
521
521
}
522
522
523
523
if (val)
524
524
wmt_setbits(data, reg_data_out, BIT(bit));
525
525
else
526
526
wmt_clearbits(data, reg_data_out, BIT(bit));
527
+
528
+
return 0;
527
529
}
528
530
529
531
static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
530
532
int value)
531
533
{
532
-
wmt_gpio_set_value(chip, offset, value);
534
+
int ret;
535
+
536
+
ret = wmt_gpio_set_value(chip, offset, value);
537
+
if (ret)
538
+
return ret;
539
+
533
540
return pinctrl_gpio_direction_output(chip, offset);
534
541
}
535
542
···
549
542
.direction_input = pinctrl_gpio_direction_input,
550
543
.direction_output = wmt_gpio_direction_output,
551
544
.get = wmt_gpio_get_value,
552
-
.set = wmt_gpio_set_value,
545
+
.set_rv = wmt_gpio_set_value,
553
546
.can_sleep = false,
554
547
};
555
548
+1
-1
drivers/rtc/rtc-stm32.c
+1
-1
drivers/rtc/rtc-stm32.c
+1
include/dt-bindings/pinctrl/stm32-pinfunc.h
+1
include/dt-bindings/pinctrl/stm32-pinfunc.h
+4
-4
include/linux/pinctrl/pinctrl.h
+4
-4
include/linux/pinctrl/pinctrl.h
···
165
165
166
166
/* External interface to pin controller */
167
167
168
-
extern int pinctrl_register_and_init(struct pinctrl_desc *pctldesc,
168
+
extern int pinctrl_register_and_init(const struct pinctrl_desc *pctldesc,
169
169
struct device *dev, void *driver_data,
170
170
struct pinctrl_dev **pctldev);
171
171
extern int pinctrl_enable(struct pinctrl_dev *pctldev);
172
172
173
173
/* Please use pinctrl_register_and_init() and pinctrl_enable() instead */
174
-
extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
174
+
extern struct pinctrl_dev *pinctrl_register(const struct pinctrl_desc *pctldesc,
175
175
struct device *dev, void *driver_data);
176
176
177
177
extern void pinctrl_unregister(struct pinctrl_dev *pctldev);
178
178
179
179
extern int devm_pinctrl_register_and_init(struct device *dev,
180
-
struct pinctrl_desc *pctldesc,
180
+
const struct pinctrl_desc *pctldesc,
181
181
void *driver_data,
182
182
struct pinctrl_dev **pctldev);
183
183
184
184
/* Please use devm_pinctrl_register_and_init() instead */
185
185
extern struct pinctrl_dev *devm_pinctrl_register(struct device *dev,
186
-
struct pinctrl_desc *pctldesc,
186
+
const struct pinctrl_desc *pctldesc,
187
187
void *driver_data);
188
188
189
189
extern void devm_pinctrl_unregister(struct device *dev,
+1
include/linux/soc/samsung/exynos-regs-pmu.h
+1
include/linux/soc/samsung/exynos-regs-pmu.h