Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Use generic hdp flush function
Except HDP v5.2 all use a common logic for HDP flush. Use a generic
function. HDP v5.2 forces NO_KIQ logic, revisit it later.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
18a878fd
d6b22b1d
+27
-48
+21
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
+21
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
···
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*/
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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+
#include <uapi/linux/kfd_ioctl.h>
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int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
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{
···
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/* hdp ras follows amdgpu_ras_block_late_init_default for late init */
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return 0;
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}
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void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg) {
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WREG32((adev->rmmio_remap.reg_offset +
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KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
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2,
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0);
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RREG32((adev->rmmio_remap.reg_offset +
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KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
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2);
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} else {
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amdgpu_ring_emit_wreg(ring,
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(adev->rmmio_remap.reg_offset +
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KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
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2,
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0);
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}
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}
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
···
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#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
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#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
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static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg) {
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WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
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} else {
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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}
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-
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static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
···
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};
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const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
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-
.flush_hdp = hdp_v4_0_flush_hdp,
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.flush_hdp = amdgpu_hdp_generic_flush,
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.invalidate_hdp = hdp_v4_0_invalidate_hdp,
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.update_clock_gating = hdp_v4_0_update_clock_gating,
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.get_clock_gating_state = hdp_v4_0_get_clockgating_state,
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
···
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#include "hdp/hdp_5_0_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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-
static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg) {
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WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
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} else {
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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}
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-
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static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
···
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}
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const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
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.flush_hdp = hdp_v5_0_flush_hdp,
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.flush_hdp = amdgpu_hdp_generic_flush,
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.invalidate_hdp = hdp_v5_0_invalidate_hdp,
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.update_clock_gating = hdp_v5_0_update_clock_gating,
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.get_clock_gating_state = hdp_v5_0_get_clockgating_state,
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
···
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#define regHDP_CLK_CNTL_V6_1 0xd5
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#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
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static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg) {
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WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
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} else {
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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}
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static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
···
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}
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const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
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.flush_hdp = hdp_v6_0_flush_hdp,
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.flush_hdp = amdgpu_hdp_generic_flush,
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.update_clock_gating = hdp_v6_0_update_clock_gating,
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.get_clock_gating_state = hdp_v6_0_get_clockgating_state,
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};
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
+1
-12
drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
···
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#include "hdp/hdp_7_0_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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-
static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg) {
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WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
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} else {
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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}
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static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
···
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}
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const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
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.flush_hdp = hdp_v7_0_flush_hdp,
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.flush_hdp = amdgpu_hdp_generic_flush,
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.update_clock_gating = hdp_v7_0_update_clock_gating,
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.get_clock_gating_state = hdp_v7_0_get_clockgating_state,
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};