Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v5.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
- Fix an altmode in the Ocelot driver
- Fix the IES control pins in the Mediatek MT8365 driver
- Sunxi (AMLogic) driver:
- Fix the UART2 function pin assignments
- Fix the signal name of the PA2 SPI pin
* tag 'pinctrl-v5.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: sunxi: f1c100s: Fix signal name comment for PA2 SPI pin
pinctrl: sunxi: fix f1c100s uart2 function
pinctrl: mediatek: mt8365: fix IES control pins
pinctrl: ocelot: Fix for lan966x alt mode
+6
-4
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
···
259
259
MTK_PIN_IES_SMT_SPEC(104, 104, 0x420, 13),
260
260
MTK_PIN_IES_SMT_SPEC(105, 109, 0x420, 14),
261
261
MTK_PIN_IES_SMT_SPEC(110, 113, 0x420, 15),
262
-
MTK_PIN_IES_SMT_SPEC(114, 112, 0x420, 16),
262
+
MTK_PIN_IES_SMT_SPEC(114, 116, 0x420, 16),
263
263
MTK_PIN_IES_SMT_SPEC(117, 119, 0x420, 17),
264
264
MTK_PIN_IES_SMT_SPEC(120, 122, 0x420, 18),
265
265
MTK_PIN_IES_SMT_SPEC(123, 125, 0x420, 19),
+3
-1
drivers/pinctrl/pinctrl-ocelot.c
+3
-1
drivers/pinctrl/pinctrl-ocelot.c
···
129
129
FUNC_PTP1,
130
130
FUNC_PTP2,
131
131
FUNC_PTP3,
132
+
FUNC_PTPSYNC_0,
132
133
FUNC_PTPSYNC_1,
133
134
FUNC_PTPSYNC_2,
134
135
FUNC_PTPSYNC_3,
···
253
252
[FUNC_PTP1] = "ptp1",
254
253
[FUNC_PTP2] = "ptp2",
255
254
[FUNC_PTP3] = "ptp3",
255
+
[FUNC_PTPSYNC_0] = "ptpsync_0",
256
256
[FUNC_PTPSYNC_1] = "ptpsync_1",
257
257
[FUNC_PTPSYNC_2] = "ptpsync_2",
258
258
[FUNC_PTPSYNC_3] = "ptpsync_3",
···
985
983
LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
986
984
LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
987
985
LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
988
-
LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R);
986
+
LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R);
989
987
LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);
990
988
LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
991
989
LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
+2
-2
drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
+2
-2
drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
···
51
51
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
52
52
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
53
53
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
54
-
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
54
+
SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
55
55
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
56
56
SUNXI_FUNCTION(0x0, "gpio_in"),
57
57
SUNXI_FUNCTION(0x1, "gpio_out"),
···
204
204
SUNXI_FUNCTION(0x0, "gpio_in"),
205
205
SUNXI_FUNCTION(0x1, "gpio_out"),
206
206
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
207
-
SUNXI_FUNCTION(0x3, "lvds1"), /* RX */
207
+
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
208
208
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
209
209
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
210
210
SUNXI_FUNCTION(0x0, "gpio_in"),