Merge tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel

-1

Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml

··· 60 60 - const: bus 61 61 - const: core 62 62 - const: vsync 63 - - const: lut 64 63 - const: tbu 65 64 - const: tbu_rt 66 65 # MSM8996 has additional iommu clock

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c

··· 88 88 } 89 89 90 90 r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, size, 91 - AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 92 - AMDGPU_VM_PAGE_EXECUTABLE); 91 + AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | 92 + AMDGPU_PTE_EXECUTABLE); 93 93 94 94 if (r) { 95 95 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);

+32 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

··· 285 285 return ret; 286 286 } 287 287 288 + static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) 289 + { 290 + struct drm_gem_object *obj = dma_buf->priv; 291 + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 292 + int ret; 293 + 294 + /* 295 + * Pin to keep buffer in place while it's vmap'ed. The actual 296 + * domain is not that important as long as it's mapable. Using 297 + * GTT and VRAM should be compatible with most use cases. 298 + */ 299 + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM); 300 + if (ret) 301 + return ret; 302 + ret = drm_gem_dmabuf_vmap(dma_buf, map); 303 + if (ret) 304 + amdgpu_bo_unpin(bo); 305 + 306 + return ret; 307 + } 308 + 309 + static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map) 310 + { 311 + struct drm_gem_object *obj = dma_buf->priv; 312 + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 313 + 314 + drm_gem_dmabuf_vunmap(dma_buf, map); 315 + amdgpu_bo_unpin(bo); 316 + } 317 + 288 318 const struct dma_buf_ops amdgpu_dmabuf_ops = { 289 319 .attach = amdgpu_dma_buf_attach, 290 320 .pin = amdgpu_dma_buf_pin, ··· 324 294 .release = drm_gem_dmabuf_release, 325 295 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, 326 296 .mmap = drm_gem_dmabuf_mmap, 327 - .vmap = drm_gem_dmabuf_vmap, 328 - .vunmap = drm_gem_dmabuf_vunmap, 297 + .vmap = amdgpu_dma_buf_vmap, 298 + .vunmap = amdgpu_dma_buf_vunmap, 329 299 }; 330 300 331 301 /**

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

··· 471 471 if (index == (uint64_t)-EINVAL) { 472 472 drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n"); 473 473 kfree(queue); 474 + r = -EINVAL; 474 475 goto unlock; 475 476 } 476 477

+9 -5

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 1612 1612 case IP_VERSION(11, 0, 2): 1613 1613 case IP_VERSION(11, 0, 3): 1614 1614 if (!adev->gfx.disable_uq && 1615 - adev->gfx.me_fw_version >= 2390 && 1616 - adev->gfx.pfp_fw_version >= 2530 && 1617 - adev->gfx.mec_fw_version >= 2600 && 1615 + adev->gfx.me_fw_version >= 2420 && 1616 + adev->gfx.pfp_fw_version >= 2580 && 1617 + adev->gfx.mec_fw_version >= 2650 && 1618 1618 adev->mes.fw_version[0] >= 120) { 1619 1619 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1620 1620 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; ··· 4129 4129 #endif 4130 4130 if (prop->tmz_queue) 4131 4131 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 4132 + if (!prop->kernel_queue) 4133 + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 4132 4134 mqd->cp_gfx_hqd_cntl = tmp; 4133 4135 4134 4136 /* set up cp_doorbell_control */ ··· 4283 4281 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4284 4282 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4285 4283 prop->allow_tunneling); 4286 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4287 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4284 + if (prop->kernel_queue) { 4285 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4286 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4287 + } 4288 4288 if (prop->tmz_queue) 4289 4289 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 4290 4290 mqd->cp_hqd_pq_control = tmp;

+6 -2

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 3026 3026 #endif 3027 3027 if (prop->tmz_queue) 3028 3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3029 + if (!prop->kernel_queue) 3030 + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3029 3031 mqd->cp_gfx_hqd_cntl = tmp; 3030 3032 3031 3033 /* set up cp_doorbell_control */ ··· 3177 3175 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3178 3176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3179 3177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3180 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3181 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3178 + if (prop->kernel_queue) { 3179 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3180 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3181 + } 3182 3182 if (prop->tmz_queue) 3183 3183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3184 3184 mqd->cp_hqd_pq_control = tmp;

+10 -8

drivers/gpu/drm/amd/pm/amdgpu_pm.c

··· 3458 3458 effective_mode &= ~S_IWUSR; 3459 3459 3460 3460 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3461 - if (((adev->family == AMDGPU_FAMILY_SI) || 3462 - ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3463 - (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)))) && 3464 - (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3465 - attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3466 - attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3467 - attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3468 - return 0; 3461 + if (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3462 + attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3463 + attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3464 + attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr) { 3465 + if (adev->family == AMDGPU_FAMILY_SI || 3466 + ((adev->flags & AMD_IS_APU) && gc_ver != IP_VERSION(10, 3, 1) && 3467 + (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4))) || 3468 + (amdgpu_sriov_vf(adev) && gc_ver == IP_VERSION(11, 0, 3))) 3469 + return 0; 3470 + } 3469 3471 3470 3472 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3471 3473 if (((adev->family == AMDGPU_FAMILY_SI) ||

+40 -40

drivers/gpu/drm/drm_gpuvm.c

··· 40 40 * mapping's backing &drm_gem_object buffers. 41 41 * 42 42 * &drm_gem_object buffers maintain a list of &drm_gpuva objects representing 43 - * all existent GPU VA mappings using this &drm_gem_object as backing buffer. 43 + * all existing GPU VA mappings using this &drm_gem_object as backing buffer. 44 44 * 45 45 * GPU VAs can be flagged as sparse, such that drivers may use GPU VAs to also 46 46 * keep track of sparse PTEs in order to support Vulkan 'Sparse Resources'. ··· 72 72 * but it can also be a 'dummy' object, which can be allocated with 73 73 * drm_gpuvm_resv_object_alloc(). 74 74 * 75 - * In order to connect a struct drm_gpuva its backing &drm_gem_object each 75 + * In order to connect a struct drm_gpuva to its backing &drm_gem_object each 76 76 * &drm_gem_object maintains a list of &drm_gpuvm_bo structures, and each 77 77 * &drm_gpuvm_bo contains a list of &drm_gpuva structures. 78 78 * ··· 81 81 * This is ensured by the API through drm_gpuvm_bo_obtain() and 82 82 * drm_gpuvm_bo_obtain_prealloc() which first look into the corresponding 83 83 * &drm_gem_object list of &drm_gpuvm_bos for an existing instance of this 84 - * particular combination. If not existent a new instance is created and linked 84 + * particular combination. If not present, a new instance is created and linked 85 85 * to the &drm_gem_object. 86 86 * 87 87 * &drm_gpuvm_bo structures, since unique for a given &drm_gpuvm, are also used ··· 108 108 * sequence of operations to satisfy a given map or unmap request. 109 109 * 110 110 * Therefore the DRM GPU VA manager provides an algorithm implementing splitting 111 - * and merging of existent GPU VA mappings with the ones that are requested to 111 + * and merging of existing GPU VA mappings with the ones that are requested to 112 112 * be mapped or unmapped. This feature is required by the Vulkan API to 113 113 * implement Vulkan 'Sparse Memory Bindings' - drivers UAPIs often refer to this 114 114 * as VM BIND. ··· 119 119 * execute in order to integrate the new mapping cleanly into the current state 120 120 * of the GPU VA space. 121 121 * 122 - * Depending on how the new GPU VA mapping intersects with the existent mappings 122 + * Depending on how the new GPU VA mapping intersects with the existing mappings 123 123 * of the GPU VA space the &drm_gpuvm_ops callbacks contain an arbitrary amount 124 124 * of unmap operations, a maximum of two remap operations and a single map 125 125 * operation. The caller might receive no callback at all if no operation is ··· 139 139 * one unmap operation and one or two map operations, such that drivers can 140 140 * derive the page table update delta accordingly. 141 141 * 142 - * Note that there can't be more than two existent mappings to split up, one at 142 + * Note that there can't be more than two existing mappings to split up, one at 143 143 * the beginning and one at the end of the new mapping, hence there is a 144 144 * maximum of two remap operations. 145 145 * 146 146 * Analogous to drm_gpuvm_sm_map() drm_gpuvm_sm_unmap() uses &drm_gpuvm_ops to 147 147 * call back into the driver in order to unmap a range of GPU VA space. The 148 - * logic behind this function is way simpler though: For all existent mappings 148 + * logic behind this function is way simpler though: For all existing mappings 149 149 * enclosed by the given range unmap operations are created. For mappings which 150 - * are only partically located within the given range, remap operations are 151 - * created such that those mappings are split up and re-mapped partically. 150 + * are only partially located within the given range, remap operations are 151 + * created such that those mappings are split up and re-mapped partially. 152 152 * 153 153 * As an alternative to drm_gpuvm_sm_map() and drm_gpuvm_sm_unmap(), 154 154 * drm_gpuvm_sm_map_ops_create() and drm_gpuvm_sm_unmap_ops_create() can be used ··· 168 168 * provided helper functions drm_gpuva_map(), drm_gpuva_remap() and 169 169 * drm_gpuva_unmap() instead. 170 170 * 171 - * The following diagram depicts the basic relationships of existent GPU VA 171 + * The following diagram depicts the basic relationships of existing GPU VA 172 172 * mappings, a newly requested mapping and the resulting mappings as implemented 173 173 * by drm_gpuvm_sm_map() - it doesn't cover any arbitrary combinations of these. 174 174 * ··· 218 218 * 219 219 * 220 220 * 4) Existent mapping is a left aligned subset of the requested one, hence 221 - * replace the existent one. 221 + * replace the existing one. 222 222 * 223 223 * :: 224 224 * ··· 236 236 * and/or non-contiguous BO offset. 237 237 * 238 238 * 239 - * 5) Requested mapping's range is a left aligned subset of the existent one, 239 + * 5) Requested mapping's range is a left aligned subset of the existing one, 240 240 * but backed by a different BO. Hence, map the requested mapping and split 241 - * the existent one adjusting its BO offset. 241 + * the existing one adjusting its BO offset. 242 242 * 243 243 * :: 244 244 * ··· 271 271 * new: |-----|-----| (a.bo_offset=n, a'.bo_offset=n+1) 272 272 * 273 273 * 274 - * 7) Requested mapping's range is a right aligned subset of the existent one, 274 + * 7) Requested mapping's range is a right aligned subset of the existing one, 275 275 * but backed by a different BO. Hence, map the requested mapping and split 276 - * the existent one, without adjusting the BO offset. 276 + * the existing one, without adjusting the BO offset. 277 277 * 278 278 * :: 279 279 * ··· 304 304 * 305 305 * 9) Existent mapping is overlapped at the end by the requested mapping backed 306 306 * by a different BO. Hence, map the requested mapping and split up the 307 - * existent one, without adjusting the BO offset. 307 + * existing one, without adjusting the BO offset. 308 308 * 309 309 * :: 310 310 * ··· 334 334 * new: |-----|-----------| (a'.bo_offset=n, a.bo_offset=n+1) 335 335 * 336 336 * 337 - * 11) Requested mapping's range is a centered subset of the existent one 337 + * 11) Requested mapping's range is a centered subset of the existing one 338 338 * having a different backing BO. Hence, map the requested mapping and split 339 - * up the existent one in two mappings, adjusting the BO offset of the right 339 + * up the existing one in two mappings, adjusting the BO offset of the right 340 340 * one accordingly. 341 341 * 342 342 * :: ··· 351 351 * new: |-----|-----|-----| (a.bo_offset=n,b.bo_offset=m,a'.bo_offset=n+2) 352 352 * 353 353 * 354 - * 12) Requested mapping is a contiguous subset of the existent one. Split it 354 + * 12) Requested mapping is a contiguous subset of the existing one. Split it 355 355 * up, but indicate that the backing PTEs could be kept. 356 356 * 357 357 * :: ··· 367 367 * 368 368 * 369 369 * 13) Existent mapping is a right aligned subset of the requested one, hence 370 - * replace the existent one. 370 + * replace the existing one. 371 371 * 372 372 * :: 373 373 * ··· 386 386 * 387 387 * 388 388 * 14) Existent mapping is a centered subset of the requested one, hence 389 - * replace the existent one. 389 + * replace the existing one. 390 390 * 391 391 * :: 392 392 * ··· 406 406 * 407 407 * 15) Existent mappings is overlapped at the beginning by the requested mapping 408 408 * backed by a different BO. Hence, map the requested mapping and split up 409 - * the existent one, adjusting its BO offset accordingly. 409 + * the existing one, adjusting its BO offset accordingly. 410 410 * 411 411 * :: 412 412 * ··· 469 469 * make use of them. 470 470 * 471 471 * The below code is strictly limited to illustrate the generic usage pattern. 472 - * To maintain simplicitly, it doesn't make use of any abstractions for common 473 - * code, different (asyncronous) stages with fence signalling critical paths, 472 + * To maintain simplicity, it doesn't make use of any abstractions for common 473 + * code, different (asynchronous) stages with fence signalling critical paths, 474 474 * any other helpers or error handling in terms of freeing memory and dropping 475 475 * previously taken locks. 476 476 * ··· 479 479 * // Allocates a new &drm_gpuva. 480 480 * struct drm_gpuva * driver_gpuva_alloc(void); 481 481 * 482 - * // Typically drivers would embedd the &drm_gpuvm and &drm_gpuva 482 + * // Typically drivers would embed the &drm_gpuvm and &drm_gpuva 483 483 * // structure in individual driver structures and lock the dma-resv with 484 484 * // drm_exec or similar helpers. 485 485 * int driver_mapping_create(struct drm_gpuvm *gpuvm, ··· 582 582 * .sm_step_unmap = driver_gpuva_unmap, 583 583 * }; 584 584 * 585 - * // Typically drivers would embedd the &drm_gpuvm and &drm_gpuva 585 + * // Typically drivers would embed the &drm_gpuvm and &drm_gpuva 586 586 * // structure in individual driver structures and lock the dma-resv with 587 587 * // drm_exec or similar helpers. 588 588 * int driver_mapping_create(struct drm_gpuvm *gpuvm, ··· 680 680 * 681 681 * This helper is here to provide lockless list iteration. Lockless as in, the 682 682 * iterator releases the lock immediately after picking the first element from 683 - * the list, so list insertion deletion can happen concurrently. 683 + * the list, so list insertion and deletion can happen concurrently. 684 684 * 685 685 * Elements popped from the original list are kept in a local list, so removal 686 686 * and is_empty checks can still happen while we're iterating the list. ··· 1160 1160 } 1161 1161 1162 1162 /** 1163 - * drm_gpuvm_prepare_objects() - prepare all assoiciated BOs 1163 + * drm_gpuvm_prepare_objects() - prepare all associated BOs 1164 1164 * @gpuvm: the &drm_gpuvm 1165 1165 * @exec: the &drm_exec locking context 1166 1166 * @num_fences: the amount of &dma_fences to reserve ··· 1230 1230 EXPORT_SYMBOL_GPL(drm_gpuvm_prepare_range); 1231 1231 1232 1232 /** 1233 - * drm_gpuvm_exec_lock() - lock all dma-resv of all assoiciated BOs 1233 + * drm_gpuvm_exec_lock() - lock all dma-resv of all associated BOs 1234 1234 * @vm_exec: the &drm_gpuvm_exec wrapper 1235 1235 * 1236 1236 * Acquires all dma-resv locks of all &drm_gem_objects the given 1237 1237 * &drm_gpuvm contains mappings of. 1238 1238 * 1239 - * Addionally, when calling this function with struct drm_gpuvm_exec::extra 1239 + * Additionally, when calling this function with struct drm_gpuvm_exec::extra 1240 1240 * being set the driver receives the given @fn callback to lock additional 1241 1241 * dma-resv in the context of the &drm_gpuvm_exec instance. Typically, drivers 1242 1242 * would call drm_exec_prepare_obj() from within this callback. ··· 1293 1293 } 1294 1294 1295 1295 /** 1296 - * drm_gpuvm_exec_lock_array() - lock all dma-resv of all assoiciated BOs 1296 + * drm_gpuvm_exec_lock_array() - lock all dma-resv of all associated BOs 1297 1297 * @vm_exec: the &drm_gpuvm_exec wrapper 1298 1298 * @objs: additional &drm_gem_objects to lock 1299 1299 * @num_objs: the number of additional &drm_gem_objects to lock ··· 1588 1588 EXPORT_SYMBOL_GPL(drm_gpuvm_bo_find); 1589 1589 1590 1590 /** 1591 - * drm_gpuvm_bo_obtain() - obtains and instance of the &drm_gpuvm_bo for the 1591 + * drm_gpuvm_bo_obtain() - obtains an instance of the &drm_gpuvm_bo for the 1592 1592 * given &drm_gpuvm and &drm_gem_object 1593 1593 * @gpuvm: The &drm_gpuvm the @obj is mapped in. 1594 1594 * @obj: The &drm_gem_object being mapped in the @gpuvm. ··· 1624 1624 EXPORT_SYMBOL_GPL(drm_gpuvm_bo_obtain); 1625 1625 1626 1626 /** 1627 - * drm_gpuvm_bo_obtain_prealloc() - obtains and instance of the &drm_gpuvm_bo 1627 + * drm_gpuvm_bo_obtain_prealloc() - obtains an instance of the &drm_gpuvm_bo 1628 1628 * for the given &drm_gpuvm and &drm_gem_object 1629 1629 * @__vm_bo: A pre-allocated struct drm_gpuvm_bo. 1630 1630 * ··· 1688 1688 * @vm_bo: the &drm_gpuvm_bo to add or remove 1689 1689 * @evict: indicates whether the object is evicted 1690 1690 * 1691 - * Adds a &drm_gpuvm_bo to or removes it from the &drm_gpuvms evicted list. 1691 + * Adds a &drm_gpuvm_bo to or removes it from the &drm_gpuvm's evicted list. 1692 1692 */ 1693 1693 void 1694 1694 drm_gpuvm_bo_evict(struct drm_gpuvm_bo *vm_bo, bool evict) ··· 1790 1790 * drm_gpuva_remove() - remove a &drm_gpuva 1791 1791 * @va: the &drm_gpuva to remove 1792 1792 * 1793 - * This removes the given &va from the underlaying tree. 1793 + * This removes the given &va from the underlying tree. 1794 1794 * 1795 1795 * It is safe to use this function using the safe versions of iterating the GPU 1796 1796 * VA space, such as drm_gpuvm_for_each_va_safe() and ··· 2358 2358 * 2359 2359 * This function iterates the given range of the GPU VA space. It utilizes the 2360 2360 * &drm_gpuvm_ops to call back into the driver providing the operations to 2361 - * unmap and, if required, split existent mappings. 2361 + * unmap and, if required, split existing mappings. 2362 2362 * 2363 2363 * Drivers may use these callbacks to update the GPU VA space right away within 2364 2364 * the callback. In case the driver decides to copy and store the operations for ··· 2430 2430 * remapped, and locks+prepares (drm_exec_prepare_object()) objects that 2431 2431 * will be newly mapped. 2432 2432 * 2433 - * The expected usage is: 2433 + * The expected usage is:: 2434 2434 * 2435 2435 * .. code-block:: c 2436 2436 * ··· 2475 2475 * required without the earlier DRIVER_OP_MAP. This is safe because we've 2476 2476 * already locked the GEM object in the earlier DRIVER_OP_MAP step. 2477 2477 * 2478 - * Returns: 0 on success or a negative error codec 2478 + * Returns: 0 on success or a negative error code 2479 2479 */ 2480 2480 int 2481 2481 drm_gpuvm_sm_map_exec_lock(struct drm_gpuvm *gpuvm, ··· 2619 2619 * @req_offset: the offset within the &drm_gem_object 2620 2620 * 2621 2621 * This function creates a list of operations to perform splitting and merging 2622 - * of existent mapping(s) with the newly requested one. 2622 + * of existing mapping(s) with the newly requested one. 2623 2623 * 2624 2624 * The list can be iterated with &drm_gpuva_for_each_op and must be processed 2625 2625 * in the given order. It can contain map, unmap and remap operations, but it 2626 2626 * also can be empty if no operation is required, e.g. if the requested mapping 2627 - * already exists is the exact same way. 2627 + * already exists in the exact same way. 2628 2628 * 2629 2629 * There can be an arbitrary amount of unmap operations, a maximum of two remap 2630 2630 * operations and a single map operation. The latter one represents the original

+14 -7

drivers/gpu/drm/mediatek/mtk_drm_drv.c

··· 387 387 388 388 of_id = of_match_node(mtk_drm_of_ids, node); 389 389 if (!of_id) 390 - continue; 390 + goto next_put_node; 391 391 392 392 pdev = of_find_device_by_node(node); 393 393 if (!pdev) 394 - continue; 394 + goto next_put_node; 395 395 396 396 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 397 397 if (!drm_dev) 398 - continue; 398 + goto next_put_device_pdev_dev; 399 399 400 400 temp_drm_priv = dev_get_drvdata(drm_dev); 401 401 if (!temp_drm_priv) 402 - continue; 402 + goto next_put_device_drm_dev; 403 403 404 404 if (temp_drm_priv->data->main_len) 405 405 all_drm_priv[CRTC_MAIN] = temp_drm_priv; ··· 411 411 if (temp_drm_priv->mtk_drm_bound) 412 412 cnt++; 413 413 414 - if (cnt == MAX_CRTC) { 415 - of_node_put(node); 414 + next_put_device_drm_dev: 415 + put_device(drm_dev); 416 + 417 + next_put_device_pdev_dev: 418 + put_device(&pdev->dev); 419 + 420 + next_put_node: 421 + of_node_put(node); 422 + 423 + if (cnt == MAX_CRTC) 416 424 break; 417 - } 418 425 } 419 426 420 427 if (drm_priv->data->mmsys_dev_num == cnt) {

+6

drivers/gpu/drm/mediatek/mtk_dsi.c

··· 1002 1002 return PTR_ERR(dsi->next_bridge); 1003 1003 } 1004 1004 1005 + /* 1006 + * set flag to request the DSI host bridge be pre-enabled before device bridge 1007 + * in the chain, so the DSI host is ready when the device bridge is pre-enabled 1008 + */ 1009 + dsi->next_bridge->pre_enable_prev_first = true; 1010 + 1005 1011 drm_bridge_add(&dsi->bridge); 1006 1012 1007 1013 ret = component_add(host->dev, &mtk_dsi_component_ops);

+4 -4

drivers/gpu/drm/mediatek/mtk_hdmi.c

··· 182 182 183 183 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 184 184 { 185 - regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL, 186 - VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH); 185 + regmap_update_bits(hdmi->regs, VIDEO_CFG_4, 186 + VIDEO_SOURCE_SEL, black ? GEN_RGB : NORMAL_PATH); 187 187 } 188 188 189 189 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) ··· 310 310 311 311 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 312 312 { 313 - regmap_update_bits(hdmi->regs, AUDIO_PACKET_OFF, 314 - GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF); 313 + regmap_update_bits(hdmi->regs, GRL_SHIFT_R2, 314 + AUDIO_PACKET_OFF, enable ? 0 : AUDIO_PACKET_OFF); 315 315 } 316 316 317 317 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)

+2 -1

drivers/gpu/drm/mediatek/mtk_plane.c

··· 292 292 wmb(); /* Make sure the above parameter is set before update */ 293 293 mtk_plane_state->pending.dirty = true; 294 294 295 - mtk_crtc_plane_disable(old_state->crtc, plane); 295 + if (old_state && old_state->crtc) 296 + mtk_crtc_plane_disable(old_state->crtc, plane); 296 297 } 297 298 298 299 static void mtk_plane_atomic_update(struct drm_plane *plane,

+33 -14

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

··· 11 11 static const unsigned int *gen7_0_0_external_core_regs[] __always_unused; 12 12 static const unsigned int *gen7_2_0_external_core_regs[] __always_unused; 13 13 static const unsigned int *gen7_9_0_external_core_regs[] __always_unused; 14 - static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused; 14 + static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused; 15 15 static const u32 gen7_9_0_cx_debugbus_blocks[] __always_unused; 16 16 17 17 #include "adreno_gen7_0_0_snapshot.h" ··· 174 174 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, 175 175 u32 *data) 176 176 { 177 - u32 reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | 178 - A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block); 177 + u32 reg; 178 + 179 + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { 180 + reg = A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | 181 + A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block); 182 + } else { 183 + reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | 184 + A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block); 185 + } 179 186 180 187 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); 181 188 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); ··· 205 198 readl((ptr) + ((offset) << 2)) 206 199 207 200 /* read a value from the CX debug bus */ 208 - static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset, 201 + static int cx_debugbus_read(struct msm_gpu *gpu, void __iomem *cxdbg, u32 block, u32 offset, 209 202 u32 *data) 210 203 { 211 - u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | 212 - A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); 204 + u32 reg; 205 + 206 + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { 207 + reg = A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | 208 + A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); 209 + } else { 210 + reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | 211 + A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); 212 + } 213 213 214 214 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A, reg); 215 215 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B, reg); ··· 329 315 ptr += debugbus_read(gpu, block->id, i, ptr); 330 316 } 331 317 332 - static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg, 318 + static void a6xx_get_cx_debugbus_block(struct msm_gpu *gpu, 319 + void __iomem *cxdbg, 333 320 struct a6xx_gpu_state *a6xx_state, 334 321 const struct a6xx_debugbus_block *block, 335 322 struct a6xx_gpu_state_obj *obj) ··· 345 330 obj->handle = block; 346 331 347 332 for (ptr = obj->data, i = 0; i < block->count; i++) 348 - ptr += cx_debugbus_read(cxdbg, block->id, i, ptr); 333 + ptr += cx_debugbus_read(gpu, cxdbg, block->id, i, ptr); 349 334 } 350 335 351 336 static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu, ··· 438 423 a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]], 439 424 &a6xx_state->debugbus[i + debugbus_blocks_count]); 440 425 } 441 - } 442 426 427 + a6xx_state->nr_debugbus = total_debugbus_blocks; 428 + } 443 429 } 444 430 445 431 static void a6xx_get_debugbus(struct msm_gpu *gpu, ··· 542 526 int i; 543 527 544 528 for (i = 0; i < nr_cx_debugbus_blocks; i++) 545 - a6xx_get_cx_debugbus_block(cxdbg, 529 + a6xx_get_cx_debugbus_block(gpu, 530 + cxdbg, 546 531 a6xx_state, 547 532 &cx_debugbus_blocks[i], 548 533 &a6xx_state->cx_debugbus[i]); ··· 776 759 size_t datasize; 777 760 int i, regcount = 0; 778 761 779 - /* Some clusters need a selector register to be programmed too */ 780 - if (cluster->sel) 781 - in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val); 782 - 783 762 in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD, 784 763 A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) | 785 764 A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) | 786 765 A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id)); 766 + 767 + /* Some clusters need a selector register to be programmed too */ 768 + if (cluster->sel) 769 + in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val); 787 770 788 771 for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) { 789 772 int count = RANGE(cluster->regs, i); ··· 1813 1796 1814 1797 print_name(p, " - type: ", a7xx_statetype_names[block->statetype]); 1815 1798 print_name(p, " - pipe: ", a7xx_pipe_names[block->pipeid]); 1799 + drm_printf(p, " - location: %d\n", block->location); 1816 1800 1817 1801 for (i = 0; i < block->num_sps; i++) { 1818 1802 drm_printf(p, " - sp: %d\n", i); ··· 1891 1873 print_name(p, " - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]); 1892 1874 print_name(p, " - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]); 1893 1875 drm_printf(p, " - context: %d\n", dbgahb->context_id); 1876 + drm_printf(p, " - location: %d\n", dbgahb->location_id); 1894 1877 a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4); 1895 1878 } 1896 1879 }

+19 -19

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

··· 419 419 REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, 420 420 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 421 421 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, 422 - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 422 + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 423 423 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 424 - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 424 + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 425 425 REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size}, 426 426 }; 427 427 428 428 static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = { 429 429 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, 430 - REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, 430 + REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL }, 431 431 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 432 432 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, 433 - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 433 + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 434 434 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 435 - { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, 436 - REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL }, 437 - { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 435 + { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR, 436 + REG_A7XX_CP_BV_SQE_STAT_DATA, 0x40, NULL }, 437 + { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 438 438 REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL }, 439 - { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 439 + { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 440 440 REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 441 - { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR, 442 - REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL }, 443 - { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 441 + { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR, 442 + REG_A7XX_CP_SQE_AC_STAT_DATA, 0x40, NULL }, 443 + { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 444 444 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL }, 445 - { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 445 + { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 446 446 REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL }, 447 - { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 447 + { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 448 448 REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL }, 449 - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 449 + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 450 450 REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size }, 451 451 }; 452 452 453 453 static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = { 454 - "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 454 + "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 455 455 REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL, 456 456 }; 457 457 458 458 static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = { 459 - { "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 460 - REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL }, 461 - { "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR, 462 - REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL }, 459 + { "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 460 + REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2200, NULL }, 461 + { "CP_BV_MEM_POOL_DBG", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR, 462 + REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2200, NULL }, 463 463 }; 464 464 465 465 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }

+13 -6

drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h

··· 81 81 A7XX_DBGBUS_USPTP_7, 82 82 }; 83 83 84 - static struct gen7_shader_block gen7_0_0_shader_blocks[] = { 84 + static const struct gen7_shader_block gen7_0_0_shader_blocks[] = { 85 85 {A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, 86 86 {A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, 87 87 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, ··· 668 668 }; 669 669 static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8)); 670 670 671 - /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ 672 - static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = { 671 + /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */ 672 + static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] = { 673 673 0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, 674 674 0x0b60f, 0x0b621, 0x0b630, 0x0b633, 675 675 UINT_MAX, UINT_MAX, 676 + }; 677 + static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registers), 8)); 678 + 679 + /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ 680 + static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = { 681 + 0x0b600, 0x0b600, 682 + UINT_MAX, UINT_MAX, 676 683 }; 677 684 static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8)); 678 685 ··· 702 695 .val = 0x9, 703 696 }; 704 697 705 - static struct gen7_cluster_registers gen7_0_0_clusters[] = { 698 + static const struct gen7_cluster_registers gen7_0_0_clusters[] = { 706 699 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 707 700 gen7_0_0_noncontext_pipe_br_registers, }, 708 701 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, ··· 771 764 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, 772 765 }; 773 766 774 - static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = { 767 + static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = { 775 768 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 776 769 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, 777 770 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, ··· 921 914 }; 922 915 static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8)); 923 916 924 - static struct gen7_reg_list gen7_0_0_reg_list[] = { 917 + static const struct gen7_reg_list gen7_0_0_reg_list[] = { 925 918 { gen7_0_0_gpu_registers, NULL }, 926 919 { gen7_0_0_cx_misc_registers, NULL }, 927 920 { gen7_0_0_dpm_registers, NULL },

+6 -4

drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h

··· 95 95 A7XX_DBGBUS_CCHE_2, 96 96 }; 97 97 98 - static struct gen7_shader_block gen7_2_0_shader_blocks[] = { 98 + static const struct gen7_shader_block gen7_2_0_shader_blocks[] = { 99 99 {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, 100 100 {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, 101 101 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, ··· 489 489 .val = 0x9, 490 490 }; 491 491 492 - static struct gen7_cluster_registers gen7_2_0_clusters[] = { 492 + static const struct gen7_cluster_registers gen7_2_0_clusters[] = { 493 493 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 494 494 gen7_2_0_noncontext_pipe_br_registers, }, 495 495 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, ··· 558 558 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, 559 559 }; 560 560 561 - static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = { 561 + static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = { 562 562 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 563 563 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, 564 564 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, ··· 573 573 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 }, 574 574 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 575 575 gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 }, 576 + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP, 577 + gen7_0_0_tpl1_noncontext_pipe_none_registers, 0xb600 }, 576 578 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, 577 579 gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 }, 578 580 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, ··· 739 737 }; 740 738 static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_registers), 8)); 741 739 742 - static struct gen7_reg_list gen7_2_0_reg_list[] = { 740 + static const struct gen7_reg_list gen7_2_0_reg_list[] = { 743 741 { gen7_2_0_gpu_registers, NULL }, 744 742 { gen7_2_0_cx_misc_registers, NULL }, 745 743 { gen7_2_0_dpm_registers, NULL },

+17 -17

drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h

··· 117 117 A7XX_DBGBUS_GBIF_CX, 118 118 }; 119 119 120 - static struct gen7_shader_block gen7_9_0_shader_blocks[] = { 120 + static const struct gen7_shader_block gen7_9_0_shader_blocks[] = { 121 121 { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 122 122 { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 123 123 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, ··· 1116 1116 .val = 0x9, 1117 1117 }; 1118 1118 1119 - static struct gen7_cluster_registers gen7_9_0_clusters[] = { 1119 + static const struct gen7_cluster_registers gen7_9_0_clusters[] = { 1120 1120 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 1121 1121 gen7_9_0_non_context_pipe_br_registers, }, 1122 1122 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, ··· 1185 1185 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, }, 1186 1186 }; 1187 1187 1188 - static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { 1188 + static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { 1189 1189 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 1190 1190 gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00}, 1191 1191 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, ··· 1294 1294 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, 1295 1295 }; 1296 1296 1297 - static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { 1297 + static const struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { 1298 1298 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, 1299 1299 REG_A6XX_CP_SQE_STAT_DATA, 0x00040}, 1300 1300 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 1301 1301 REG_A6XX_CP_DRAW_STATE_DATA, 0x00200}, 1302 - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 1302 + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 1303 1303 REG_A6XX_CP_ROQ_DBG_DATA, 0x00800}, 1304 - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 1304 + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 1305 1305 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000}, 1306 - { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 1306 + { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 1307 1307 REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200}, 1308 - { "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR, 1308 + { "CP_BV_ROQ_DBG", REG_A7XX_CP_BV_ROQ_DBG_ADDR, 1309 1309 REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800}, 1310 - { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 1310 + { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 1311 1311 REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000}, 1312 - { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, 1312 + { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR, 1313 1313 REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040}, 1314 - { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR, 1314 + { "CP_RESOURCE_TABLE_DBG", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR, 1315 1315 REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100}, 1316 - { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 1316 + { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 1317 1317 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200}, 1318 - { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR, 1318 + { "CP_LPAC_ROQ_DBG", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR, 1319 1319 REG_A7XX_CP_LPAC_ROQ_DBG_DATA, 0x00200}, 1320 - { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 1320 + { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 1321 1321 REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x08000}, 1322 - { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR, 1322 + { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR, 1323 1323 REG_A7XX_CP_SQE_AC_STAT_DATA, 0x00040}, 1324 - { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 1324 + { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 1325 1325 REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x00040}, 1326 1326 { "CP_AQE_ROQ_0", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0, 1327 1327 REG_A7XX_CP_AQE_ROQ_DBG_DATA_0, 0x00100}, ··· 1337 1337 REG_A7XX_CP_AQE_STAT_DATA_1, 0x00040}, 1338 1338 }; 1339 1339 1340 - static struct gen7_reg_list gen7_9_0_reg_list[] = { 1340 + static const struct gen7_reg_list gen7_9_0_reg_list[] = { 1341 1341 { gen7_9_0_gpu_registers, NULL}, 1342 1342 { gen7_9_0_cx_misc_registers, NULL}, 1343 1343 { gen7_9_0_cx_dbgc_registers, NULL},

+1 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

··· 596 596 597 597 spin_lock_irqsave(&dev->event_lock, flags); 598 598 if (dpu_crtc->event) { 599 - DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 599 + DRM_DEBUG_VBL("%s: send event: %p\n", dpu_crtc->name, 600 600 dpu_crtc->event); 601 601 trace_dpu_crtc_complete_flip(DRMID(crtc)); 602 602 drm_crtc_send_vblank_event(crtc, dpu_crtc->event);

+2

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

··· 730 730 return false; 731 731 732 732 conn_state = drm_atomic_get_new_connector_state(state, connector); 733 + if (!conn_state) 734 + return false; 733 735 734 736 /** 735 737 * These checks are duplicated from dpu_encoder_update_topology() since

+2 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

··· 31 31 u32 base; 32 32 33 33 if (!ctx) { 34 - DRM_ERROR("invalid ctx %pK\n", ctx); 34 + DRM_ERROR("invalid ctx %p\n", ctx); 35 35 return; 36 36 } 37 37 38 38 base = ctx->cap->sblk->pcc.base; 39 39 40 40 if (!base) { 41 - DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base); 41 + DRM_ERROR("invalid ctx %p pcc base 0x%x\n", ctx, base); 42 42 return; 43 43 } 44 44

+2 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

··· 1345 1345 dpu_kms->mmio = NULL; 1346 1346 return ret; 1347 1347 } 1348 - DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1348 + DRM_DEBUG("mapped dpu address space @%p\n", dpu_kms->mmio); 1349 1349 1350 1350 dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev, 1351 1351 dpu_kms->pdev, ··· 1380 1380 dpu_kms->mmio = NULL; 1381 1381 return ret; 1382 1382 } 1383 - DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1383 + DRM_DEBUG("mapped dpu address space @%p\n", dpu_kms->mmio); 1384 1384 1385 1385 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); 1386 1386 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {

+2 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

··· 1129 1129 struct drm_plane_state *old_plane_state = 1130 1130 drm_atomic_get_old_plane_state(state, plane); 1131 1131 struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1132 - struct drm_crtc_state *crtc_state; 1132 + struct drm_crtc_state *crtc_state = NULL; 1133 1133 int ret; 1134 1134 1135 1135 if (IS_ERR(plane_state)) ··· 1162 1162 if (!old_plane_state || !old_plane_state->fb || 1163 1163 old_plane_state->src_w != plane_state->src_w || 1164 1164 old_plane_state->src_h != plane_state->src_h || 1165 - old_plane_state->src_w != plane_state->src_w || 1165 + old_plane_state->crtc_w != plane_state->crtc_w || 1166 1166 old_plane_state->crtc_h != plane_state->crtc_h || 1167 1167 msm_framebuffer_format(old_plane_state->fb) != 1168 1168 msm_framebuffer_format(plane_state->fb))

+18 -41

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

··· 5 5 6 6 #include <linux/clk-provider.h> 7 7 #include <linux/platform_device.h> 8 + #include <linux/pm_clock.h> 9 + #include <linux/pm_runtime.h> 8 10 #include <dt-bindings/phy/phy.h> 9 11 10 12 #include "dsi_phy.h" ··· 513 511 return 0; 514 512 } 515 513 516 - static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) 517 - { 518 - struct device *dev = &phy->pdev->dev; 519 - int ret; 520 - 521 - ret = pm_runtime_resume_and_get(dev); 522 - if (ret) 523 - return ret; 524 - 525 - ret = clk_prepare_enable(phy->ahb_clk); 526 - if (ret) { 527 - DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret); 528 - pm_runtime_put_sync(dev); 529 - } 530 - 531 - return ret; 532 - } 533 - 534 - static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) 535 - { 536 - clk_disable_unprepare(phy->ahb_clk); 537 - pm_runtime_put(&phy->pdev->dev); 538 - } 539 - 540 514 static const struct of_device_id dsi_phy_dt_match[] = { 541 515 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY 542 516 { .compatible = "qcom,dsi-phy-28nm-hpm", ··· 676 698 if (ret) 677 699 return ret; 678 700 679 - phy->ahb_clk = msm_clk_get(pdev, "iface"); 680 - if (IS_ERR(phy->ahb_clk)) 681 - return dev_err_probe(dev, PTR_ERR(phy->ahb_clk), 682 - "Unable to get ahb clk\n"); 701 + platform_set_drvdata(pdev, phy); 683 702 684 - ret = devm_pm_runtime_enable(&pdev->dev); 703 + ret = devm_pm_runtime_enable(dev); 685 704 if (ret) 686 705 return ret; 687 706 688 - /* PLL init will call into clk_register which requires 689 - * register access, so we need to enable power and ahb clock. 690 - */ 691 - ret = dsi_phy_enable_resource(phy); 707 + ret = devm_pm_clk_create(dev); 692 708 if (ret) 693 709 return ret; 710 + 711 + ret = pm_clk_add(dev, "iface"); 712 + if (ret < 0) 713 + return dev_err_probe(dev, ret, "Unable to get iface clk\n"); 694 714 695 715 if (phy->cfg->ops.pll_init) { 696 716 ret = phy->cfg->ops.pll_init(phy); ··· 703 727 return dev_err_probe(dev, ret, 704 728 "Failed to register clk provider\n"); 705 729 706 - dsi_phy_disable_resource(phy); 707 - 708 - platform_set_drvdata(pdev, phy); 709 - 710 730 return 0; 711 731 } 732 + 733 + static const struct dev_pm_ops dsi_phy_pm_ops = { 734 + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 735 + }; 712 736 713 737 static struct platform_driver dsi_phy_platform_driver = { 714 738 .probe = dsi_phy_driver_probe, 715 739 .driver = { 716 740 .name = "msm_dsi_phy", 717 741 .of_match_table = dsi_phy_dt_match, 742 + .pm = &dsi_phy_pm_ops, 718 743 }, 719 744 }; 720 745 ··· 741 764 742 765 dev = &phy->pdev->dev; 743 766 744 - ret = dsi_phy_enable_resource(phy); 767 + ret = pm_runtime_resume_and_get(dev); 745 768 if (ret) { 746 - DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n", 769 + DRM_DEV_ERROR(dev, "%s: resume failed, %d\n", 747 770 __func__, ret); 748 771 goto res_en_fail; 749 772 } ··· 787 810 phy_en_fail: 788 811 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); 789 812 reg_en_fail: 790 - dsi_phy_disable_resource(phy); 813 + pm_runtime_put(dev); 791 814 res_en_fail: 792 815 return ret; 793 816 } ··· 800 823 phy->cfg->ops.disable(phy); 801 824 802 825 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); 803 - dsi_phy_disable_resource(phy); 826 + pm_runtime_put(&phy->pdev->dev); 804 827 } 805 828 806 829 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,

-1

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

··· 104 104 phys_addr_t lane_size; 105 105 int id; 106 106 107 - struct clk *ahb_clk; 108 107 struct regulator_bulk_data *supplies; 109 108 110 109 struct msm_dsi_dphy_timing timing;

+7 -4

drivers/gpu/drm/msm/msm_debugfs.c

··· 325 325 326 326 static int late_init_minor(struct drm_minor *minor) 327 327 { 328 - struct drm_device *dev = minor->dev; 329 - struct msm_drm_private *priv = dev->dev_private; 328 + struct drm_device *dev; 329 + struct msm_drm_private *priv; 330 330 int ret; 331 331 332 332 if (!minor) 333 333 return 0; 334 + 335 + dev = minor->dev; 336 + priv = dev->dev_private; 334 337 335 338 if (!priv->gpu_pdev) 336 339 return 0; 337 340 338 341 ret = msm_rd_debugfs_init(minor); 339 342 if (ret) { 340 - DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); 343 + DRM_DEV_ERROR(dev->dev, "could not install rd debugfs\n"); 341 344 return ret; 342 345 } 343 346 344 347 ret = msm_perf_debugfs_init(minor); 345 348 if (ret) { 346 - DRM_DEV_ERROR(minor->dev->dev, "could not install perf debugfs\n"); 349 + DRM_DEV_ERROR(dev->dev, "could not install perf debugfs\n"); 347 350 return ret; 348 351 } 349 352

+11 -2

drivers/gpu/drm/msm/msm_gem.c

··· 95 95 void msm_gem_vma_put(struct drm_gem_object *obj) 96 96 { 97 97 struct msm_drm_private *priv = obj->dev->dev_private; 98 - struct drm_exec exec; 99 98 100 99 if (atomic_dec_return(&to_msm_bo(obj)->vma_ref)) 101 100 return; ··· 102 103 if (!priv->kms) 103 104 return; 104 105 106 + #ifdef CONFIG_DRM_MSM_KMS 107 + struct drm_exec exec; 108 + 105 109 msm_gem_lock_vm_and_obj(&exec, obj, priv->kms->vm); 106 110 put_iova_spaces(obj, priv->kms->vm, true, "vma_put"); 107 111 drm_exec_fini(&exec); /* drop locks */ 112 + #endif 108 113 } 109 114 110 115 /* ··· 666 663 667 664 static bool is_kms_vm(struct drm_gpuvm *vm) 668 665 { 666 + #ifdef CONFIG_DRM_MSM_KMS 669 667 struct msm_drm_private *priv = vm->drm->dev_private; 670 668 671 669 return priv->kms && (priv->kms->vm == vm); 670 + #else 671 + return false; 672 + #endif 672 673 } 673 674 674 675 /* ··· 1120 1113 put_pages(obj); 1121 1114 } 1122 1115 1123 - if (msm_obj->flags & MSM_BO_NO_SHARE) { 1116 + if (obj->resv != &obj->_resv) { 1124 1117 struct drm_gem_object *r_obj = 1125 1118 container_of(obj->resv, struct drm_gem_object, _resv); 1119 + 1120 + WARN_ON(!(msm_obj->flags & MSM_BO_NO_SHARE)); 1126 1121 1127 1122 /* Drop reference we hold to shared resv obj: */ 1128 1123 drm_gem_object_put(r_obj);

+1 -1

drivers/gpu/drm/msm/msm_gem.h

··· 100 100 * 101 101 * Only used for kernel managed VMs, unused for user managed VMs. 102 102 * 103 - * Protected by @mm_lock. 103 + * Protected by vm lock. See msm_gem_lock_vm_and_obj(), for ex. 104 104 */ 105 105 struct drm_mm mm; 106 106

+41 -35

drivers/gpu/drm/msm/msm_gem_submit.c

··· 271 271 return ret; 272 272 } 273 273 274 + static int submit_lock_objects_vmbind(struct msm_gem_submit *submit) 275 + { 276 + unsigned flags = DRM_EXEC_INTERRUPTIBLE_WAIT | DRM_EXEC_IGNORE_DUPLICATES; 277 + struct drm_exec *exec = &submit->exec; 278 + int ret = 0; 279 + 280 + drm_exec_init(&submit->exec, flags, submit->nr_bos); 281 + 282 + drm_exec_until_all_locked (&submit->exec) { 283 + ret = drm_gpuvm_prepare_vm(submit->vm, exec, 1); 284 + drm_exec_retry_on_contention(exec); 285 + if (ret) 286 + break; 287 + 288 + ret = drm_gpuvm_prepare_objects(submit->vm, exec, 1); 289 + drm_exec_retry_on_contention(exec); 290 + if (ret) 291 + break; 292 + } 293 + 294 + return ret; 295 + } 296 + 274 297 /* This is where we make sure all the bo's are reserved and pin'd: */ 275 298 static int submit_lock_objects(struct msm_gem_submit *submit) 276 299 { 277 300 unsigned flags = DRM_EXEC_INTERRUPTIBLE_WAIT; 278 - struct drm_exec *exec = &submit->exec; 279 - int ret; 301 + int ret = 0; 280 302 281 - if (msm_context_is_vmbind(submit->queue->ctx)) { 282 - flags |= DRM_EXEC_IGNORE_DUPLICATES; 283 - 284 - drm_exec_init(&submit->exec, flags, submit->nr_bos); 285 - 286 - drm_exec_until_all_locked (&submit->exec) { 287 - ret = drm_gpuvm_prepare_vm(submit->vm, exec, 1); 288 - drm_exec_retry_on_contention(exec); 289 - if (ret) 290 - return ret; 291 - 292 - ret = drm_gpuvm_prepare_objects(submit->vm, exec, 1); 293 - drm_exec_retry_on_contention(exec); 294 - if (ret) 295 - return ret; 296 - } 297 - 298 - return 0; 299 - } 303 + if (msm_context_is_vmbind(submit->queue->ctx)) 304 + return submit_lock_objects_vmbind(submit); 300 305 301 306 drm_exec_init(&submit->exec, flags, submit->nr_bos); 302 307 ··· 310 305 drm_gpuvm_resv_obj(submit->vm)); 311 306 drm_exec_retry_on_contention(&submit->exec); 312 307 if (ret) 313 - return ret; 308 + break; 314 309 for (unsigned i = 0; i < submit->nr_bos; i++) { 315 310 struct drm_gem_object *obj = submit->bos[i].obj; 316 311 ret = drm_exec_prepare_obj(&submit->exec, obj, 1); 317 312 drm_exec_retry_on_contention(&submit->exec); 318 313 if (ret) 319 - return ret; 314 + break; 320 315 } 321 316 } 322 317 323 - return 0; 318 + return ret; 324 319 } 325 320 326 321 static int submit_fence_sync(struct msm_gem_submit *submit) ··· 519 514 */ 520 515 static void submit_cleanup(struct msm_gem_submit *submit, bool error) 521 516 { 517 + if (error) 518 + submit_unpin_objects(submit); 519 + 522 520 if (submit->exec.objects) 523 521 drm_exec_fini(&submit->exec); 524 522 525 - if (error) { 526 - submit_unpin_objects(submit); 527 - /* job wasn't enqueued to scheduler, so early retirement: */ 523 + /* if job wasn't enqueued to scheduler, early retirement: */ 524 + if (error) 528 525 msm_submit_retire(submit); 529 - } 530 526 } 531 527 532 528 void msm_submit_retire(struct msm_gem_submit *submit) ··· 775 769 776 770 if (ret == 0 && args->flags & MSM_SUBMIT_FENCE_FD_OUT) { 777 771 sync_file = sync_file_create(submit->user_fence); 778 - if (!sync_file) { 772 + if (!sync_file) 779 773 ret = -ENOMEM; 780 - } else { 781 - fd_install(out_fence_fd, sync_file->file); 782 - args->fence_fd = out_fence_fd; 783 - } 784 774 } 785 775 786 776 if (ret) ··· 814 812 out_unlock: 815 813 mutex_unlock(&queue->lock); 816 814 out_post_unlock: 817 - if (ret && (out_fence_fd >= 0)) { 818 - put_unused_fd(out_fence_fd); 815 + if (ret) { 816 + if (out_fence_fd >= 0) 817 + put_unused_fd(out_fence_fd); 819 818 if (sync_file) 820 819 fput(sync_file->file); 820 + } else if (sync_file) { 821 + fd_install(out_fence_fd, sync_file->file); 822 + args->fence_fd = out_fence_fd; 821 823 } 822 824 823 825 if (!IS_ERR_OR_NULL(submit)) {

+45 -15

drivers/gpu/drm/msm/msm_gem_vma.c

··· 319 319 mutex_lock(&vm->mmu_lock); 320 320 321 321 /* 322 - * NOTE: iommu/io-pgtable can allocate pages, so we cannot hold 322 + * NOTE: if not using pgtable preallocation, we cannot hold 323 323 * a lock across map/unmap which is also used in the job_run() 324 324 * path, as this can cause deadlock in job_run() vs shrinker/ 325 325 * reclaim. 326 - * 327 - * Revisit this if we can come up with a scheme to pre-alloc pages 328 - * for the pgtable in map/unmap ops. 329 326 */ 330 327 ret = vm_map_op(vm, &(struct msm_vm_map_op){ 331 328 .iova = vma->va.addr, ··· 451 454 struct op_arg { 452 455 unsigned flags; 453 456 struct msm_vm_bind_job *job; 457 + const struct msm_vm_bind_op *op; 458 + bool kept; 454 459 }; 455 460 456 461 static void ··· 474 475 } 475 476 476 477 static int 477 - msm_gem_vm_sm_step_map(struct drm_gpuva_op *op, void *arg) 478 + msm_gem_vm_sm_step_map(struct drm_gpuva_op *op, void *_arg) 478 479 { 479 - struct msm_vm_bind_job *job = ((struct op_arg *)arg)->job; 480 + struct op_arg *arg = _arg; 481 + struct msm_vm_bind_job *job = arg->job; 480 482 struct drm_gem_object *obj = op->map.gem.obj; 481 483 struct drm_gpuva *vma; 482 484 struct sg_table *sgt; 483 485 unsigned prot; 486 + 487 + if (arg->kept) 488 + return 0; 484 489 485 490 vma = vma_from_op(arg, &op->map); 486 491 if (WARN_ON(IS_ERR(vma))) ··· 605 602 } 606 603 607 604 static int 608 - msm_gem_vm_sm_step_unmap(struct drm_gpuva_op *op, void *arg) 605 + msm_gem_vm_sm_step_unmap(struct drm_gpuva_op *op, void *_arg) 609 606 { 610 - struct msm_vm_bind_job *job = ((struct op_arg *)arg)->job; 607 + struct op_arg *arg = _arg; 608 + struct msm_vm_bind_job *job = arg->job; 611 609 struct drm_gpuva *vma = op->unmap.va; 612 610 struct msm_gem_vma *msm_vma = to_msm_vma(vma); 613 611 614 612 vm_dbg("%p:%p:%p: %016llx %016llx", vma->vm, vma, vma->gem.obj, 615 613 vma->va.addr, vma->va.range); 614 + 615 + /* 616 + * Detect in-place remap. Turnip does this to change the vma flags, 617 + * in particular MSM_VMA_DUMP. In this case we want to avoid actually 618 + * touching the page tables, as that would require synchronization 619 + * against SUBMIT jobs running on the GPU. 620 + */ 621 + if (op->unmap.keep && 622 + (arg->op->op == MSM_VM_BIND_OP_MAP) && 623 + (vma->gem.obj == arg->op->obj) && 624 + (vma->gem.offset == arg->op->obj_offset) && 625 + (vma->va.addr == arg->op->iova) && 626 + (vma->va.range == arg->op->range)) { 627 + /* We are only expecting a single in-place unmap+map cb pair: */ 628 + WARN_ON(arg->kept); 629 + 630 + /* Leave the existing VMA in place, but signal that to the map cb: */ 631 + arg->kept = true; 632 + 633 + /* Only flags are changing, so update that in-place: */ 634 + unsigned orig_flags = vma->flags & (DRM_GPUVA_USERBITS - 1); 635 + vma->flags = orig_flags | arg->flags; 636 + 637 + return 0; 638 + } 616 639 617 640 if (!msm_vma->mapped) 618 641 goto out_close; ··· 1300 1271 const struct msm_vm_bind_op *op = &job->ops[i]; 1301 1272 struct op_arg arg = { 1302 1273 .job = job, 1274 + .op = op, 1303 1275 }; 1304 1276 1305 1277 switch (op->op) { ··· 1490 1460 1491 1461 if (args->flags & MSM_VM_BIND_FENCE_FD_OUT) { 1492 1462 sync_file = sync_file_create(job->fence); 1493 - if (!sync_file) { 1463 + if (!sync_file) 1494 1464 ret = -ENOMEM; 1495 - } else { 1496 - fd_install(out_fence_fd, sync_file->file); 1497 - args->fence_fd = out_fence_fd; 1498 - } 1499 1465 } 1500 1466 1501 1467 if (ret) ··· 1520 1494 out_unlock: 1521 1495 mutex_unlock(&queue->lock); 1522 1496 out_post_unlock: 1523 - if (ret && (out_fence_fd >= 0)) { 1524 - put_unused_fd(out_fence_fd); 1497 + if (ret) { 1498 + if (out_fence_fd >= 0) 1499 + put_unused_fd(out_fence_fd); 1525 1500 if (sync_file) 1526 1501 fput(sync_file->file); 1502 + } else if (sync_file) { 1503 + fd_install(out_fence_fd, sync_file->file); 1504 + args->fence_fd = out_fence_fd; 1527 1505 } 1528 1506 1529 1507 if (!IS_ERR_OR_NULL(job)) {

+16 -4

drivers/gpu/drm/msm/msm_gpu.c

··· 465 465 struct msm_gem_submit *submit; 466 466 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 467 467 char *comm = NULL, *cmd = NULL; 468 + struct task_struct *task; 468 469 int i; 469 470 470 471 mutex_lock(&gpu->lock); ··· 483 482 484 483 /* Increment the fault counts */ 485 484 submit->queue->faults++; 486 - if (submit->vm) { 485 + 486 + task = get_pid_task(submit->pid, PIDTYPE_PID); 487 + if (!task) 488 + gpu->global_faults++; 489 + else { 487 490 struct msm_gem_vm *vm = to_msm_vm(submit->vm); 488 491 489 492 vm->faults++; 490 493 491 494 /* 492 495 * If userspace has opted-in to VM_BIND (and therefore userspace 493 - * management of the VM), faults mark the VM as unusuable. This 496 + * management of the VM), faults mark the VM as unusable. This 494 497 * matches vulkan expectations (vulkan is the main target for 495 - * VM_BIND) 498 + * VM_BIND). 496 499 */ 497 500 if (!vm->managed) 498 501 msm_gem_vm_unusable(submit->vm); ··· 558 553 unsigned long flags; 559 554 560 555 spin_lock_irqsave(&ring->submit_lock, flags); 561 - list_for_each_entry(submit, &ring->submits, node) 556 + list_for_each_entry(submit, &ring->submits, node) { 557 + /* 558 + * If the submit uses an unusable vm make sure 559 + * we don't actually run it 560 + */ 561 + if (to_msm_vm(submit->vm)->unusable) 562 + submit->nr_cmds = 0; 562 563 gpu->funcs->submit(gpu, submit); 564 + } 563 565 spin_unlock_irqrestore(&ring->submit_lock, flags); 564 566 } 565 567 }

+12 -4

drivers/gpu/drm/msm/msm_iommu.c

··· 14 14 struct msm_iommu { 15 15 struct msm_mmu base; 16 16 struct iommu_domain *domain; 17 - atomic_t pagetables; 17 + 18 + struct mutex init_lock; /* protects pagetables counter and prr_page */ 19 + int pagetables; 18 20 struct page *prr_page; 19 21 20 22 struct kmem_cache *pt_cache; ··· 229 227 * If this is the last attached pagetable for the parent, 230 228 * disable TTBR0 in the arm-smmu driver 231 229 */ 232 - if (atomic_dec_return(&iommu->pagetables) == 0) { 230 + mutex_lock(&iommu->init_lock); 231 + if (--iommu->pagetables == 0) { 233 232 adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL); 234 233 235 234 if (adreno_smmu->set_prr_bit) { ··· 239 236 iommu->prr_page = NULL; 240 237 } 241 238 } 239 + mutex_unlock(&iommu->init_lock); 242 240 243 241 free_io_pgtable_ops(pagetable->pgtbl_ops); 244 242 kfree(pagetable); ··· 572 568 * If this is the first pagetable that we've allocated, send it back to 573 569 * the arm-smmu driver as a trigger to set up TTBR0 574 570 */ 575 - if (atomic_inc_return(&iommu->pagetables) == 1) { 571 + mutex_lock(&iommu->init_lock); 572 + if (iommu->pagetables++ == 0) { 576 573 ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg); 577 574 if (ret) { 575 + iommu->pagetables--; 576 + mutex_unlock(&iommu->init_lock); 578 577 free_io_pgtable_ops(pagetable->pgtbl_ops); 579 578 kfree(pagetable); 580 579 return ERR_PTR(ret); ··· 602 595 adreno_smmu->set_prr_bit(adreno_smmu->cookie, true); 603 596 } 604 597 } 598 + mutex_unlock(&iommu->init_lock); 605 599 606 600 /* Needed later for TLB flush */ 607 601 pagetable->parent = parent; ··· 738 730 iommu->domain = domain; 739 731 msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); 740 732 741 - atomic_set(&iommu->pagetables, 0); 733 + mutex_init(&iommu->init_lock); 742 734 743 735 ret = iommu_attach_device(iommu->domain, dev); 744 736 if (ret) {

+6 -4

drivers/gpu/drm/msm/msm_kms.c

··· 275 275 if (ret) 276 276 return ret; 277 277 278 + ret = msm_disp_snapshot_init(ddev); 279 + if (ret) { 280 + DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 281 + return ret; 282 + } 283 + 278 284 ret = priv->kms_init(ddev); 279 285 if (ret) { 280 286 DRM_DEV_ERROR(dev, "failed to load kms\n"); ··· 332 326 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 333 327 goto err_msm_uninit; 334 328 } 335 - 336 - ret = msm_disp_snapshot_init(ddev); 337 - if (ret) 338 - DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 339 329 340 330 drm_mode_config_reset(ddev); 341 331

+1 -1

drivers/gpu/drm/msm/msm_mdss.c

··· 423 423 if (IS_ERR(msm_mdss->mmio)) 424 424 return ERR_CAST(msm_mdss->mmio); 425 425 426 - dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 426 + dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio); 427 427 428 428 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 429 429 if (ret)

+13 -1

drivers/gpu/drm/msm/registers/adreno/a6xx.xml

··· 594 594 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 595 595 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 596 596 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 597 - <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D"> 597 + <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A6XX"> 598 598 <bitfield high="7" low="0" name="PING_INDEX"/> 599 599 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 600 + </reg32> 601 + <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A7XX-"> 602 + <bitfield high="7" low="0" name="PING_INDEX"/> 603 + <bitfield high="24" low="16" name="PING_BLK_SEL"/> 600 604 </reg32> 601 605 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 602 606 <bitfield high="5" low="0" name="TRACEEN"/> ··· 3798 3794 3799 3795 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 3800 3796 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 3797 + </domain> 3798 + 3799 + <domain name="A7XX_CX_DBGC" width="32"> 3800 +  3801 + <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 3802 + <bitfield high="7" low="0" name="PING_INDEX"/> 3803 + <bitfield high="24" low="16" name="PING_BLK_SEL"/> 3804 + </reg32> 3801 3805 </domain> 3802 3806 3803 3807 <domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">

+14 -14

drivers/gpu/drm/msm/registers/display/dsi.xml

··· 159 159 <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/> 160 160 </reg32> 161 161 <reg32 offset="0x00020" name="ACTIVE_H"> 162 - <bitfield name="START" low="0" high="11" type="uint"/> 163 - <bitfield name="END" low="16" high="27" type="uint"/> 162 + <bitfield name="START" low="0" high="15" type="uint"/> 163 + <bitfield name="END" low="16" high="31" type="uint"/> 164 164 </reg32> 165 165 <reg32 offset="0x00024" name="ACTIVE_V"> 166 - <bitfield name="START" low="0" high="11" type="uint"/> 167 - <bitfield name="END" low="16" high="27" type="uint"/> 166 + <bitfield name="START" low="0" high="15" type="uint"/> 167 + <bitfield name="END" low="16" high="31" type="uint"/> 168 168 </reg32> 169 169 <reg32 offset="0x00028" name="TOTAL"> 170 - <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> 171 - <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> 170 + <bitfield name="H_TOTAL" low="0" high="15" type="uint"/> 171 + <bitfield name="V_TOTAL" low="16" high="31" type="uint"/> 172 172 </reg32> 173 173 <reg32 offset="0x0002c" name="ACTIVE_HSYNC"> 174 - <bitfield name="START" low="0" high="11" type="uint"/> 175 - <bitfield name="END" low="16" high="27" type="uint"/> 174 + <bitfield name="START" low="0" high="15" type="uint"/> 175 + <bitfield name="END" low="16" high="31" type="uint"/> 176 176 </reg32> 177 177 <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS"> 178 - <bitfield name="START" low="0" high="11" type="uint"/> 179 - <bitfield name="END" low="16" high="27" type="uint"/> 178 + <bitfield name="START" low="0" high="15" type="uint"/> 179 + <bitfield name="END" low="16" high="31" type="uint"/> 180 180 </reg32> 181 181 <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS"> 182 - <bitfield name="START" low="0" high="11" type="uint"/> 183 - <bitfield name="END" low="16" high="27" type="uint"/> 182 + <bitfield name="START" low="0" high="15" type="uint"/> 183 + <bitfield name="END" low="16" high="31" type="uint"/> 184 184 </reg32> 185 185 186 186 <reg32 offset="0x00038" name="CMD_DMA_CTRL"> ··· 209 209 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/> 210 210 </reg32> 211 211 <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL"> 212 - <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> 213 - <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> 212 + <bitfield name="H_TOTAL" low="0" high="15" type="uint"/> 213 + <bitfield name="V_TOTAL" low="16" high="31" type="uint"/> 214 214 </reg32> 215 215 <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL"> 216 216 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>

+4

drivers/gpu/drm/nouveau/dispnv50/wndw.c

··· 795 795 struct nouveau_drm *drm = nouveau_drm(plane->dev); 796 796 uint8_t i; 797 797 798 + /* All chipsets can display all formats in linear layout */ 799 + if (modifier == DRM_FORMAT_MOD_LINEAR) 800 + return true; 801 + 798 802 if (drm->client.device.info.chipset < 0xc0) { 799 803 const struct drm_format_info *info = drm_format_info(format); 800 804 const uint8_t kind = (modifier >> 12) & 0xff;

+4 -11

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

··· 103 103 static void 104 104 gm200_flcn_pio_imem_wr(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len, u16 tag) 105 105 { 106 - nvkm_falcon_wr32(falcon, 0x188 + (port * 0x10), tag++); 106 + nvkm_falcon_wr32(falcon, 0x188 + (port * 0x10), tag); 107 107 while (len >= 4) { 108 108 nvkm_falcon_wr32(falcon, 0x184 + (port * 0x10), *(u32 *)img); 109 109 img += 4; ··· 249 249 gm200_flcn_fw_load(struct nvkm_falcon_fw *fw) 250 250 { 251 251 struct nvkm_falcon *falcon = fw->falcon; 252 - int target, ret; 252 + int ret; 253 253 254 254 if (fw->inst) { 255 + int target; 256 + 255 257 nvkm_falcon_mask(falcon, 0x048, 0x00000001, 0x00000001); 256 258 257 259 switch (nvkm_memory_target(fw->inst)) { ··· 287 285 } 288 286 289 287 if (fw->boot) { 290 - switch (nvkm_memory_target(&fw->fw.mem.memory)) { 291 - case NVKM_MEM_TARGET_VRAM: target = 4; break; 292 - case NVKM_MEM_TARGET_HOST: target = 5; break; 293 - case NVKM_MEM_TARGET_NCOH: target = 6; break; 294 - default: 295 - WARN_ON(1); 296 - return -EINVAL; 297 - } 298 - 299 288 ret = nvkm_falcon_pio_wr(falcon, fw->boot, 0, 0, 300 289 IMEM, falcon->code.limit - fw->boot_size, fw->boot_size, 301 290 fw->boot_addr >> 8, false);

+3 -2

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c

··· 209 209 fw->boot_addr = bld->start_tag << 8; 210 210 fw->boot_size = bld->code_size; 211 211 fw->boot = kmemdup(bl->data + hdr->data_offset + bld->code_off, fw->boot_size, GFP_KERNEL); 212 - if (!fw->boot) 213 - ret = -ENOMEM; 214 212 215 213 nvkm_firmware_put(bl); 214 + 215 + if (!fw->boot) 216 + return -ENOMEM; 216 217 217 218 /* Patch in interface data. */ 218 219 return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd);

+1 -1

drivers/gpu/drm/tegra/gem.c

··· 526 526 if (drm_gem_is_imported(gem)) { 527 527 dma_buf_unmap_attachment_unlocked(gem->import_attach, bo->sgt, 528 528 DMA_TO_DEVICE); 529 - dma_buf_detach(gem->dma_buf, gem->import_attach); 529 + dma_buf_detach(gem->import_attach->dmabuf, gem->import_attach); 530 530 } 531 531 } 532 532

+4 -4

drivers/gpu/drm/xe/xe_bo.c

··· 812 812 } 813 813 814 814 if (ttm_bo->type == ttm_bo_type_sg) { 815 - ret = xe_bo_move_notify(bo, ctx); 815 + if (new_mem->mem_type == XE_PL_SYSTEM) 816 + ret = xe_bo_move_notify(bo, ctx); 816 817 if (!ret) 817 818 ret = xe_bo_move_dmabuf(ttm_bo, new_mem); 818 819 return ret; ··· 2439 2438 .no_wait_gpu = false, 2440 2439 .gfp_retry_mayfail = true, 2441 2440 }; 2442 - struct pin_cookie cookie; 2443 2441 int ret; 2444 2442 2445 2443 if (vm) { ··· 2449 2449 ctx.resv = xe_vm_resv(vm); 2450 2450 } 2451 2451 2452 - cookie = xe_vm_set_validating(vm, allow_res_evict); 2452 + xe_vm_set_validating(vm, allow_res_evict); 2453 2453 trace_xe_bo_validate(bo); 2454 2454 ret = ttm_bo_validate(&bo->ttm, &bo->placement, &ctx); 2455 - xe_vm_clear_validating(vm, allow_res_evict, cookie); 2455 + xe_vm_clear_validating(vm, allow_res_evict); 2456 2456 2457 2457 return ret; 2458 2458 }

+9 -1

drivers/gpu/drm/xe/xe_gen_wa_oob.c

··· 123 123 return 0; 124 124 } 125 125 126 + /* Avoid GNU vs POSIX basename() discrepancy, just use our own */ 127 + static const char *xbasename(const char *s) 128 + { 129 + const char *p = strrchr(s, '/'); 130 + 131 + return p ? p + 1 : s; 132 + } 133 + 126 134 static int fn_to_prefix(const char *fn, char *prefix, size_t size) 127 135 { 128 136 size_t len; 129 137 130 - fn = basename(fn); 138 + fn = xbasename(fn); 131 139 len = strlen(fn); 132 140 133 141 if (len > size - 1)

+1 -1

drivers/gpu/drm/xe/xe_sync.c

··· 77 77 { 78 78 struct xe_user_fence *ufence = container_of(w, struct xe_user_fence, worker); 79 79 80 + WRITE_ONCE(ufence->signalled, 1); 80 81 if (mmget_not_zero(ufence->mm)) { 81 82 kthread_use_mm(ufence->mm); 82 83 if (copy_to_user(ufence->addr, &ufence->value, sizeof(ufence->value))) ··· 92 91 * Wake up waiters only after updating the ufence state, allowing the UMD 93 92 * to safely reuse the same ufence without encountering -EBUSY errors. 94 93 */ 95 - WRITE_ONCE(ufence->signalled, 1); 96 94 wake_up_all(&ufence->xe->ufence_wq); 97 95 user_fence_put(ufence); 98 96 }

+6 -2

drivers/gpu/drm/xe/xe_vm.c

··· 1610 1610 1611 1611 for (i = MAX_HUGEPTE_LEVEL; i < vm->pt_root[id]->level; i++) { 1612 1612 vm->scratch_pt[id][i] = xe_pt_create(vm, tile, i); 1613 - if (IS_ERR(vm->scratch_pt[id][i])) 1614 - return PTR_ERR(vm->scratch_pt[id][i]); 1613 + if (IS_ERR(vm->scratch_pt[id][i])) { 1614 + int err = PTR_ERR(vm->scratch_pt[id][i]); 1615 + 1616 + vm->scratch_pt[id][i] = NULL; 1617 + return err; 1618 + } 1615 1619 1616 1620 xe_pt_populate_empty(tile, vm, vm->scratch_pt[id][i]); 1617 1621 }

+2 -13

drivers/gpu/drm/xe/xe_vm.h

··· 315 315 * Register this task as currently making bos resident for the vm. Intended 316 316 * to avoid eviction by the same task of shared bos bound to the vm. 317 317 * Call with the vm's resv lock held. 318 - * 319 - * Return: A pin cookie that should be used for xe_vm_clear_validating(). 320 318 */ 321 - static inline struct pin_cookie xe_vm_set_validating(struct xe_vm *vm, 322 - bool allow_res_evict) 319 + static inline void xe_vm_set_validating(struct xe_vm *vm, bool allow_res_evict) 323 320 { 324 - struct pin_cookie cookie = {}; 325 - 326 321 if (vm && !allow_res_evict) { 327 322 xe_vm_assert_held(vm); 328 - cookie = lockdep_pin_lock(&xe_vm_resv(vm)->lock.base); 329 323 /* Pairs with READ_ONCE in xe_vm_is_validating() */ 330 324 WRITE_ONCE(vm->validating, current); 331 325 } 332 - 333 - return cookie; 334 326 } 335 327 336 328 /** ··· 330 338 * @vm: Pointer to the vm or NULL 331 339 * @allow_res_evict: Eviction from @vm was allowed. Must be set to the same 332 340 * value as for xe_vm_set_validation(). 333 - * @cookie: Cookie obtained from xe_vm_set_validating(). 334 341 * 335 342 * Register this task as currently making bos resident for the vm. Intended 336 343 * to avoid eviction by the same task of shared bos bound to the vm. 337 344 * Call with the vm's resv lock held. 338 345 */ 339 - static inline void xe_vm_clear_validating(struct xe_vm *vm, bool allow_res_evict, 340 - struct pin_cookie cookie) 346 + static inline void xe_vm_clear_validating(struct xe_vm *vm, bool allow_res_evict) 341 347 { 342 348 if (vm && !allow_res_evict) { 343 - lockdep_unpin_lock(&xe_vm_resv(vm)->lock.base, cookie); 344 349 /* Pairs with READ_ONCE in xe_vm_is_validating() */ 345 350 WRITE_ONCE(vm->validating, NULL); 346 351 }

+20 -3

drivers/soc/qcom/ubwc_config.c

··· 12 12 13 13 #include <linux/soc/qcom/ubwc.h> 14 14 15 + static const struct qcom_ubwc_cfg_data no_ubwc_data = { 16 + /* no UBWC, no HBB */ 17 + }; 18 + 15 19 static const struct qcom_ubwc_cfg_data msm8937_data = { 16 20 .ubwc_enc_version = UBWC_1_0, 17 21 .ubwc_dec_version = UBWC_1_0, ··· 219 215 }; 220 216 221 217 static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { 218 + { .compatible = "qcom,apq8016", .data = &no_ubwc_data }, 219 + { .compatible = "qcom,apq8026", .data = &no_ubwc_data }, 220 + { .compatible = "qcom,apq8074", .data = &no_ubwc_data }, 222 221 { .compatible = "qcom,apq8096", .data = &msm8998_data }, 223 - { .compatible = "qcom,msm8917", .data = &msm8937_data }, 222 + { .compatible = "qcom,msm8226", .data = &no_ubwc_data }, 223 + { .compatible = "qcom,msm8916", .data = &no_ubwc_data }, 224 + { .compatible = "qcom,msm8917", .data = &no_ubwc_data }, 224 225 { .compatible = "qcom,msm8937", .data = &msm8937_data }, 226 + { .compatible = "qcom,msm8929", .data = &no_ubwc_data }, 227 + { .compatible = "qcom,msm8939", .data = &no_ubwc_data }, 225 228 { .compatible = "qcom,msm8953", .data = &msm8937_data }, 226 - { .compatible = "qcom,msm8956", .data = &msm8937_data }, 227 - { .compatible = "qcom,msm8976", .data = &msm8937_data }, 229 + { .compatible = "qcom,msm8956", .data = &no_ubwc_data }, 230 + { .compatible = "qcom,msm8974", .data = &no_ubwc_data }, 231 + { .compatible = "qcom,msm8976", .data = &no_ubwc_data }, 228 232 { .compatible = "qcom,msm8996", .data = &msm8998_data }, 229 233 { .compatible = "qcom,msm8998", .data = &msm8998_data }, 230 234 { .compatible = "qcom,qcm2290", .data = &qcm2290_data, }, ··· 245 233 { .compatible = "qcom,sc7280", .data = &sc7280_data, }, 246 234 { .compatible = "qcom,sc8180x", .data = &sc8180x_data, }, 247 235 { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, }, 236 + { .compatible = "qcom,sda660", .data = &msm8937_data }, 237 + { .compatible = "qcom,sdm450", .data = &msm8937_data }, 248 238 { .compatible = "qcom,sdm630", .data = &msm8937_data }, 239 + { .compatible = "qcom,sdm632", .data = &msm8937_data }, 249 240 { .compatible = "qcom,sdm636", .data = &msm8937_data }, 250 241 { .compatible = "qcom,sdm660", .data = &msm8937_data }, 251 242 { .compatible = "qcom,sdm670", .data = &sdm670_data, }, ··· 261 246 { .compatible = "qcom,sm6375", .data = &sm6350_data, }, 262 247 { .compatible = "qcom,sm7125", .data = &sc7180_data }, 263 248 { .compatible = "qcom,sm7150", .data = &sm7150_data, }, 249 + { .compatible = "qcom,sm7225", .data = &sm6350_data, }, 250 + { .compatible = "qcom,sm7325", .data = &sc7280_data, }, 264 251 { .compatible = "qcom,sm8150", .data = &sm8150_data, }, 265 252 { .compatible = "qcom,sm8250", .data = &sm8250_data, }, 266 253 { .compatible = "qcom,sm8350", .data = &sm8350_data, },

+5 -5

include/drm/drm_gpuvm.h

··· 103 103 } va; 104 104 105 105 /** 106 - * @gem: structure containing the &drm_gem_object and it's offset 106 + * @gem: structure containing the &drm_gem_object and its offset 107 107 */ 108 108 struct { 109 109 /** ··· 843 843 } va; 844 844 845 845 /** 846 - * @gem: structure containing the &drm_gem_object and it's offset 846 + * @gem: structure containing the &drm_gem_object and its offset 847 847 */ 848 848 struct { 849 849 /** ··· 1189 1189 1190 1190 /** 1191 1191 * @sm_step_unmap: called from &drm_gpuvm_sm_map and 1192 - * &drm_gpuvm_sm_unmap to unmap an existent mapping 1192 + * &drm_gpuvm_sm_unmap to unmap an existing mapping 1193 1193 * 1194 - * This callback is called when existent mapping needs to be unmapped. 1194 + * This callback is called when existing mapping needs to be unmapped. 1195 1195 * This is the case when either a newly requested mapping encloses an 1196 - * existent mapping or an unmap of an existent mapping is requested. 1196 + * existing mapping or an unmap of an existing mapping is requested. 1197 1197 * 1198 1198 * The &priv pointer matches the one the driver passed to 1199 1199 * &drm_gpuvm_sm_map or &drm_gpuvm_sm_unmap, respectively.

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