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drm/i915/vrr: Pause DC Balancing for DSB commits

Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)

--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.

--v4:
- Move events to separate function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-17-mitulkumar.ajitkumar.golani@intel.com

authored by

Ville Syrjälä and committed by
Ankit Nautiyal 192bc98c 27a4250c

+22
+19
drivers/gpu/drm/i915/display/intel_display.c
··· 7330 7330 if (new_crtc_state->use_flipq) 7331 7331 intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); 7332 7332 7333 + if (new_crtc_state->vrr.dc_balance.enable) { 7334 + /* 7335 + * Pause the DMC DC balancing for the remainder of 7336 + * the commit so that vmin/vmax won't change after 7337 + * we've baked them into the DSB vblank evasion 7338 + * commands. 7339 + * 7340 + * FIXME maybe need a small delay here to make sure 7341 + * DMC has finished updating the values? Or we need 7342 + * a better DMC<->driver protocol that gives is real 7343 + * guarantees about that... 7344 + */ 7345 + intel_pipedmc_dcb_disable(NULL, crtc); 7346 + } 7347 + 7333 7348 if (intel_crtc_needs_color_update(new_crtc_state)) 7334 7349 intel_color_commit_noarm(new_crtc_state->dsb_commit, 7335 7350 new_crtc_state); ··· 7398 7383 intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); 7399 7384 intel_vrr_check_push_sent(new_crtc_state->dsb_commit, 7400 7385 new_crtc_state); 7386 + 7387 + if (new_crtc_state->vrr.dc_balance.enable) 7388 + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); 7389 + 7401 7390 intel_dsb_interrupt(new_crtc_state->dsb_commit); 7402 7391 } 7403 7392
+3
drivers/gpu/drm/i915/display/intel_vrr.c
··· 10 10 #include "intel_de.h" 11 11 #include "intel_display_regs.h" 12 12 #include "intel_display_types.h" 13 + #include "intel_dmc.h" 13 14 #include "intel_dmc_regs.h" 14 15 #include "intel_dp.h" 15 16 #include "intel_psr.h" ··· 825 824 crtc_state->vrr.dc_balance.vblank_target); 826 825 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 827 826 ADAPTIVE_SYNC_COUNTER_EN); 827 + intel_pipedmc_dcb_enable(NULL, crtc); 828 828 } 829 829 830 830 static void ··· 839 837 if (!old_crtc_state->vrr.dc_balance.enable) 840 838 return; 841 839 840 + intel_pipedmc_dcb_disable(NULL, crtc); 842 841 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); 843 842 intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); 844 843 intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);