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drm/amdgpu/pm: align Hawaii mclk workaround with radeon

Align the hawaii mclk workaround with radeon and windows.

Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816
Fixes: 9f4b35411cfe ("drm/amd/powerplay: add CI asics support to smumgr (v3)")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 9649528b637f668c5af9f2b83ca4ad8576ae2121)
Cc: stable@vger.kernel.org

Alex Deucher 1987c79b 2a561b36

+4 -4
+4 -4
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
··· 1336 1336 if ((dpm_table->mclk_table.count >= 2) && 1337 1337 ((dev_id == 0x67B0) || (dev_id == 0x67B1)) && 1338 1338 (adev->pdev->revision == 0)) { 1339 - smu_data->smc_state_table.MemoryLevel[1].MinVddci = 1340 - smu_data->smc_state_table.MemoryLevel[0].MinVddci; 1341 - smu_data->smc_state_table.MemoryLevel[1].MinMvdd = 1342 - smu_data->smc_state_table.MemoryLevel[0].MinMvdd; 1339 + smu_data->smc_state_table.MemoryLevel[1].MinVddc = 1340 + smu_data->smc_state_table.MemoryLevel[0].MinVddc; 1341 + smu_data->smc_state_table.MemoryLevel[1].MinVddcPhases = 1342 + smu_data->smc_state_table.MemoryLevel[0].MinVddcPhases; 1343 1343 } 1344 1344 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; 1345 1345 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);