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phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write

inno_write is used to configure 0xaa reg, that also hold the
POST_PLL_POWER_DOWN bit.
When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not
taken into consideration.

Fix this by keeping the power down bit until configuration is complete.
Also reorder the reg write order for consistency.

Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-5-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Jonas Karlman and committed by
Vinod Koul 19a1d46b b001c27d

+4 -2
+4 -2
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
··· 1020 1020 1021 1021 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); 1022 1022 if (cfg->postdiv == 1) { 1023 - inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); 1024 1023 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | 1025 1024 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); 1025 + inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | 1026 + RK3328_POST_PLL_POWER_DOWN); 1026 1027 } else { 1027 1028 v = (cfg->postdiv / 2) - 1; 1028 1029 v &= RK3328_POST_PLL_POST_DIV_MASK; ··· 1031 1030 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | 1032 1031 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); 1033 1032 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | 1034 - RK3328_POST_PLL_REFCLK_SEL_TMDS); 1033 + RK3328_POST_PLL_REFCLK_SEL_TMDS | 1034 + RK3328_POST_PLL_POWER_DOWN); 1035 1035 } 1036 1036 1037 1037 for (v = 0; v < 14; v++)