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clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes

Parent select bits for shared PLLs are in PLL_CON0, not PLL_CON3.
Using the wrong register leads to incorrect parent selection and rates.

Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-1-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Denzeel Oliva and committed by
Krzysztof Kozlowski 19b50ab0 e278e39b

+11 -4
+11 -4
drivers/clk/samsung/clk-exynos990.c
··· 239 239 PLL_LOCKTIME_PLL_SHARED2, 240 240 PLL_LOCKTIME_PLL_SHARED3, 241 241 PLL_LOCKTIME_PLL_SHARED4, 242 + PLL_CON0_PLL_G3D, 242 243 PLL_CON3_PLL_G3D, 244 + PLL_CON0_PLL_MMC, 243 245 PLL_CON3_PLL_MMC, 246 + PLL_CON0_PLL_SHARED0, 244 247 PLL_CON3_PLL_SHARED0, 248 + PLL_CON0_PLL_SHARED1, 245 249 PLL_CON3_PLL_SHARED1, 250 + PLL_CON0_PLL_SHARED2, 246 251 PLL_CON3_PLL_SHARED2, 252 + PLL_CON0_PLL_SHARED3, 247 253 PLL_CON3_PLL_SHARED3, 254 + PLL_CON0_PLL_SHARED4, 248 255 PLL_CON3_PLL_SHARED4, 249 256 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 250 257 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, ··· 696 689 697 690 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 698 691 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, 699 - PLL_CON3_PLL_SHARED0, 4, 1), 692 + PLL_CON0_PLL_SHARED0, 4, 1), 700 693 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, 701 - PLL_CON3_PLL_SHARED1, 4, 1), 694 + PLL_CON0_PLL_SHARED1, 4, 1), 702 695 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, 703 - PLL_CON3_PLL_SHARED2, 4, 1), 696 + PLL_CON0_PLL_SHARED2, 4, 1), 704 697 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, 705 - PLL_CON3_PLL_SHARED3, 4, 1), 698 + PLL_CON0_PLL_SHARED3, 4, 1), 706 699 MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p, 707 700 PLL_CON0_PLL_SHARED4, 4, 1), 708 701 MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,