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drm/amd/display: Rework YCbCr422 DSC policy

- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSC
enabled based on DSC caps and stream signal type

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Relja Vojvodic and committed by
Alex Deucher
19b79e4f 3967ab83

+25 -20
+1 -1
drivers/gpu/drm/amd/display/dc/dc.h
··· 563 563 bool frame_update_cmd_version2; 564 564 struct spl_sharpness_range dcn_sharpness_range; 565 565 struct spl_sharpness_range dcn_override_sharpness_range; 566 + bool no_native422_support; 566 567 }; 567 568 568 569 enum visual_confirm { ··· 988 987 * causing an issue or not. 989 988 */ 990 989 struct dc_debug_options { 991 - bool native422_support; 992 990 bool disable_dsc; 993 991 enum visual_confirm visual_confirm; 994 992 int visual_confirm_rect_height;
+1
drivers/gpu/drm/amd/display/dc/dc_dsc.h
··· 52 52 uint32_t max_target_bpp; 53 53 uint32_t min_target_bpp; 54 54 bool enable_dsc_when_not_needed; 55 + bool ycbcr422_simple; 55 56 }; 56 57 57 58 struct dc_dsc_config_options {
+3 -3
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
··· 1174 1174 const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index) 1175 1175 { 1176 1176 unsigned int plane_id; 1177 - int i = 0; 1178 - int location = -1; 1177 + unsigned int i = 0; 1178 + unsigned int location = UINT_MAX; 1179 1179 1180 1180 if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { 1181 1181 ASSERT(false); 1182 - return -1; 1182 + return UINT_MAX; 1183 1183 } 1184 1184 1185 1185 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
+6 -7
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
··· 680 680 } else { 681 681 build_dsc_enc_caps(dsc, dsc_enc_caps); 682 682 } 683 - 684 - if (dsc->ctx->dc->debug.native422_support) 685 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 686 683 } 687 684 688 685 /* Returns 'false' if no intersection was found for at least one capability. ··· 1097 1100 branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps; 1098 1101 break; 1099 1102 case PIXEL_ENCODING_YCBCR422: 1100 - is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; 1101 - sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; 1102 - branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; 1103 - if (!is_dsc_possible) { 1103 + if (policy.ycbcr422_simple) { 1104 1104 is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422; 1105 1105 dsc_cfg->ycbcr422_simple = is_dsc_possible; 1106 1106 sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps; 1107 + } else { 1108 + is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; 1109 + sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; 1110 + branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; 1107 1111 } 1108 1112 break; 1109 1113 case PIXEL_ENCODING_YCBCR420: ··· 1404 1406 policy->min_target_bpp = 8; 1405 1407 /* DP specs limits to 3 x bpc */ 1406 1408 policy->max_target_bpp = 3 * bpc; 1409 + policy->ycbcr422_simple = true; 1407 1410 break; 1408 1411 case PIXEL_ENCODING_YCBCR420: 1409 1412 /* DP specs limits to 6 */
+1 -1
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
··· 100 100 dsc_enc_caps->color_formats.bits.RGB = 1; 101 101 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 102 102 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 103 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 103 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 104 104 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 105 105 106 106 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
+1 -1
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
··· 128 128 dsc_enc_caps->color_formats.bits.RGB = 1; 129 129 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 130 130 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 131 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 131 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 132 132 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 133 133 134 134 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
+1 -1
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
··· 78 78 dsc_enc_caps->color_formats.bits.RGB = 1; 79 79 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 80 80 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 81 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 81 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 82 82 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 83 83 84 84 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
+2
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
··· 1963 1963 dc->config.use_pipe_ctx_sync_logic = true; 1964 1964 dc->config.disable_hbr_audio_dp2 = true; 1965 1965 1966 + dc->config.no_native422_support = true; 1967 + 1966 1968 /* read VBIOS LTTPR caps */ 1967 1969 { 1968 1970 if (ctx->dc_bios->funcs->get_lttpr_caps) {
+2
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
··· 1925 1925 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1926 1926 dc->caps.color.mpc.ocsc = 1; 1927 1927 1928 + dc->config.no_native422_support = true; 1929 + 1928 1930 /* read VBIOS LTTPR caps */ 1929 1931 { 1930 1932 if (ctx->dc_bios->funcs->get_lttpr_caps) {