Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King:
"Mainly a group of fixes, the only exception is the wiring up of the
kcmp syscall now that those patches went in during the last merge
window."
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations
ARM: 7667/1: perf: Fix section mismatch on armpmu_init()
ARM: 7666/1: decompressor: add -mno-single-pic-base for building the decompressor
ARM: 7665/1: Wire up kcmp syscall
ARM: 7664/1: perf: remove erroneous semicolon from event initialisation
ARM: 7663/1: perf: fix ARMv7 EVTYPE_MASK to include NSH bit
ARM: 7662/1: hw_breakpoint: reset debug logic on secondary CPUs in s2ram resume
ARM: 7661/1: mm: perform explicit branch predictor maintenance when required
ARM: 7660/1: tlb: add branch predictor maintenance operations
ARM: 7659/1: mm: make mm->context.id an atomic64_t variable
ARM: 7658/1: mm: fix race updating mm->context.id on ASID rollover
ARM: 7657/1: head: fix swapper and idmap population with LPAE and big-endian
ARM: 7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmp
ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.id
ARM: 7642/1: netx: bump IRQ offset to 64
+178
-109
+1
-1
arch/arm/boot/compressed/Makefile
+1
-1
arch/arm/boot/compressed/Makefile
···
120
120
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
121
121
endif
122
122
123
-
ccflags-y := -fpic -fno-builtin -I$(obj)
123
+
ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
124
124
asflags-y := -Wa,-march=all -DZIMAGE
125
125
126
126
# Supply kernel BSS size to the decompressor via a linker symbol.
+4
-4
arch/arm/include/asm/mmu.h
+4
-4
arch/arm/include/asm/mmu.h
···
5
5
6
6
typedef struct {
7
7
#ifdef CONFIG_CPU_HAS_ASID
8
-
u64 id;
8
+
atomic64_t id;
9
9
#endif
10
-
unsigned int vmalloc_seq;
10
+
unsigned int vmalloc_seq;
11
11
} mm_context_t;
12
12
13
13
#ifdef CONFIG_CPU_HAS_ASID
14
14
#define ASID_BITS 8
15
15
#define ASID_MASK ((~0ULL) << ASID_BITS)
16
-
#define ASID(mm) ((mm)->context.id & ~ASID_MASK)
16
+
#define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK)
17
17
#else
18
18
#define ASID(mm) (0)
19
19
#endif
···
26
26
* modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
27
27
*/
28
28
typedef struct {
29
-
unsigned long end_brk;
29
+
unsigned long end_brk;
30
30
} mm_context_t;
31
31
32
32
#endif
+1
-1
arch/arm/include/asm/mmu_context.h
+1
-1
arch/arm/include/asm/mmu_context.h
···
25
25
#ifdef CONFIG_CPU_HAS_ASID
26
26
27
27
void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
28
-
#define init_new_context(tsk,mm) ({ mm->context.id = 0; })
28
+
#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
29
29
30
30
#else /* !CONFIG_CPU_HAS_ASID */
31
31
+28
-6
arch/arm/include/asm/tlbflush.h
+28
-6
arch/arm/include/asm/tlbflush.h
···
34
34
#define TLB_V6_D_ASID (1 << 17)
35
35
#define TLB_V6_I_ASID (1 << 18)
36
36
37
+
#define TLB_V6_BP (1 << 19)
38
+
37
39
/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
38
-
#define TLB_V7_UIS_PAGE (1 << 19)
39
-
#define TLB_V7_UIS_FULL (1 << 20)
40
-
#define TLB_V7_UIS_ASID (1 << 21)
40
+
#define TLB_V7_UIS_PAGE (1 << 20)
41
+
#define TLB_V7_UIS_FULL (1 << 21)
42
+
#define TLB_V7_UIS_ASID (1 << 22)
43
+
#define TLB_V7_UIS_BP (1 << 23)
41
44
42
45
#define TLB_BARRIER (1 << 28)
43
46
#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
···
153
150
#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
154
151
TLB_V6_I_FULL | TLB_V6_D_FULL | \
155
152
TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
156
-
TLB_V6_I_ASID | TLB_V6_D_ASID)
153
+
TLB_V6_I_ASID | TLB_V6_D_ASID | \
154
+
TLB_V6_BP)
157
155
158
156
#ifdef CONFIG_CPU_TLB_V6
159
157
# define v6wbi_possible_flags v6wbi_tlb_flags
···
170
166
#endif
171
167
172
168
#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
173
-
TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
169
+
TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
170
+
TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
174
171
#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
175
-
TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
172
+
TLB_V6_U_FULL | TLB_V6_U_PAGE | \
173
+
TLB_V6_U_ASID | TLB_V6_BP)
176
174
177
175
#ifdef CONFIG_CPU_TLB_V7
178
176
···
436
430
}
437
431
}
438
432
433
+
static inline void local_flush_bp_all(void)
434
+
{
435
+
const int zero = 0;
436
+
const unsigned int __tlb_flag = __cpu_tlb_flags;
437
+
438
+
if (tlb_flag(TLB_V7_UIS_BP))
439
+
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
440
+
else if (tlb_flag(TLB_V6_BP))
441
+
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
442
+
443
+
if (tlb_flag(TLB_BARRIER))
444
+
isb();
445
+
}
446
+
439
447
/*
440
448
* flush_pmd_entry
441
449
*
···
500
480
#define flush_tlb_kernel_page local_flush_tlb_kernel_page
501
481
#define flush_tlb_range local_flush_tlb_range
502
482
#define flush_tlb_kernel_range local_flush_tlb_kernel_range
483
+
#define flush_bp_all local_flush_bp_all
503
484
#else
504
485
extern void flush_tlb_all(void);
505
486
extern void flush_tlb_mm(struct mm_struct *mm);
···
508
487
extern void flush_tlb_kernel_page(unsigned long kaddr);
509
488
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
510
489
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
490
+
extern void flush_bp_all(void);
511
491
#endif
512
492
513
493
/*
+1
-1
arch/arm/include/uapi/asm/unistd.h
+1
-1
arch/arm/include/uapi/asm/unistd.h
···
404
404
#define __NR_setns (__NR_SYSCALL_BASE+375)
405
405
#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376)
406
406
#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377)
407
-
/* 378 for kcmp */
407
+
#define __NR_kcmp (__NR_SYSCALL_BASE+378)
408
408
#define __NR_finit_module (__NR_SYSCALL_BASE+379)
409
409
410
410
/*
+1
-1
arch/arm/kernel/asm-offsets.c
+1
-1
arch/arm/kernel/asm-offsets.c
···
110
110
BLANK();
111
111
#endif
112
112
#ifdef CONFIG_CPU_HAS_ASID
113
-
DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
113
+
DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
114
114
BLANK();
115
115
#endif
116
116
DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
+1
-1
arch/arm/kernel/calls.S
+1
-1
arch/arm/kernel/calls.S
···
387
387
/* 375 */ CALL(sys_setns)
388
388
CALL(sys_process_vm_readv)
389
389
CALL(sys_process_vm_writev)
390
-
CALL(sys_ni_syscall) /* reserved for sys_kcmp */
390
+
CALL(sys_kcmp)
391
391
CALL(sys_finit_module)
392
392
#ifndef syscalls_counted
393
393
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
+22
-4
arch/arm/kernel/head.S
+22
-4
arch/arm/kernel/head.S
···
184
184
orr r3, r3, #3 @ PGD block type
185
185
mov r6, #4 @ PTRS_PER_PGD
186
186
mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
187
-
1: str r3, [r0], #4 @ set bottom PGD entry bits
187
+
1:
188
+
#ifdef CONFIG_CPU_ENDIAN_BE8
188
189
str r7, [r0], #4 @ set top PGD entry bits
190
+
str r3, [r0], #4 @ set bottom PGD entry bits
191
+
#else
192
+
str r3, [r0], #4 @ set bottom PGD entry bits
193
+
str r7, [r0], #4 @ set top PGD entry bits
194
+
#endif
189
195
add r3, r3, #0x1000 @ next PMD table
190
196
subs r6, r6, #1
191
197
bne 1b
192
198
193
199
add r4, r4, #0x1000 @ point to the PMD tables
200
+
#ifdef CONFIG_CPU_ENDIAN_BE8
201
+
add r4, r4, #4 @ we only write the bottom word
202
+
#endif
194
203
#endif
195
204
196
205
ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
···
267
258
addne r6, r6, #1 << SECTION_SHIFT
268
259
strne r6, [r3]
269
260
261
+
#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
262
+
sub r4, r4, #4 @ Fixup page table pointer
263
+
@ for 64-bit descriptors
264
+
#endif
265
+
270
266
#ifdef CONFIG_DEBUG_LL
271
267
#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
272
268
/*
···
290
276
orr r3, r7, r3, lsl #SECTION_SHIFT
291
277
#ifdef CONFIG_ARM_LPAE
292
278
mov r7, #1 << (54 - 32) @ XN
279
+
#ifdef CONFIG_CPU_ENDIAN_BE8
280
+
str r7, [r0], #4
281
+
str r3, [r0], #4
282
+
#else
283
+
str r3, [r0], #4
284
+
str r7, [r0], #4
285
+
#endif
293
286
#else
294
287
orr r3, r3, #PMD_SECT_XN
295
-
#endif
296
288
str r3, [r0], #4
297
-
#ifdef CONFIG_ARM_LPAE
298
-
str r7, [r0], #4
299
289
#endif
300
290
301
291
#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
+1
-1
arch/arm/kernel/hw_breakpoint.c
+1
-1
arch/arm/kernel/hw_breakpoint.c
···
1023
1023
static int __cpuinit dbg_reset_notify(struct notifier_block *self,
1024
1024
unsigned long action, void *cpu)
1025
1025
{
1026
-
if (action == CPU_ONLINE)
1026
+
if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
1027
1027
smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
1028
1028
1029
1029
return NOTIFY_OK;
+2
-2
arch/arm/kernel/perf_event.c
+2
-2
arch/arm/kernel/perf_event.c
···
400
400
}
401
401
402
402
if (event->group_leader != event) {
403
-
if (validate_group(event) != 0);
403
+
if (validate_group(event) != 0)
404
404
return -EINVAL;
405
405
}
406
406
···
484
484
SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
485
485
};
486
486
487
-
static void __init armpmu_init(struct arm_pmu *armpmu)
487
+
static void armpmu_init(struct arm_pmu *armpmu)
488
488
{
489
489
atomic_set(&armpmu->active_events, 0);
490
490
mutex_init(&armpmu->reserve_mutex);
+1
-1
arch/arm/kernel/perf_event_v7.c
+1
-1
arch/arm/kernel/perf_event_v7.c
+1
arch/arm/kernel/smp.c
+1
arch/arm/kernel/smp.c
+12
arch/arm/kernel/smp_tlb.c
+12
arch/arm/kernel/smp_tlb.c
···
64
64
local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
65
65
}
66
66
67
+
static inline void ipi_flush_bp_all(void *ignored)
68
+
{
69
+
local_flush_bp_all();
70
+
}
71
+
67
72
void flush_tlb_all(void)
68
73
{
69
74
if (tlb_ops_need_broadcast())
···
132
127
local_flush_tlb_kernel_range(start, end);
133
128
}
134
129
130
+
void flush_bp_all(void)
131
+
{
132
+
if (tlb_ops_need_broadcast())
133
+
on_each_cpu(ipi_flush_bp_all, NULL, 1);
134
+
else
135
+
local_flush_bp_all();
136
+
}
+4
arch/arm/kernel/smp_twd.c
+4
arch/arm/kernel/smp_twd.c
···
22
22
#include <linux/of_irq.h>
23
23
#include <linux/of_address.h>
24
24
25
+
#include <asm/smp_plat.h>
25
26
#include <asm/smp_twd.h>
26
27
#include <asm/localtimer.h>
27
28
···
373
372
{
374
373
struct device_node *np;
375
374
int err;
375
+
376
+
if (!is_smp() || !setup_max_cpus)
377
+
return;
376
378
377
379
np = of_find_matching_node(NULL, twd_of_match);
378
380
if (!np)
+1
arch/arm/kernel/suspend.c
+1
arch/arm/kernel/suspend.c
+44
-41
arch/arm/lib/memset.S
+44
-41
arch/arm/lib/memset.S
···
19
19
1: subs r2, r2, #4 @ 1 do we have enough
20
20
blt 5f @ 1 bytes to align with?
21
21
cmp r3, #2 @ 1
22
-
strltb r1, [r0], #1 @ 1
23
-
strleb r1, [r0], #1 @ 1
24
-
strb r1, [r0], #1 @ 1
22
+
strltb r1, [ip], #1 @ 1
23
+
strleb r1, [ip], #1 @ 1
24
+
strb r1, [ip], #1 @ 1
25
25
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
26
26
/*
27
27
* The pointer is now aligned and the length is adjusted. Try doing the
···
29
29
*/
30
30
31
31
ENTRY(memset)
32
-
ands r3, r0, #3 @ 1 unaligned?
32
+
/*
33
+
* Preserve the contents of r0 for the return value.
34
+
*/
35
+
mov ip, r0
36
+
ands r3, ip, #3 @ 1 unaligned?
33
37
bne 1b @ 1
34
38
/*
35
-
* we know that the pointer in r0 is aligned to a word boundary.
39
+
* we know that the pointer in ip is aligned to a word boundary.
36
40
*/
37
41
orr r1, r1, r1, lsl #8
38
42
orr r1, r1, r1, lsl #16
···
47
43
#if ! CALGN(1)+0
48
44
49
45
/*
50
-
* We need an extra register for this loop - save the return address and
51
-
* use the LR
46
+
* We need 2 extra registers for this loop - use r8 and the LR
52
47
*/
53
-
str lr, [sp, #-4]!
54
-
mov ip, r1
48
+
stmfd sp!, {r8, lr}
49
+
mov r8, r1
55
50
mov lr, r1
56
51
57
52
2: subs r2, r2, #64
58
-
stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
59
-
stmgeia r0!, {r1, r3, ip, lr}
60
-
stmgeia r0!, {r1, r3, ip, lr}
61
-
stmgeia r0!, {r1, r3, ip, lr}
53
+
stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
54
+
stmgeia ip!, {r1, r3, r8, lr}
55
+
stmgeia ip!, {r1, r3, r8, lr}
56
+
stmgeia ip!, {r1, r3, r8, lr}
62
57
bgt 2b
63
-
ldmeqfd sp!, {pc} @ Now <64 bytes to go.
58
+
ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
64
59
/*
65
60
* No need to correct the count; we're only testing bits from now on
66
61
*/
67
62
tst r2, #32
68
-
stmneia r0!, {r1, r3, ip, lr}
69
-
stmneia r0!, {r1, r3, ip, lr}
63
+
stmneia ip!, {r1, r3, r8, lr}
64
+
stmneia ip!, {r1, r3, r8, lr}
70
65
tst r2, #16
71
-
stmneia r0!, {r1, r3, ip, lr}
72
-
ldr lr, [sp], #4
66
+
stmneia ip!, {r1, r3, r8, lr}
67
+
ldmfd sp!, {r8, lr}
73
68
74
69
#else
75
70
···
77
74
* whole cache lines at once.
78
75
*/
79
76
80
-
stmfd sp!, {r4-r7, lr}
77
+
stmfd sp!, {r4-r8, lr}
81
78
mov r4, r1
82
79
mov r5, r1
83
80
mov r6, r1
84
81
mov r7, r1
85
-
mov ip, r1
82
+
mov r8, r1
86
83
mov lr, r1
87
84
88
85
cmp r2, #96
89
-
tstgt r0, #31
86
+
tstgt ip, #31
90
87
ble 3f
91
88
92
-
and ip, r0, #31
93
-
rsb ip, ip, #32
94
-
sub r2, r2, ip
95
-
movs ip, ip, lsl #(32 - 4)
96
-
stmcsia r0!, {r4, r5, r6, r7}
97
-
stmmiia r0!, {r4, r5}
98
-
tst ip, #(1 << 30)
99
-
mov ip, r1
100
-
strne r1, [r0], #4
89
+
and r8, ip, #31
90
+
rsb r8, r8, #32
91
+
sub r2, r2, r8
92
+
movs r8, r8, lsl #(32 - 4)
93
+
stmcsia ip!, {r4, r5, r6, r7}
94
+
stmmiia ip!, {r4, r5}
95
+
tst r8, #(1 << 30)
96
+
mov r8, r1
97
+
strne r1, [ip], #4
101
98
102
99
3: subs r2, r2, #64
103
-
stmgeia r0!, {r1, r3-r7, ip, lr}
104
-
stmgeia r0!, {r1, r3-r7, ip, lr}
100
+
stmgeia ip!, {r1, r3-r8, lr}
101
+
stmgeia ip!, {r1, r3-r8, lr}
105
102
bgt 3b
106
-
ldmeqfd sp!, {r4-r7, pc}
103
+
ldmeqfd sp!, {r4-r8, pc}
107
104
108
105
tst r2, #32
109
-
stmneia r0!, {r1, r3-r7, ip, lr}
106
+
stmneia ip!, {r1, r3-r8, lr}
110
107
tst r2, #16
111
-
stmneia r0!, {r4-r7}
112
-
ldmfd sp!, {r4-r7, lr}
108
+
stmneia ip!, {r4-r7}
109
+
ldmfd sp!, {r4-r8, lr}
113
110
114
111
#endif
115
112
116
113
4: tst r2, #8
117
-
stmneia r0!, {r1, r3}
114
+
stmneia ip!, {r1, r3}
118
115
tst r2, #4
119
-
strne r1, [r0], #4
116
+
strne r1, [ip], #4
120
117
/*
121
118
* When we get here, we've got less than 4 bytes to zero. We
122
119
* may have an unaligned pointer as well.
123
120
*/
124
121
5: tst r2, #2
125
-
strneb r1, [r0], #1
126
-
strneb r1, [r0], #1
122
+
strneb r1, [ip], #1
123
+
strneb r1, [ip], #1
127
124
tst r2, #1
128
-
strneb r1, [r0], #1
125
+
strneb r1, [ip], #1
129
126
mov pc, lr
130
127
ENDPROC(memset)
+1
-1
arch/arm/mach-netx/generic.c
+1
-1
arch/arm/mach-netx/generic.c
+32
-32
arch/arm/mach-netx/include/mach/irqs.h
+32
-32
arch/arm/mach-netx/include/mach/irqs.h
···
17
17
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
18
*/
19
19
20
-
#define NETX_IRQ_VIC_START 0
21
-
#define NETX_IRQ_SOFTINT 0
22
-
#define NETX_IRQ_TIMER0 1
23
-
#define NETX_IRQ_TIMER1 2
24
-
#define NETX_IRQ_TIMER2 3
25
-
#define NETX_IRQ_SYSTIME_NS 4
26
-
#define NETX_IRQ_SYSTIME_S 5
27
-
#define NETX_IRQ_GPIO_15 6
28
-
#define NETX_IRQ_WATCHDOG 7
29
-
#define NETX_IRQ_UART0 8
30
-
#define NETX_IRQ_UART1 9
31
-
#define NETX_IRQ_UART2 10
32
-
#define NETX_IRQ_USB 11
33
-
#define NETX_IRQ_SPI 12
34
-
#define NETX_IRQ_I2C 13
35
-
#define NETX_IRQ_LCD 14
36
-
#define NETX_IRQ_HIF 15
37
-
#define NETX_IRQ_GPIO_0_14 16
38
-
#define NETX_IRQ_XPEC0 17
39
-
#define NETX_IRQ_XPEC1 18
40
-
#define NETX_IRQ_XPEC2 19
41
-
#define NETX_IRQ_XPEC3 20
42
-
#define NETX_IRQ_XPEC(no) (17 + (no))
43
-
#define NETX_IRQ_MSYNC0 21
44
-
#define NETX_IRQ_MSYNC1 22
45
-
#define NETX_IRQ_MSYNC2 23
46
-
#define NETX_IRQ_MSYNC3 24
47
-
#define NETX_IRQ_IRQ_PHY 25
48
-
#define NETX_IRQ_ISO_AREA 26
20
+
#define NETX_IRQ_VIC_START 64
21
+
#define NETX_IRQ_SOFTINT (NETX_IRQ_VIC_START + 0)
22
+
#define NETX_IRQ_TIMER0 (NETX_IRQ_VIC_START + 1)
23
+
#define NETX_IRQ_TIMER1 (NETX_IRQ_VIC_START + 2)
24
+
#define NETX_IRQ_TIMER2 (NETX_IRQ_VIC_START + 3)
25
+
#define NETX_IRQ_SYSTIME_NS (NETX_IRQ_VIC_START + 4)
26
+
#define NETX_IRQ_SYSTIME_S (NETX_IRQ_VIC_START + 5)
27
+
#define NETX_IRQ_GPIO_15 (NETX_IRQ_VIC_START + 6)
28
+
#define NETX_IRQ_WATCHDOG (NETX_IRQ_VIC_START + 7)
29
+
#define NETX_IRQ_UART0 (NETX_IRQ_VIC_START + 8)
30
+
#define NETX_IRQ_UART1 (NETX_IRQ_VIC_START + 9)
31
+
#define NETX_IRQ_UART2 (NETX_IRQ_VIC_START + 10)
32
+
#define NETX_IRQ_USB (NETX_IRQ_VIC_START + 11)
33
+
#define NETX_IRQ_SPI (NETX_IRQ_VIC_START + 12)
34
+
#define NETX_IRQ_I2C (NETX_IRQ_VIC_START + 13)
35
+
#define NETX_IRQ_LCD (NETX_IRQ_VIC_START + 14)
36
+
#define NETX_IRQ_HIF (NETX_IRQ_VIC_START + 15)
37
+
#define NETX_IRQ_GPIO_0_14 (NETX_IRQ_VIC_START + 16)
38
+
#define NETX_IRQ_XPEC0 (NETX_IRQ_VIC_START + 17)
39
+
#define NETX_IRQ_XPEC1 (NETX_IRQ_VIC_START + 18)
40
+
#define NETX_IRQ_XPEC2 (NETX_IRQ_VIC_START + 19)
41
+
#define NETX_IRQ_XPEC3 (NETX_IRQ_VIC_START + 20)
42
+
#define NETX_IRQ_XPEC(no) (NETX_IRQ_VIC_START + 17 + (no))
43
+
#define NETX_IRQ_MSYNC0 (NETX_IRQ_VIC_START + 21)
44
+
#define NETX_IRQ_MSYNC1 (NETX_IRQ_VIC_START + 22)
45
+
#define NETX_IRQ_MSYNC2 (NETX_IRQ_VIC_START + 23)
46
+
#define NETX_IRQ_MSYNC3 (NETX_IRQ_VIC_START + 24)
47
+
#define NETX_IRQ_IRQ_PHY (NETX_IRQ_VIC_START + 25)
48
+
#define NETX_IRQ_ISO_AREA (NETX_IRQ_VIC_START + 26)
49
49
/* int 27 is reserved */
50
50
/* int 28 is reserved */
51
-
#define NETX_IRQ_TIMER3 29
52
-
#define NETX_IRQ_TIMER4 30
51
+
#define NETX_IRQ_TIMER3 (NETX_IRQ_VIC_START + 29)
52
+
#define NETX_IRQ_TIMER4 (NETX_IRQ_VIC_START + 30)
53
53
/* int 31 is reserved */
54
54
55
-
#define NETX_IRQS 32
55
+
#define NETX_IRQS (NETX_IRQ_VIC_START + 32)
56
56
57
57
/* for multiplexed irqs on gpio 0..14 */
58
58
#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
+18
-11
arch/arm/mm/context.c
+18
-11
arch/arm/mm/context.c
···
152
152
return 0;
153
153
}
154
154
155
-
static void new_context(struct mm_struct *mm, unsigned int cpu)
155
+
static u64 new_context(struct mm_struct *mm, unsigned int cpu)
156
156
{
157
-
u64 asid = mm->context.id;
157
+
u64 asid = atomic64_read(&mm->context.id);
158
158
u64 generation = atomic64_read(&asid_generation);
159
159
160
160
if (asid != 0 && is_reserved_asid(asid)) {
···
181
181
cpumask_clear(mm_cpumask(mm));
182
182
}
183
183
184
-
mm->context.id = asid;
184
+
return asid;
185
185
}
186
186
187
187
void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
188
188
{
189
189
unsigned long flags;
190
190
unsigned int cpu = smp_processor_id();
191
+
u64 asid;
191
192
192
193
if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
193
194
__check_vmalloc_seq(mm);
···
199
198
*/
200
199
cpu_set_reserved_ttbr0();
201
200
202
-
if (!((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
203
-
&& atomic64_xchg(&per_cpu(active_asids, cpu), mm->context.id))
201
+
asid = atomic64_read(&mm->context.id);
202
+
if (!((asid ^ atomic64_read(&asid_generation)) >> ASID_BITS)
203
+
&& atomic64_xchg(&per_cpu(active_asids, cpu), asid))
204
204
goto switch_mm_fastpath;
205
205
206
206
raw_spin_lock_irqsave(&cpu_asid_lock, flags);
207
207
/* Check that our ASID belongs to the current generation. */
208
-
if ((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
209
-
new_context(mm, cpu);
208
+
asid = atomic64_read(&mm->context.id);
209
+
if ((asid ^ atomic64_read(&asid_generation)) >> ASID_BITS) {
210
+
asid = new_context(mm, cpu);
211
+
atomic64_set(&mm->context.id, asid);
212
+
}
210
213
211
-
atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
212
-
cpumask_set_cpu(cpu, mm_cpumask(mm));
213
-
214
-
if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
214
+
if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
215
+
local_flush_bp_all();
215
216
local_flush_tlb_all();
217
+
}
218
+
219
+
atomic64_set(&per_cpu(active_asids, cpu), asid);
220
+
cpumask_set_cpu(cpu, mm_cpumask(mm));
216
221
raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
217
222
218
223
switch_mm_fastpath:
+1
arch/arm/mm/idmap.c
+1
arch/arm/mm/idmap.c