tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"Here's the weekly batch of fixes from arm-soc.

The delta is a largeish negative delta, due to revert of SMP support
for Broadcom's STB SoC -- it was accidentally merged before some
issues had been addressed, so they will make a new attempt for 3.18.
I didn't see a need for a full revert of the whole platform due to
this, we're keeping the rest enabled.

The rest is mostly:

- a handful of DT fixes for i.MX (Hummingboard/Cubox-i in particular)
- some MTD/NAND fixes for OMAP
- minor DT fixes for shmobile
- warning fix for UP builds on vexpress/spc

There's also a couple of patches that wires up hwmod on TI's DRA7 SoC
so it can boot. Drivers and the rest had landed for 3.17, and it's
small and isolated so it made sense to pick up now even if it's not a
bugfix"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
vexpress/spc: fix a build warning on array bounds
ARM: DRA7: hwmod: Add dra74x and dra72x specific ocp interface lists
ARM: DRA7: Add support for soc_is_dra74x() and soc_is_dra72x() variants
MAINTAINERS: catch special Rockchip code locations
ARM: dts: microsom-ar8035: MDIO pad must be set open drain
ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
ARM: brcmstb: revert SMP support
ARM: OMAP2+: hwmod: Rearm wake-up interrupts for DT when MUSB is idled
ARM: dts: Enable UART wake-up events for beagleboard
ARM: dts: Remove twl6030 clk32g "regulator"
ARM: OMAP2+: omap_device: remove warning that clk alias already exists
ARM: OMAP: fix %d confusingly prefixed with 0x in format string
ARM: dts: DRA7: fix interrupt-cells for GPIO
mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc()
ARM: dts: omap3430-sdp: Revert to using software ECC for NAND
ARM: OMAP2+: GPMC: Support Software ECC scheme via DT
mtd: nand: omap: Revert to using software ECC by default
ARM: dts: hummingboard/cubox-i: change SPDIF output to be more descriptive
ARM: dts: hummingboard/cubox-i: add USB OC pinctrl configuration
ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
...

Linus Torvalds 19ed3eb9 81bbadc6

+133 -464
+1 -1
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
··· 22 22 width of 8 is assumed. 23 23 24 24 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: 25 - "sw" <deprecated> use "ham1" instead 25 + "sw" 1-bit Hamming ecc code via software 26 26 "hw" <deprecated> use "ham1" instead 27 27 "hw-romcode" <deprecated> use "ham1" instead 28 28 "ham1" 1-bit Hamming ecc code
+5
MAINTAINERS
··· 1279 1279 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1280 1280 L: linux-rockchip@lists.infradead.org 1281 1281 S: Maintained 1282 + F: arch/arm/boot/dts/rk3* 1282 1283 F: arch/arm/mach-rockchip/ 1284 + F: drivers/clk/rockchip/ 1285 + F: drivers/i2c/busses/i2c-rk3x.c 1283 1286 F: drivers/*/*rockchip* 1287 + F: drivers/*/*/*rockchip* 1288 + F: sound/soc/rockchip/ 1284 1289 1285 1290 ARM/SAMSUNG ARM ARCHITECTURES 1286 1291 M: Ben Dooks <ben-linux@fluff.org>
+8 -8
arch/arm/boot/dts/dra7.dtsi
··· 245 245 gpio-controller; 246 246 #gpio-cells = <2>; 247 247 interrupt-controller; 248 - #interrupt-cells = <1>; 248 + #interrupt-cells = <2>; 249 249 }; 250 250 251 251 gpio2: gpio@48055000 { ··· 256 256 gpio-controller; 257 257 #gpio-cells = <2>; 258 258 interrupt-controller; 259 - #interrupt-cells = <1>; 259 + #interrupt-cells = <2>; 260 260 }; 261 261 262 262 gpio3: gpio@48057000 { ··· 267 267 gpio-controller; 268 268 #gpio-cells = <2>; 269 269 interrupt-controller; 270 - #interrupt-cells = <1>; 270 + #interrupt-cells = <2>; 271 271 }; 272 272 273 273 gpio4: gpio@48059000 { ··· 278 278 gpio-controller; 279 279 #gpio-cells = <2>; 280 280 interrupt-controller; 281 - #interrupt-cells = <1>; 281 + #interrupt-cells = <2>; 282 282 }; 283 283 284 284 gpio5: gpio@4805b000 { ··· 289 289 gpio-controller; 290 290 #gpio-cells = <2>; 291 291 interrupt-controller; 292 - #interrupt-cells = <1>; 292 + #interrupt-cells = <2>; 293 293 }; 294 294 295 295 gpio6: gpio@4805d000 { ··· 300 300 gpio-controller; 301 301 #gpio-cells = <2>; 302 302 interrupt-controller; 303 - #interrupt-cells = <1>; 303 + #interrupt-cells = <2>; 304 304 }; 305 305 306 306 gpio7: gpio@48051000 { ··· 311 311 gpio-controller; 312 312 #gpio-cells = <2>; 313 313 interrupt-controller; 314 - #interrupt-cells = <1>; 314 + #interrupt-cells = <2>; 315 315 }; 316 316 317 317 gpio8: gpio@48053000 { ··· 322 322 gpio-controller; 323 323 #gpio-cells = <2>; 324 324 interrupt-controller; 325 - #interrupt-cells = <1>; 325 + #interrupt-cells = <2>; 326 326 }; 327 327 328 328 uart1: serial@4806a000 {
+8
arch/arm/boot/dts/imx53-qsrb.dts
··· 28 28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 29 29 >; 30 30 }; 31 + 32 + pinctrl_pmic: pmicgrp { 33 + fsl,pins = < 34 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */ 35 + >; 36 + }; 31 37 }; 32 38 }; 33 39 ··· 44 38 45 39 pmic: mc34708@8 { 46 40 compatible = "fsl,mc34708"; 41 + pinctrl-names = "default"; 42 + pinctrl-0 = <&pinctrl_pmic>; 47 43 reg = <0x08>; 48 44 interrupt-parent = <&gpio5>; 49 45 interrupts = <23 0x8>;
+3 -1
arch/arm/boot/dts/imx6dl-hummingboard.dts
··· 58 58 59 59 sound-spdif { 60 60 compatible = "fsl,imx-audio-spdif"; 61 - model = "imx-spdif"; 61 + model = "On-board SPDIF"; 62 62 /* IMX6 doesn't implement this yet */ 63 63 spdif-controller = <&spdif>; 64 64 spdif-out; ··· 181 181 }; 182 182 183 183 &usbh1 { 184 + disable-over-current; 184 185 vbus-supply = <&reg_usbh1_vbus>; 185 186 status = "okay"; 186 187 }; 187 188 188 189 &usbotg { 190 + disable-over-current; 189 191 pinctrl-names = "default"; 190 192 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; 191 193 vbus-supply = <&reg_usbotg_vbus>;
+14 -5
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
··· 61 61 62 62 sound-spdif { 63 63 compatible = "fsl,imx-audio-spdif"; 64 - model = "imx-spdif"; 64 + model = "Integrated SPDIF"; 65 65 /* IMX6 doesn't implement this yet */ 66 66 spdif-controller = <&spdif>; 67 67 spdif-out; ··· 130 130 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 131 131 }; 132 132 133 + pinctrl_cubox_i_usbh1: cubox-i-usbh1 { 134 + fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>; 135 + }; 136 + 133 137 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { 134 138 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>; 135 139 }; 136 140 137 - pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id { 141 + pinctrl_cubox_i_usbotg: cubox-i-usbotg { 138 142 /* 139 - * The Cubox-i pulls this low, but as it's pointless 143 + * The Cubox-i pulls ID low, but as it's pointless 140 144 * leaving it as a pull-up, even if it is just 10uA. 141 145 */ 142 - fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; 146 + fsl,pins = < 147 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 148 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 149 + >; 143 150 }; 144 151 145 152 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { ··· 180 173 }; 181 174 182 175 &usbh1 { 176 + pinctrl-names = "default"; 177 + pinctrl-0 = <&pinctrl_cubox_i_usbh1>; 183 178 vbus-supply = <&reg_usbh1_vbus>; 184 179 status = "okay"; 185 180 }; 186 181 187 182 &usbotg { 188 183 pinctrl-names = "default"; 189 - pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>; 184 + pinctrl-0 = <&pinctrl_cubox_i_usbotg>; 190 185 vbus-supply = <&reg_usbotg_vbus>; 191 186 status = "okay"; 192 187 };
+1 -1
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
··· 17 17 enet { 18 18 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { 19 19 fsl,pins = < 20 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 20 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 21 21 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 22 22 /* AR8035 reset */ 23 23 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
+1
arch/arm/boot/dts/omap3-beagle.dts
··· 292 292 &uart3 { 293 293 pinctrl-names = "default"; 294 294 pinctrl-0 = <&uart3_pins>; 295 + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 295 296 }; 296 297 297 298 &gpio1 {
+1 -1
arch/arm/boot/dts/omap3430-sdp.dts
··· 107 107 #address-cells = <1>; 108 108 #size-cells = <1>; 109 109 reg = <1 0 0x08000000>; 110 - ti,nand-ecc-opt = "ham1"; 110 + ti,nand-ecc-opt = "sw"; 111 111 nand-bus-width = <8>; 112 112 gpmc,cs-on-ns = <0>; 113 113 gpmc,cs-rd-off-ns = <36>;
+10 -6
arch/arm/boot/dts/omap54xx-clocks.dtsi
··· 367 367 368 368 l3_iclk_div: l3_iclk_div { 369 369 #clock-cells = <0>; 370 - compatible = "fixed-factor-clock"; 370 + compatible = "ti,divider-clock"; 371 + ti,max-div = <2>; 372 + ti,bit-shift = <4>; 373 + reg = <0x100>; 371 374 clocks = <&dpll_core_h12x2_ck>; 372 - clock-mult = <1>; 373 - clock-div = <1>; 375 + ti,index-power-of-two; 374 376 }; 375 377 376 378 gpu_l3_iclk: gpu_l3_iclk { ··· 385 383 386 384 l4_root_clk_div: l4_root_clk_div { 387 385 #clock-cells = <0>; 388 - compatible = "fixed-factor-clock"; 386 + compatible = "ti,divider-clock"; 387 + ti,max-div = <2>; 388 + ti,bit-shift = <8>; 389 + reg = <0x100>; 389 390 clocks = <&l3_iclk_div>; 390 - clock-mult = <1>; 391 - clock-div = <1>; 391 + ti,index-power-of-two; 392 392 }; 393 393 394 394 slimbus1_slimbus_clk: slimbus1_slimbus_clk {
-4
arch/arm/boot/dts/twl6030.dtsi
··· 83 83 regulator-always-on; 84 84 }; 85 85 86 - clk32kg: regulator-clk32kg { 87 - compatible = "ti,twl6030-clk32kg"; 88 - }; 89 - 90 86 twl_usb_comparator: usb-comparator { 91 87 compatible = "ti,twl6030-usb"; 92 88 interrupts = <4>, <10>;
-1
arch/arm/mach-bcm/Makefile
··· 36 36 37 37 ifeq ($(CONFIG_ARCH_BRCMSTB),y) 38 38 obj-y += brcmstb.o 39 - obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o 40 39 endif
-19
arch/arm/mach-bcm/brcmstb.h
··· 1 - /* 2 - * Copyright (C) 2013-2014 Broadcom Corporation 3 - * 4 - * This program is free software; you can redistribute it and/or 5 - * modify it under the terms of the GNU General Public License as 6 - * published by the Free Software Foundation version 2. 7 - * 8 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 - * kind, whether express or implied; without even the implied warranty 10 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 - * GNU General Public License for more details. 12 - */ 13 - 14 - #ifndef __BRCMSTB_H__ 15 - #define __BRCMSTB_H__ 16 - 17 - void brcmstb_secondary_startup(void); 18 - 19 - #endif /* __BRCMSTB_H__ */
-33
arch/arm/mach-bcm/headsmp-brcmstb.S
··· 1 - /* 2 - * SMP boot code for secondary CPUs 3 - * Based on arch/arm/mach-tegra/headsmp.S 4 - * 5 - * Copyright (C) 2010 NVIDIA, Inc. 6 - * Copyright (C) 2013-2014 Broadcom Corporation 7 - * 8 - * This program is free software; you can redistribute it and/or 9 - * modify it under the terms of the GNU General Public License as 10 - * published by the Free Software Foundation version 2. 11 - * 12 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 - * kind, whether express or implied; without even the implied warranty 14 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - */ 17 - 18 - #include <asm/assembler.h> 19 - #include <linux/linkage.h> 20 - #include <linux/init.h> 21 - 22 - .section ".text.head", "ax" 23 - 24 - ENTRY(brcmstb_secondary_startup) 25 - /* 26 - * Ensure CPU is in a sane state by disabling all IRQs and switching 27 - * into SVC mode. 28 - */ 29 - setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0 30 - 31 - bl v7_invalidate_l1 32 - b secondary_startup 33 - ENDPROC(brcmstb_secondary_startup)
-363
arch/arm/mach-bcm/platsmp-brcmstb.c
··· 1 - /* 2 - * Broadcom STB CPU SMP and hotplug support for ARM 3 - * 4 - * Copyright (C) 2013-2014 Broadcom Corporation 5 - * 6 - * This program is free software; you can redistribute it and/or 7 - * modify it under the terms of the GNU General Public License as 8 - * published by the Free Software Foundation version 2. 9 - * 10 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 - * kind, whether express or implied; without even the implied warranty 12 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 - * GNU General Public License for more details. 14 - */ 15 - 16 - #include <linux/delay.h> 17 - #include <linux/errno.h> 18 - #include <linux/init.h> 19 - #include <linux/io.h> 20 - #include <linux/of_address.h> 21 - #include <linux/of_platform.h> 22 - #include <linux/printk.h> 23 - #include <linux/regmap.h> 24 - #include <linux/smp.h> 25 - #include <linux/mfd/syscon.h> 26 - #include <linux/spinlock.h> 27 - 28 - #include <asm/cacheflush.h> 29 - #include <asm/cp15.h> 30 - #include <asm/mach-types.h> 31 - #include <asm/smp_plat.h> 32 - 33 - #include "brcmstb.h" 34 - 35 - enum { 36 - ZONE_MAN_CLKEN_MASK = BIT(0), 37 - ZONE_MAN_RESET_CNTL_MASK = BIT(1), 38 - ZONE_MAN_MEM_PWR_MASK = BIT(4), 39 - ZONE_RESERVED_1_MASK = BIT(5), 40 - ZONE_MAN_ISO_CNTL_MASK = BIT(6), 41 - ZONE_MANUAL_CONTROL_MASK = BIT(7), 42 - ZONE_PWR_DN_REQ_MASK = BIT(9), 43 - ZONE_PWR_UP_REQ_MASK = BIT(10), 44 - ZONE_BLK_RST_ASSERT_MASK = BIT(12), 45 - ZONE_PWR_OFF_STATE_MASK = BIT(25), 46 - ZONE_PWR_ON_STATE_MASK = BIT(26), 47 - ZONE_DPG_PWR_STATE_MASK = BIT(28), 48 - ZONE_MEM_PWR_STATE_MASK = BIT(29), 49 - ZONE_RESET_STATE_MASK = BIT(31), 50 - CPU0_PWR_ZONE_CTRL_REG = 1, 51 - CPU_RESET_CONFIG_REG = 2, 52 - }; 53 - 54 - static void __iomem *cpubiuctrl_block; 55 - static void __iomem *hif_cont_block; 56 - static u32 cpu0_pwr_zone_ctrl_reg; 57 - static u32 cpu_rst_cfg_reg; 58 - static u32 hif_cont_reg; 59 - 60 - #ifdef CONFIG_HOTPLUG_CPU 61 - static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state); 62 - 63 - static int per_cpu_sw_state_rd(u32 cpu) 64 - { 65 - sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu))); 66 - return per_cpu(per_cpu_sw_state, cpu); 67 - } 68 - 69 - static void per_cpu_sw_state_wr(u32 cpu, int val) 70 - { 71 - per_cpu(per_cpu_sw_state, cpu) = val; 72 - dmb(); 73 - sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu))); 74 - dsb_sev(); 75 - } 76 - #else 77 - static inline void per_cpu_sw_state_wr(u32 cpu, int val) { } 78 - #endif 79 - 80 - static void __iomem *pwr_ctrl_get_base(u32 cpu) 81 - { 82 - void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg; 83 - base += (cpu_logical_map(cpu) * 4); 84 - return base; 85 - } 86 - 87 - static u32 pwr_ctrl_rd(u32 cpu) 88 - { 89 - void __iomem *base = pwr_ctrl_get_base(cpu); 90 - return readl_relaxed(base); 91 - } 92 - 93 - static void pwr_ctrl_wr(u32 cpu, u32 val) 94 - { 95 - void __iomem *base = pwr_ctrl_get_base(cpu); 96 - writel(val, base); 97 - } 98 - 99 - static void cpu_rst_cfg_set(u32 cpu, int set) 100 - { 101 - u32 val; 102 - val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg); 103 - if (set) 104 - val |= BIT(cpu_logical_map(cpu)); 105 - else 106 - val &= ~BIT(cpu_logical_map(cpu)); 107 - writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg); 108 - } 109 - 110 - static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr) 111 - { 112 - const int reg_ofs = cpu_logical_map(cpu) * 8; 113 - writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs); 114 - writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs); 115 - } 116 - 117 - static void brcmstb_cpu_boot(u32 cpu) 118 - { 119 - pr_info("SMP: Booting CPU%d...\n", cpu); 120 - 121 - /* 122 - * set the reset vector to point to the secondary_startup 123 - * routine 124 - */ 125 - cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup)); 126 - 127 - /* unhalt the cpu */ 128 - cpu_rst_cfg_set(cpu, 0); 129 - } 130 - 131 - static void brcmstb_cpu_power_on(u32 cpu) 132 - { 133 - /* 134 - * The secondary cores power was cut, so we must go through 135 - * power-on initialization. 136 - */ 137 - u32 tmp; 138 - 139 - pr_info("SMP: Powering up CPU%d...\n", cpu); 140 - 141 - /* Request zone power up */ 142 - pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK); 143 - 144 - /* Wait for the power up FSM to complete */ 145 - do { 146 - tmp = pwr_ctrl_rd(cpu); 147 - } while (!(tmp & ZONE_PWR_ON_STATE_MASK)); 148 - 149 - per_cpu_sw_state_wr(cpu, 1); 150 - } 151 - 152 - static int brcmstb_cpu_get_power_state(u32 cpu) 153 - { 154 - int tmp = pwr_ctrl_rd(cpu); 155 - return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1; 156 - } 157 - 158 - #ifdef CONFIG_HOTPLUG_CPU 159 - 160 - static void brcmstb_cpu_die(u32 cpu) 161 - { 162 - v7_exit_coherency_flush(all); 163 - 164 - /* Prevent all interrupts from reaching this CPU. */ 165 - arch_local_irq_disable(); 166 - 167 - /* 168 - * Final full barrier to ensure everything before this instruction has 169 - * quiesced. 170 - */ 171 - isb(); 172 - dsb(); 173 - 174 - per_cpu_sw_state_wr(cpu, 0); 175 - 176 - /* Sit and wait to die */ 177 - wfi(); 178 - 179 - /* We should never get here... */ 180 - panic("Spurious interrupt on CPU %d received!\n", cpu); 181 - } 182 - 183 - static int brcmstb_cpu_kill(u32 cpu) 184 - { 185 - u32 tmp; 186 - 187 - pr_info("SMP: Powering down CPU%d...\n", cpu); 188 - 189 - while (per_cpu_sw_state_rd(cpu)) 190 - ; 191 - 192 - /* Program zone reset */ 193 - pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK | 194 - ZONE_PWR_DN_REQ_MASK); 195 - 196 - /* Verify zone reset */ 197 - tmp = pwr_ctrl_rd(cpu); 198 - if (!(tmp & ZONE_RESET_STATE_MASK)) 199 - pr_err("%s: Zone reset bit for CPU %d not asserted!\n", 200 - __func__, cpu); 201 - 202 - /* Wait for power down */ 203 - do { 204 - tmp = pwr_ctrl_rd(cpu); 205 - } while (!(tmp & ZONE_PWR_OFF_STATE_MASK)); 206 - 207 - /* Settle-time from Broadcom-internal DVT reference code */ 208 - udelay(7); 209 - 210 - /* Assert reset on the CPU */ 211 - cpu_rst_cfg_set(cpu, 1); 212 - 213 - return 1; 214 - } 215 - 216 - #endif /* CONFIG_HOTPLUG_CPU */ 217 - 218 - static int __init setup_hifcpubiuctrl_regs(struct device_node *np) 219 - { 220 - int rc = 0; 221 - char *name; 222 - struct device_node *syscon_np = NULL; 223 - 224 - name = "syscon-cpu"; 225 - 226 - syscon_np = of_parse_phandle(np, name, 0); 227 - if (!syscon_np) { 228 - pr_err("can't find phandle %s\n", name); 229 - rc = -EINVAL; 230 - goto cleanup; 231 - } 232 - 233 - cpubiuctrl_block = of_iomap(syscon_np, 0); 234 - if (!cpubiuctrl_block) { 235 - pr_err("iomap failed for cpubiuctrl_block\n"); 236 - rc = -EINVAL; 237 - goto cleanup; 238 - } 239 - 240 - rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG, 241 - &cpu0_pwr_zone_ctrl_reg); 242 - if (rc) { 243 - pr_err("failed to read 1st entry from %s property (%d)\n", name, 244 - rc); 245 - rc = -EINVAL; 246 - goto cleanup; 247 - } 248 - 249 - rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG, 250 - &cpu_rst_cfg_reg); 251 - if (rc) { 252 - pr_err("failed to read 2nd entry from %s property (%d)\n", name, 253 - rc); 254 - rc = -EINVAL; 255 - goto cleanup; 256 - } 257 - 258 - cleanup: 259 - if (syscon_np) 260 - of_node_put(syscon_np); 261 - 262 - return rc; 263 - } 264 - 265 - static int __init setup_hifcont_regs(struct device_node *np) 266 - { 267 - int rc = 0; 268 - char *name; 269 - struct device_node *syscon_np = NULL; 270 - 271 - name = "syscon-cont"; 272 - 273 - syscon_np = of_parse_phandle(np, name, 0); 274 - if (!syscon_np) { 275 - pr_err("can't find phandle %s\n", name); 276 - rc = -EINVAL; 277 - goto cleanup; 278 - } 279 - 280 - hif_cont_block = of_iomap(syscon_np, 0); 281 - if (!hif_cont_block) { 282 - pr_err("iomap failed for hif_cont_block\n"); 283 - rc = -EINVAL; 284 - goto cleanup; 285 - } 286 - 287 - /* offset is at top of hif_cont_block */ 288 - hif_cont_reg = 0; 289 - 290 - cleanup: 291 - if (syscon_np) 292 - of_node_put(syscon_np); 293 - 294 - return rc; 295 - } 296 - 297 - static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus) 298 - { 299 - int rc; 300 - struct device_node *np; 301 - char *name; 302 - 303 - name = "brcm,brcmstb-smpboot"; 304 - np = of_find_compatible_node(NULL, NULL, name); 305 - if (!np) { 306 - pr_err("can't find compatible node %s\n", name); 307 - return; 308 - } 309 - 310 - rc = setup_hifcpubiuctrl_regs(np); 311 - if (rc) 312 - return; 313 - 314 - rc = setup_hifcont_regs(np); 315 - if (rc) 316 - return; 317 - } 318 - 319 - static DEFINE_SPINLOCK(boot_lock); 320 - 321 - static void brcmstb_secondary_init(unsigned int cpu) 322 - { 323 - /* 324 - * Synchronise with the boot thread. 325 - */ 326 - spin_lock(&boot_lock); 327 - spin_unlock(&boot_lock); 328 - } 329 - 330 - static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle) 331 - { 332 - /* 333 - * set synchronisation state between this boot processor 334 - * and the secondary one 335 - */ 336 - spin_lock(&boot_lock); 337 - 338 - /* Bring up power to the core if necessary */ 339 - if (brcmstb_cpu_get_power_state(cpu) == 0) 340 - brcmstb_cpu_power_on(cpu); 341 - 342 - brcmstb_cpu_boot(cpu); 343 - 344 - /* 345 - * now the secondary core is starting up let it run its 346 - * calibrations, then wait for it to finish 347 - */ 348 - spin_unlock(&boot_lock); 349 - 350 - return 0; 351 - } 352 - 353 - static struct smp_operations brcmstb_smp_ops __initdata = { 354 - .smp_prepare_cpus = brcmstb_cpu_ctrl_setup, 355 - .smp_secondary_init = brcmstb_secondary_init, 356 - .smp_boot_secondary = brcmstb_boot_secondary, 357 - #ifdef CONFIG_HOTPLUG_CPU 358 - .cpu_kill = brcmstb_cpu_kill, 359 - .cpu_die = brcmstb_cpu_die, 360 - #endif 361 - }; 362 - 363 - CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
+1 -1
arch/arm/mach-omap2/board-flash.c
··· 142 142 board_nand_data.nr_parts = nr_parts; 143 143 board_nand_data.devsize = nand_type; 144 144 145 - board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW; 145 + board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW; 146 146 gpmc_nand_init(&board_nand_data, gpmc_t); 147 147 } 148 148 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
+2 -1
arch/arm/mach-omap2/gpmc-nand.c
··· 49 49 return 0; 50 50 51 51 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ 52 - if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) 52 + if (ecc_opt == OMAP_ECC_HAM1_CODE_HW || 53 + ecc_opt == OMAP_ECC_HAM1_CODE_SW) 53 54 return 1; 54 55 else 55 56 return 0;
+5 -2
arch/arm/mach-omap2/gpmc.c
··· 1403 1403 pr_err("%s: ti,nand-ecc-opt not found\n", __func__); 1404 1404 return -ENODEV; 1405 1405 } 1406 - if (!strcmp(s, "ham1") || !strcmp(s, "sw") || 1407 - !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) 1406 + 1407 + if (!strcmp(s, "sw")) 1408 + gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW; 1409 + else if (!strcmp(s, "ham1") || 1410 + !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) 1408 1411 gpmc_nand_data->ecc_opt = 1409 1412 OMAP_ECC_HAM1_CODE_HW; 1410 1413 else if (!strcmp(s, "bch4"))
+1 -1
arch/arm/mach-omap2/id.c
··· 663 663 664 664 default: 665 665 /* Unknown default to latest silicon rev as default*/ 666 - pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", 666 + pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", 667 667 __func__, idcode, hawkeye, rev); 668 668 omap_revision = DRA752_REV_ES1_1; 669 669 }
+1 -1
arch/arm/mach-omap2/omap_device.c
··· 56 56 57 57 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); 58 58 if (!IS_ERR(r)) { 59 - dev_warn(&od->pdev->dev, 59 + dev_dbg(&od->pdev->dev, 60 60 "alias %s already exists\n", clk_alias); 61 61 clk_put(r); 62 62 return;
+7
arch/arm/mach-omap2/omap_hwmod.c
··· 2185 2185 oh->mux->pads_dynamic))) { 2186 2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); 2187 2187 _reconfigure_io_chain(); 2188 + } else if (oh->flags & HWMOD_FORCE_MSTANDBY) { 2189 + _reconfigure_io_chain(); 2188 2190 } 2189 2191 2190 2192 _add_initiator_dep(oh, mpu_oh); ··· 2292 2290 /* Mux pins for device idle if populated */ 2293 2291 if (oh->mux && oh->mux->pads_dynamic) { 2294 2292 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); 2293 + _reconfigure_io_chain(); 2294 + } else if (oh->flags & HWMOD_FORCE_MSTANDBY) { 2295 2295 _reconfigure_io_chain(); 2296 2296 } 2297 2297 ··· 3347 3343 return -EINVAL; 3348 3344 3349 3345 if (!ois) 3346 + return 0; 3347 + 3348 + if (ois[0] == NULL) /* Empty list */ 3350 3349 return 0; 3351 3350 3352 3351 if (!linkspace) {
+20 -2
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
··· 35 35 #include "i2c.h" 36 36 #include "mmc.h" 37 37 #include "wd_timer.h" 38 + #include "soc.h" 38 39 39 40 /* Base offset for all DRA7XX interrupts external to MPUSS */ 40 41 #define DRA7XX_IRQ_GIC_START 32 ··· 3262 3261 &dra7xx_l4_per3__usb_otg_ss1, 3263 3262 &dra7xx_l4_per3__usb_otg_ss2, 3264 3263 &dra7xx_l4_per3__usb_otg_ss3, 3265 - &dra7xx_l4_per3__usb_otg_ss4, 3266 3264 &dra7xx_l3_main_1__vcp1, 3267 3265 &dra7xx_l4_per2__vcp1, 3268 3266 &dra7xx_l3_main_1__vcp2, ··· 3270 3270 NULL, 3271 3271 }; 3272 3272 3273 + static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { 3274 + &dra7xx_l4_per3__usb_otg_ss4, 3275 + NULL, 3276 + }; 3277 + 3278 + static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { 3279 + NULL, 3280 + }; 3281 + 3273 3282 int __init dra7xx_hwmod_init(void) 3274 3283 { 3284 + int ret; 3285 + 3275 3286 omap_hwmod_init(); 3276 - return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); 3287 + ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); 3288 + 3289 + if (!ret && soc_is_dra74x()) 3290 + return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); 3291 + else if (!ret && soc_is_dra72x()) 3292 + return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); 3293 + 3294 + return ret; 3277 3295 }
+6
arch/arm/mach-omap2/soc.h
··· 245 245 #define soc_is_omap54xx() 0 246 246 #define soc_is_omap543x() 0 247 247 #define soc_is_dra7xx() 0 248 + #define soc_is_dra74x() 0 249 + #define soc_is_dra72x() 0 248 250 249 251 #if defined(MULTI_OMAP2) 250 252 # if defined(CONFIG_ARCH_OMAP2) ··· 395 393 396 394 #if defined(CONFIG_SOC_DRA7XX) 397 395 #undef soc_is_dra7xx 396 + #undef soc_is_dra74x 397 + #undef soc_is_dra72x 398 398 #define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) 399 + #define soc_is_dra74x() (of_machine_is_compatible("ti,dra74")) 400 + #define soc_is_dra72x() (of_machine_is_compatible("ti,dra72")) 399 401 #endif 400 402 401 403 /* Various silicon revisions for omap2 */
+2 -2
arch/arm/mach-shmobile/clock-r8a7790.c
··· 183 183 184 184 static struct clk div4_clks[DIV4_NR] = { 185 185 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 186 - [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 187 - [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), 186 + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT), 187 + [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT), 188 188 }; 189 189 190 190 /* DIV6 clocks */
+1 -1
arch/arm/mach-shmobile/clock-r8a7791.c
··· 152 152 153 153 static struct clk div4_clks[DIV4_NR] = { 154 154 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 155 - [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 155 + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT), 156 156 }; 157 157 158 158 /* DIV6 clocks */
+1 -1
arch/arm/mach-shmobile/clock-sh73a0.c
··· 644 644 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ 645 645 CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */ 646 646 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ 647 - CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */ 647 + CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */ 648 648 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 649 649 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */ 650 650 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+11 -3
arch/arm/mach-vexpress/spc.c
··· 426 426 427 427 static int ve_init_opp_table(struct device *cpu_dev) 428 428 { 429 - int cluster = topology_physical_package_id(cpu_dev->id); 430 - int idx, ret = 0, max_opp = info->num_opps[cluster]; 431 - struct ve_spc_opp *opps = info->opps[cluster]; 429 + int cluster; 430 + int idx, ret = 0, max_opp; 431 + struct ve_spc_opp *opps; 432 + 433 + cluster = topology_physical_package_id(cpu_dev->id); 434 + cluster = cluster < 0 ? 0 : cluster; 435 + 436 + max_opp = info->num_opps[cluster]; 437 + opps = info->opps[cluster]; 432 438 433 439 for (idx = 0; idx < max_opp; idx++, opps++) { 434 440 ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); ··· 542 536 543 537 spc->hw.init = &init; 544 538 spc->cluster = topology_physical_package_id(cpu_dev->id); 539 + 540 + spc->cluster = spc->cluster < 0 ? 0 : spc->cluster; 545 541 546 542 init.name = dev_name(cpu_dev); 547 543 init.ops = &clk_spc_ops;
+12 -4
drivers/mtd/nand/omap2.c
··· 931 931 u32 val; 932 932 933 933 val = readl(info->reg.gpmc_ecc_config); 934 - if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) 934 + if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) 935 935 return -EINVAL; 936 936 937 937 /* read ecc result */ ··· 1794 1794 } 1795 1795 1796 1796 /* populate MTD interface based on ECC scheme */ 1797 - nand_chip->ecc.layout = &omap_oobinfo; 1798 1797 ecclayout = &omap_oobinfo; 1799 1798 switch (info->ecc_opt) { 1799 + case OMAP_ECC_HAM1_CODE_SW: 1800 + nand_chip->ecc.mode = NAND_ECC_SOFT; 1801 + break; 1802 + 1800 1803 case OMAP_ECC_HAM1_CODE_HW: 1801 1804 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); 1802 1805 nand_chip->ecc.mode = NAND_ECC_HW; ··· 1851 1848 nand_chip->ecc.priv = nand_bch_init(mtd, 1852 1849 nand_chip->ecc.size, 1853 1850 nand_chip->ecc.bytes, 1854 - &nand_chip->ecc.layout); 1851 + &ecclayout); 1855 1852 if (!nand_chip->ecc.priv) { 1856 1853 pr_err("nand: error: unable to use s/w BCH library\n"); 1857 1854 err = -EINVAL; ··· 1926 1923 nand_chip->ecc.priv = nand_bch_init(mtd, 1927 1924 nand_chip->ecc.size, 1928 1925 nand_chip->ecc.bytes, 1929 - &nand_chip->ecc.layout); 1926 + &ecclayout); 1930 1927 if (!nand_chip->ecc.priv) { 1931 1928 pr_err("nand: error: unable to use s/w BCH library\n"); 1932 1929 err = -EINVAL; ··· 2015 2012 goto return_error; 2016 2013 } 2017 2014 2015 + if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) 2016 + goto scan_tail; 2017 + 2018 2018 /* all OOB bytes from oobfree->offset till end off OOB are free */ 2019 2019 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; 2020 2020 /* check if NAND device's OOB is enough to store ECC signatures */ ··· 2027 2021 err = -EINVAL; 2028 2022 goto return_error; 2029 2023 } 2024 + nand_chip->ecc.layout = ecclayout; 2030 2025 2026 + scan_tail: 2031 2027 /* second phase scan */ 2032 2028 if (nand_scan_tail(mtd)) { 2033 2029 err = -ENXIO;
+11 -2
include/linux/platform_data/mtd-nand-omap2.h
··· 21 21 }; 22 22 23 23 enum omap_ecc { 24 - /* 1-bit ECC calculation by GPMC, Error detection by Software */ 25 - OMAP_ECC_HAM1_CODE_HW = 0, 24 + /* 25 + * 1-bit ECC: calculation and correction by SW 26 + * ECC stored at end of spare area 27 + */ 28 + OMAP_ECC_HAM1_CODE_SW = 0, 29 + 30 + /* 31 + * 1-bit ECC: calculation by GPMC, Error detection by Software 32 + * ECC layout compatible with ROM code layout 33 + */ 34 + OMAP_ECC_HAM1_CODE_HW, 26 35 /* 4-bit ECC calculation by GPMC, Error detection by Software */ 27 36 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, 28 37 /* 4-bit ECC calculation by GPMC, Error detection by ELM */