+423

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h

reviewed

··· 1 1 + /* 2 2 + * Copyright (C) 2025 Advanced Micro Devices, Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included 12 12 + * in all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 20 + */ 21 21 + #ifndef _mp_15_0_0_OFFSET_HEADER 22 22 + #define _mp_15_0_0_OFFSET_HEADER 23 23 + 24 24 + 25 25 + 26 26 + // addressBlock: mp_SmuMpASP_SmnDec 27 27 + // base address: 0x0 28 28 + #define regMPASP_SMN_C2PMSG_60 0x007c 29 29 + #define regMPASP_SMN_C2PMSG_60_BASE_IDX 0 30 30 + #define regMPASP_SMN_C2PMSG_61 0x007d 31 31 + #define regMPASP_SMN_C2PMSG_61_BASE_IDX 0 32 32 + #define regMPASP_SMN_C2PMSG_62 0x007e 33 33 + #define regMPASP_SMN_C2PMSG_62_BASE_IDX 0 34 34 + #define regMPASP_SMN_C2PMSG_63 0x007f 35 35 + #define regMPASP_SMN_C2PMSG_63_BASE_IDX 0 36 36 + #define regMPASP_SMN_C2PMSG_64 0x0080 37 37 + #define regMPASP_SMN_C2PMSG_64_BASE_IDX 0 38 38 + #define regMPASP_SMN_C2PMSG_65 0x0081 39 39 + #define regMPASP_SMN_C2PMSG_65_BASE_IDX 0 40 40 + #define regMPASP_SMN_C2PMSG_66 0x0082 41 41 + #define regMPASP_SMN_C2PMSG_66_BASE_IDX 0 42 42 + #define regMPASP_SMN_C2PMSG_67 0x0083 43 43 + #define regMPASP_SMN_C2PMSG_67_BASE_IDX 0 44 44 + #define regMPASP_SMN_C2PMSG_68 0x0084 45 45 + #define regMPASP_SMN_C2PMSG_68_BASE_IDX 0 46 46 + #define regMPASP_SMN_C2PMSG_69 0x0085 47 47 + #define regMPASP_SMN_C2PMSG_69_BASE_IDX 0 48 48 + #define regMPASP_SMN_C2PMSG_70 0x0086 49 49 + #define regMPASP_SMN_C2PMSG_70_BASE_IDX 0 50 50 + #define regMPASP_SMN_C2PMSG_71 0x0087 51 51 + #define regMPASP_SMN_C2PMSG_71_BASE_IDX 0 52 52 + #define regMPASP_SMN_C2PMSG_72 0x0088 53 53 + #define regMPASP_SMN_C2PMSG_72_BASE_IDX 0 54 54 + #define regMPASP_SMN_C2PMSG_73 0x0089 55 55 + #define regMPASP_SMN_C2PMSG_73_BASE_IDX 0 56 56 + #define regMPASP_SMN_C2PMSG_74 0x008a 57 57 + #define regMPASP_SMN_C2PMSG_74_BASE_IDX 0 58 58 + #define regMPASP_SMN_C2PMSG_75 0x008b 59 59 + #define regMPASP_SMN_C2PMSG_75_BASE_IDX 0 60 60 + #define regMPASP_SMN_C2PMSG_76 0x008c 61 61 + #define regMPASP_SMN_C2PMSG_76_BASE_IDX 0 62 62 + #define regMPASP_SMN_C2PMSG_77 0x008d 63 63 + #define regMPASP_SMN_C2PMSG_77_BASE_IDX 0 64 64 + #define regMPASP_SMN_C2PMSG_78 0x008e 65 65 + #define regMPASP_SMN_C2PMSG_78_BASE_IDX 0 66 66 + #define regMPASP_SMN_C2PMSG_79 0x008f 67 67 + #define regMPASP_SMN_C2PMSG_79_BASE_IDX 0 68 68 + #define regMPASP_SMN_C2PMSG_100 0x00a4 69 69 + #define regMPASP_SMN_C2PMSG_100_BASE_IDX 0 70 70 + #define regMPASP_SMN_C2PMSG_101 0x00a5 71 71 + #define regMPASP_SMN_C2PMSG_101_BASE_IDX 0 72 72 + #define regMPASP_SMN_C2PMSG_102 0x00a6 73 73 + #define regMPASP_SMN_C2PMSG_102_BASE_IDX 0 74 74 + #define regMPASP_SMN_C2PMSG_103 0x00a7 75 75 + #define regMPASP_SMN_C2PMSG_103_BASE_IDX 0 76 76 + #define regMPASP_SMN_C2PMSG_109 0x00ad 77 77 + #define regMPASP_SMN_C2PMSG_109_BASE_IDX 0 78 78 + #define regMPASP_SMN_IH_CREDIT 0x0140 79 79 + #define regMPASP_SMN_IH_CREDIT_BASE_IDX 0 80 80 + #define regMPASP_SMN_IH_SW_INT 0x0141 81 81 + #define regMPASP_SMN_IH_SW_INT_BASE_IDX 0 82 82 + #define regMPASP_SMN_IH_SW_INT_CTRL 0x0142 83 83 + #define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0 84 84 + 85 85 + 86 86 + // addressBlock: mp_SmuMp1_SmnDec 87 87 + // base address: 0x0 88 88 + #define regMP1_SMN_C2PMSG_0 0x0040 89 89 + #define regMP1_SMN_C2PMSG_0_BASE_IDX 1 90 90 + #define regMP1_SMN_C2PMSG_1 0x0041 91 91 + #define regMP1_SMN_C2PMSG_1_BASE_IDX 1 92 92 + #define regMP1_SMN_C2PMSG_2 0x0042 93 93 + #define regMP1_SMN_C2PMSG_2_BASE_IDX 1 94 94 + #define regMP1_SMN_C2PMSG_3 0x0043 95 95 + #define regMP1_SMN_C2PMSG_3_BASE_IDX 1 96 96 + #define regMP1_SMN_C2PMSG_4 0x0044 97 97 + #define regMP1_SMN_C2PMSG_4_BASE_IDX 1 98 98 + #define regMP1_SMN_C2PMSG_5 0x0045 99 99 + #define regMP1_SMN_C2PMSG_5_BASE_IDX 1 100 100 + #define regMP1_SMN_C2PMSG_6 0x0046 101 101 + #define regMP1_SMN_C2PMSG_6_BASE_IDX 1 102 102 + #define regMP1_SMN_C2PMSG_7 0x0047 103 103 + #define regMP1_SMN_C2PMSG_7_BASE_IDX 1 104 104 + #define regMP1_SMN_C2PMSG_8 0x0048 105 105 + #define regMP1_SMN_C2PMSG_8_BASE_IDX 1 106 106 + #define regMP1_SMN_C2PMSG_9 0x0049 107 107 + #define regMP1_SMN_C2PMSG_9_BASE_IDX 1 108 108 + #define regMP1_SMN_C2PMSG_10 0x004a 109 109 + #define regMP1_SMN_C2PMSG_10_BASE_IDX 1 110 110 + #define regMP1_SMN_C2PMSG_11 0x004b 111 111 + #define regMP1_SMN_C2PMSG_11_BASE_IDX 1 112 112 + #define regMP1_SMN_C2PMSG_12 0x004c 113 113 + #define regMP1_SMN_C2PMSG_12_BASE_IDX 1 114 114 + #define regMP1_SMN_C2PMSG_13 0x004d 115 115 + #define regMP1_SMN_C2PMSG_13_BASE_IDX 1 116 116 + #define regMP1_SMN_C2PMSG_14 0x004e 117 117 + #define regMP1_SMN_C2PMSG_14_BASE_IDX 1 118 118 + #define regMP1_SMN_C2PMSG_15 0x004f 119 119 + #define regMP1_SMN_C2PMSG_15_BASE_IDX 1 120 120 + #define regMP1_SMN_C2PMSG_16 0x0050 121 121 + #define regMP1_SMN_C2PMSG_16_BASE_IDX 1 122 122 + #define regMP1_SMN_C2PMSG_17 0x0051 123 123 + #define regMP1_SMN_C2PMSG_17_BASE_IDX 1 124 124 + #define regMP1_SMN_C2PMSG_18 0x0052 125 125 + #define regMP1_SMN_C2PMSG_18_BASE_IDX 1 126 126 + #define regMP1_SMN_C2PMSG_19 0x0053 127 127 + #define regMP1_SMN_C2PMSG_19_BASE_IDX 1 128 128 + #define regMP1_SMN_C2PMSG_20 0x0054 129 129 + #define regMP1_SMN_C2PMSG_20_BASE_IDX 1 130 130 + #define regMP1_SMN_C2PMSG_21 0x0055 131 131 + #define regMP1_SMN_C2PMSG_21_BASE_IDX 1 132 132 + #define regMP1_SMN_C2PMSG_22 0x0056 133 133 + #define regMP1_SMN_C2PMSG_22_BASE_IDX 1 134 134 + #define regMP1_SMN_C2PMSG_23 0x0057 135 135 + #define regMP1_SMN_C2PMSG_23_BASE_IDX 1 136 136 + #define regMP1_SMN_C2PMSG_24 0x0058 137 137 + #define regMP1_SMN_C2PMSG_24_BASE_IDX 1 138 138 + #define regMP1_SMN_C2PMSG_25 0x0059 139 139 + #define regMP1_SMN_C2PMSG_25_BASE_IDX 1 140 140 + #define regMP1_SMN_C2PMSG_26 0x005a 141 141 + #define regMP1_SMN_C2PMSG_26_BASE_IDX 1 142 142 + #define regMP1_SMN_C2PMSG_27 0x005b 143 143 + #define regMP1_SMN_C2PMSG_27_BASE_IDX 1 144 144 + #define regMP1_SMN_C2PMSG_28 0x005c 145 145 + #define regMP1_SMN_C2PMSG_28_BASE_IDX 1 146 146 + #define regMP1_SMN_C2PMSG_29 0x005d 147 147 + #define regMP1_SMN_C2PMSG_29_BASE_IDX 1 148 148 + #define regMP1_SMN_C2PMSG_30 0x005e 149 149 + #define regMP1_SMN_C2PMSG_30_BASE_IDX 1 150 150 + #define regMP1_SMN_C2PMSG_31 0x005f 151 151 + #define regMP1_SMN_C2PMSG_31_BASE_IDX 1 152 152 + #define regMP1_SMN_C2PMSG_32 0x0060 153 153 + #define regMP1_SMN_C2PMSG_32_BASE_IDX 1 154 154 + #define regMP1_SMN_C2PMSG_33 0x0061 155 155 + #define regMP1_SMN_C2PMSG_33_BASE_IDX 1 156 156 + #define regMP1_SMN_C2PMSG_34 0x0062 157 157 + #define regMP1_SMN_C2PMSG_34_BASE_IDX 1 158 158 + #define regMP1_SMN_C2PMSG_35 0x0063 159 159 + #define regMP1_SMN_C2PMSG_35_BASE_IDX 1 160 160 + #define regMP1_SMN_C2PMSG_36 0x0064 161 161 + #define regMP1_SMN_C2PMSG_36_BASE_IDX 1 162 162 + #define regMP1_SMN_C2PMSG_37 0x0065 163 163 + #define regMP1_SMN_C2PMSG_37_BASE_IDX 1 164 164 + #define regMP1_SMN_C2PMSG_38 0x0066 165 165 + #define regMP1_SMN_C2PMSG_38_BASE_IDX 1 166 166 + #define regMP1_SMN_C2PMSG_39 0x0067 167 167 + #define regMP1_SMN_C2PMSG_39_BASE_IDX 1 168 168 + #define regMP1_SMN_C2PMSG_40 0x0068 169 169 + #define regMP1_SMN_C2PMSG_40_BASE_IDX 1 170 170 + #define regMP1_SMN_C2PMSG_41 0x0069 171 171 + #define regMP1_SMN_C2PMSG_41_BASE_IDX 1 172 172 + #define regMP1_SMN_C2PMSG_42 0x006a 173 173 + #define regMP1_SMN_C2PMSG_42_BASE_IDX 1 174 174 + #define regMP1_SMN_C2PMSG_43 0x006b 175 175 + #define regMP1_SMN_C2PMSG_43_BASE_IDX 1 176 176 + #define regMP1_SMN_C2PMSG_44 0x006c 177 177 + #define regMP1_SMN_C2PMSG_44_BASE_IDX 1 178 178 + #define regMP1_SMN_C2PMSG_45 0x006d 179 179 + #define regMP1_SMN_C2PMSG_45_BASE_IDX 1 180 180 + #define regMP1_SMN_C2PMSG_46 0x006e 181 181 + #define regMP1_SMN_C2PMSG_46_BASE_IDX 1 182 182 + #define regMP1_SMN_C2PMSG_47 0x006f 183 183 + #define regMP1_SMN_C2PMSG_47_BASE_IDX 1 184 184 + #define regMP1_SMN_C2PMSG_48 0x0070 185 185 + #define regMP1_SMN_C2PMSG_48_BASE_IDX 1 186 186 + #define regMP1_SMN_C2PMSG_49 0x0071 187 187 + #define regMP1_SMN_C2PMSG_49_BASE_IDX 1 188 188 + #define regMP1_SMN_C2PMSG_50 0x0072 189 189 + #define regMP1_SMN_C2PMSG_50_BASE_IDX 1 190 190 + #define regMP1_SMN_C2PMSG_51 0x0073 191 191 + #define regMP1_SMN_C2PMSG_51_BASE_IDX 1 192 192 + #define regMP1_SMN_C2PMSG_52 0x0074 193 193 + #define regMP1_SMN_C2PMSG_52_BASE_IDX 1 194 194 + #define regMP1_SMN_C2PMSG_53 0x0075 195 195 + #define regMP1_SMN_C2PMSG_53_BASE_IDX 1 196 196 + #define regMP1_SMN_C2PMSG_54 0x0076 197 197 + #define regMP1_SMN_C2PMSG_54_BASE_IDX 1 198 198 + #define regMP1_SMN_C2PMSG_55 0x0077 199 199 + #define regMP1_SMN_C2PMSG_55_BASE_IDX 1 200 200 + #define regMP1_SMN_C2PMSG_56 0x0078 201 201 + #define regMP1_SMN_C2PMSG_56_BASE_IDX 1 202 202 + #define regMP1_SMN_C2PMSG_57 0x0079 203 203 + #define regMP1_SMN_C2PMSG_57_BASE_IDX 1 204 204 + #define regMP1_SMN_C2PMSG_58 0x007a 205 205 + #define regMP1_SMN_C2PMSG_58_BASE_IDX 1 206 206 + #define regMP1_SMN_C2PMSG_59 0x007b 207 207 + #define regMP1_SMN_C2PMSG_59_BASE_IDX 1 208 208 + #define regMP1_SMN_C2PMSG_60 0x007c 209 209 + #define regMP1_SMN_C2PMSG_60_BASE_IDX 1 210 210 + #define regMP1_SMN_C2PMSG_61 0x007d 211 211 + #define regMP1_SMN_C2PMSG_61_BASE_IDX 1 212 212 + #define regMP1_SMN_C2PMSG_62 0x007e 213 213 + #define regMP1_SMN_C2PMSG_62_BASE_IDX 1 214 214 + #define regMP1_SMN_C2PMSG_63 0x007f 215 215 + #define regMP1_SMN_C2PMSG_63_BASE_IDX 1 216 216 + #define regMP1_SMN_C2PMSG_64 0x0080 217 217 + #define regMP1_SMN_C2PMSG_64_BASE_IDX 1 218 218 + #define regMP1_SMN_C2PMSG_65 0x0081 219 219 + #define regMP1_SMN_C2PMSG_65_BASE_IDX 1 220 220 + #define regMP1_SMN_C2PMSG_66 0x0082 221 221 + #define regMP1_SMN_C2PMSG_66_BASE_IDX 1 222 222 + #define regMP1_SMN_C2PMSG_67 0x0083 223 223 + #define regMP1_SMN_C2PMSG_67_BASE_IDX 1 224 224 + #define regMP1_SMN_C2PMSG_68 0x0084 225 225 + #define regMP1_SMN_C2PMSG_68_BASE_IDX 1 226 226 + #define regMP1_SMN_C2PMSG_69 0x0085 227 227 + #define regMP1_SMN_C2PMSG_69_BASE_IDX 1 228 228 + #define regMP1_SMN_C2PMSG_70 0x0086 229 229 + #define regMP1_SMN_C2PMSG_70_BASE_IDX 1 230 230 + #define regMP1_SMN_C2PMSG_71 0x0087 231 231 + #define regMP1_SMN_C2PMSG_71_BASE_IDX 1 232 232 + #define regMP1_SMN_C2PMSG_72 0x0088 233 233 + #define regMP1_SMN_C2PMSG_72_BASE_IDX 1 234 234 + #define regMP1_SMN_C2PMSG_73 0x0089 235 235 + #define regMP1_SMN_C2PMSG_73_BASE_IDX 1 236 236 + #define regMP1_SMN_C2PMSG_74 0x008a 237 237 + #define regMP1_SMN_C2PMSG_74_BASE_IDX 1 238 238 + #define regMP1_SMN_C2PMSG_75 0x008b 239 239 + #define regMP1_SMN_C2PMSG_75_BASE_IDX 1 240 240 + #define regMP1_SMN_C2PMSG_76 0x008c 241 241 + #define regMP1_SMN_C2PMSG_76_BASE_IDX 1 242 242 + #define regMP1_SMN_C2PMSG_77 0x008d 243 243 + #define regMP1_SMN_C2PMSG_77_BASE_IDX 1 244 244 + #define regMP1_SMN_C2PMSG_78 0x008e 245 245 + #define regMP1_SMN_C2PMSG_78_BASE_IDX 1 246 246 + #define regMP1_SMN_C2PMSG_79 0x008f 247 247 + #define regMP1_SMN_C2PMSG_79_BASE_IDX 1 248 248 + #define regMP1_SMN_C2PMSG_80 0x0090 249 249 + #define regMP1_SMN_C2PMSG_80_BASE_IDX 1 250 250 + #define regMP1_SMN_C2PMSG_81 0x0091 251 251 + #define regMP1_SMN_C2PMSG_81_BASE_IDX 1 252 252 + #define regMP1_SMN_C2PMSG_82 0x0092 253 253 + #define regMP1_SMN_C2PMSG_82_BASE_IDX 1 254 254 + #define regMP1_SMN_C2PMSG_83 0x0093 255 255 + #define regMP1_SMN_C2PMSG_83_BASE_IDX 1 256 256 + #define regMP1_SMN_C2PMSG_84 0x0094 257 257 + #define regMP1_SMN_C2PMSG_84_BASE_IDX 1 258 258 + #define regMP1_SMN_C2PMSG_85 0x0095 259 259 + #define regMP1_SMN_C2PMSG_85_BASE_IDX 1 260 260 + #define regMP1_SMN_C2PMSG_86 0x0096 261 261 + #define regMP1_SMN_C2PMSG_86_BASE_IDX 1 262 262 + #define regMP1_SMN_C2PMSG_87 0x0097 263 263 + #define regMP1_SMN_C2PMSG_87_BASE_IDX 1 264 264 + #define regMP1_SMN_C2PMSG_88 0x0098 265 265 + #define regMP1_SMN_C2PMSG_88_BASE_IDX 1 266 266 + #define regMP1_SMN_C2PMSG_89 0x0099 267 267 + #define regMP1_SMN_C2PMSG_89_BASE_IDX 1 268 268 + #define regMP1_SMN_C2PMSG_90 0x009a 269 269 + #define regMP1_SMN_C2PMSG_90_BASE_IDX 1 270 270 + #define regMP1_SMN_C2PMSG_91 0x009b 271 271 + #define regMP1_SMN_C2PMSG_91_BASE_IDX 1 272 272 + #define regMP1_SMN_C2PMSG_92 0x009c 273 273 + #define regMP1_SMN_C2PMSG_92_BASE_IDX 1 274 274 + #define regMP1_SMN_C2PMSG_93 0x009d 275 275 + #define regMP1_SMN_C2PMSG_93_BASE_IDX 1 276 276 + #define regMP1_SMN_C2PMSG_94 0x009e 277 277 + #define regMP1_SMN_C2PMSG_94_BASE_IDX 1 278 278 + #define regMP1_SMN_C2PMSG_95 0x009f 279 279 + #define regMP1_SMN_C2PMSG_95_BASE_IDX 1 280 280 + #define regMP1_SMN_C2PMSG_96 0x00a0 281 281 + #define regMP1_SMN_C2PMSG_96_BASE_IDX 1 282 282 + #define regMP1_SMN_C2PMSG_97 0x00a1 283 283 + #define regMP1_SMN_C2PMSG_97_BASE_IDX 1 284 284 + #define regMP1_SMN_C2PMSG_98 0x00a2 285 285 + #define regMP1_SMN_C2PMSG_98_BASE_IDX 1 286 286 + #define regMP1_SMN_C2PMSG_99 0x00a3 287 287 + #define regMP1_SMN_C2PMSG_99_BASE_IDX 1 288 288 + #define regMP1_SMN_C2PMSG_100 0x00a4 289 289 + #define regMP1_SMN_C2PMSG_100_BASE_IDX 1 290 290 + #define regMP1_SMN_C2PMSG_101 0x00a5 291 291 + #define regMP1_SMN_C2PMSG_101_BASE_IDX 1 292 292 + #define regMP1_SMN_C2PMSG_102 0x00a6 293 293 + #define regMP1_SMN_C2PMSG_102_BASE_IDX 1 294 294 + #define regMP1_SMN_C2PMSG_103 0x00a7 295 295 + #define regMP1_SMN_C2PMSG_103_BASE_IDX 1 296 296 + #define regMP1_SMN_C2PMSG_104 0x00a8 297 297 + #define regMP1_SMN_C2PMSG_104_BASE_IDX 1 298 298 + #define regMP1_SMN_C2PMSG_105 0x00a9 299 299 + #define regMP1_SMN_C2PMSG_105_BASE_IDX 1 300 300 + #define regMP1_SMN_C2PMSG_106 0x00aa 301 301 + #define regMP1_SMN_C2PMSG_106_BASE_IDX 1 302 302 + #define regMP1_SMN_C2PMSG_107 0x00ab 303 303 + #define regMP1_SMN_C2PMSG_107_BASE_IDX 1 304 304 + #define regMP1_SMN_C2PMSG_108 0x00ac 305 305 + #define regMP1_SMN_C2PMSG_108_BASE_IDX 1 306 306 + #define regMP1_SMN_C2PMSG_109 0x00ad 307 307 + #define regMP1_SMN_C2PMSG_109_BASE_IDX 1 308 308 + #define regMP1_SMN_C2PMSG_110 0x00ae 309 309 + #define regMP1_SMN_C2PMSG_110_BASE_IDX 1 310 310 + #define regMP1_SMN_C2PMSG_111 0x00af 311 311 + #define regMP1_SMN_C2PMSG_111_BASE_IDX 1 312 312 + #define regMP1_SMN_C2PMSG_112 0x00b0 313 313 + #define regMP1_SMN_C2PMSG_112_BASE_IDX 1 314 314 + #define regMP1_SMN_C2PMSG_113 0x00b1 315 315 + #define regMP1_SMN_C2PMSG_113_BASE_IDX 1 316 316 + #define regMP1_SMN_C2PMSG_114 0x00b2 317 317 + #define regMP1_SMN_C2PMSG_114_BASE_IDX 1 318 318 + #define regMP1_SMN_C2PMSG_115 0x00b3 319 319 + #define regMP1_SMN_C2PMSG_115_BASE_IDX 1 320 320 + #define regMP1_SMN_C2PMSG_116 0x00b4 321 321 + #define regMP1_SMN_C2PMSG_116_BASE_IDX 1 322 322 + #define regMP1_SMN_C2PMSG_117 0x00b5 323 323 + #define regMP1_SMN_C2PMSG_117_BASE_IDX 1 324 324 + #define regMP1_SMN_C2PMSG_118 0x00b6 325 325 + #define regMP1_SMN_C2PMSG_118_BASE_IDX 1 326 326 + #define regMP1_SMN_C2PMSG_119 0x00b7 327 327 + #define regMP1_SMN_C2PMSG_119_BASE_IDX 1 328 328 + #define regMP1_SMN_C2PMSG_120 0x00b8 329 329 + #define regMP1_SMN_C2PMSG_120_BASE_IDX 1 330 330 + #define regMP1_SMN_C2PMSG_121 0x00b9 331 331 + #define regMP1_SMN_C2PMSG_121_BASE_IDX 1 332 332 + #define regMP1_SMN_C2PMSG_122 0x00ba 333 333 + #define regMP1_SMN_C2PMSG_122_BASE_IDX 1 334 334 + #define regMP1_SMN_C2PMSG_123 0x00bb 335 335 + #define regMP1_SMN_C2PMSG_123_BASE_IDX 1 336 336 + #define regMP1_SMN_C2PMSG_124 0x00bc 337 337 + #define regMP1_SMN_C2PMSG_124_BASE_IDX 1 338 338 + #define regMP1_SMN_C2PMSG_125 0x00bd 339 339 + #define regMP1_SMN_C2PMSG_125_BASE_IDX 1 340 340 + #define regMP1_SMN_C2PMSG_126 0x00be 341 341 + #define regMP1_SMN_C2PMSG_126_BASE_IDX 1 342 342 + #define regMP1_SMN_C2PMSG_127 0x00bf 343 343 + #define regMP1_SMN_C2PMSG_127_BASE_IDX 1 344 344 + #define regMP1_SMN_IH_CREDIT 0x0140 345 345 + #define regMP1_SMN_IH_CREDIT_BASE_IDX 1 346 346 + #define regMP1_SMN_IH_SW_INT 0x0141 347 347 + #define regMP1_SMN_IH_SW_INT_BASE_IDX 1 348 348 + #define regMP1_SMN_IH_SW_INT_CTRL 0x0142 349 349 + #define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 1 350 350 + #define regMP1_SMN_FPS_CNT 0x0143 351 351 + #define regMP1_SMN_FPS_CNT_BASE_IDX 1 352 352 + #define regMP1_SMN_EXT_SCRATCH0 0x01c0 353 353 + #define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 1 354 354 + #define regMP1_SMN_EXT_SCRATCH1 0x01c1 355 355 + #define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 1 356 356 + #define regMP1_SMN_EXT_SCRATCH2 0x01c2 357 357 + #define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 1 358 358 + #define regMP1_SMN_EXT_SCRATCH3 0x01c3 359 359 + #define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 1 360 360 + #define regMP1_SMN_EXT_SCRATCH4 0x01c4 361 361 + #define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 1 362 362 + #define regMP1_SMN_EXT_SCRATCH5 0x01c5 363 363 + #define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 1 364 364 + #define regMP1_SMN_EXT_SCRATCH6 0x01c6 365 365 + #define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 1 366 366 + #define regMP1_SMN_EXT_SCRATCH7 0x01c7 367 367 + #define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 1 368 368 + #define regMP1_SMN_EXT_SCRATCH8 0x01c8 369 369 + #define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 1 370 370 + #define regMP1_SMN_EXT_SCRATCH9 0x01c9 371 371 + #define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 1 372 372 + #define regMP1_SMN_EXT_SCRATCH10 0x01ca 373 373 + #define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 1 374 374 + #define regMP1_SMN_EXT_SCRATCH11 0x01cb 375 375 + #define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 1 376 376 + #define regMP1_SMN_EXT_SCRATCH12 0x01cc 377 377 + #define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 1 378 378 + #define regMP1_SMN_EXT_SCRATCH13 0x01cd 379 379 + #define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 1 380 380 + #define regMP1_SMN_EXT_SCRATCH14 0x01ce 381 381 + #define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 1 382 382 + #define regMP1_SMN_EXT_SCRATCH15 0x01cf 383 383 + #define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 1 384 384 + #define regMP1_SMN_EXT_SCRATCH16 0x01d0 385 385 + #define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 1 386 386 + #define regMP1_SMN_EXT_SCRATCH17 0x01d1 387 387 + #define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 1 388 388 + #define regMP1_SMN_EXT_SCRATCH18 0x01d2 389 389 + #define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 1 390 390 + #define regMP1_SMN_EXT_SCRATCH19 0x01d3 391 391 + #define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 1 392 392 + #define regMP1_SMN_EXT_SCRATCH20 0x01d4 393 393 + #define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 1 394 394 + #define regMP1_SMN_EXT_SCRATCH21 0x01d5 395 395 + #define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 1 396 396 + #define regMP1_SMN_EXT_SCRATCH22 0x01d6 397 397 + #define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 1 398 398 + #define regMP1_SMN_EXT_SCRATCH23 0x01d7 399 399 + #define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 1 400 400 + #define regMP1_SMN_EXT_SCRATCH24 0x01d8 401 401 + #define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 1 402 402 + #define regMP1_SMN_EXT_SCRATCH25 0x01d9 403 403 + #define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 1 404 404 + #define regMP1_SMN_EXT_SCRATCH26 0x01da 405 405 + #define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 1 406 406 + #define regMP1_SMN_EXT_SCRATCH27 0x01db 407 407 + #define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 1 408 408 + #define regMP1_SMN_EXT_SCRATCH28 0x01dc 409 409 + #define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 1 410 410 + #define regMP1_SMN_EXT_SCRATCH29 0x01dd 411 411 + #define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 1 412 412 + #define regMP1_SMN_EXT_SCRATCH30 0x01de 413 413 + #define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 1 414 414 + #define regMP1_SMN_EXT_SCRATCH31 0x01df 415 415 + #define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 1 416 416 + 417 417 + 418 418 + // addressBlock: mp_SmuMp1Pub_CruDec 419 419 + // base address: 0x3b00000 420 420 + #define regMP1_CRU1_MP1_FIRMWARE_FLAGS 0x4009 421 421 + #define regMP1_CRU1_MP1_FIRMWARE_FLAGS_BASE_IDX 5 422 422 + 423 423 + #endif

+626

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_sh_mask.h

reviewed

··· 1 1 + /* 2 2 + * Copyright (C) 2025 Advanced Micro Devices, Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included 12 12 + * in all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 20 + */ 21 21 + #ifndef _mp_15_0_0_SH_MASK_HEADER 22 22 + #define _mp_15_0_0_SH_MASK_HEADER 23 23 + 24 24 + 25 25 + // addressBlock: mp_SmuMpASP_SmnDec 26 26 + //MPASP_SMN_C2PMSG_60 27 27 + #define MPASP_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 28 28 + #define MPASP_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 29 29 + //MPASP_SMN_C2PMSG_61 30 30 + #define MPASP_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 31 31 + #define MPASP_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 32 32 + //MPASP_SMN_C2PMSG_62 33 33 + #define MPASP_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 34 34 + #define MPASP_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 35 35 + //MPASP_SMN_C2PMSG_63 36 36 + #define MPASP_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 37 37 + #define MPASP_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 38 38 + //MPASP_SMN_C2PMSG_64 39 39 + #define MPASP_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 40 40 + #define MPASP_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 41 41 + //MPASP_SMN_C2PMSG_65 42 42 + #define MPASP_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 43 43 + #define MPASP_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 44 44 + //MPASP_SMN_C2PMSG_66 45 45 + #define MPASP_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 46 46 + #define MPASP_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 47 47 + //MPASP_SMN_C2PMSG_67 48 48 + #define MPASP_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 49 49 + #define MPASP_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 50 50 + //MPASP_SMN_C2PMSG_68 51 51 + #define MPASP_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 52 52 + #define MPASP_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 53 53 + //MPASP_SMN_C2PMSG_69 54 54 + #define MPASP_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 55 55 + #define MPASP_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 56 56 + //MPASP_SMN_C2PMSG_70 57 57 + #define MPASP_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 58 58 + #define MPASP_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 59 59 + //MPASP_SMN_C2PMSG_71 60 60 + #define MPASP_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 61 61 + #define MPASP_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 62 62 + //MPASP_SMN_C2PMSG_72 63 63 + #define MPASP_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 64 64 + #define MPASP_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 65 65 + //MPASP_SMN_C2PMSG_73 66 66 + #define MPASP_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 67 67 + #define MPASP_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 68 68 + //MPASP_SMN_C2PMSG_74 69 69 + #define MPASP_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 70 70 + #define MPASP_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 71 71 + //MPASP_SMN_C2PMSG_75 72 72 + #define MPASP_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 73 73 + #define MPASP_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 74 74 + //MPASP_SMN_C2PMSG_76 75 75 + #define MPASP_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 76 76 + #define MPASP_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 77 77 + //MPASP_SMN_C2PMSG_77 78 78 + #define MPASP_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 79 79 + #define MPASP_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 80 80 + //MPASP_SMN_C2PMSG_78 81 81 + #define MPASP_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 82 82 + #define MPASP_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 83 83 + //MPASP_SMN_C2PMSG_79 84 84 + #define MPASP_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 85 85 + #define MPASP_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 86 86 + //MPASP_SMN_C2PMSG_100 87 87 + #define MPASP_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 88 88 + #define MPASP_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 89 89 + //MPASP_SMN_C2PMSG_101 90 90 + #define MPASP_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 91 91 + #define MPASP_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 92 92 + //MPASP_SMN_C2PMSG_102 93 93 + #define MPASP_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 94 94 + #define MPASP_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 95 95 + //MPASP_SMN_C2PMSG_103 96 96 + #define MPASP_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 97 97 + #define MPASP_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 98 98 + //MPASP_SMN_C2PMSG_109 99 99 + #define MPASP_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 100 100 + #define MPASP_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 101 101 + //MPASP_SMN_IH_CREDIT 102 102 + #define MPASP_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 103 103 + #define MPASP_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 104 104 + #define MPASP_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 105 105 + #define MPASP_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 106 106 + //MPASP_SMN_IH_SW_INT 107 107 + #define MPASP_SMN_IH_SW_INT__ID__SHIFT 0x0 108 108 + #define MPASP_SMN_IH_SW_INT__VALID__SHIFT 0x8 109 109 + #define MPASP_SMN_IH_SW_INT__ID_MASK 0x000000FFL 110 110 + #define MPASP_SMN_IH_SW_INT__VALID_MASK 0x00000100L 111 111 + //MPASP_SMN_IH_SW_INT_CTRL 112 112 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 113 113 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 114 114 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 115 115 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 116 116 + 117 117 + 118 118 + // addressBlock: mp_SmuMp1_SmnDec 119 119 + //MP1_SMN_C2PMSG_0 120 120 + #define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0 121 121 + #define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 122 122 + //MP1_SMN_C2PMSG_1 123 123 + #define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0 124 124 + #define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 125 125 + //MP1_SMN_C2PMSG_2 126 126 + #define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0 127 127 + #define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 128 128 + //MP1_SMN_C2PMSG_3 129 129 + #define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0 130 130 + #define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 131 131 + //MP1_SMN_C2PMSG_4 132 132 + #define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0 133 133 + #define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 134 134 + //MP1_SMN_C2PMSG_5 135 135 + #define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0 136 136 + #define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 137 137 + //MP1_SMN_C2PMSG_6 138 138 + #define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0 139 139 + #define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 140 140 + //MP1_SMN_C2PMSG_7 141 141 + #define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0 142 142 + #define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 143 143 + //MP1_SMN_C2PMSG_8 144 144 + #define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0 145 145 + #define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 146 146 + //MP1_SMN_C2PMSG_9 147 147 + #define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0 148 148 + #define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 149 149 + //MP1_SMN_C2PMSG_10 150 150 + #define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0 151 151 + #define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 152 152 + //MP1_SMN_C2PMSG_11 153 153 + #define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0 154 154 + #define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 155 155 + //MP1_SMN_C2PMSG_12 156 156 + #define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0 157 157 + #define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 158 158 + //MP1_SMN_C2PMSG_13 159 159 + #define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0 160 160 + #define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 161 161 + //MP1_SMN_C2PMSG_14 162 162 + #define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0 163 163 + #define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 164 164 + //MP1_SMN_C2PMSG_15 165 165 + #define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0 166 166 + #define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 167 167 + //MP1_SMN_C2PMSG_16 168 168 + #define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0 169 169 + #define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 170 170 + //MP1_SMN_C2PMSG_17 171 171 + #define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0 172 172 + #define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 173 173 + //MP1_SMN_C2PMSG_18 174 174 + #define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0 175 175 + #define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 176 176 + //MP1_SMN_C2PMSG_19 177 177 + #define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0 178 178 + #define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 179 179 + //MP1_SMN_C2PMSG_20 180 180 + #define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0 181 181 + #define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 182 182 + //MP1_SMN_C2PMSG_21 183 183 + #define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0 184 184 + #define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 185 185 + //MP1_SMN_C2PMSG_22 186 186 + #define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0 187 187 + #define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 188 188 + //MP1_SMN_C2PMSG_23 189 189 + #define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0 190 190 + #define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 191 191 + //MP1_SMN_C2PMSG_24 192 192 + #define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0 193 193 + #define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 194 194 + //MP1_SMN_C2PMSG_25 195 195 + #define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0 196 196 + #define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 197 197 + //MP1_SMN_C2PMSG_26 198 198 + #define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0 199 199 + #define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 200 200 + //MP1_SMN_C2PMSG_27 201 201 + #define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0 202 202 + #define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 203 203 + //MP1_SMN_C2PMSG_28 204 204 + #define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0 205 205 + #define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 206 206 + //MP1_SMN_C2PMSG_29 207 207 + #define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0 208 208 + #define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 209 209 + //MP1_SMN_C2PMSG_30 210 210 + #define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0 211 211 + #define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 212 212 + //MP1_SMN_C2PMSG_31 213 213 + #define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0 214 214 + #define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 215 215 + //MP1_SMN_C2PMSG_32 216 216 + #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 217 217 + #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 218 218 + //MP1_SMN_C2PMSG_33 219 219 + #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 220 220 + #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 221 221 + //MP1_SMN_C2PMSG_34 222 222 + #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 223 223 + #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 224 224 + //MP1_SMN_C2PMSG_35 225 225 + #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 226 226 + #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 227 227 + //MP1_SMN_C2PMSG_36 228 228 + #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 229 229 + #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 230 230 + //MP1_SMN_C2PMSG_37 231 231 + #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 232 232 + #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 233 233 + //MP1_SMN_C2PMSG_38 234 234 + #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 235 235 + #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 236 236 + //MP1_SMN_C2PMSG_39 237 237 + #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 238 238 + #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 239 239 + //MP1_SMN_C2PMSG_40 240 240 + #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 241 241 + #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 242 242 + //MP1_SMN_C2PMSG_41 243 243 + #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 244 244 + #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 245 245 + //MP1_SMN_C2PMSG_42 246 246 + #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 247 247 + #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 248 248 + //MP1_SMN_C2PMSG_43 249 249 + #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 250 250 + #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 251 251 + //MP1_SMN_C2PMSG_44 252 252 + #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 253 253 + #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 254 254 + //MP1_SMN_C2PMSG_45 255 255 + #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 256 256 + #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 257 257 + //MP1_SMN_C2PMSG_46 258 258 + #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 259 259 + #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 260 260 + //MP1_SMN_C2PMSG_47 261 261 + #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 262 262 + #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 263 263 + //MP1_SMN_C2PMSG_48 264 264 + #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 265 265 + #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 266 266 + //MP1_SMN_C2PMSG_49 267 267 + #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 268 268 + #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 269 269 + //MP1_SMN_C2PMSG_50 270 270 + #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 271 271 + #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 272 272 + //MP1_SMN_C2PMSG_51 273 273 + #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 274 274 + #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 275 275 + //MP1_SMN_C2PMSG_52 276 276 + #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 277 277 + #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 278 278 + //MP1_SMN_C2PMSG_53 279 279 + #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 280 280 + #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 281 281 + //MP1_SMN_C2PMSG_54 282 282 + #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 283 283 + #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 284 284 + //MP1_SMN_C2PMSG_55 285 285 + #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 286 286 + #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 287 287 + //MP1_SMN_C2PMSG_56 288 288 + #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 289 289 + #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 290 290 + //MP1_SMN_C2PMSG_57 291 291 + #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 292 292 + #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 293 293 + //MP1_SMN_C2PMSG_58 294 294 + #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 295 295 + #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 296 296 + //MP1_SMN_C2PMSG_59 297 297 + #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 298 298 + #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 299 299 + //MP1_SMN_C2PMSG_60 300 300 + #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 301 301 + #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 302 302 + //MP1_SMN_C2PMSG_61 303 303 + #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 304 304 + #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 305 305 + //MP1_SMN_C2PMSG_62 306 306 + #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 307 307 + #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 308 308 + //MP1_SMN_C2PMSG_63 309 309 + #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 310 310 + #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 311 311 + //MP1_SMN_C2PMSG_64 312 312 + #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 313 313 + #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 314 314 + //MP1_SMN_C2PMSG_65 315 315 + #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 316 316 + #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 317 317 + //MP1_SMN_C2PMSG_66 318 318 + #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 319 319 + #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 320 320 + //MP1_SMN_C2PMSG_67 321 321 + #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 322 322 + #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 323 323 + //MP1_SMN_C2PMSG_68 324 324 + #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 325 325 + #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 326 326 + //MP1_SMN_C2PMSG_69 327 327 + #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 328 328 + #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 329 329 + //MP1_SMN_C2PMSG_70 330 330 + #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 331 331 + #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 332 332 + //MP1_SMN_C2PMSG_71 333 333 + #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 334 334 + #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 335 335 + //MP1_SMN_C2PMSG_72 336 336 + #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 337 337 + #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 338 338 + //MP1_SMN_C2PMSG_73 339 339 + #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 340 340 + #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 341 341 + //MP1_SMN_C2PMSG_74 342 342 + #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 343 343 + #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 344 344 + //MP1_SMN_C2PMSG_75 345 345 + #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 346 346 + #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 347 347 + //MP1_SMN_C2PMSG_76 348 348 + #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 349 349 + #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 350 350 + //MP1_SMN_C2PMSG_77 351 351 + #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 352 352 + #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 353 353 + //MP1_SMN_C2PMSG_78 354 354 + #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 355 355 + #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 356 356 + //MP1_SMN_C2PMSG_79 357 357 + #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 358 358 + #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 359 359 + //MP1_SMN_C2PMSG_80 360 360 + #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 361 361 + #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 362 362 + //MP1_SMN_C2PMSG_81 363 363 + #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 364 364 + #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 365 365 + //MP1_SMN_C2PMSG_82 366 366 + #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 367 367 + #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 368 368 + //MP1_SMN_C2PMSG_83 369 369 + #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 370 370 + #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 371 371 + //MP1_SMN_C2PMSG_84 372 372 + #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 373 373 + #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 374 374 + //MP1_SMN_C2PMSG_85 375 375 + #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 376 376 + #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 377 377 + //MP1_SMN_C2PMSG_86 378 378 + #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 379 379 + #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 380 380 + //MP1_SMN_C2PMSG_87 381 381 + #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 382 382 + #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 383 383 + //MP1_SMN_C2PMSG_88 384 384 + #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 385 385 + #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 386 386 + //MP1_SMN_C2PMSG_89 387 387 + #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 388 388 + #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 389 389 + //MP1_SMN_C2PMSG_90 390 390 + #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 391 391 + #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 392 392 + //MP1_SMN_C2PMSG_91 393 393 + #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 394 394 + #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 395 395 + //MP1_SMN_C2PMSG_92 396 396 + #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 397 397 + #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 398 398 + //MP1_SMN_C2PMSG_93 399 399 + #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 400 400 + #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 401 401 + //MP1_SMN_C2PMSG_94 402 402 + #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 403 403 + #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 404 404 + //MP1_SMN_C2PMSG_95 405 405 + #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 406 406 + #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 407 407 + //MP1_SMN_C2PMSG_96 408 408 + #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 409 409 + #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 410 410 + //MP1_SMN_C2PMSG_97 411 411 + #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 412 412 + #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 413 413 + //MP1_SMN_C2PMSG_98 414 414 + #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 415 415 + #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 416 416 + //MP1_SMN_C2PMSG_99 417 417 + #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 418 418 + #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 419 419 + //MP1_SMN_C2PMSG_100 420 420 + #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 421 421 + #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 422 422 + //MP1_SMN_C2PMSG_101 423 423 + #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 424 424 + #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 425 425 + //MP1_SMN_C2PMSG_102 426 426 + #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 427 427 + #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 428 428 + //MP1_SMN_C2PMSG_103 429 429 + #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 430 430 + #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 431 431 + //MP1_SMN_C2PMSG_104 432 432 + #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 433 433 + #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 434 434 + //MP1_SMN_C2PMSG_105 435 435 + #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 436 436 + #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 437 437 + //MP1_SMN_C2PMSG_106 438 438 + #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 439 439 + #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 440 440 + //MP1_SMN_C2PMSG_107 441 441 + #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 442 442 + #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 443 443 + //MP1_SMN_C2PMSG_108 444 444 + #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 445 445 + #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 446 446 + //MP1_SMN_C2PMSG_109 447 447 + #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 448 448 + #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 449 449 + //MP1_SMN_C2PMSG_110 450 450 + #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 451 451 + #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 452 452 + //MP1_SMN_C2PMSG_111 453 453 + #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 454 454 + #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 455 455 + //MP1_SMN_C2PMSG_112 456 456 + #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 457 457 + #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 458 458 + //MP1_SMN_C2PMSG_113 459 459 + #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 460 460 + #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 461 461 + //MP1_SMN_C2PMSG_114 462 462 + #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 463 463 + #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 464 464 + //MP1_SMN_C2PMSG_115 465 465 + #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 466 466 + #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 467 467 + //MP1_SMN_C2PMSG_116 468 468 + #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 469 469 + #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 470 470 + //MP1_SMN_C2PMSG_117 471 471 + #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 472 472 + #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 473 473 + //MP1_SMN_C2PMSG_118 474 474 + #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 475 475 + #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 476 476 + //MP1_SMN_C2PMSG_119 477 477 + #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 478 478 + #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 479 479 + //MP1_SMN_C2PMSG_120 480 480 + #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 481 481 + #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 482 482 + //MP1_SMN_C2PMSG_121 483 483 + #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 484 484 + #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 485 485 + //MP1_SMN_C2PMSG_122 486 486 + #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 487 487 + #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 488 488 + //MP1_SMN_C2PMSG_123 489 489 + #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 490 490 + #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 491 491 + //MP1_SMN_C2PMSG_124 492 492 + #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 493 493 + #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 494 494 + //MP1_SMN_C2PMSG_125 495 495 + #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 496 496 + #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 497 497 + //MP1_SMN_C2PMSG_126 498 498 + #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 499 499 + #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 500 500 + //MP1_SMN_C2PMSG_127 501 501 + #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 502 502 + #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 503 503 + //MP1_SMN_IH_CREDIT 504 504 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 505 505 + #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 506 506 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 507 507 + #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 508 508 + //MP1_SMN_IH_SW_INT 509 509 + #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 510 510 + #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 511 511 + #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 512 512 + #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 513 513 + //MP1_SMN_IH_SW_INT_CTRL 514 514 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 515 515 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 516 516 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 517 517 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 518 518 + //MP1_SMN_FPS_CNT 519 519 + #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 520 520 + #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 521 521 + //MP1_SMN_EXT_SCRATCH0 522 522 + #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 523 523 + #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 524 524 + //MP1_SMN_EXT_SCRATCH1 525 525 + #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 526 526 + #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 527 527 + //MP1_SMN_EXT_SCRATCH2 528 528 + #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 529 529 + #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 530 530 + //MP1_SMN_EXT_SCRATCH3 531 531 + #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 532 532 + #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 533 533 + //MP1_SMN_EXT_SCRATCH4 534 534 + #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 535 535 + #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 536 536 + //MP1_SMN_EXT_SCRATCH5 537 537 + #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 538 538 + #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 539 539 + //MP1_SMN_EXT_SCRATCH6 540 540 + #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 541 541 + #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 542 542 + //MP1_SMN_EXT_SCRATCH7 543 543 + #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 544 544 + #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 545 545 + //MP1_SMN_EXT_SCRATCH8 546 546 + #define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 547 547 + #define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL 548 548 + //MP1_SMN_EXT_SCRATCH9 549 549 + #define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0 550 550 + #define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL 551 551 + //MP1_SMN_EXT_SCRATCH10 552 552 + #define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 553 553 + #define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL 554 554 + //MP1_SMN_EXT_SCRATCH11 555 555 + #define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 556 556 + #define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL 557 557 + //MP1_SMN_EXT_SCRATCH12 558 558 + #define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 559 559 + #define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL 560 560 + //MP1_SMN_EXT_SCRATCH13 561 561 + #define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 562 562 + #define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL 563 563 + //MP1_SMN_EXT_SCRATCH14 564 564 + #define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 565 565 + #define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL 566 566 + //MP1_SMN_EXT_SCRATCH15 567 567 + #define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 568 568 + #define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL 569 569 + //MP1_SMN_EXT_SCRATCH16 570 570 + #define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 571 571 + #define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL 572 572 + //MP1_SMN_EXT_SCRATCH17 573 573 + #define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 574 574 + #define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL 575 575 + //MP1_SMN_EXT_SCRATCH18 576 576 + #define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 577 577 + #define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL 578 578 + //MP1_SMN_EXT_SCRATCH19 579 579 + #define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 580 580 + #define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL 581 581 + //MP1_SMN_EXT_SCRATCH20 582 582 + #define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 583 583 + #define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL 584 584 + //MP1_SMN_EXT_SCRATCH21 585 585 + #define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 586 586 + #define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL 587 587 + //MP1_SMN_EXT_SCRATCH22 588 588 + #define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 589 589 + #define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL 590 590 + //MP1_SMN_EXT_SCRATCH23 591 591 + #define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 592 592 + #define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL 593 593 + //MP1_SMN_EXT_SCRATCH24 594 594 + #define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 595 595 + #define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL 596 596 + //MP1_SMN_EXT_SCRATCH25 597 597 + #define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 598 598 + #define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL 599 599 + //MP1_SMN_EXT_SCRATCH26 600 600 + #define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 601 601 + #define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL 602 602 + //MP1_SMN_EXT_SCRATCH27 603 603 + #define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 604 604 + #define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL 605 605 + //MP1_SMN_EXT_SCRATCH28 606 606 + #define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 607 607 + #define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL 608 608 + //MP1_SMN_EXT_SCRATCH29 609 609 + #define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 610 610 + #define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL 611 611 + //MP1_SMN_EXT_SCRATCH30 612 612 + #define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 613 613 + #define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL 614 614 + //MP1_SMN_EXT_SCRATCH31 615 615 + #define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 616 616 + #define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL 617 617 + 618 618 + 619 619 + // addressBlock: mp_SmuMp1Pub_CruDec 620 620 + //MP1_CRU1_MP1_FIRMWARE_FLAGS 621 621 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 622 622 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 623 623 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 624 624 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 625 625 + 626 626 + #endif