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dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain

To configure the video PLLs and enable the video GDSCs on SM8450,
SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
with MMCX. Therefore, update the videocc bindings to include
the MXC power domain on these platforms.

Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Jagadeesh Kona and committed by
Bjorn Andersson 1a42f4d4 19272b37

+12 -6
+12 -6
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
··· 32 32 - description: Video AHB clock from GCC 33 33 34 34 power-domains: 35 - maxItems: 1 36 35 description: 37 - MMCX power domain. 36 + Power domains required for the clock controller to operate 37 + items: 38 + - description: MMCX power domain 39 + - description: MXC power domain 38 40 39 41 required-opps: 40 - maxItems: 1 41 42 description: 42 - A phandle to an OPP node describing required MMCX performance point. 43 + OPP nodes that describe required performance points on power domains 44 + items: 45 + - description: MMCX performance point 46 + - description: MXC performance point 43 47 44 48 required: 45 49 - compatible ··· 76 72 reg = <0x0aaf0000 0x10000>; 77 73 clocks = <&rpmhcc RPMH_CXO_CLK>, 78 74 <&gcc GCC_VIDEO_AHB_CLK>; 79 - power-domains = <&rpmhpd RPMHPD_MMCX>; 80 - required-opps = <&rpmhpd_opp_low_svs>; 75 + power-domains = <&rpmhpd RPMHPD_MMCX>, 76 + <&rpmhpd RPMHPD_MXC>; 77 + required-opps = <&rpmhpd_opp_low_svs>, 78 + <&rpmhpd_opp_low_svs>; 81 79 #clock-cells = <1>; 82 80 #reset-cells = <1>; 83 81 #power-domain-cells = <1>;