tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings

Add bindings for the MediaTek External Memory Interface Interconnect,
which providers support system bandwidth requirements through Dynamic
Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.

This adds bindings for MediaTek MT8183 and MT8195 SoCs.

Note that this is modeled as a subnode of DVFSRC for multiple reasons:
- Some SoCs have more than one interconnect on the DVFSRC (and two
different kinds of EMI interconnect, and also a SMI interconnect);

- Some boards will want to not enable the interconnect driver because
some of those are not battery powered (so they just keep the knobs
at full thrust from the bootloader and never care scaling busses);

- Some DVFSRC interconnect features may depend on firmware.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240610085735.147134-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Georgi Djakov 1a8009e1 1613e604

+118
+51
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interconnect/mediatek,mt8183-emi.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MediaTek External Memory Interface (EMI) Interconnect 8 + 9 + maintainers: 10 + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 11 + 12 + description: | 13 + EMI interconnect providers support system bandwidth requirements through 14 + Dynamic Voltage Frequency Scaling Resource Collector (DVFSRC) hardware. 15 + The provider is able to communicate with the DVFSRC through Secure Monitor 16 + Call (SMC). 17 + 18 + ICC provider ICC Nodes 19 + ---- ---- 20 + _________ |CPU | |--- |VPU | 21 + _____ | |----- ---- | ---- 22 + | |->| DRAM | ---- | ---- 23 + |DRAM |->|scheduler|----- |GPU | |--- |DISP| 24 + | |->| (EMI) | ---- | ---- 25 + |_____|->|_________|---. ----- | ---- 26 + /|\ `-|MMSYS|--|--- |VDEC| 27 + | ----- | ---- 28 + | | ---- 29 + | change DRAM freq |--- |VENC| 30 + -------- | ---- 31 + SMC --> | DVFSRC | | ---- 32 + -------- |--- |IMG | 33 + | ---- 34 + | ---- 35 + |--- |CAM | 36 + ---- 37 + 38 + properties: 39 + compatible: 40 + enum: 41 + - mediatek,mt8183-emi 42 + - mediatek,mt8195-emi 43 + 44 + '#interconnect-cells': 45 + const: 1 46 + 47 + required: 48 + - compatible 49 + - '#interconnect-cells' 50 + 51 + unevaluatedProperties: false
+23
include/dt-bindings/interconnect/mediatek,mt8183.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + * Copyright (c) 2024 Collabora Ltd. 5 + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H 9 + #define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H 10 + 11 + #define SLAVE_DDR_EMI 0 12 + #define MASTER_MCUSYS 1 13 + #define MASTER_MFG 2 14 + #define MASTER_MMSYS 3 15 + #define MASTER_MM_VPU 4 16 + #define MASTER_MM_DISP 5 17 + #define MASTER_MM_VDEC 6 18 + #define MASTER_MM_VENC 7 19 + #define MASTER_MM_CAM 8 20 + #define MASTER_MM_IMG 9 21 + #define MASTER_MM_MDP 10 22 + 23 + #endif
+44
include/dt-bindings/interconnect/mediatek,mt8195.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2020 MediaTek Inc. 4 + * Copyright (c) 2024 Collabora Ltd. 5 + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H 9 + #define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H 10 + 11 + #define SLAVE_DDR_EMI 0 12 + #define MASTER_MCUSYS 1 13 + #define MASTER_GPUSYS 2 14 + #define MASTER_MMSYS 3 15 + #define MASTER_MM_VPU 4 16 + #define MASTER_MM_DISP 5 17 + #define MASTER_MM_VDEC 6 18 + #define MASTER_MM_VENC 7 19 + #define MASTER_MM_CAM 8 20 + #define MASTER_MM_IMG 9 21 + #define MASTER_MM_MDP 10 22 + #define MASTER_VPUSYS 11 23 + #define MASTER_VPU_0 12 24 + #define MASTER_VPU_1 13 25 + #define MASTER_MDLASYS 14 26 + #define MASTER_MDLA_0 15 27 + #define MASTER_UFS 16 28 + #define MASTER_PCIE_0 17 29 + #define MASTER_PCIE_1 18 30 + #define MASTER_USB 19 31 + #define MASTER_DBGIF 20 32 + #define SLAVE_HRT_DDR_EMI 21 33 + #define MASTER_HRT_MMSYS 22 34 + #define MASTER_HRT_MM_DISP 23 35 + #define MASTER_HRT_MM_VDEC 24 36 + #define MASTER_HRT_MM_VENC 25 37 + #define MASTER_HRT_MM_CAM 26 38 + #define MASTER_HRT_MM_IMG 27 39 + #define MASTER_HRT_MM_MDP 28 40 + #define MASTER_HRT_DBGIF 29 41 + #define MASTER_WIFI 30 42 + #define MASTER_BT 31 43 + #define MASTER_NETSYS 32 44 + #endif