Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Remove this driver's HIWORD_UPDATE macro, and replace instances of it
with either FIELD_PREP_WM16 or FIELD_PREP_WM16_CONST, depending on
whether they're in an initializer. This gives us better error checking,
which already saved me some trouble during this refactor.
The driver's HIWORD_UPDATE macro doesn't shift up the value, but expects
a pre-shifted value. Meanwhile, FIELD_PREP_WM16 and
FIELD_PREP_WM16_CONST will shift the value for us, based on the given
mask. So a few things that used to be a HIWORD_UPDATE(VERY_LONG_FOO,
VERY_LONG_FOO) are now a somewhat more pleasant
FIELD_PREP_WM16(VERY_LONG_FOO, 1).
There are some non-trivial refactors here. A few literals needed a UL
suffix added to stop them from unintentionally overflowing as a signed
long. To make sure all of these cases are caught, and not just the ones
where the FIELD_PREP_WM16* macros use such a value as a mask, just mark
every literal that's used as a mask as unsigned.
Non-contiguous masks also have to be split into multiple
FIELD_PREP_WM16* instances, as the macro's checks and shifting logic
rely on contiguous masks.
This is compile-tested only.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
authored by
Nicolas Frattaroli
and committed by
Yury Norov
1a99efa3
48d47732
+68
-74
+68
-74
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+68
-74
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
···
7
7
*/
8
8
9
9
#include <linux/clk.h>
10
+
#include <linux/hw_bitfield.h>
10
11
#include <linux/iopoll.h>
11
12
#include <linux/math64.h>
12
13
#include <linux/mfd/syscon.h>
···
149
148
#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
150
149
151
150
#define PX30_GRF_PD_VO_CON1 0x0438
152
-
#define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
151
+
#define PX30_DSI_FORCETXSTOPMODE (0xfUL << 7)
153
152
#define PX30_DSI_FORCERXMODE BIT(6)
154
153
#define PX30_DSI_TURNDISABLE BIT(5)
155
154
#define PX30_DSI_LCDC_SEL BIT(0)
···
168
167
#define RK3399_DSI1_LCDC_SEL BIT(4)
169
168
170
169
#define RK3399_GRF_SOC_CON22 0x6258
171
-
#define RK3399_DSI0_TURNREQUEST (0xf << 12)
172
-
#define RK3399_DSI0_TURNDISABLE (0xf << 8)
173
-
#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
174
-
#define RK3399_DSI0_FORCERXMODE (0xf << 0)
170
+
#define RK3399_DSI0_TURNREQUEST (0xfUL << 12)
171
+
#define RK3399_DSI0_TURNDISABLE (0xfUL << 8)
172
+
#define RK3399_DSI0_FORCETXSTOPMODE (0xfUL << 4)
173
+
#define RK3399_DSI0_FORCERXMODE (0xfUL << 0)
175
174
176
175
#define RK3399_GRF_SOC_CON23 0x625c
177
-
#define RK3399_DSI1_TURNDISABLE (0xf << 12)
178
-
#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
179
-
#define RK3399_DSI1_FORCERXMODE (0xf << 4)
180
-
#define RK3399_DSI1_ENABLE (0xf << 0)
176
+
#define RK3399_DSI1_TURNDISABLE (0xfUL << 12)
177
+
#define RK3399_DSI1_FORCETXSTOPMODE (0xfUL << 8)
178
+
#define RK3399_DSI1_FORCERXMODE (0xfUL << 4)
179
+
#define RK3399_DSI1_ENABLE (0xfUL << 0)
181
180
182
181
#define RK3399_GRF_SOC_CON24 0x6260
183
182
#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
···
187
186
#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0)
188
187
189
188
#define RK3568_GRF_VO_CON2 0x0368
190
-
#define RK3568_DSI0_SKEWCALHS (0x1f << 11)
191
-
#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4)
189
+
#define RK3568_DSI0_SKEWCALHS (0x1fUL << 11)
190
+
#define RK3568_DSI0_FORCETXSTOPMODE (0xfUL << 4)
192
191
#define RK3568_DSI0_TURNDISABLE BIT(2)
193
192
#define RK3568_DSI0_FORCERXMODE BIT(0)
194
193
···
198
197
* come from. Name GRF_VO_CON3 is assumed.
199
198
*/
200
199
#define RK3568_GRF_VO_CON3 0x36c
201
-
#define RK3568_DSI1_SKEWCALHS (0x1f << 11)
202
-
#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4)
200
+
#define RK3568_DSI1_SKEWCALHS (0x1fUL << 11)
201
+
#define RK3568_DSI1_FORCETXSTOPMODE (0xfUL << 4)
203
202
#define RK3568_DSI1_TURNDISABLE BIT(2)
204
203
#define RK3568_DSI1_FORCERXMODE BIT(0)
205
204
206
205
#define RV1126_GRF_DSIPHY_CON 0x10220
207
-
#define RV1126_DSI_FORCETXSTOPMODE (0xf << 4)
206
+
#define RV1126_DSI_FORCETXSTOPMODE (0xfUL << 4)
208
207
#define RV1126_DSI_TURNDISABLE BIT(2)
209
208
#define RV1126_DSI_FORCERXMODE BIT(0)
210
-
211
-
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
212
209
213
210
enum {
214
211
DW_DSI_USAGE_IDLE,
···
1483
1484
{
1484
1485
.reg = 0xff450000,
1485
1486
.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1486
-
.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1487
-
.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1488
-
PX30_DSI_LCDC_SEL),
1487
+
.lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0),
1488
+
.lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1),
1489
1489
1490
1490
.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1491
-
.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1492
-
PX30_DSI_FORCERXMODE |
1493
-
PX30_DSI_FORCETXSTOPMODE),
1491
+
.lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE |
1492
+
PX30_DSI_FORCERXMODE |
1493
+
PX30_DSI_FORCETXSTOPMODE), 0),
1494
1494
1495
1495
.max_data_lanes = 4,
1496
1496
},
···
1500
1502
{
1501
1503
.reg = 0x10110000,
1502
1504
.lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
1503
-
.lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
1504
-
RK3128_DSI_FORCERXMODE |
1505
-
RK3128_DSI_FORCETXSTOPMODE),
1505
+
.lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE |
1506
+
RK3128_DSI_FORCERXMODE |
1507
+
RK3128_DSI_FORCETXSTOPMODE), 0),
1506
1508
.max_data_lanes = 4,
1507
1509
},
1508
1510
{ /* sentinel */ }
···
1512
1514
{
1513
1515
.reg = 0xff960000,
1514
1516
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1515
-
.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1516
-
.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1517
+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0),
1518
+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1),
1517
1519
1518
1520
.max_data_lanes = 4,
1519
1521
},
1520
1522
{
1521
1523
.reg = 0xff964000,
1522
1524
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1523
-
.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1524
-
.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1525
+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0),
1526
+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1),
1525
1527
1526
1528
.max_data_lanes = 4,
1527
1529
},
···
1537
1539
* Assume ISP0 is supplied by the RX0 dphy.
1538
1540
*/
1539
1541
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1540
-
HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1542
+
FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0));
1541
1543
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1542
-
HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1544
+
FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
1543
1545
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1544
-
HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1546
+
FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0));
1545
1547
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1546
-
HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1548
+
FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
1547
1549
1548
1550
return 0;
1549
1551
}
···
1557
1559
usleep_range(100, 150);
1558
1560
1559
1561
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1560
-
HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1562
+
FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
1561
1563
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1562
-
HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1564
+
FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1));
1563
1565
1564
1566
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1565
-
HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1567
+
FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0));
1566
1568
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1567
-
HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1569
+
FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0));
1568
1570
1569
1571
/* Disable lane turn around, which is ignored in receive mode */
1570
1572
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1571
-
HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1573
+
FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0));
1572
1574
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1573
-
HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1574
-
RK3399_DSI1_TURNDISABLE));
1575
+
FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf));
1575
1576
usleep_range(100, 150);
1576
1577
1577
1578
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
···
1578
1581
1579
1582
/* Enable dphy lanes */
1580
1583
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1581
-
HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1582
-
RK3399_DSI1_ENABLE));
1584
+
FIELD_PREP_WM16(RK3399_DSI1_ENABLE,
1585
+
GENMASK(dsi->dphy_config.lanes - 1, 0)));
1583
1586
1584
1587
usleep_range(100, 150);
1585
1588
···
1591
1594
struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1592
1595
1593
1596
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1594
-
HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1597
+
FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
1595
1598
1596
1599
return 0;
1597
1600
}
···
1600
1603
{
1601
1604
.reg = 0xff960000,
1602
1605
.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1603
-
.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1604
-
.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1605
-
RK3399_DSI0_LCDC_SEL),
1606
+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0),
1607
+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1),
1606
1608
1607
1609
.lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1608
-
.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1609
-
RK3399_DSI0_TURNDISABLE |
1610
-
RK3399_DSI0_FORCETXSTOPMODE |
1611
-
RK3399_DSI0_FORCERXMODE),
1610
+
.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST |
1611
+
RK3399_DSI0_TURNDISABLE |
1612
+
RK3399_DSI0_FORCETXSTOPMODE |
1613
+
RK3399_DSI0_FORCERXMODE), 0),
1612
1614
1613
1615
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1614
1616
.max_data_lanes = 4,
···
1615
1619
{
1616
1620
.reg = 0xff968000,
1617
1621
.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1618
-
.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1619
-
.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1620
-
RK3399_DSI1_LCDC_SEL),
1622
+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0),
1623
+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1),
1624
+
1621
1625
1622
1626
.lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1623
-
.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1624
-
RK3399_DSI1_FORCETXSTOPMODE |
1625
-
RK3399_DSI1_FORCERXMODE |
1626
-
RK3399_DSI1_ENABLE),
1627
+
.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE |
1628
+
RK3399_DSI1_FORCETXSTOPMODE |
1629
+
RK3399_DSI1_FORCERXMODE |
1630
+
RK3399_DSI1_ENABLE), 0),
1627
1631
1628
1632
.lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1629
-
.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1630
-
RK3399_TXRX_ENABLECLK,
1631
-
RK3399_TXRX_MASTERSLAVEZ |
1632
-
RK3399_TXRX_ENABLECLK |
1633
-
RK3399_TXRX_BASEDIR),
1633
+
.lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) |
1634
+
FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) |
1635
+
FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)),
1634
1636
1635
1637
.enable_grf_reg = RK3399_GRF_SOC_CON23,
1636
-
.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1638
+
.enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1637
1639
1638
1640
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1639
1641
.max_data_lanes = 4,
···
1647
1653
{
1648
1654
.reg = 0xfe060000,
1649
1655
.lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
1650
-
.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
1651
-
RK3568_DSI0_FORCETXSTOPMODE |
1652
-
RK3568_DSI0_TURNDISABLE |
1653
-
RK3568_DSI0_FORCERXMODE),
1656
+
.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) |
1657
+
FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) |
1658
+
FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) |
1659
+
FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)),
1654
1660
.max_data_lanes = 4,
1655
1661
},
1656
1662
{
1657
1663
.reg = 0xfe070000,
1658
1664
.lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
1659
-
.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
1660
-
RK3568_DSI1_FORCETXSTOPMODE |
1661
-
RK3568_DSI1_TURNDISABLE |
1662
-
RK3568_DSI1_FORCERXMODE),
1665
+
.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) |
1666
+
FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) |
1667
+
FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) |
1668
+
FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)),
1663
1669
.max_data_lanes = 4,
1664
1670
},
1665
1671
{ /* sentinel */ }
···
1669
1675
{
1670
1676
.reg = 0xffb30000,
1671
1677
.lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,
1672
-
.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |
1673
-
RV1126_DSI_FORCERXMODE |
1674
-
RV1126_DSI_FORCETXSTOPMODE),
1678
+
.lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) |
1679
+
FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) |
1680
+
FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)),
1675
1681
.max_data_lanes = 4,
1676
1682
},
1677
1683
{ /* sentinel */ }