tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

crypto: caam - optimize RNG sample size

TRNG "sample size" (the total number of entropy samples that will be taken
during entropy generation) default / POR value is very conservatively
set to 2500.

Let's set it to 512, the same as the caam driver in U-boot
(drivers/crypto/fsl_caam.c) does.

This solves the issue of RNG performance dropping after a suspend/resume
cycle on parts where caam loses power, since the initial U-boot setttings
are lost and kernel does not restore them when resuming.

Note: when changing the sample size, the self-test parameters need to be
updated accordingly.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Meenakshi Aggarwal and committed by
Herbert Xu 1abc8966 2be0d806

+43 -21
+31 -19
drivers/crypto/caam/ctrl.c
··· 358 358 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); 359 359 struct caam_ctrl __iomem *ctrl; 360 360 struct rng4tst __iomem *r4tst; 361 - u32 val; 361 + u32 val, rtsdctl; 362 362 363 363 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 364 364 r4tst = &ctrl->r4tst[0]; ··· 374 374 * Performance-wise, it does not make sense to 375 375 * set the delay to a value that is lower 376 376 * than the last one that worked (i.e. the state handles 377 - * were instantiated properly. Thus, instead of wasting 378 - * time trying to set the values controlling the sample 379 - * frequency, the function simply returns. 377 + * were instantiated properly). 380 378 */ 381 - val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) 382 - >> RTSDCTL_ENT_DLY_SHIFT; 383 - if (ent_delay <= val) 384 - goto start_rng; 379 + rtsdctl = rd_reg32(&r4tst->rtsdctl); 380 + val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT; 381 + if (ent_delay > val) { 382 + val = ent_delay; 383 + /* min. freq. count, equal to 1/4 of the entropy sample length */ 384 + wr_reg32(&r4tst->rtfrqmin, val >> 2); 385 + /* max. freq. count, equal to 16 times the entropy sample length */ 386 + wr_reg32(&r4tst->rtfrqmax, val << 4); 387 + } 385 388 386 - val = rd_reg32(&r4tst->rtsdctl); 387 - val = (val & ~RTSDCTL_ENT_DLY_MASK) | 388 - (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 389 - wr_reg32(&r4tst->rtsdctl, val); 390 - /* min. freq. count, equal to 1/4 of the entropy sample length */ 391 - wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); 392 - /* max. freq. count, equal to 16 times the entropy sample length */ 393 - wr_reg32(&r4tst->rtfrqmax, ent_delay << 4); 394 - /* read the control register */ 395 - val = rd_reg32(&r4tst->rtmctl); 396 - start_rng: 389 + wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) | 390 + RTSDCTL_SAMP_SIZE_VAL); 391 + 392 + /* 393 + * To avoid reprogramming the self-test parameters over and over again, 394 + * use RTSDCTL[SAMP_SIZE] as an indicator. 395 + */ 396 + if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) { 397 + wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32); 398 + wr_reg32(&r4tst->rtpkrrng, 570); 399 + wr_reg32(&r4tst->rtpkrmax, 1600); 400 + wr_reg32(&r4tst->rtscml, (122 << 16) | 317); 401 + wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107); 402 + wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62); 403 + wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39); 404 + wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26); 405 + wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18); 406 + wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17); 407 + } 408 + 397 409 /* 398 410 * select raw sampling in both entropy shifter 399 411 * and statistical checker; ; put RNG4 into run mode
+12 -2
drivers/crypto/caam/regs.h
··· 3 3 * CAAM hardware register-level view 4 4 * 5 5 * Copyright 2008-2011 Freescale Semiconductor, Inc. 6 - * Copyright 2018 NXP 6 + * Copyright 2018, 2023 NXP 7 7 */ 8 8 9 9 #ifndef REGS_H ··· 523 523 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 524 524 #define RTSDCTL_ENT_DLY_MIN 3200 525 525 #define RTSDCTL_ENT_DLY_MAX 12800 526 + #define RTSDCTL_SAMP_SIZE_MASK 0xffff 527 + #define RTSDCTL_SAMP_SIZE_VAL 512 526 528 u32 rtsdctl; /* seed control register */ 527 529 union { 528 530 u32 rtsblim; /* PRGM=1: sparse bit limit register */ ··· 536 534 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 537 535 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 538 536 }; 539 - u32 rsvd1[40]; 537 + union { 538 + u32 rtscmc; /* statistical check run monobit count */ 539 + u32 rtscml; /* statistical check run monobit limit */ 540 + }; 541 + union { 542 + u32 rtscrc[6]; /* statistical check run length count */ 543 + u32 rtscrl[6]; /* statistical check run length limit */ 544 + }; 545 + u32 rsvd1[33]; 540 546 #define RDSTA_SKVT 0x80000000 541 547 #define RDSTA_SKVN 0x40000000 542 548 #define RDSTA_PR0 BIT(4)