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drm/msm/dpu: Set vsync source irrespective of mdp top support

Since DPU 5.x the vsync source TE setup is split between MDP TOP and
INTF blocks. Currently all code to setup vsync_source is only executed
if MDP TOP implements the setup_vsync_source() callback. However on
DPU >= 8.x this callback is not implemented, making DPU driver skip all
vsync setup. Move the INTF part out of this condition, letting DPU
driver to setup TE vsync selection on all new DPU devices.

Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Fixes: 2f69e5458447 ("drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450")
[DB: restored top->ops.setup_vsync_source call]
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696584/
Link: https://lore.kernel.org/r/20251230-intf-fix-wd-v6-1-98203d150611@oss.qualcomm.com

authored by

Teguh Sobirin and committed by
Dmitry Baryshkov 1ad9880f 2892de3f

+8 -8
+8 -8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
··· 785 785 return; 786 786 } 787 787 788 + vsync_cfg.vsync_source = disp_info->vsync_source; 789 + 788 790 if (hw_mdptop->ops.setup_vsync_source) { 789 791 for (i = 0; i < dpu_enc->num_phys_encs; i++) 790 792 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; ··· 794 792 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 795 793 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 796 794 797 - vsync_cfg.vsync_source = disp_info->vsync_source; 798 - 799 795 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 796 + } 800 797 801 - for (i = 0; i < dpu_enc->num_phys_encs; i++) { 802 - phys_enc = dpu_enc->phys_encs[i]; 798 + for (i = 0; i < dpu_enc->num_phys_encs; i++) { 799 + phys_enc = dpu_enc->phys_encs[i]; 803 800 804 - if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 805 - phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 806 - vsync_cfg.vsync_source); 807 - } 801 + if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 802 + phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 803 + vsync_cfg.vsync_source); 808 804 } 809 805 } 810 806