drm/amdgpu: Register aqua vanjaram jpeg poison irq

+83

2 changed files

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drivers

gpu

drm

amd

amdgpu

jpeg_v4_0_3.c

jpeg_v4_0_3.h

+76

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

··· 149 149 return r; 150 150 } 151 151 152 + /* JPEG DJPEG POISON EVENT */ 153 + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 154 + VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 155 + if (r) 156 + return r; 157 + 158 + /* JPEG EJPEG POISON EVENT */ 159 + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 160 + VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 161 + if (r) 162 + return r; 163 + 152 164 r = amdgpu_jpeg_sw_init(adev); 153 165 if (r) 154 166 return r; ··· 445 433 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 446 434 ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 447 435 } 436 + 437 + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 438 + amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 448 439 449 440 return ret; 450 441 } ··· 1056 1041 return 0; 1057 1042 } 1058 1043 1044 + static int jpeg_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1045 + struct amdgpu_irq_src *source, 1046 + unsigned int type, 1047 + enum amdgpu_interrupt_state state) 1048 + { 1049 + return 0; 1050 + } 1051 + 1059 1052 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1060 1053 struct amdgpu_irq_src *source, 1061 1054 struct amdgpu_iv_entry *entry) ··· 1223 1200 .process = jpeg_v4_0_3_process_interrupt, 1224 1201 }; 1225 1202 1203 + static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_ras_irq_funcs = { 1204 + .set = jpeg_v4_0_3_set_ras_interrupt_state, 1205 + .process = amdgpu_jpeg_process_poison_irq, 1206 + }; 1207 + 1226 1208 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1227 1209 { 1228 1210 int i; ··· 1236 1208 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1237 1209 } 1238 1210 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1211 + 1212 + adev->jpeg.inst->ras_poison_irq.num_types = 1; 1213 + adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs; 1239 1214 } 1240 1215 1241 1216 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { ··· 1335 1304 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1336 1305 } 1337 1306 1307 + static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1308 + uint32_t instance, uint32_t sub_block) 1309 + { 1310 + uint32_t poison_stat = 0, reg_value = 0; 1311 + 1312 + switch (sub_block) { 1313 + case AMDGPU_JPEG_V4_0_3_JPEG0: 1314 + reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 1315 + poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 1316 + break; 1317 + case AMDGPU_JPEG_V4_0_3_JPEG1: 1318 + reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 1319 + poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 1320 + break; 1321 + default: 1322 + break; 1323 + } 1324 + 1325 + if (poison_stat) 1326 + dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 1327 + instance, sub_block); 1328 + 1329 + return poison_stat; 1330 + } 1331 + 1332 + static bool jpeg_v4_0_3_query_ras_poison_status(struct amdgpu_device *adev) 1333 + { 1334 + uint32_t inst = 0, sub = 0, poison_stat = 0; 1335 + 1336 + for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 1337 + for (sub = 0; sub < AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK; sub++) 1338 + poison_stat += 1339 + jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub); 1340 + 1341 + return !!poison_stat; 1342 + } 1343 + 1338 1344 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1339 1345 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1340 1346 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1347 + .query_poison_status = jpeg_v4_0_3_query_ras_poison_status, 1341 1348 }; 1342 1349 1343 1350 static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, ··· 1451 1382 r = amdgpu_ras_block_late_init(adev, ras_block); 1452 1383 if (r) 1453 1384 return r; 1385 + 1386 + if (amdgpu_ras_is_supported(adev, ras_block->block) && 1387 + adev->jpeg.inst->ras_poison_irq.funcs) { 1388 + r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0); 1389 + if (r) 1390 + goto late_fini; 1391 + } 1454 1392 1455 1393 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, 1456 1394 &jpeg_v4_0_3_aca_info, NULL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h

··· 46 46 47 47 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 48 48 49 + enum amdgpu_jpeg_v4_0_3_sub_block { 50 + AMDGPU_JPEG_V4_0_3_JPEG0 = 0, 51 + AMDGPU_JPEG_V4_0_3_JPEG1, 52 + 53 + AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK, 54 + }; 55 + 49 56 extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block; 50 57 51 58 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,

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