Merge branch 'net-hns3-some-code-optimizations-bugfixes'

+3 -1

drivers/net/ethernet/hisilicon/hns3/hnae3.h

··· 213 213 const struct hnae3_ae_ops *ops; 214 214 struct list_head node; 215 215 u32 flag; 216 - u8 override_pci_need_reset; /* fix to stop multiple reset happening */ 217 216 unsigned long hw_err_reset_req; 218 217 enum hnae3_reset_type reset_type; 219 218 void *priv; ··· 263 264 * get auto autonegotiation of pause frame use 264 265 * restart_autoneg() 265 266 * restart autonegotiation 267 + * halt_autoneg() 268 + * halt/resume autonegotiation when autonegotiation on 266 269 * get_coalesce_usecs() 267 270 * get usecs to delay a TX interrupt after a packet is sent 268 271 * get_rx_max_coalesced_frames() ··· 384 383 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 385 384 int (*get_autoneg)(struct hnae3_handle *handle); 386 385 int (*restart_autoneg)(struct hnae3_handle *handle); 386 + int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 387 387 388 388 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 389 389 u32 *tx_usecs, u32 *rx_usecs);

+1 -1

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

··· 1950 1950 ops = ae_dev->ops; 1951 1951 /* request the reset */ 1952 1952 if (ops->reset_event) { 1953 - if (!ae_dev->override_pci_need_reset) { 1953 + if (ae_dev->hw_err_reset_req) { 1954 1954 reset_type = ops->get_reset_level(ae_dev, 1955 1955 &ae_dev->hw_err_reset_req); 1956 1956 ops->set_default_reset_request(ae_dev, reset_type);

+10

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

··· 336 336 h->ae_algo->ops->enable_vlan_filter(h, false); 337 337 #endif 338 338 339 + /* Tell firmware to stop mac autoneg before loopback test start, 340 + * otherwise loopback test may be failed when the port is still 341 + * negotiating. 342 + */ 343 + if (h->ae_algo->ops->halt_autoneg) 344 + h->ae_algo->ops->halt_autoneg(h, true); 345 + 339 346 set_bit(HNS3_NIC_STATE_TESTING, &priv->state); 340 347 341 348 for (i = 0; i < HNS3_SELF_TEST_TYPE_NUM; i++) { ··· 364 357 } 365 358 366 359 clear_bit(HNS3_NIC_STATE_TESTING, &priv->state); 360 + 361 + if (h->ae_algo->ops->halt_autoneg) 362 + h->ae_algo->ops->halt_autoneg(h, false); 367 363 368 364 #if IS_ENABLED(CONFIG_VLAN_8021Q) 369 365 if (dis_vlan_filter)

+72 -53

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

··· 1060 1060 return ret; 1061 1061 } 1062 1062 1063 + /* hclge_query_bd_num: query number of buffer descriptors 1064 + * @hdev: pointer to struct hclge_dev 1065 + * @is_ras: true for ras, false for msix 1066 + * @mpf_bd_num: number of main PF interrupt buffer descriptors 1067 + * @pf_bd_num: number of not main PF interrupt buffer descriptors 1068 + * 1069 + * This function querys number of mpf and pf buffer descriptors. 1070 + */ 1071 + static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras, 1072 + int *mpf_bd_num, int *pf_bd_num) 1073 + { 1074 + struct device *dev = &hdev->pdev->dev; 1075 + u32 mpf_min_bd_num, pf_min_bd_num; 1076 + enum hclge_opcode_type opcode; 1077 + struct hclge_desc desc_bd; 1078 + int ret; 1079 + 1080 + if (is_ras) { 1081 + opcode = HCLGE_QUERY_RAS_INT_STS_BD_NUM; 1082 + mpf_min_bd_num = HCLGE_MPF_RAS_INT_MIN_BD_NUM; 1083 + pf_min_bd_num = HCLGE_PF_RAS_INT_MIN_BD_NUM; 1084 + } else { 1085 + opcode = HCLGE_QUERY_MSIX_INT_STS_BD_NUM; 1086 + mpf_min_bd_num = HCLGE_MPF_MSIX_INT_MIN_BD_NUM; 1087 + pf_min_bd_num = HCLGE_PF_MSIX_INT_MIN_BD_NUM; 1088 + } 1089 + 1090 + hclge_cmd_setup_basic_desc(&desc_bd, opcode, true); 1091 + ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1); 1092 + if (ret) { 1093 + dev_err(dev, "fail(%d) to query msix int status bd num\n", 1094 + ret); 1095 + return ret; 1096 + } 1097 + 1098 + *mpf_bd_num = le32_to_cpu(desc_bd.data[0]); 1099 + *pf_bd_num = le32_to_cpu(desc_bd.data[1]); 1100 + if (*mpf_bd_num < mpf_min_bd_num || *pf_bd_num < pf_min_bd_num) { 1101 + dev_err(dev, "Invalid bd num: mpf(%d), pf(%d)\n", 1102 + *mpf_bd_num, *pf_bd_num); 1103 + return -EINVAL; 1104 + } 1105 + 1106 + return 0; 1107 + } 1108 + 1063 1109 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors 1064 1110 * @hdev: pointer to struct hclge_dev 1065 1111 * @desc: descriptor for describing the command ··· 1337 1291 1338 1292 static int hclge_handle_all_ras_errors(struct hclge_dev *hdev) 1339 1293 { 1340 - struct device *dev = &hdev->pdev->dev; 1341 1294 u32 mpf_bd_num, pf_bd_num, bd_num; 1342 - struct hclge_desc desc_bd; 1343 1295 struct hclge_desc *desc; 1344 1296 int ret; 1345 1297 1346 1298 /* query the number of registers in the RAS int status */ 1347 - hclge_cmd_setup_basic_desc(&desc_bd, HCLGE_QUERY_RAS_INT_STS_BD_NUM, 1348 - true); 1349 - ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1); 1350 - if (ret) { 1351 - dev_err(dev, "fail(%d) to query ras int status bd num\n", ret); 1299 + ret = hclge_query_bd_num(hdev, true, &mpf_bd_num, &pf_bd_num); 1300 + if (ret) 1352 1301 return ret; 1353 - } 1354 - mpf_bd_num = le32_to_cpu(desc_bd.data[0]); 1355 - pf_bd_num = le32_to_cpu(desc_bd.data[1]); 1356 - bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1357 1302 1303 + bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1358 1304 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1359 1305 if (!desc) 1360 1306 return -ENOMEM; ··· 1644 1606 if (status & HCLGE_RAS_REG_NFE_MASK || 1645 1607 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) 1646 1608 ae_dev->hw_err_reset_req = 0; 1609 + else 1610 + goto out; 1647 1611 1648 1612 /* Handling Non-fatal HNS RAS errors */ 1649 1613 if (status & HCLGE_RAS_REG_NFE_MASK) { ··· 1653 1613 "HNS Non-Fatal RAS error(status=0x%x) identified\n", 1654 1614 status); 1655 1615 hclge_handle_all_ras_errors(hdev); 1656 - } else { 1657 - if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 1658 - hdev->pdev->revision < 0x21) { 1659 - ae_dev->override_pci_need_reset = 1; 1660 - return PCI_ERS_RESULT_RECOVERED; 1661 - } 1662 1616 } 1663 1617 1664 - if (status & HCLGE_RAS_REG_ROCEE_ERR_MASK) { 1665 - dev_warn(dev, "ROCEE uncorrected RAS error identified\n"); 1618 + /* Handling Non-fatal Rocee RAS errors */ 1619 + if (hdev->pdev->revision >= 0x21 && 1620 + status & HCLGE_RAS_REG_ROCEE_ERR_MASK) { 1621 + dev_warn(dev, "ROCEE Non-Fatal RAS error identified\n"); 1666 1622 hclge_handle_rocee_ras_error(ae_dev); 1667 1623 } 1668 1624 1669 - if ((status & HCLGE_RAS_REG_NFE_MASK || 1670 - status & HCLGE_RAS_REG_ROCEE_ERR_MASK) && 1671 - ae_dev->hw_err_reset_req) { 1672 - ae_dev->override_pci_need_reset = 0; 1673 - return PCI_ERS_RESULT_NEED_RESET; 1674 - } 1675 - ae_dev->override_pci_need_reset = 1; 1625 + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 1626 + goto out; 1676 1627 1628 + if (ae_dev->hw_err_reset_req) 1629 + return PCI_ERS_RESULT_NEED_RESET; 1630 + 1631 + out: 1677 1632 return PCI_ERS_RESULT_RECOVERED; 1678 1633 } 1679 1634 ··· 1882 1847 struct hclge_mac_tnl_stats mac_tnl_stats; 1883 1848 struct device *dev = &hdev->pdev->dev; 1884 1849 u32 mpf_bd_num, pf_bd_num, bd_num; 1885 - struct hclge_desc desc_bd; 1886 1850 struct hclge_desc *desc; 1887 1851 u32 status; 1888 1852 int ret; 1889 1853 1890 1854 /* query the number of bds for the MSIx int status */ 1891 - hclge_cmd_setup_basic_desc(&desc_bd, HCLGE_QUERY_MSIX_INT_STS_BD_NUM, 1892 - true); 1893 - ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1); 1894 - if (ret) { 1895 - dev_err(dev, "fail(%d) to query msix int status bd num\n", 1896 - ret); 1897 - return ret; 1898 - } 1899 - 1900 - mpf_bd_num = le32_to_cpu(desc_bd.data[0]); 1901 - pf_bd_num = le32_to_cpu(desc_bd.data[1]); 1902 - bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1903 - 1904 - desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1905 - if (!desc) 1855 + ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num); 1856 + if (ret) 1906 1857 goto out; 1858 + 1859 + bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1860 + desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1861 + if (!desc) { 1862 + ret = -ENOMEM; 1863 + goto out; 1864 + } 1907 1865 1908 1866 ret = hclge_handle_mpf_msix_error(hdev, desc, mpf_bd_num, 1909 1867 reset_requests); ··· 1959 1931 struct hclge_dev *hdev = ae_dev->priv; 1960 1932 struct device *dev = &hdev->pdev->dev; 1961 1933 u32 mpf_bd_num, pf_bd_num, bd_num; 1962 - struct hclge_desc desc_bd; 1963 1934 struct hclge_desc *desc; 1964 1935 u32 status; 1965 1936 int ret; ··· 1967 1940 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG); 1968 1941 1969 1942 /* query the number of bds for the MSIx int status */ 1970 - hclge_cmd_setup_basic_desc(&desc_bd, HCLGE_QUERY_MSIX_INT_STS_BD_NUM, 1971 - true); 1972 - ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1); 1973 - if (ret) { 1974 - dev_err(dev, "fail(%d) to query msix int status bd num\n", 1975 - ret); 1943 + ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num); 1944 + if (ret) 1976 1945 return; 1977 - } 1978 1946 1979 - mpf_bd_num = le32_to_cpu(desc_bd.data[0]); 1980 - pf_bd_num = le32_to_cpu(desc_bd.data[1]); 1981 1947 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1982 - 1983 1948 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1984 1949 if (!desc) 1985 1950 return;

+5

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

··· 6 6 7 7 #include "hclge_main.h" 8 8 9 + #define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10 10 + #define HCLGE_PF_RAS_INT_MIN_BD_NUM 4 11 + #define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 10 12 + #define HCLGE_PF_MSIX_INT_MIN_BD_NUM 4 13 + 9 14 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 10 15 #define HCLGE_RAS_REG_NFE_MASK 0xFF00 11 16 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000

+140 -26

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

··· 35 35 36 36 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 37 37 static int hclge_init_vlan_config(struct hclge_dev *hdev); 38 + static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 38 39 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 39 40 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 40 41 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, ··· 2316 2315 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2317 2316 } 2318 2317 2318 + static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2319 + { 2320 + struct hclge_vport *vport = hclge_get_vport(handle); 2321 + struct hclge_dev *hdev = vport->back; 2322 + 2323 + if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2324 + return hclge_set_autoneg_en(hdev, !halt); 2325 + 2326 + return 0; 2327 + } 2328 + 2319 2329 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2320 2330 { 2321 2331 struct hclge_config_fec_cmd *req; ··· 2398 2386 dev_err(&hdev->pdev->dev, 2399 2387 "Config mac speed dup fail ret=%d\n", ret); 2400 2388 return ret; 2389 + } 2390 + 2391 + if (hdev->hw.mac.support_autoneg) { 2392 + ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2393 + if (ret) { 2394 + dev_err(&hdev->pdev->dev, 2395 + "Config mac autoneg fail ret=%d\n", ret); 2396 + return ret; 2397 + } 2401 2398 } 2402 2399 2403 2400 mac->link = 0; ··· 3549 3528 hclge_update_port_info(hdev); 3550 3529 hclge_update_link_status(hdev); 3551 3530 hclge_update_vport_alive(hdev); 3531 + hclge_sync_vlan_filter(hdev); 3552 3532 if (hdev->fd_arfs_expire_timer >= HCLGE_FD_ARFS_EXPIRE_TIMER_INTERVAL) { 3553 3533 hclge_rfs_filter_expire(hdev); 3554 3534 hdev->fd_arfs_expire_timer = 0; ··· 7123 7101 if (!req0->resp_code) 7124 7102 return 0; 7125 7103 7126 - if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) { 7127 - dev_warn(&hdev->pdev->dev, 7128 - "vlan %d filter is not in vf vlan table\n", 7129 - vlan); 7104 + /* vf vlan filter is disabled when vf vlan table is full, 7105 + * then new vlan id will not be added into vf vlan table. 7106 + * Just return 0 without warning, avoid massive verbose 7107 + * print logs when unload. 7108 + */ 7109 + if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 7130 7110 return 0; 7131 - } 7132 7111 7133 7112 dev_err(&hdev->pdev->dev, 7134 7113 "Kill vf vlan filter fail, ret =%d.\n", ··· 7753 7730 bool writen_to_tbl = false; 7754 7731 int ret = 0; 7755 7732 7756 - /* when port based VLAN enabled, we use port based VLAN as the VLAN 7757 - * filter entry. In this case, we don't update VLAN filter table 7758 - * when user add new VLAN or remove exist VLAN, just update the vport 7759 - * VLAN list. The VLAN id in VLAN list won't be writen in VLAN filter 7760 - * table until port based VLAN disabled 7733 + /* When device is resetting, firmware is unable to handle 7734 + * mailbox. Just record the vlan id, and remove it after 7735 + * reset finished. 7736 + */ 7737 + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && is_kill) { 7738 + set_bit(vlan_id, vport->vlan_del_fail_bmap); 7739 + return -EBUSY; 7740 + } 7741 + 7742 + /* When port base vlan enabled, we use port base vlan as the vlan 7743 + * filter entry. In this case, we don't update vlan filter table 7744 + * when user add new vlan or remove exist vlan, just update the vport 7745 + * vlan list. The vlan id in vlan list will be writen in vlan filter 7746 + * table until port base vlan disabled 7761 7747 */ 7762 7748 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7763 7749 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, ··· 7774 7742 writen_to_tbl = true; 7775 7743 } 7776 7744 7777 - if (ret) 7778 - return ret; 7745 + if (!ret) { 7746 + if (is_kill) 7747 + hclge_rm_vport_vlan_table(vport, vlan_id, false); 7748 + else 7749 + hclge_add_vport_vlan_table(vport, vlan_id, 7750 + writen_to_tbl); 7751 + } else if (is_kill) { 7752 + /* When remove hw vlan filter failed, record the vlan id, 7753 + * and try to remove it from hw later, to be consistence 7754 + * with stack 7755 + */ 7756 + set_bit(vlan_id, vport->vlan_del_fail_bmap); 7757 + } 7758 + return ret; 7759 + } 7779 7760 7780 - if (is_kill) 7781 - hclge_rm_vport_vlan_table(vport, vlan_id, false); 7782 - else 7783 - hclge_add_vport_vlan_table(vport, vlan_id, 7784 - writen_to_tbl); 7761 + static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 7762 + { 7763 + #define HCLGE_MAX_SYNC_COUNT 60 7785 7764 7786 - return 0; 7765 + int i, ret, sync_cnt = 0; 7766 + u16 vlan_id; 7767 + 7768 + /* start from vport 1 for PF is always alive */ 7769 + for (i = 0; i < hdev->num_alloc_vport; i++) { 7770 + struct hclge_vport *vport = &hdev->vport[i]; 7771 + 7772 + vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 7773 + VLAN_N_VID); 7774 + while (vlan_id != VLAN_N_VID) { 7775 + ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7776 + vport->vport_id, vlan_id, 7777 + 0, true); 7778 + if (ret && ret != -EINVAL) 7779 + return; 7780 + 7781 + clear_bit(vlan_id, vport->vlan_del_fail_bmap); 7782 + hclge_rm_vport_vlan_table(vport, vlan_id, false); 7783 + 7784 + sync_cnt++; 7785 + if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 7786 + return; 7787 + 7788 + vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 7789 + VLAN_N_VID); 7790 + } 7791 + } 7787 7792 } 7788 7793 7789 7794 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) ··· 8282 8213 { 8283 8214 struct hnae3_client *client = vport->nic.client; 8284 8215 struct hclge_dev *hdev = ae_dev->priv; 8216 + int rst_cnt; 8285 8217 int ret; 8286 8218 8219 + rst_cnt = hdev->rst_stats.reset_cnt; 8287 8220 ret = client->ops->init_instance(&vport->nic); 8288 8221 if (ret) 8289 8222 return ret; 8290 8223 8291 8224 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8292 - hnae3_set_client_init_flag(client, ae_dev, 1); 8225 + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8226 + rst_cnt != hdev->rst_stats.reset_cnt) { 8227 + ret = -EBUSY; 8228 + goto init_nic_err; 8229 + } 8293 8230 8294 8231 /* Enable nic hw error interrupts */ 8295 8232 ret = hclge_config_nic_hw_error(hdev, true); 8296 - if (ret) 8233 + if (ret) { 8297 8234 dev_err(&ae_dev->pdev->dev, 8298 8235 "fail(%d) to enable hw error interrupts\n", ret); 8236 + goto init_nic_err; 8237 + } 8238 + 8239 + hnae3_set_client_init_flag(client, ae_dev, 1); 8299 8240 8300 8241 if (netif_msg_drv(&hdev->vport->nic)) 8301 8242 hclge_info_show(hdev); 8243 + 8244 + return ret; 8245 + 8246 + init_nic_err: 8247 + clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8248 + while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8249 + msleep(HCLGE_WAIT_RESET_DONE); 8250 + 8251 + client->ops->uninit_instance(&vport->nic, 0); 8302 8252 8303 8253 return ret; 8304 8254 } ··· 8327 8239 { 8328 8240 struct hnae3_client *client = vport->roce.client; 8329 8241 struct hclge_dev *hdev = ae_dev->priv; 8242 + int rst_cnt; 8330 8243 int ret; 8331 8244 8332 8245 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || ··· 8339 8250 if (ret) 8340 8251 return ret; 8341 8252 8253 + rst_cnt = hdev->rst_stats.reset_cnt; 8342 8254 ret = client->ops->init_instance(&vport->roce); 8343 8255 if (ret) 8344 8256 return ret; 8345 8257 8346 8258 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8259 + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8260 + rst_cnt != hdev->rst_stats.reset_cnt) { 8261 + ret = -EBUSY; 8262 + goto init_roce_err; 8263 + } 8264 + 8265 + /* Enable roce ras interrupts */ 8266 + ret = hclge_config_rocee_ras_interrupt(hdev, true); 8267 + if (ret) { 8268 + dev_err(&ae_dev->pdev->dev, 8269 + "fail(%d) to enable roce ras interrupts\n", ret); 8270 + goto init_roce_err; 8271 + } 8272 + 8347 8273 hnae3_set_client_init_flag(client, ae_dev, 1); 8348 8274 8349 8275 return 0; 8276 + 8277 + init_roce_err: 8278 + clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8279 + while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8280 + msleep(HCLGE_WAIT_RESET_DONE); 8281 + 8282 + hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 8283 + 8284 + return ret; 8350 8285 } 8351 8286 8352 8287 static int hclge_init_client_instance(struct hnae3_client *client, ··· 8413 8300 } 8414 8301 } 8415 8302 8416 - /* Enable roce ras interrupts */ 8417 - ret = hclge_config_rocee_ras_interrupt(hdev, true); 8418 - if (ret) 8419 - dev_err(&ae_dev->pdev->dev, 8420 - "fail(%d) to enable roce ras interrupts\n", ret); 8421 - 8422 8303 return ret; 8423 8304 8424 8305 clear_nic: ··· 8436 8329 vport = &hdev->vport[i]; 8437 8330 if (hdev->roce_client) { 8438 8331 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8332 + while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8333 + msleep(HCLGE_WAIT_RESET_DONE); 8334 + 8439 8335 hdev->roce_client->ops->uninit_instance(&vport->roce, 8440 8336 0); 8441 8337 hdev->roce_client = NULL; ··· 8448 8338 return; 8449 8339 if (hdev->nic_client && client->ops->uninit_instance) { 8450 8340 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8341 + while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8342 + msleep(HCLGE_WAIT_RESET_DONE); 8343 + 8451 8344 client->ops->uninit_instance(&vport->nic, 0); 8452 8345 hdev->nic_client = NULL; 8453 8346 vport->nic.client = NULL; ··· 9378 9265 .set_autoneg = hclge_set_autoneg, 9379 9266 .get_autoneg = hclge_get_autoneg, 9380 9267 .restart_autoneg = hclge_restart_autoneg, 9268 + .halt_autoneg = hclge_halt_autoneg, 9381 9269 .get_pauseparam = hclge_get_pauseparam, 9382 9270 .set_pauseparam = hclge_set_pauseparam, 9383 9271 .set_mtu = hclge_set_mtu,

+2

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

··· 700 700 }; 701 701 702 702 #define HCLGE_RESET_INTERVAL (10 * HZ) 703 + #define HCLGE_WAIT_RESET_DONE 100 703 704 704 705 #pragma pack(1) 705 706 struct hclge_vf_vlan_cfg { ··· 930 929 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 931 930 u8 dwrr; 932 931 932 + unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 933 933 struct hclge_port_base_vlan_config port_base_vlan_cfg; 934 934 struct hclge_tx_vtag_cfg txvlan_cfg; 935 935 struct hclge_rx_vtag_cfg rxvlan_cfg;

+47 -3

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

··· 1244 1244 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1245 1245 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1246 1246 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1247 + int ret; 1247 1248 1248 1249 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1249 1250 return -EINVAL; ··· 1252 1251 if (proto != htons(ETH_P_8021Q)) 1253 1252 return -EPROTONOSUPPORT; 1254 1253 1254 + /* When device is resetting, firmware is unable to handle 1255 + * mailbox. Just record the vlan id, and remove it after 1256 + * reset finished. 1257 + */ 1258 + if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1259 + set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1260 + return -EBUSY; 1261 + } 1262 + 1255 1263 msg_data[0] = is_kill; 1256 1264 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1257 1265 memcpy(&msg_data[3], &proto, sizeof(proto)); 1258 - return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1259 - HCLGE_MBX_VLAN_FILTER, msg_data, 1260 - HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1266 + ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1267 + HCLGE_MBX_VLAN_FILTER, msg_data, 1268 + HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1269 + 1270 + /* When remove hw vlan filter failed, record the vlan id, 1271 + * and try to remove it from hw later, to be consistence 1272 + * with stack. 1273 + */ 1274 + if (is_kill && ret) 1275 + set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1276 + 1277 + return ret; 1278 + } 1279 + 1280 + static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1281 + { 1282 + #define HCLGEVF_MAX_SYNC_COUNT 60 1283 + struct hnae3_handle *handle = &hdev->nic; 1284 + int ret, sync_cnt = 0; 1285 + u16 vlan_id; 1286 + 1287 + vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1288 + while (vlan_id != VLAN_N_VID) { 1289 + ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1290 + vlan_id, true); 1291 + if (ret) 1292 + return; 1293 + 1294 + clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1295 + sync_cnt++; 1296 + if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1297 + return; 1298 + 1299 + vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1300 + } 1261 1301 } 1262 1302 1263 1303 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) ··· 1838 1796 hclgevf_request_link_info(hdev); 1839 1797 1840 1798 hclgevf_update_link_mode(hdev); 1799 + 1800 + hclgevf_sync_vlan_filter(hdev); 1841 1801 1842 1802 hclgevf_deferred_task_schedule(hdev); 1843 1803

+3

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h

··· 4 4 #ifndef __HCLGEVF_MAIN_H 5 5 #define __HCLGEVF_MAIN_H 6 6 #include <linux/fs.h> 7 + #include <linux/if_vlan.h> 7 8 #include <linux/types.h> 8 9 #include "hclge_mbx.h" 9 10 #include "hclgevf_cmd.h" ··· 270 269 u32 base_msi_vector; 271 270 u16 *vector_status; 272 271 int *vector_irq; 272 + 273 + unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 273 274 274 275 bool mbx_event_pending; 275 276 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */

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