tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg Kroah-Hartman:
"Here are some small char/misc driver fixes that resolve issues
recently reported against the 3.9-rc kernels. All have been in
linux-next for a while."

* tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
VMCI: Fix process-to-process DRGAMs.
mei: ME hardware reset needs to be synchronized
mei: add mei_stop function to stop mei device
extcon: max77693: Initialize register of MUIC device to bring up it without platform data
extcon: max77693: Fix bug of wrong pointer when platform data is not used
extcon: max8997: Check the pointer of platform data to protect null pointer error

Linus Torvalds 1b6a4db2 dfca53fb

+185 -99
+80 -23
drivers/extcon/extcon-max77693.c
··· 32 32 #define DEV_NAME "max77693-muic" 33 33 #define DELAY_MS_DEFAULT 20000 /* unit: millisecond */ 34 34 35 + /* 36 + * Default value of MAX77693 register to bring up MUIC device. 37 + * If user don't set some initial value for MUIC device through platform data, 38 + * extcon-max77693 driver use 'default_init_data' to bring up base operation 39 + * of MAX77693 MUIC device. 40 + */ 41 + struct max77693_reg_data default_init_data[] = { 42 + { 43 + /* STATUS2 - [3]ChgDetRun */ 44 + .addr = MAX77693_MUIC_REG_STATUS2, 45 + .data = STATUS2_CHGDETRUN_MASK, 46 + }, { 47 + /* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */ 48 + .addr = MAX77693_MUIC_REG_INTMASK1, 49 + .data = INTMASK1_ADC1K_MASK 50 + | INTMASK1_ADC_MASK, 51 + }, { 52 + /* INTMASK2 - Unmask [0]ChgTypM */ 53 + .addr = MAX77693_MUIC_REG_INTMASK2, 54 + .data = INTMASK2_CHGTYP_MASK, 55 + }, { 56 + /* INTMASK3 - Mask all of interrupts */ 57 + .addr = MAX77693_MUIC_REG_INTMASK3, 58 + .data = 0x0, 59 + }, { 60 + /* CDETCTRL2 */ 61 + .addr = MAX77693_MUIC_REG_CDETCTRL2, 62 + .data = CDETCTRL2_VIDRMEN_MASK 63 + | CDETCTRL2_DXOVPEN_MASK, 64 + }, 65 + }; 66 + 35 67 enum max77693_muic_adc_debounce_time { 36 68 ADC_DEBOUNCE_TIME_5MS = 0, 37 69 ADC_DEBOUNCE_TIME_10MS, ··· 1077 1045 { 1078 1046 struct max77693_dev *max77693 = dev_get_drvdata(pdev->dev.parent); 1079 1047 struct max77693_platform_data *pdata = dev_get_platdata(max77693->dev); 1080 - struct max77693_muic_platform_data *muic_pdata = pdata->muic_data; 1081 1048 struct max77693_muic_info *info; 1049 + struct max77693_reg_data *init_data; 1050 + int num_init_data; 1082 1051 int delay_jiffies; 1083 1052 int ret; 1084 1053 int i; ··· 1178 1145 goto err_irq; 1179 1146 } 1180 1147 1181 - /* Initialize MUIC register by using platform data */ 1182 - for (i = 0 ; i < muic_pdata->num_init_data ; i++) { 1183 - enum max77693_irq_source irq_src = MAX77693_IRQ_GROUP_NR; 1148 + 1149 + /* Initialize MUIC register by using platform data or default data */ 1150 + if (pdata->muic_data) { 1151 + init_data = pdata->muic_data->init_data; 1152 + num_init_data = pdata->muic_data->num_init_data; 1153 + } else { 1154 + init_data = default_init_data; 1155 + num_init_data = ARRAY_SIZE(default_init_data); 1156 + } 1157 + 1158 + for (i = 0 ; i < num_init_data ; i++) { 1159 + enum max77693_irq_source irq_src 1160 + = MAX77693_IRQ_GROUP_NR; 1184 1161 1185 1162 max77693_write_reg(info->max77693->regmap_muic, 1186 - muic_pdata->init_data[i].addr, 1187 - muic_pdata->init_data[i].data); 1163 + init_data[i].addr, 1164 + init_data[i].data); 1188 1165 1189 - switch (muic_pdata->init_data[i].addr) { 1166 + switch (init_data[i].addr) { 1190 1167 case MAX77693_MUIC_REG_INTMASK1: 1191 1168 irq_src = MUIC_INT1; 1192 1169 break; ··· 1210 1167 1211 1168 if (irq_src < MAX77693_IRQ_GROUP_NR) 1212 1169 info->max77693->irq_masks_cur[irq_src] 1213 - = muic_pdata->init_data[i].data; 1170 + = init_data[i].data; 1214 1171 } 1215 1172 1216 - /* 1217 - * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB 1218 - * h/w path of COMP2/COMN1 on CONTROL1 register. 1219 - */ 1220 - if (muic_pdata->path_uart) 1221 - info->path_uart = muic_pdata->path_uart; 1222 - else 1223 - info->path_uart = CONTROL1_SW_UART; 1173 + if (pdata->muic_data) { 1174 + struct max77693_muic_platform_data *muic_pdata = pdata->muic_data; 1224 1175 1225 - if (muic_pdata->path_usb) 1226 - info->path_usb = muic_pdata->path_usb; 1227 - else 1176 + /* 1177 + * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB 1178 + * h/w path of COMP2/COMN1 on CONTROL1 register. 1179 + */ 1180 + if (muic_pdata->path_uart) 1181 + info->path_uart = muic_pdata->path_uart; 1182 + else 1183 + info->path_uart = CONTROL1_SW_UART; 1184 + 1185 + if (muic_pdata->path_usb) 1186 + info->path_usb = muic_pdata->path_usb; 1187 + else 1188 + info->path_usb = CONTROL1_SW_USB; 1189 + 1190 + /* 1191 + * Default delay time for detecting cable state 1192 + * after certain time. 1193 + */ 1194 + if (muic_pdata->detcable_delay_ms) 1195 + delay_jiffies = 1196 + msecs_to_jiffies(muic_pdata->detcable_delay_ms); 1197 + else 1198 + delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 1199 + } else { 1228 1200 info->path_usb = CONTROL1_SW_USB; 1201 + info->path_uart = CONTROL1_SW_UART; 1202 + delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 1203 + } 1229 1204 1230 1205 /* Set initial path for UART */ 1231 1206 max77693_muic_set_path(info, info->path_uart, true); ··· 1269 1208 * driver should notify cable state to upper layer. 1270 1209 */ 1271 1210 INIT_DELAYED_WORK(&info->wq_detcable, max77693_muic_detect_cable_wq); 1272 - if (muic_pdata->detcable_delay_ms) 1273 - delay_jiffies = msecs_to_jiffies(muic_pdata->detcable_delay_ms); 1274 - else 1275 - delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 1276 1211 schedule_delayed_work(&info->wq_detcable, delay_jiffies); 1277 1212 1278 1213 return ret;
+33 -21
drivers/extcon/extcon-max8997.c
··· 712 712 goto err_irq; 713 713 } 714 714 715 - /* Initialize registers according to platform data */ 716 715 if (pdata->muic_pdata) { 717 - struct max8997_muic_platform_data *mdata = info->muic_pdata; 716 + struct max8997_muic_platform_data *muic_pdata 717 + = pdata->muic_pdata; 718 718 719 - for (i = 0; i < mdata->num_init_data; i++) { 720 - max8997_write_reg(info->muic, mdata->init_data[i].addr, 721 - mdata->init_data[i].data); 719 + /* Initialize registers according to platform data */ 720 + for (i = 0; i < muic_pdata->num_init_data; i++) { 721 + max8997_write_reg(info->muic, 722 + muic_pdata->init_data[i].addr, 723 + muic_pdata->init_data[i].data); 722 724 } 723 - } 724 725 725 - /* 726 - * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB 727 - * h/w path of COMP2/COMN1 on CONTROL1 register. 728 - */ 729 - if (pdata->muic_pdata->path_uart) 730 - info->path_uart = pdata->muic_pdata->path_uart; 731 - else 726 + /* 727 + * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB 728 + * h/w path of COMP2/COMN1 on CONTROL1 register. 729 + */ 730 + if (muic_pdata->path_uart) 731 + info->path_uart = muic_pdata->path_uart; 732 + else 733 + info->path_uart = CONTROL1_SW_UART; 734 + 735 + if (muic_pdata->path_usb) 736 + info->path_usb = muic_pdata->path_usb; 737 + else 738 + info->path_usb = CONTROL1_SW_USB; 739 + 740 + /* 741 + * Default delay time for detecting cable state 742 + * after certain time. 743 + */ 744 + if (muic_pdata->detcable_delay_ms) 745 + delay_jiffies = 746 + msecs_to_jiffies(muic_pdata->detcable_delay_ms); 747 + else 748 + delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 749 + } else { 732 750 info->path_uart = CONTROL1_SW_UART; 733 - 734 - if (pdata->muic_pdata->path_usb) 735 - info->path_usb = pdata->muic_pdata->path_usb; 736 - else 737 751 info->path_usb = CONTROL1_SW_USB; 752 + delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 753 + } 738 754 739 755 /* Set initial path for UART */ 740 756 max8997_muic_set_path(info, info->path_uart, true); ··· 767 751 * driver should notify cable state to upper layer. 768 752 */ 769 753 INIT_DELAYED_WORK(&info->wq_detcable, max8997_muic_detect_cable_wq); 770 - if (pdata->muic_pdata->detcable_delay_ms) 771 - delay_jiffies = msecs_to_jiffies(pdata->muic_pdata->detcable_delay_ms); 772 - else 773 - delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 774 754 schedule_delayed_work(&info->wq_detcable, delay_jiffies); 775 755 776 756 return 0;
+20 -9
drivers/misc/mei/hw-me.c
··· 152 152 } 153 153 154 154 /** 155 + * mei_me_hw_reset_release - release device from the reset 156 + * 157 + * @dev: the device structure 158 + */ 159 + static void mei_me_hw_reset_release(struct mei_device *dev) 160 + { 161 + struct mei_me_hw *hw = to_me_hw(dev); 162 + u32 hcsr = mei_hcsr_read(hw); 163 + 164 + hcsr |= H_IG; 165 + hcsr &= ~H_RST; 166 + mei_hcsr_set(hw, hcsr); 167 + } 168 + /** 155 169 * mei_me_hw_reset - resets fw via mei csr register. 156 170 * 157 171 * @dev: the device structure ··· 183 169 if (intr_enable) 184 170 hcsr |= H_IE; 185 171 else 186 - hcsr &= ~H_IE; 172 + hcsr |= ~H_IE; 187 173 188 174 mei_hcsr_set(hw, hcsr); 189 175 190 - hcsr = mei_hcsr_read(hw) | H_IG; 191 - hcsr &= ~H_RST; 176 + if (dev->dev_state == MEI_DEV_POWER_DOWN) 177 + mei_me_hw_reset_release(dev); 192 178 193 - mei_hcsr_set(hw, hcsr); 194 - 195 - hcsr = mei_hcsr_read(hw); 196 - 197 - dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr); 179 + dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw)); 198 180 } 199 181 200 182 /** ··· 476 466 mutex_unlock(&dev->device_lock); 477 467 return IRQ_HANDLED; 478 468 } else { 479 - dev_dbg(&dev->pdev->dev, "FW not ready.\n"); 469 + dev_dbg(&dev->pdev->dev, "Reset Completed.\n"); 470 + mei_me_hw_reset_release(dev); 480 471 mutex_unlock(&dev->device_lock); 481 472 return IRQ_HANDLED; 482 473 }
+18
drivers/misc/mei/init.c
··· 183 183 mei_cl_all_write_clear(dev); 184 184 } 185 185 186 + void mei_stop(struct mei_device *dev) 187 + { 188 + dev_dbg(&dev->pdev->dev, "stopping the device.\n"); 189 + 190 + mutex_lock(&dev->device_lock); 191 + 192 + cancel_delayed_work(&dev->timer_work); 193 + 194 + mei_wd_stop(dev); 195 + 196 + dev->dev_state = MEI_DEV_POWER_DOWN; 197 + mei_reset(dev, 0); 198 + 199 + mutex_unlock(&dev->device_lock); 200 + 201 + flush_scheduled_work(); 202 + } 203 + 186 204 187 205 188 206
+1
drivers/misc/mei/mei_dev.h
··· 381 381 void mei_device_init(struct mei_device *dev); 382 382 void mei_reset(struct mei_device *dev, int interrupts); 383 383 int mei_hw_init(struct mei_device *dev); 384 + void mei_stop(struct mei_device *dev); 384 385 385 386 /* 386 387 * MEI interrupt functions prototype
+7 -45
drivers/misc/mei/pci-me.c
··· 247 247 248 248 hw = to_me_hw(dev); 249 249 250 - mutex_lock(&dev->device_lock); 251 250 252 - cancel_delayed_work(&dev->timer_work); 253 - 254 - mei_wd_stop(dev); 251 + dev_err(&pdev->dev, "stop\n"); 252 + mei_stop(dev); 255 253 256 254 mei_pdev = NULL; 257 255 258 - if (dev->iamthif_cl.state == MEI_FILE_CONNECTED) { 259 - dev->iamthif_cl.state = MEI_FILE_DISCONNECTING; 260 - mei_cl_disconnect(&dev->iamthif_cl); 261 - } 262 - if (dev->wd_cl.state == MEI_FILE_CONNECTED) { 263 - dev->wd_cl.state = MEI_FILE_DISCONNECTING; 264 - mei_cl_disconnect(&dev->wd_cl); 265 - } 266 - 267 - /* Unregistering watchdog device */ 268 256 mei_watchdog_unregister(dev); 269 - 270 - /* remove entry if already in list */ 271 - dev_dbg(&pdev->dev, "list del iamthif and wd file list.\n"); 272 - 273 - if (dev->open_handle_count > 0) 274 - dev->open_handle_count--; 275 - mei_cl_unlink(&dev->wd_cl); 276 - 277 - if (dev->open_handle_count > 0) 278 - dev->open_handle_count--; 279 - mei_cl_unlink(&dev->iamthif_cl); 280 - 281 - dev->iamthif_current_cb = NULL; 282 - dev->me_clients_num = 0; 283 - 284 - mutex_unlock(&dev->device_lock); 285 - 286 - flush_scheduled_work(); 287 257 288 258 /* disable interrupts */ 289 259 mei_disable_interrupts(dev); ··· 278 308 { 279 309 struct pci_dev *pdev = to_pci_dev(device); 280 310 struct mei_device *dev = pci_get_drvdata(pdev); 281 - int err; 282 311 283 312 if (!dev) 284 313 return -ENODEV; 285 - mutex_lock(&dev->device_lock); 286 314 287 - cancel_delayed_work(&dev->timer_work); 315 + dev_err(&pdev->dev, "suspend\n"); 288 316 289 - /* Stop watchdog if exists */ 290 - err = mei_wd_stop(dev); 291 - /* Set new mei state */ 292 - if (dev->dev_state == MEI_DEV_ENABLED || 293 - dev->dev_state == MEI_DEV_RECOVERING_FROM_RESET) { 294 - dev->dev_state = MEI_DEV_POWER_DOWN; 295 - mei_reset(dev, 0); 296 - } 297 - mutex_unlock(&dev->device_lock); 317 + mei_stop(dev); 318 + 319 + mei_disable_interrupts(dev); 298 320 299 321 free_irq(pdev->irq, dev); 300 322 pci_disable_msi(pdev); 301 323 302 - return err; 324 + return 0; 303 325 } 304 326 305 327 static int mei_pci_resume(struct device *device)
+3 -1
drivers/misc/vmw_vmci/vmci_datagram.c
··· 42 42 43 43 struct delayed_datagram_info { 44 44 struct datagram_entry *entry; 45 - struct vmci_datagram msg; 46 45 struct work_struct work; 47 46 bool in_dg_host_queue; 47 + /* msg and msg_payload must be together. */ 48 + struct vmci_datagram msg; 49 + u8 msg_payload[]; 48 50 }; 49 51 50 52 /* Number of in-flight host->host datagrams */
+23
include/linux/mfd/max77693-private.h
··· 106 106 MAX77693_MUIC_REG_END, 107 107 }; 108 108 109 + /* MAX77693 INTMASK1~2 Register */ 110 + #define INTMASK1_ADC1K_SHIFT 3 111 + #define INTMASK1_ADCERR_SHIFT 2 112 + #define INTMASK1_ADCLOW_SHIFT 1 113 + #define INTMASK1_ADC_SHIFT 0 114 + #define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT) 115 + #define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT) 116 + #define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT) 117 + #define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT) 118 + 119 + #define INTMASK2_VIDRM_SHIFT 5 120 + #define INTMASK2_VBVOLT_SHIFT 4 121 + #define INTMASK2_DXOVP_SHIFT 3 122 + #define INTMASK2_DCDTMR_SHIFT 2 123 + #define INTMASK2_CHGDETRUN_SHIFT 1 124 + #define INTMASK2_CHGTYP_SHIFT 0 125 + #define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT) 126 + #define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT) 127 + #define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT) 128 + #define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT) 129 + #define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT) 130 + #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT) 131 + 109 132 /* MAX77693 MUIC - STATUS1~3 Register */ 110 133 #define STATUS1_ADC_SHIFT (0) 111 134 #define STATUS1_ADCLOW_SHIFT (5)